359 lines
12 KiB
C
359 lines
12 KiB
C
/*
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* timers.c
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*
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* Created on: 4 янв. 2026 г.
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* Author: v0stap
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*/
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#include "main.h"
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void Timers_Init(void) {
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var.Send_Data_IRQ = 0;
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TIM1_Init();
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TIM2_Init();
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TIM3_Init();
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TIM7_Init();
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TIM14_Init();
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TIM15_Init();
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TIM16_Init();
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TIM17_Init();
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TIM6_Init();
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//Init Timer1 PWM Input 1
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}
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void TIM1_Init(void) { //configure IN1 as Iddle input PA8 TIM1 CH1
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// PB4 AF1 TIM3 Input1
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
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GPIOA->MODER &= ~(3 << (8 * 2));
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GPIOA->MODER |= (2 << (8 * 2));
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GPIOA->OTYPER &= ~(1 << (8 * 1));
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GPIOA->OSPEEDR &= ~(3 << (8 * 2));
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GPIOA->PUPDR &= ~(3 << (8 * 2));
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GPIOA->AFR[1] &= ~(15 << (0 * 4));
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GPIOA->AFR[1] |= (2 << (0 * 4));
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
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select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
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/* (2) Select TI1FP1 as valid trigger input (TS = 101)
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configure the slave mode in reset mode (SMS = 100) */
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/* (3) Enable capture by setting CC1E and CC2E
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select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
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value),
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select the falling edge on CC2 (CC2P = 1). */
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/* (4) Enable interrupt on Capture/Compare 1 */
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/* (5) Enable counter */
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TIM1->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
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TIM1->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
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TIM1->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
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TIM1->DIER |= TIM_DIER_CC1IE; /* (4) */
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TIM1->CR1 |= TIM_CR1_CEN; /* (5) */
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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}
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void TIM2_Init(void) { //configure IN1 as PWM input PA15 TIM2
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// PB4 AF1 TIM3 Input1
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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GPIOA->MODER &= ~(3 << (15 * 2));
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GPIOA->MODER |= (2 << (15 * 2));
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GPIOA->OTYPER &= ~(1 << (15 * 1));
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GPIOA->OSPEEDR &= ~(3 << (15 * 2));
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GPIOA->PUPDR &= ~(3 << (15 * 2));
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GPIOA->AFR[1] &= ~(15 << (7 * 4));
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GPIOA->AFR[1] |= (2 << (7 * 4));
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
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select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
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/* (2) Select TI1FP1 as valid trigger input (TS = 101)
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configure the slave mode in reset mode (SMS = 100) */
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/* (3) Enable capture by setting CC1E and CC2E
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select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
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value),
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select the falling edge on CC2 (CC2P = 1). */
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/* (4) Enable interrupt on Capture/Compare 1 */
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/* (5) Enable counter */
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TIM2->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
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TIM2->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
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TIM2->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
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TIM2->DIER |= TIM_DIER_CC1IE; /* (4) */
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TIM2->CR1 |= TIM_CR1_CEN; /* (5) */
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NVIC_EnableIRQ(TIM2_IRQn);
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}
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void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3
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// PB4 AF1 TIM3 Input1
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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// GPIOB->MODER &= ~(3 << (4 * 2));
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// GPIOB->MODER |= (2 << (4 * 2));
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// GPIOB->OTYPER &= ~(1 << 4 * 1);
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// GPIOB->OSPEEDR &= ~(3 << (4 * 2));
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// GPIOB->PUPDR &= ~(3 << (4 * 2));
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// GPIOB->AFR[0] &= ~(15 << (4 * 4));
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// GPIOB->AFR[0] |= (1 << (4 * 4));
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GPIOB->MODER &= ~(3 << (5 * 2));
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GPIOB->MODER |= (2 << (5 * 2));
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GPIOB->OTYPER &= ~(1 << (5 * 1));
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GPIOB->OSPEEDR &= ~(3 << (5 * 2));
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GPIOB->PUPDR &= ~(3 << (5 * 2));
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GPIOB->AFR[0] &= ~(15 << (5 * 4));
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GPIOB->AFR[0] |= (1 << (5 * 4));
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
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select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
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/* (2) Select TI1FP1 as valid trigger input (TS = 101)
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configure the slave mode in reset mode (SMS = 100) */
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/* (3) Enable capture by setting CC1E and CC2E
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select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
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value),
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select the falling edge on CC2 (CC2P = 1). */
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/* (4) Enable interrupt on Capture/Compare 1 */
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/* (5) Enable counter */
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TIM3->CCMR1 |= TIM_CCMR1_CC1S_1 | TIM_CCMR1_CC2S_0; /* (1)*/
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TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
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TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
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TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */
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TIM3->CR1 |= TIM_CR1_CEN; /* (5) */
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NVIC_EnableIRQ(TIM3_IRQn);
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}
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void TIM6_Init(void) {
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// Init Timer 6
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RCC->APB1ENR |= RCC_APB1ENR_TIM6EN;
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TIM6->PSC = 479;
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TIM6->ARR = 2000;
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TIM6->CR1 |= 1 << 0 | 1 << 7;
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TIM6->CR2 = 0;
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TIM6->SMCR = 0;
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TIM6->DIER = 1 << 0;
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TIM6->CCMR1 = 0;
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TIM6->CCMR2 = 0;
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TIM6->CCER = 0x1111;
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TIM6->SR = 0;
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NVIC_EnableIRQ(TIM6_IRQn);
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}
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void TIM7_Init(void) {
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// Init Timer 6
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RCC->APB1ENR |= RCC_APB1ENR_TIM7EN;
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TIM7->PSC = 4799;
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TIM7->ARR = 1000;
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TIM7->CR1 |= 1 << 0 | 1 << 7;
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TIM7->CR2 = 0;
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TIM7->SMCR = 0;
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TIM7->DIER = 1 << 0;
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TIM7->CCMR1 = 0;
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TIM7->CCMR2 = 0;
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TIM7->CCER = 0x1111;
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TIM7->SR = 0;
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NVIC_EnableIRQ(TIM7_IRQn);
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}
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void TIM14_Init(void) {
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/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
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/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
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/* (3) Set CCRx = 4, , the signal will be high during 4 us */
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/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
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enable preload register on OC1 (OC1PE = 1) */
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/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
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enable the output on OC1 (CC1E = 1)*/
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/* (6) Enable output (MOE = 1)*/
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/* (7) Enable counter (CEN = 1)
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select edge aligned mode (CMS = 00, reset value)
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select direction as upcounter (DIR = 0, reset value) */
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/* (8) Force update generation (UG = 1) */
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TIM14->PSC = 48 - 1; /* (1) */
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TIM14->ARR = 1000; /* (2) */
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TIM14->CCR1 = 500; /* (3) */
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TIM14->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
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| TIM_CCMR1_OC1PE; /* (4) */
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TIM14->CCER |= TIM_CCER_CC1E; /* (5) */
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TIM14->BDTR |= TIM_BDTR_MOE; /* (6) */
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TIM14->CR1 |= TIM_CR1_CEN; /* (7) */
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TIM14->EGR |= TIM_EGR_UG; /* (8) */
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}
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void TIM15_Init(void) { //configure IN1 as Iddle input PB4 TIM3
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// PB4 AF1 TIM3 Input1
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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GPIOB->MODER &= ~(3 << (14 * 2));
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GPIOB->MODER |= (2 << (14 * 2));
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GPIOB->OTYPER &= ~(1 << (14 * 1));
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GPIOB->OSPEEDR &= ~(3 << (4 * 2));
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GPIOB->PUPDR &= ~(3 << (4 * 2));
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GPIOB->AFR[0] &= ~(15 << (6 * 4));
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GPIOB->AFR[0] |= (1 << (6 * 4));
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RCC->APB2ENR |= RCC_APB2ENR_TIM15EN;
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/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
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select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
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/* (2) Select TI1FP1 as valid trigger input (TS = 101)
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configure the slave mode in reset mode (SMS = 100) */
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/* (3) Enable capture by setting CC1E and CC2E
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select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
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value),
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select the falling edge on CC2 (CC2P = 1). */
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/* (4) Enable interrupt on Capture/Compare 1 */
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/* (5) Enable counter */
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TIM15->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
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TIM15->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
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TIM15->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
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TIM15->DIER |= TIM_DIER_CC1IE; /* (4) */
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TIM15->CR1 |= TIM_CR1_CEN; /* (5) */
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NVIC_EnableIRQ(TIM15_IRQn);
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}
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void TIM16_Init(void) {
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/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
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/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
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/* (3) Set CCRx = 4, , the signal will be high during 4 us */
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/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
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enable preload register on OC1 (OC1PE = 1) */
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/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
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enable the output on OC1 (CC1E = 1)*/
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/* (6) Enable output (MOE = 1)*/
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/* (7) Enable counter (CEN = 1)
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select edge aligned mode (CMS = 00, reset value)
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select direction as upcounter (DIR = 0, reset value) */
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/* (8) Force update generation (UG = 1) */
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TIM16->PSC = 48 - 1; /* (1) */
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TIM16->ARR = 1000; /* (2) */
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TIM16->CCR1 = 500; /* (3) */
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TIM16->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
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| TIM_CCMR1_OC1PE; /* (4) */
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TIM16->CCER |= TIM_CCER_CC1E; /* (5) */
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TIM16->BDTR |= TIM_BDTR_MOE; /* (6) */
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TIM16->CR1 |= TIM_CR1_CEN; /* (7) */
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TIM16->EGR |= TIM_EGR_UG; /* (8) */
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}
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void TIM17_Init(void) {
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/* (1) Set prescaler to 47, so APBCLK/48 i.e 1MHz */
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/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
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/* (3) Set CCRx = 4, , the signal will be high during 4 us */
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/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
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enable preload register on OC1 (OC1PE = 1) */
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/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
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enable the output on OC1 (CC1E = 1)*/
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/* (6) Enable output (MOE = 1)*/
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/* (7) Enable counter (CEN = 1)
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select edge aligned mode (CMS = 00, reset value)
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select direction as upcounter (DIR = 0, reset value) */
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/* (8) Force update generation (UG = 1) */
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TIM17->PSC = 48 - 1; /* (1) */
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TIM17->ARR = 1000; /* (2) */
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TIM17->CCR1 = 0; /* (3) */
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TIM17->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
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| TIM_CCMR1_OC1PE; /* (4) */
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TIM17->CCER |= TIM_CCER_CC1E; /* (5) */
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TIM17->BDTR |= TIM_BDTR_MOE; /* (6) */
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TIM17->CR1 |= TIM_CR1_CEN; /* (7) */
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TIM17->EGR |= TIM_EGR_UG; /* (8) */
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}
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void TIM1_CC_IRQHandler(void) {
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if ((TIM1->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM1->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
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{
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM1->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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return;
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} else {
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var.dvi_fr[0] = TIM1->CCR1;
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var.dvi_dt[0] = (TIM1->CCR2) * 100 / var.dvi_fr[0]; //Get DC
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var.dvi_fr[0] = 48000000 / var.dvi_fr[0];
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// printf("data1 =%d; data2 =%d \n",counter0,counter1);
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}
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} else {
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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void TIM2_IRQHandler(void) {
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var.tim2_timeout = 0;
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if ((TIM2->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM2->SR & TIM_SR_CC1OF) != 0) {/* Check the overflow */
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM2->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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return;
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} else {
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var.dvi_fr[1] = TIM2->CCR1;
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var.dvi_dt[1] = (TIM2->CCR2) * 100 / var.dvi_fr[1]; //Get DC
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var.dvi_fr[1] = 48000000 / var.dvi_fr[1];
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// printf("data1 =%d; data2 =%d \n",counter0,counter1);
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}
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} else {
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var.dvi_dt[1] = 0xff00;
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var.dvi_fr[1] = 0;
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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void TIM3_IRQHandler(void) {
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if ((TIM3->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
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{
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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return;
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} else {
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var.dvi_fr[2] = TIM3->CCR1;
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var.dvi_dt[2] = (TIM3->CCR2) * 1000 / var.dvi_fr[2]; //Get DC
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var.dvi_fr[2] = 48000000 / var.dvi_fr[2];
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// printf("data1 =%d; data2 =%d \n",counter0,counter1);
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}
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} else {
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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void TIM6_DAC_IRQHandler(void) {
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TIM6->SR &= ~(1 << 0);
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//TIM2->CNT = 600;
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var.Send_Data_IRQ = 4;
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if (var.tim1_timeout < 254)
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var.tim1_timeout++;
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if (var.tim2_timeout < 254)
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var.tim2_timeout++;
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if (var.tim3_timeout < 254)
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var.tim3_timeout++;
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if (var.tim15_timeout < 254)
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var.tim15_timeout++;
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if (var.can_timeout < 254)
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var.can_timeout++;
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}
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void TIM7_IRQHandler(void) {
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TIM7->SR &= ~(1 << 0);
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if (var.dvo_dt[3] == 0)
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HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
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else
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HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
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}
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void TIM15_IRQHandler(void) {
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if ((TIM15->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM15->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
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{
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM15->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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return;
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} else {
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var.dvi_fr[3] = TIM15->CCR1;
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var.dvi_dt[3] = (TIM15->CCR2) * 100 / TIM15->CCR1; //Get DC
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var.dvi_fr[3] = 48000000 / var.dvi_fr[3];
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// printf("data1 =%d; data2 =%d \n",counter0,counter1);
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}
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} else {
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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