21339 lines
860 KiB
Plaintext
21339 lines
860 KiB
Plaintext
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DBW_V2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000000c0 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .config 00000358 0800f000 0800f000 0000b000 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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2 .text 000088d4 080000c0 080000c0 000010c0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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3 .rodata 0000018c 08008994 08008994 00009994 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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4 .ARM.extab 00000000 08008b20 08008b20 0000b358 2**0
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CONTENTS
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5 .ARM 00000000 08008b20 08008b20 0000b358 2**0
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CONTENTS
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6 .preinit_array 00000000 08008b20 08008b20 0000b358 2**0
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CONTENTS, ALLOC, LOAD, DATA
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7 .init_array 00000004 08008b20 08008b20 00009b20 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .fini_array 00000004 08008b24 08008b24 00009b24 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .data 00000414 20000000 08008b28 0000a000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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10 .bss 000009b8 20000418 08008f3c 0000a418 2**3
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ALLOC
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11 ._user_heap_stack 00000600 20000dd0 08008f3c 0000add0 2**0
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ALLOC
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12 .ARM.attributes 00000028 00000000 00000000 0000b358 2**0
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CONTENTS, READONLY
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13 .debug_info 0000c9d8 00000000 00000000 0000b380 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_abbrev 00002cfc 00000000 00000000 00017d58 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_aranges 00000b28 00000000 00000000 0001aa58 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_rnglists 00000882 00000000 00000000 0001b580 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_macro 0001afcf 00000000 00000000 0001be02 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_line 000107b0 00000000 00000000 00036dd1 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_str 0009656c 00000000 00000000 00047581 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .comment 00000043 00000000 00000000 000ddaed 2**0
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CONTENTS, READONLY
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21 .debug_frame 000028b8 00000000 00000000 000ddb30 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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22 .debug_line_str 0000005b 00000000 00000000 000e03e8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080000c0 <__do_global_dtors_aux>:
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80000c0: b510 push {r4, lr}
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80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>)
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80000c4: 7823 ldrb r3, [r4, #0]
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80000c6: 2b00 cmp r3, #0
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80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
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80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>)
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80000cc: 2b00 cmp r3, #0
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80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>)
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80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d4: bf00 nop
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80000d6: 2301 movs r3, #1
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80000d8: 7023 strb r3, [r4, #0]
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80000da: bd10 pop {r4, pc}
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80000dc: 20000418 .word 0x20000418
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80000e0: 00000000 .word 0x00000000
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80000e4: 0800897c .word 0x0800897c
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080000e8 <frame_dummy>:
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80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc <frame_dummy+0x14>)
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80000ea: b510 push {r4, lr}
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80000ec: 2b00 cmp r3, #0
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80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
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80000f0: 4903 ldr r1, [pc, #12] @ (8000100 <frame_dummy+0x18>)
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80000f2: 4804 ldr r0, [pc, #16] @ (8000104 <frame_dummy+0x1c>)
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80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
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80000f6: bf00 nop
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80000f8: bd10 pop {r4, pc}
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80000fa: 46c0 nop @ (mov r8, r8)
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80000fc: 00000000 .word 0x00000000
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8000100: 2000041c .word 0x2000041c
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8000104: 0800897c .word 0x0800897c
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08000108 <__udivsi3>:
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8000108: 2200 movs r2, #0
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800010a: 0843 lsrs r3, r0, #1
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800010c: 428b cmp r3, r1
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800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
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8000110: 0903 lsrs r3, r0, #4
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8000112: 428b cmp r3, r1
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8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
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8000116: 0a03 lsrs r3, r0, #8
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8000118: 428b cmp r3, r1
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800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
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800011c: 0b03 lsrs r3, r0, #12
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800011e: 428b cmp r3, r1
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8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
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8000122: 0c03 lsrs r3, r0, #16
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8000124: 428b cmp r3, r1
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8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
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8000128: 22ff movs r2, #255 @ 0xff
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800012a: 0209 lsls r1, r1, #8
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800012c: ba12 rev r2, r2
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800012e: 0c03 lsrs r3, r0, #16
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8000130: 428b cmp r3, r1
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8000132: d302 bcc.n 800013a <__udivsi3+0x32>
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8000134: 1212 asrs r2, r2, #8
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8000136: 0209 lsls r1, r1, #8
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8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
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800013a: 0b03 lsrs r3, r0, #12
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800013c: 428b cmp r3, r1
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800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
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8000140: e000 b.n 8000144 <__udivsi3+0x3c>
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8000142: 0a09 lsrs r1, r1, #8
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8000144: 0bc3 lsrs r3, r0, #15
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8000146: 428b cmp r3, r1
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8000148: d301 bcc.n 800014e <__udivsi3+0x46>
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800014a: 03cb lsls r3, r1, #15
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800014c: 1ac0 subs r0, r0, r3
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800014e: 4152 adcs r2, r2
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8000150: 0b83 lsrs r3, r0, #14
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8000152: 428b cmp r3, r1
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8000154: d301 bcc.n 800015a <__udivsi3+0x52>
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8000156: 038b lsls r3, r1, #14
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8000158: 1ac0 subs r0, r0, r3
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800015a: 4152 adcs r2, r2
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800015c: 0b43 lsrs r3, r0, #13
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800015e: 428b cmp r3, r1
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8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
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8000162: 034b lsls r3, r1, #13
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8000164: 1ac0 subs r0, r0, r3
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8000166: 4152 adcs r2, r2
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8000168: 0b03 lsrs r3, r0, #12
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800016a: 428b cmp r3, r1
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800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
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800016e: 030b lsls r3, r1, #12
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8000170: 1ac0 subs r0, r0, r3
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8000172: 4152 adcs r2, r2
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8000174: 0ac3 lsrs r3, r0, #11
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8000176: 428b cmp r3, r1
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8000178: d301 bcc.n 800017e <__udivsi3+0x76>
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800017a: 02cb lsls r3, r1, #11
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800017c: 1ac0 subs r0, r0, r3
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800017e: 4152 adcs r2, r2
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8000180: 0a83 lsrs r3, r0, #10
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8000182: 428b cmp r3, r1
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8000184: d301 bcc.n 800018a <__udivsi3+0x82>
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8000186: 028b lsls r3, r1, #10
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8000188: 1ac0 subs r0, r0, r3
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800018a: 4152 adcs r2, r2
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800018c: 0a43 lsrs r3, r0, #9
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800018e: 428b cmp r3, r1
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8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
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8000192: 024b lsls r3, r1, #9
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8000194: 1ac0 subs r0, r0, r3
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8000196: 4152 adcs r2, r2
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8000198: 0a03 lsrs r3, r0, #8
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800019a: 428b cmp r3, r1
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800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
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800019e: 020b lsls r3, r1, #8
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80001a0: 1ac0 subs r0, r0, r3
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80001a2: 4152 adcs r2, r2
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80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
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80001a6: 09c3 lsrs r3, r0, #7
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80001a8: 428b cmp r3, r1
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80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
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80001ac: 01cb lsls r3, r1, #7
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80001ae: 1ac0 subs r0, r0, r3
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80001b0: 4152 adcs r2, r2
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80001b2: 0983 lsrs r3, r0, #6
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80001b4: 428b cmp r3, r1
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80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
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80001b8: 018b lsls r3, r1, #6
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80001ba: 1ac0 subs r0, r0, r3
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80001bc: 4152 adcs r2, r2
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80001be: 0943 lsrs r3, r0, #5
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80001c0: 428b cmp r3, r1
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80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
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80001c4: 014b lsls r3, r1, #5
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80001c6: 1ac0 subs r0, r0, r3
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80001c8: 4152 adcs r2, r2
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80001ca: 0903 lsrs r3, r0, #4
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80001cc: 428b cmp r3, r1
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80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
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80001d0: 010b lsls r3, r1, #4
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80001d2: 1ac0 subs r0, r0, r3
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80001d4: 4152 adcs r2, r2
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80001d6: 08c3 lsrs r3, r0, #3
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80001d8: 428b cmp r3, r1
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80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
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80001dc: 00cb lsls r3, r1, #3
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80001de: 1ac0 subs r0, r0, r3
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80001e0: 4152 adcs r2, r2
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80001e2: 0883 lsrs r3, r0, #2
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80001e4: 428b cmp r3, r1
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80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
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80001e8: 008b lsls r3, r1, #2
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80001ea: 1ac0 subs r0, r0, r3
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80001ec: 4152 adcs r2, r2
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80001ee: 0843 lsrs r3, r0, #1
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80001f0: 428b cmp r3, r1
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80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
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80001f4: 004b lsls r3, r1, #1
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80001f6: 1ac0 subs r0, r0, r3
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80001f8: 4152 adcs r2, r2
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80001fa: 1a41 subs r1, r0, r1
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80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
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80001fe: 4601 mov r1, r0
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8000200: 4152 adcs r2, r2
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8000202: 4610 mov r0, r2
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8000204: 4770 bx lr
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8000206: e7ff b.n 8000208 <__udivsi3+0x100>
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8000208: b501 push {r0, lr}
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800020a: 2000 movs r0, #0
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800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0>
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8000210: bd02 pop {r1, pc}
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8000212: 46c0 nop @ (mov r8, r8)
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08000214 <__aeabi_uidivmod>:
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8000214: 2900 cmp r1, #0
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8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
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8000218: e776 b.n 8000108 <__udivsi3>
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800021a: 4770 bx lr
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0800021c <__divsi3>:
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800021c: 4603 mov r3, r0
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800021e: 430b orrs r3, r1
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8000220: d47f bmi.n 8000322 <__divsi3+0x106>
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8000222: 2200 movs r2, #0
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8000224: 0843 lsrs r3, r0, #1
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8000226: 428b cmp r3, r1
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8000228: d374 bcc.n 8000314 <__divsi3+0xf8>
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800022a: 0903 lsrs r3, r0, #4
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800022c: 428b cmp r3, r1
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800022e: d35f bcc.n 80002f0 <__divsi3+0xd4>
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8000230: 0a03 lsrs r3, r0, #8
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8000232: 428b cmp r3, r1
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8000234: d344 bcc.n 80002c0 <__divsi3+0xa4>
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8000236: 0b03 lsrs r3, r0, #12
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8000238: 428b cmp r3, r1
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800023a: d328 bcc.n 800028e <__divsi3+0x72>
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800023c: 0c03 lsrs r3, r0, #16
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800023e: 428b cmp r3, r1
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8000240: d30d bcc.n 800025e <__divsi3+0x42>
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8000242: 22ff movs r2, #255 @ 0xff
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8000244: 0209 lsls r1, r1, #8
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8000246: ba12 rev r2, r2
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8000248: 0c03 lsrs r3, r0, #16
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800024a: 428b cmp r3, r1
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800024c: d302 bcc.n 8000254 <__divsi3+0x38>
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800024e: 1212 asrs r2, r2, #8
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8000250: 0209 lsls r1, r1, #8
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8000252: d065 beq.n 8000320 <__divsi3+0x104>
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8000254: 0b03 lsrs r3, r0, #12
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8000256: 428b cmp r3, r1
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8000258: d319 bcc.n 800028e <__divsi3+0x72>
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800025a: e000 b.n 800025e <__divsi3+0x42>
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800025c: 0a09 lsrs r1, r1, #8
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800025e: 0bc3 lsrs r3, r0, #15
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8000260: 428b cmp r3, r1
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8000262: d301 bcc.n 8000268 <__divsi3+0x4c>
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8000264: 03cb lsls r3, r1, #15
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8000266: 1ac0 subs r0, r0, r3
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8000268: 4152 adcs r2, r2
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800026a: 0b83 lsrs r3, r0, #14
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800026c: 428b cmp r3, r1
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800026e: d301 bcc.n 8000274 <__divsi3+0x58>
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8000270: 038b lsls r3, r1, #14
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8000272: 1ac0 subs r0, r0, r3
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8000274: 4152 adcs r2, r2
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8000276: 0b43 lsrs r3, r0, #13
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8000278: 428b cmp r3, r1
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800027a: d301 bcc.n 8000280 <__divsi3+0x64>
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800027c: 034b lsls r3, r1, #13
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800027e: 1ac0 subs r0, r0, r3
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8000280: 4152 adcs r2, r2
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8000282: 0b03 lsrs r3, r0, #12
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8000284: 428b cmp r3, r1
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8000286: d301 bcc.n 800028c <__divsi3+0x70>
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8000288: 030b lsls r3, r1, #12
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800028a: 1ac0 subs r0, r0, r3
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800028c: 4152 adcs r2, r2
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800028e: 0ac3 lsrs r3, r0, #11
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8000290: 428b cmp r3, r1
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8000292: d301 bcc.n 8000298 <__divsi3+0x7c>
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8000294: 02cb lsls r3, r1, #11
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8000296: 1ac0 subs r0, r0, r3
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8000298: 4152 adcs r2, r2
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800029a: 0a83 lsrs r3, r0, #10
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800029c: 428b cmp r3, r1
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800029e: d301 bcc.n 80002a4 <__divsi3+0x88>
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80002a0: 028b lsls r3, r1, #10
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80002a2: 1ac0 subs r0, r0, r3
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80002a4: 4152 adcs r2, r2
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80002a6: 0a43 lsrs r3, r0, #9
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80002a8: 428b cmp r3, r1
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80002aa: d301 bcc.n 80002b0 <__divsi3+0x94>
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80002ac: 024b lsls r3, r1, #9
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80002ae: 1ac0 subs r0, r0, r3
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80002b0: 4152 adcs r2, r2
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80002b2: 0a03 lsrs r3, r0, #8
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80002b4: 428b cmp r3, r1
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80002b6: d301 bcc.n 80002bc <__divsi3+0xa0>
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80002b8: 020b lsls r3, r1, #8
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80002ba: 1ac0 subs r0, r0, r3
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80002bc: 4152 adcs r2, r2
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80002be: d2cd bcs.n 800025c <__divsi3+0x40>
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80002c0: 09c3 lsrs r3, r0, #7
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80002c2: 428b cmp r3, r1
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80002c4: d301 bcc.n 80002ca <__divsi3+0xae>
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80002c6: 01cb lsls r3, r1, #7
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80002c8: 1ac0 subs r0, r0, r3
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80002ca: 4152 adcs r2, r2
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80002cc: 0983 lsrs r3, r0, #6
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80002ce: 428b cmp r3, r1
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80002d0: d301 bcc.n 80002d6 <__divsi3+0xba>
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80002d2: 018b lsls r3, r1, #6
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80002d4: 1ac0 subs r0, r0, r3
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80002d6: 4152 adcs r2, r2
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80002d8: 0943 lsrs r3, r0, #5
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80002da: 428b cmp r3, r1
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80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6>
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80002de: 014b lsls r3, r1, #5
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80002e0: 1ac0 subs r0, r0, r3
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80002e2: 4152 adcs r2, r2
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80002e4: 0903 lsrs r3, r0, #4
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80002e6: 428b cmp r3, r1
|
|
80002e8: d301 bcc.n 80002ee <__divsi3+0xd2>
|
|
80002ea: 010b lsls r3, r1, #4
|
|
80002ec: 1ac0 subs r0, r0, r3
|
|
80002ee: 4152 adcs r2, r2
|
|
80002f0: 08c3 lsrs r3, r0, #3
|
|
80002f2: 428b cmp r3, r1
|
|
80002f4: d301 bcc.n 80002fa <__divsi3+0xde>
|
|
80002f6: 00cb lsls r3, r1, #3
|
|
80002f8: 1ac0 subs r0, r0, r3
|
|
80002fa: 4152 adcs r2, r2
|
|
80002fc: 0883 lsrs r3, r0, #2
|
|
80002fe: 428b cmp r3, r1
|
|
8000300: d301 bcc.n 8000306 <__divsi3+0xea>
|
|
8000302: 008b lsls r3, r1, #2
|
|
8000304: 1ac0 subs r0, r0, r3
|
|
8000306: 4152 adcs r2, r2
|
|
8000308: 0843 lsrs r3, r0, #1
|
|
800030a: 428b cmp r3, r1
|
|
800030c: d301 bcc.n 8000312 <__divsi3+0xf6>
|
|
800030e: 004b lsls r3, r1, #1
|
|
8000310: 1ac0 subs r0, r0, r3
|
|
8000312: 4152 adcs r2, r2
|
|
8000314: 1a41 subs r1, r0, r1
|
|
8000316: d200 bcs.n 800031a <__divsi3+0xfe>
|
|
8000318: 4601 mov r1, r0
|
|
800031a: 4152 adcs r2, r2
|
|
800031c: 4610 mov r0, r2
|
|
800031e: 4770 bx lr
|
|
8000320: e05d b.n 80003de <__divsi3+0x1c2>
|
|
8000322: 0fca lsrs r2, r1, #31
|
|
8000324: d000 beq.n 8000328 <__divsi3+0x10c>
|
|
8000326: 4249 negs r1, r1
|
|
8000328: 1003 asrs r3, r0, #32
|
|
800032a: d300 bcc.n 800032e <__divsi3+0x112>
|
|
800032c: 4240 negs r0, r0
|
|
800032e: 4053 eors r3, r2
|
|
8000330: 2200 movs r2, #0
|
|
8000332: 469c mov ip, r3
|
|
8000334: 0903 lsrs r3, r0, #4
|
|
8000336: 428b cmp r3, r1
|
|
8000338: d32d bcc.n 8000396 <__divsi3+0x17a>
|
|
800033a: 0a03 lsrs r3, r0, #8
|
|
800033c: 428b cmp r3, r1
|
|
800033e: d312 bcc.n 8000366 <__divsi3+0x14a>
|
|
8000340: 22fc movs r2, #252 @ 0xfc
|
|
8000342: 0189 lsls r1, r1, #6
|
|
8000344: ba12 rev r2, r2
|
|
8000346: 0a03 lsrs r3, r0, #8
|
|
8000348: 428b cmp r3, r1
|
|
800034a: d30c bcc.n 8000366 <__divsi3+0x14a>
|
|
800034c: 0189 lsls r1, r1, #6
|
|
800034e: 1192 asrs r2, r2, #6
|
|
8000350: 428b cmp r3, r1
|
|
8000352: d308 bcc.n 8000366 <__divsi3+0x14a>
|
|
8000354: 0189 lsls r1, r1, #6
|
|
8000356: 1192 asrs r2, r2, #6
|
|
8000358: 428b cmp r3, r1
|
|
800035a: d304 bcc.n 8000366 <__divsi3+0x14a>
|
|
800035c: 0189 lsls r1, r1, #6
|
|
800035e: d03a beq.n 80003d6 <__divsi3+0x1ba>
|
|
8000360: 1192 asrs r2, r2, #6
|
|
8000362: e000 b.n 8000366 <__divsi3+0x14a>
|
|
8000364: 0989 lsrs r1, r1, #6
|
|
8000366: 09c3 lsrs r3, r0, #7
|
|
8000368: 428b cmp r3, r1
|
|
800036a: d301 bcc.n 8000370 <__divsi3+0x154>
|
|
800036c: 01cb lsls r3, r1, #7
|
|
800036e: 1ac0 subs r0, r0, r3
|
|
8000370: 4152 adcs r2, r2
|
|
8000372: 0983 lsrs r3, r0, #6
|
|
8000374: 428b cmp r3, r1
|
|
8000376: d301 bcc.n 800037c <__divsi3+0x160>
|
|
8000378: 018b lsls r3, r1, #6
|
|
800037a: 1ac0 subs r0, r0, r3
|
|
800037c: 4152 adcs r2, r2
|
|
800037e: 0943 lsrs r3, r0, #5
|
|
8000380: 428b cmp r3, r1
|
|
8000382: d301 bcc.n 8000388 <__divsi3+0x16c>
|
|
8000384: 014b lsls r3, r1, #5
|
|
8000386: 1ac0 subs r0, r0, r3
|
|
8000388: 4152 adcs r2, r2
|
|
800038a: 0903 lsrs r3, r0, #4
|
|
800038c: 428b cmp r3, r1
|
|
800038e: d301 bcc.n 8000394 <__divsi3+0x178>
|
|
8000390: 010b lsls r3, r1, #4
|
|
8000392: 1ac0 subs r0, r0, r3
|
|
8000394: 4152 adcs r2, r2
|
|
8000396: 08c3 lsrs r3, r0, #3
|
|
8000398: 428b cmp r3, r1
|
|
800039a: d301 bcc.n 80003a0 <__divsi3+0x184>
|
|
800039c: 00cb lsls r3, r1, #3
|
|
800039e: 1ac0 subs r0, r0, r3
|
|
80003a0: 4152 adcs r2, r2
|
|
80003a2: 0883 lsrs r3, r0, #2
|
|
80003a4: 428b cmp r3, r1
|
|
80003a6: d301 bcc.n 80003ac <__divsi3+0x190>
|
|
80003a8: 008b lsls r3, r1, #2
|
|
80003aa: 1ac0 subs r0, r0, r3
|
|
80003ac: 4152 adcs r2, r2
|
|
80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148>
|
|
80003b0: 0843 lsrs r3, r0, #1
|
|
80003b2: 428b cmp r3, r1
|
|
80003b4: d301 bcc.n 80003ba <__divsi3+0x19e>
|
|
80003b6: 004b lsls r3, r1, #1
|
|
80003b8: 1ac0 subs r0, r0, r3
|
|
80003ba: 4152 adcs r2, r2
|
|
80003bc: 1a41 subs r1, r0, r1
|
|
80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6>
|
|
80003c0: 4601 mov r1, r0
|
|
80003c2: 4663 mov r3, ip
|
|
80003c4: 4152 adcs r2, r2
|
|
80003c6: 105b asrs r3, r3, #1
|
|
80003c8: 4610 mov r0, r2
|
|
80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4>
|
|
80003cc: 4240 negs r0, r0
|
|
80003ce: 2b00 cmp r3, #0
|
|
80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8>
|
|
80003d2: 4249 negs r1, r1
|
|
80003d4: 4770 bx lr
|
|
80003d6: 4663 mov r3, ip
|
|
80003d8: 105b asrs r3, r3, #1
|
|
80003da: d300 bcc.n 80003de <__divsi3+0x1c2>
|
|
80003dc: 4240 negs r0, r0
|
|
80003de: b501 push {r0, lr}
|
|
80003e0: 2000 movs r0, #0
|
|
80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0>
|
|
80003e6: bd02 pop {r1, pc}
|
|
|
|
080003e8 <__aeabi_idivmod>:
|
|
80003e8: 2900 cmp r1, #0
|
|
80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2>
|
|
80003ec: e716 b.n 800021c <__divsi3>
|
|
80003ee: 4770 bx lr
|
|
|
|
080003f0 <__aeabi_idiv0>:
|
|
80003f0: 4770 bx lr
|
|
80003f2: 46c0 nop @ (mov r8, r8)
|
|
|
|
080003f4 <__aeabi_cfrcmple>:
|
|
80003f4: 4684 mov ip, r0
|
|
80003f6: 0008 movs r0, r1
|
|
80003f8: 4661 mov r1, ip
|
|
80003fa: e7ff b.n 80003fc <__aeabi_cfcmpeq>
|
|
|
|
080003fc <__aeabi_cfcmpeq>:
|
|
80003fc: b51f push {r0, r1, r2, r3, r4, lr}
|
|
80003fe: f000 fbfd bl 8000bfc <__lesf2>
|
|
8000402: 2800 cmp r0, #0
|
|
8000404: d401 bmi.n 800040a <__aeabi_cfcmpeq+0xe>
|
|
8000406: 2100 movs r1, #0
|
|
8000408: 42c8 cmn r0, r1
|
|
800040a: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|
|
|
0800040c <__aeabi_fcmpeq>:
|
|
800040c: b510 push {r4, lr}
|
|
800040e: f000 fb85 bl 8000b1c <__eqsf2>
|
|
8000412: 4240 negs r0, r0
|
|
8000414: 3001 adds r0, #1
|
|
8000416: bd10 pop {r4, pc}
|
|
|
|
08000418 <__aeabi_fcmplt>:
|
|
8000418: b510 push {r4, lr}
|
|
800041a: f000 fbef bl 8000bfc <__lesf2>
|
|
800041e: 2800 cmp r0, #0
|
|
8000420: db01 blt.n 8000426 <__aeabi_fcmplt+0xe>
|
|
8000422: 2000 movs r0, #0
|
|
8000424: bd10 pop {r4, pc}
|
|
8000426: 2001 movs r0, #1
|
|
8000428: bd10 pop {r4, pc}
|
|
800042a: 46c0 nop @ (mov r8, r8)
|
|
|
|
0800042c <__aeabi_fcmple>:
|
|
800042c: b510 push {r4, lr}
|
|
800042e: f000 fbe5 bl 8000bfc <__lesf2>
|
|
8000432: 2800 cmp r0, #0
|
|
8000434: dd01 ble.n 800043a <__aeabi_fcmple+0xe>
|
|
8000436: 2000 movs r0, #0
|
|
8000438: bd10 pop {r4, pc}
|
|
800043a: 2001 movs r0, #1
|
|
800043c: bd10 pop {r4, pc}
|
|
800043e: 46c0 nop @ (mov r8, r8)
|
|
|
|
08000440 <__aeabi_fcmpgt>:
|
|
8000440: b510 push {r4, lr}
|
|
8000442: f000 fb93 bl 8000b6c <__gesf2>
|
|
8000446: 2800 cmp r0, #0
|
|
8000448: dc01 bgt.n 800044e <__aeabi_fcmpgt+0xe>
|
|
800044a: 2000 movs r0, #0
|
|
800044c: bd10 pop {r4, pc}
|
|
800044e: 2001 movs r0, #1
|
|
8000450: bd10 pop {r4, pc}
|
|
8000452: 46c0 nop @ (mov r8, r8)
|
|
|
|
08000454 <__aeabi_fcmpge>:
|
|
8000454: b510 push {r4, lr}
|
|
8000456: f000 fb89 bl 8000b6c <__gesf2>
|
|
800045a: 2800 cmp r0, #0
|
|
800045c: da01 bge.n 8000462 <__aeabi_fcmpge+0xe>
|
|
800045e: 2000 movs r0, #0
|
|
8000460: bd10 pop {r4, pc}
|
|
8000462: 2001 movs r0, #1
|
|
8000464: bd10 pop {r4, pc}
|
|
8000466: 46c0 nop @ (mov r8, r8)
|
|
|
|
08000468 <__aeabi_f2uiz>:
|
|
8000468: 219e movs r1, #158 @ 0x9e
|
|
800046a: b510 push {r4, lr}
|
|
800046c: 05c9 lsls r1, r1, #23
|
|
800046e: 1c04 adds r4, r0, #0
|
|
8000470: f7ff fff0 bl 8000454 <__aeabi_fcmpge>
|
|
8000474: 2800 cmp r0, #0
|
|
8000476: d103 bne.n 8000480 <__aeabi_f2uiz+0x18>
|
|
8000478: 1c20 adds r0, r4, #0
|
|
800047a: f000 ff9b bl 80013b4 <__aeabi_f2iz>
|
|
800047e: bd10 pop {r4, pc}
|
|
8000480: 219e movs r1, #158 @ 0x9e
|
|
8000482: 1c20 adds r0, r4, #0
|
|
8000484: 05c9 lsls r1, r1, #23
|
|
8000486: f000 fd53 bl 8000f30 <__aeabi_fsub>
|
|
800048a: f000 ff93 bl 80013b4 <__aeabi_f2iz>
|
|
800048e: 2380 movs r3, #128 @ 0x80
|
|
8000490: 061b lsls r3, r3, #24
|
|
8000492: 469c mov ip, r3
|
|
8000494: 4460 add r0, ip
|
|
8000496: e7f2 b.n 800047e <__aeabi_f2uiz+0x16>
|
|
|
|
08000498 <__aeabi_d2uiz>:
|
|
8000498: b570 push {r4, r5, r6, lr}
|
|
800049a: 2200 movs r2, #0
|
|
800049c: 4b0c ldr r3, [pc, #48] @ (80004d0 <__aeabi_d2uiz+0x38>)
|
|
800049e: 0004 movs r4, r0
|
|
80004a0: 000d movs r5, r1
|
|
80004a2: f001 ffdb bl 800245c <__aeabi_dcmpge>
|
|
80004a6: 2800 cmp r0, #0
|
|
80004a8: d104 bne.n 80004b4 <__aeabi_d2uiz+0x1c>
|
|
80004aa: 0020 movs r0, r4
|
|
80004ac: 0029 movs r1, r5
|
|
80004ae: f001 ff37 bl 8002320 <__aeabi_d2iz>
|
|
80004b2: bd70 pop {r4, r5, r6, pc}
|
|
80004b4: 4b06 ldr r3, [pc, #24] @ (80004d0 <__aeabi_d2uiz+0x38>)
|
|
80004b6: 2200 movs r2, #0
|
|
80004b8: 0020 movs r0, r4
|
|
80004ba: 0029 movs r1, r5
|
|
80004bc: f001 faf8 bl 8001ab0 <__aeabi_dsub>
|
|
80004c0: f001 ff2e bl 8002320 <__aeabi_d2iz>
|
|
80004c4: 2380 movs r3, #128 @ 0x80
|
|
80004c6: 061b lsls r3, r3, #24
|
|
80004c8: 469c mov ip, r3
|
|
80004ca: 4460 add r0, ip
|
|
80004cc: e7f1 b.n 80004b2 <__aeabi_d2uiz+0x1a>
|
|
80004ce: 46c0 nop @ (mov r8, r8)
|
|
80004d0: 41e00000 .word 0x41e00000
|
|
|
|
080004d4 <__aeabi_fadd>:
|
|
80004d4: 024a lsls r2, r1, #9
|
|
80004d6: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80004d8: 0a53 lsrs r3, r2, #9
|
|
80004da: 46ce mov lr, r9
|
|
80004dc: 4699 mov r9, r3
|
|
80004de: 004b lsls r3, r1, #1
|
|
80004e0: 0fc9 lsrs r1, r1, #31
|
|
80004e2: 4647 mov r7, r8
|
|
80004e4: 4688 mov r8, r1
|
|
80004e6: 0046 lsls r6, r0, #1
|
|
80004e8: 0245 lsls r5, r0, #9
|
|
80004ea: 0e36 lsrs r6, r6, #24
|
|
80004ec: 0e1b lsrs r3, r3, #24
|
|
80004ee: b580 push {r7, lr}
|
|
80004f0: 0fc4 lsrs r4, r0, #31
|
|
80004f2: 0a6f lsrs r7, r5, #9
|
|
80004f4: 0992 lsrs r2, r2, #6
|
|
80004f6: 09ad lsrs r5, r5, #6
|
|
80004f8: 1af1 subs r1, r6, r3
|
|
80004fa: 4544 cmp r4, r8
|
|
80004fc: d04b beq.n 8000596 <__aeabi_fadd+0xc2>
|
|
80004fe: 2900 cmp r1, #0
|
|
8000500: dd38 ble.n 8000574 <__aeabi_fadd+0xa0>
|
|
8000502: 2b00 cmp r3, #0
|
|
8000504: d100 bne.n 8000508 <__aeabi_fadd+0x34>
|
|
8000506: e074 b.n 80005f2 <__aeabi_fadd+0x11e>
|
|
8000508: 2eff cmp r6, #255 @ 0xff
|
|
800050a: d100 bne.n 800050e <__aeabi_fadd+0x3a>
|
|
800050c: e0be b.n 800068c <__aeabi_fadd+0x1b8>
|
|
800050e: 2380 movs r3, #128 @ 0x80
|
|
8000510: 04db lsls r3, r3, #19
|
|
8000512: 431a orrs r2, r3
|
|
8000514: 291b cmp r1, #27
|
|
8000516: dc00 bgt.n 800051a <__aeabi_fadd+0x46>
|
|
8000518: e0fd b.n 8000716 <__aeabi_fadd+0x242>
|
|
800051a: 3d01 subs r5, #1
|
|
800051c: 016b lsls r3, r5, #5
|
|
800051e: d400 bmi.n 8000522 <__aeabi_fadd+0x4e>
|
|
8000520: e0af b.n 8000682 <__aeabi_fadd+0x1ae>
|
|
8000522: 2501 movs r5, #1
|
|
8000524: 426d negs r5, r5
|
|
8000526: 01ad lsls r5, r5, #6
|
|
8000528: 09af lsrs r7, r5, #6
|
|
800052a: 0038 movs r0, r7
|
|
800052c: f001 ffa0 bl 8002470 <__clzsi2>
|
|
8000530: 003b movs r3, r7
|
|
8000532: 3805 subs r0, #5
|
|
8000534: 4083 lsls r3, r0
|
|
8000536: 4286 cmp r6, r0
|
|
8000538: dc00 bgt.n 800053c <__aeabi_fadd+0x68>
|
|
800053a: e0d3 b.n 80006e4 <__aeabi_fadd+0x210>
|
|
800053c: 4db9 ldr r5, [pc, #740] @ (8000824 <__aeabi_fadd+0x350>)
|
|
800053e: 1a31 subs r1, r6, r0
|
|
8000540: 401d ands r5, r3
|
|
8000542: 075a lsls r2, r3, #29
|
|
8000544: d100 bne.n 8000548 <__aeabi_fadd+0x74>
|
|
8000546: e09e b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
8000548: 220f movs r2, #15
|
|
800054a: 4013 ands r3, r2
|
|
800054c: 2b04 cmp r3, #4
|
|
800054e: d100 bne.n 8000552 <__aeabi_fadd+0x7e>
|
|
8000550: e099 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
8000552: 3504 adds r5, #4
|
|
8000554: 016b lsls r3, r5, #5
|
|
8000556: d400 bmi.n 800055a <__aeabi_fadd+0x86>
|
|
8000558: e095 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
800055a: 1c48 adds r0, r1, #1
|
|
800055c: 29fe cmp r1, #254 @ 0xfe
|
|
800055e: d151 bne.n 8000604 <__aeabi_fadd+0x130>
|
|
8000560: 20ff movs r0, #255 @ 0xff
|
|
8000562: 2300 movs r3, #0
|
|
8000564: 05c0 lsls r0, r0, #23
|
|
8000566: 4318 orrs r0, r3
|
|
8000568: 07e4 lsls r4, r4, #31
|
|
800056a: 4320 orrs r0, r4
|
|
800056c: bcc0 pop {r6, r7}
|
|
800056e: 46b9 mov r9, r7
|
|
8000570: 46b0 mov r8, r6
|
|
8000572: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
8000574: 2900 cmp r1, #0
|
|
8000576: d049 beq.n 800060c <__aeabi_fadd+0x138>
|
|
8000578: 1b99 subs r1, r3, r6
|
|
800057a: 2e00 cmp r6, #0
|
|
800057c: d172 bne.n 8000664 <__aeabi_fadd+0x190>
|
|
800057e: 2d00 cmp r5, #0
|
|
8000580: d100 bne.n 8000584 <__aeabi_fadd+0xb0>
|
|
8000582: e133 b.n 80007ec <__aeabi_fadd+0x318>
|
|
8000584: 1e4c subs r4, r1, #1
|
|
8000586: 2901 cmp r1, #1
|
|
8000588: d100 bne.n 800058c <__aeabi_fadd+0xb8>
|
|
800058a: e159 b.n 8000840 <__aeabi_fadd+0x36c>
|
|
800058c: 29ff cmp r1, #255 @ 0xff
|
|
800058e: d100 bne.n 8000592 <__aeabi_fadd+0xbe>
|
|
8000590: e14c b.n 800082c <__aeabi_fadd+0x358>
|
|
8000592: 0021 movs r1, r4
|
|
8000594: e06c b.n 8000670 <__aeabi_fadd+0x19c>
|
|
8000596: 2900 cmp r1, #0
|
|
8000598: dc00 bgt.n 800059c <__aeabi_fadd+0xc8>
|
|
800059a: e081 b.n 80006a0 <__aeabi_fadd+0x1cc>
|
|
800059c: 2b00 cmp r3, #0
|
|
800059e: d155 bne.n 800064c <__aeabi_fadd+0x178>
|
|
80005a0: 2a00 cmp r2, #0
|
|
80005a2: d070 beq.n 8000686 <__aeabi_fadd+0x1b2>
|
|
80005a4: 1e4b subs r3, r1, #1
|
|
80005a6: 2901 cmp r1, #1
|
|
80005a8: d100 bne.n 80005ac <__aeabi_fadd+0xd8>
|
|
80005aa: e12b b.n 8000804 <__aeabi_fadd+0x330>
|
|
80005ac: 29ff cmp r1, #255 @ 0xff
|
|
80005ae: d06d beq.n 800068c <__aeabi_fadd+0x1b8>
|
|
80005b0: 2b1b cmp r3, #27
|
|
80005b2: dc50 bgt.n 8000656 <__aeabi_fadd+0x182>
|
|
80005b4: 0019 movs r1, r3
|
|
80005b6: 2320 movs r3, #32
|
|
80005b8: 1a5b subs r3, r3, r1
|
|
80005ba: 0010 movs r0, r2
|
|
80005bc: 409a lsls r2, r3
|
|
80005be: 40c8 lsrs r0, r1
|
|
80005c0: 1e53 subs r3, r2, #1
|
|
80005c2: 419a sbcs r2, r3
|
|
80005c4: 4302 orrs r2, r0
|
|
80005c6: 18ad adds r5, r5, r2
|
|
80005c8: 2380 movs r3, #128 @ 0x80
|
|
80005ca: 04db lsls r3, r3, #19
|
|
80005cc: 421d tst r5, r3
|
|
80005ce: d100 bne.n 80005d2 <__aeabi_fadd+0xfe>
|
|
80005d0: e0ad b.n 800072e <__aeabi_fadd+0x25a>
|
|
80005d2: 1c71 adds r1, r6, #1
|
|
80005d4: 2efe cmp r6, #254 @ 0xfe
|
|
80005d6: d0c3 beq.n 8000560 <__aeabi_fadd+0x8c>
|
|
80005d8: 2001 movs r0, #1
|
|
80005da: 086a lsrs r2, r5, #1
|
|
80005dc: 4028 ands r0, r5
|
|
80005de: 4d92 ldr r5, [pc, #584] @ (8000828 <__aeabi_fadd+0x354>)
|
|
80005e0: 4015 ands r5, r2
|
|
80005e2: 4305 orrs r5, r0
|
|
80005e4: 076a lsls r2, r5, #29
|
|
80005e6: d000 beq.n 80005ea <__aeabi_fadd+0x116>
|
|
80005e8: e08b b.n 8000702 <__aeabi_fadd+0x22e>
|
|
80005ea: 421d tst r5, r3
|
|
80005ec: d1b5 bne.n 800055a <__aeabi_fadd+0x86>
|
|
80005ee: 08ef lsrs r7, r5, #3
|
|
80005f0: e034 b.n 800065c <__aeabi_fadd+0x188>
|
|
80005f2: 2a00 cmp r2, #0
|
|
80005f4: d047 beq.n 8000686 <__aeabi_fadd+0x1b2>
|
|
80005f6: 1e4b subs r3, r1, #1
|
|
80005f8: 2901 cmp r1, #1
|
|
80005fa: d066 beq.n 80006ca <__aeabi_fadd+0x1f6>
|
|
80005fc: 29ff cmp r1, #255 @ 0xff
|
|
80005fe: d045 beq.n 800068c <__aeabi_fadd+0x1b8>
|
|
8000600: 0019 movs r1, r3
|
|
8000602: e787 b.n 8000514 <__aeabi_fadd+0x40>
|
|
8000604: b2c0 uxtb r0, r0
|
|
8000606: 01ab lsls r3, r5, #6
|
|
8000608: 0a5b lsrs r3, r3, #9
|
|
800060a: e7ab b.n 8000564 <__aeabi_fadd+0x90>
|
|
800060c: 23fe movs r3, #254 @ 0xfe
|
|
800060e: 469c mov ip, r3
|
|
8000610: 1c70 adds r0, r6, #1
|
|
8000612: 0003 movs r3, r0
|
|
8000614: 4660 mov r0, ip
|
|
8000616: 4218 tst r0, r3
|
|
8000618: d000 beq.n 800061c <__aeabi_fadd+0x148>
|
|
800061a: e092 b.n 8000742 <__aeabi_fadd+0x26e>
|
|
800061c: 2e00 cmp r6, #0
|
|
800061e: d000 beq.n 8000622 <__aeabi_fadd+0x14e>
|
|
8000620: e0e7 b.n 80007f2 <__aeabi_fadd+0x31e>
|
|
8000622: 2d00 cmp r5, #0
|
|
8000624: d100 bne.n 8000628 <__aeabi_fadd+0x154>
|
|
8000626: e119 b.n 800085c <__aeabi_fadd+0x388>
|
|
8000628: 2a00 cmp r2, #0
|
|
800062a: d017 beq.n 800065c <__aeabi_fadd+0x188>
|
|
800062c: 2380 movs r3, #128 @ 0x80
|
|
800062e: 1aaf subs r7, r5, r2
|
|
8000630: 04db lsls r3, r3, #19
|
|
8000632: 421f tst r7, r3
|
|
8000634: d100 bne.n 8000638 <__aeabi_fadd+0x164>
|
|
8000636: e142 b.n 80008be <__aeabi_fadd+0x3ea>
|
|
8000638: 4644 mov r4, r8
|
|
800063a: 1b55 subs r5, r2, r5
|
|
800063c: d100 bne.n 8000640 <__aeabi_fadd+0x16c>
|
|
800063e: e087 b.n 8000750 <__aeabi_fadd+0x27c>
|
|
8000640: 2001 movs r0, #1
|
|
8000642: 421d tst r5, r3
|
|
8000644: d1df bne.n 8000606 <__aeabi_fadd+0x132>
|
|
8000646: 2100 movs r1, #0
|
|
8000648: 08ef lsrs r7, r5, #3
|
|
800064a: e007 b.n 800065c <__aeabi_fadd+0x188>
|
|
800064c: 2eff cmp r6, #255 @ 0xff
|
|
800064e: d01d beq.n 800068c <__aeabi_fadd+0x1b8>
|
|
8000650: 291b cmp r1, #27
|
|
8000652: dc00 bgt.n 8000656 <__aeabi_fadd+0x182>
|
|
8000654: e094 b.n 8000780 <__aeabi_fadd+0x2ac>
|
|
8000656: 0031 movs r1, r6
|
|
8000658: 3505 adds r5, #5
|
|
800065a: 08ef lsrs r7, r5, #3
|
|
800065c: 027b lsls r3, r7, #9
|
|
800065e: 0a5b lsrs r3, r3, #9
|
|
8000660: b2c8 uxtb r0, r1
|
|
8000662: e77f b.n 8000564 <__aeabi_fadd+0x90>
|
|
8000664: 2bff cmp r3, #255 @ 0xff
|
|
8000666: d100 bne.n 800066a <__aeabi_fadd+0x196>
|
|
8000668: e0e0 b.n 800082c <__aeabi_fadd+0x358>
|
|
800066a: 2080 movs r0, #128 @ 0x80
|
|
800066c: 04c0 lsls r0, r0, #19
|
|
800066e: 4305 orrs r5, r0
|
|
8000670: 291b cmp r1, #27
|
|
8000672: dc00 bgt.n 8000676 <__aeabi_fadd+0x1a2>
|
|
8000674: e088 b.n 8000788 <__aeabi_fadd+0x2b4>
|
|
8000676: 1e55 subs r5, r2, #1
|
|
8000678: 4644 mov r4, r8
|
|
800067a: 001e movs r6, r3
|
|
800067c: 0169 lsls r1, r5, #5
|
|
800067e: d500 bpl.n 8000682 <__aeabi_fadd+0x1ae>
|
|
8000680: e74f b.n 8000522 <__aeabi_fadd+0x4e>
|
|
8000682: 0031 movs r1, r6
|
|
8000684: 3504 adds r5, #4
|
|
8000686: 08ef lsrs r7, r5, #3
|
|
8000688: 29ff cmp r1, #255 @ 0xff
|
|
800068a: d1e7 bne.n 800065c <__aeabi_fadd+0x188>
|
|
800068c: 2f00 cmp r7, #0
|
|
800068e: d100 bne.n 8000692 <__aeabi_fadd+0x1be>
|
|
8000690: e766 b.n 8000560 <__aeabi_fadd+0x8c>
|
|
8000692: 2380 movs r3, #128 @ 0x80
|
|
8000694: 03db lsls r3, r3, #15
|
|
8000696: 433b orrs r3, r7
|
|
8000698: 025b lsls r3, r3, #9
|
|
800069a: 20ff movs r0, #255 @ 0xff
|
|
800069c: 0a5b lsrs r3, r3, #9
|
|
800069e: e761 b.n 8000564 <__aeabi_fadd+0x90>
|
|
80006a0: 2900 cmp r1, #0
|
|
80006a2: d058 beq.n 8000756 <__aeabi_fadd+0x282>
|
|
80006a4: 1b99 subs r1, r3, r6
|
|
80006a6: 2e00 cmp r6, #0
|
|
80006a8: d000 beq.n 80006ac <__aeabi_fadd+0x1d8>
|
|
80006aa: e089 b.n 80007c0 <__aeabi_fadd+0x2ec>
|
|
80006ac: 2d00 cmp r5, #0
|
|
80006ae: d100 bne.n 80006b2 <__aeabi_fadd+0x1de>
|
|
80006b0: e09d b.n 80007ee <__aeabi_fadd+0x31a>
|
|
80006b2: 1e4e subs r6, r1, #1
|
|
80006b4: 2901 cmp r1, #1
|
|
80006b6: d100 bne.n 80006ba <__aeabi_fadd+0x1e6>
|
|
80006b8: e0a4 b.n 8000804 <__aeabi_fadd+0x330>
|
|
80006ba: 29ff cmp r1, #255 @ 0xff
|
|
80006bc: d100 bne.n 80006c0 <__aeabi_fadd+0x1ec>
|
|
80006be: e0b6 b.n 800082e <__aeabi_fadd+0x35a>
|
|
80006c0: 2e1b cmp r6, #27
|
|
80006c2: dd00 ble.n 80006c6 <__aeabi_fadd+0x1f2>
|
|
80006c4: e0b8 b.n 8000838 <__aeabi_fadd+0x364>
|
|
80006c6: 0031 movs r1, r6
|
|
80006c8: e081 b.n 80007ce <__aeabi_fadd+0x2fa>
|
|
80006ca: 1aaa subs r2, r5, r2
|
|
80006cc: 0153 lsls r3, r2, #5
|
|
80006ce: d400 bmi.n 80006d2 <__aeabi_fadd+0x1fe>
|
|
80006d0: e0af b.n 8000832 <__aeabi_fadd+0x35e>
|
|
80006d2: 0197 lsls r7, r2, #6
|
|
80006d4: 09bf lsrs r7, r7, #6
|
|
80006d6: 0038 movs r0, r7
|
|
80006d8: f001 feca bl 8002470 <__clzsi2>
|
|
80006dc: 003b movs r3, r7
|
|
80006de: 3805 subs r0, #5
|
|
80006e0: 4083 lsls r3, r0
|
|
80006e2: 2601 movs r6, #1
|
|
80006e4: 001d movs r5, r3
|
|
80006e6: 1b81 subs r1, r0, r6
|
|
80006e8: 2020 movs r0, #32
|
|
80006ea: 3101 adds r1, #1
|
|
80006ec: 40cd lsrs r5, r1
|
|
80006ee: 1a41 subs r1, r0, r1
|
|
80006f0: 408b lsls r3, r1
|
|
80006f2: 1e59 subs r1, r3, #1
|
|
80006f4: 418b sbcs r3, r1
|
|
80006f6: 431d orrs r5, r3
|
|
80006f8: d02a beq.n 8000750 <__aeabi_fadd+0x27c>
|
|
80006fa: 2100 movs r1, #0
|
|
80006fc: 076b lsls r3, r5, #29
|
|
80006fe: d100 bne.n 8000702 <__aeabi_fadd+0x22e>
|
|
8000700: e0f0 b.n 80008e4 <__aeabi_fadd+0x410>
|
|
8000702: 230f movs r3, #15
|
|
8000704: 402b ands r3, r5
|
|
8000706: 2b04 cmp r3, #4
|
|
8000708: d000 beq.n 800070c <__aeabi_fadd+0x238>
|
|
800070a: e722 b.n 8000552 <__aeabi_fadd+0x7e>
|
|
800070c: 016b lsls r3, r5, #5
|
|
800070e: d500 bpl.n 8000712 <__aeabi_fadd+0x23e>
|
|
8000710: e723 b.n 800055a <__aeabi_fadd+0x86>
|
|
8000712: 08ef lsrs r7, r5, #3
|
|
8000714: e7a2 b.n 800065c <__aeabi_fadd+0x188>
|
|
8000716: 2320 movs r3, #32
|
|
8000718: 1a5b subs r3, r3, r1
|
|
800071a: 0010 movs r0, r2
|
|
800071c: 409a lsls r2, r3
|
|
800071e: 40c8 lsrs r0, r1
|
|
8000720: 1e53 subs r3, r2, #1
|
|
8000722: 419a sbcs r2, r3
|
|
8000724: 4302 orrs r2, r0
|
|
8000726: 1aad subs r5, r5, r2
|
|
8000728: 016b lsls r3, r5, #5
|
|
800072a: d500 bpl.n 800072e <__aeabi_fadd+0x25a>
|
|
800072c: e6fb b.n 8000526 <__aeabi_fadd+0x52>
|
|
800072e: 076b lsls r3, r5, #29
|
|
8000730: d100 bne.n 8000734 <__aeabi_fadd+0x260>
|
|
8000732: e0d5 b.n 80008e0 <__aeabi_fadd+0x40c>
|
|
8000734: 230f movs r3, #15
|
|
8000736: 0031 movs r1, r6
|
|
8000738: 402b ands r3, r5
|
|
800073a: 2b04 cmp r3, #4
|
|
800073c: d000 beq.n 8000740 <__aeabi_fadd+0x26c>
|
|
800073e: e708 b.n 8000552 <__aeabi_fadd+0x7e>
|
|
8000740: e7a1 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
8000742: 1aaf subs r7, r5, r2
|
|
8000744: 017b lsls r3, r7, #5
|
|
8000746: d44e bmi.n 80007e6 <__aeabi_fadd+0x312>
|
|
8000748: 2f00 cmp r7, #0
|
|
800074a: d000 beq.n 800074e <__aeabi_fadd+0x27a>
|
|
800074c: e6ed b.n 800052a <__aeabi_fadd+0x56>
|
|
800074e: 2400 movs r4, #0
|
|
8000750: 2000 movs r0, #0
|
|
8000752: 2300 movs r3, #0
|
|
8000754: e706 b.n 8000564 <__aeabi_fadd+0x90>
|
|
8000756: 23fe movs r3, #254 @ 0xfe
|
|
8000758: 1c71 adds r1, r6, #1
|
|
800075a: 420b tst r3, r1
|
|
800075c: d121 bne.n 80007a2 <__aeabi_fadd+0x2ce>
|
|
800075e: 2e00 cmp r6, #0
|
|
8000760: d000 beq.n 8000764 <__aeabi_fadd+0x290>
|
|
8000762: e081 b.n 8000868 <__aeabi_fadd+0x394>
|
|
8000764: 2d00 cmp r5, #0
|
|
8000766: d100 bne.n 800076a <__aeabi_fadd+0x296>
|
|
8000768: e09f b.n 80008aa <__aeabi_fadd+0x3d6>
|
|
800076a: 2a00 cmp r2, #0
|
|
800076c: d100 bne.n 8000770 <__aeabi_fadd+0x29c>
|
|
800076e: e0b2 b.n 80008d6 <__aeabi_fadd+0x402>
|
|
8000770: 18ab adds r3, r5, r2
|
|
8000772: 015a lsls r2, r3, #5
|
|
8000774: d400 bmi.n 8000778 <__aeabi_fadd+0x2a4>
|
|
8000776: e0b0 b.n 80008da <__aeabi_fadd+0x406>
|
|
8000778: 019b lsls r3, r3, #6
|
|
800077a: 2001 movs r0, #1
|
|
800077c: 0a5b lsrs r3, r3, #9
|
|
800077e: e6f1 b.n 8000564 <__aeabi_fadd+0x90>
|
|
8000780: 2380 movs r3, #128 @ 0x80
|
|
8000782: 04db lsls r3, r3, #19
|
|
8000784: 431a orrs r2, r3
|
|
8000786: e716 b.n 80005b6 <__aeabi_fadd+0xe2>
|
|
8000788: 2420 movs r4, #32
|
|
800078a: 0028 movs r0, r5
|
|
800078c: 40c8 lsrs r0, r1
|
|
800078e: 1a61 subs r1, r4, r1
|
|
8000790: 408d lsls r5, r1
|
|
8000792: 0029 movs r1, r5
|
|
8000794: 1e4c subs r4, r1, #1
|
|
8000796: 41a1 sbcs r1, r4
|
|
8000798: 4301 orrs r1, r0
|
|
800079a: 4644 mov r4, r8
|
|
800079c: 001e movs r6, r3
|
|
800079e: 1a55 subs r5, r2, r1
|
|
80007a0: e7c2 b.n 8000728 <__aeabi_fadd+0x254>
|
|
80007a2: 29ff cmp r1, #255 @ 0xff
|
|
80007a4: d100 bne.n 80007a8 <__aeabi_fadd+0x2d4>
|
|
80007a6: e6db b.n 8000560 <__aeabi_fadd+0x8c>
|
|
80007a8: 18af adds r7, r5, r2
|
|
80007aa: 087f lsrs r7, r7, #1
|
|
80007ac: 077b lsls r3, r7, #29
|
|
80007ae: d005 beq.n 80007bc <__aeabi_fadd+0x2e8>
|
|
80007b0: 230f movs r3, #15
|
|
80007b2: 1d3d adds r5, r7, #4
|
|
80007b4: 403b ands r3, r7
|
|
80007b6: 2b04 cmp r3, #4
|
|
80007b8: d000 beq.n 80007bc <__aeabi_fadd+0x2e8>
|
|
80007ba: e764 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
80007bc: 08ff lsrs r7, r7, #3
|
|
80007be: e74d b.n 800065c <__aeabi_fadd+0x188>
|
|
80007c0: 2bff cmp r3, #255 @ 0xff
|
|
80007c2: d034 beq.n 800082e <__aeabi_fadd+0x35a>
|
|
80007c4: 291b cmp r1, #27
|
|
80007c6: dc37 bgt.n 8000838 <__aeabi_fadd+0x364>
|
|
80007c8: 2080 movs r0, #128 @ 0x80
|
|
80007ca: 04c0 lsls r0, r0, #19
|
|
80007cc: 4305 orrs r5, r0
|
|
80007ce: 0028 movs r0, r5
|
|
80007d0: 2620 movs r6, #32
|
|
80007d2: 40c8 lsrs r0, r1
|
|
80007d4: 1a71 subs r1, r6, r1
|
|
80007d6: 408d lsls r5, r1
|
|
80007d8: 0029 movs r1, r5
|
|
80007da: 1e4d subs r5, r1, #1
|
|
80007dc: 41a9 sbcs r1, r5
|
|
80007de: 4301 orrs r1, r0
|
|
80007e0: 001e movs r6, r3
|
|
80007e2: 188d adds r5, r1, r2
|
|
80007e4: e6f0 b.n 80005c8 <__aeabi_fadd+0xf4>
|
|
80007e6: 4644 mov r4, r8
|
|
80007e8: 1b57 subs r7, r2, r5
|
|
80007ea: e69e b.n 800052a <__aeabi_fadd+0x56>
|
|
80007ec: 4644 mov r4, r8
|
|
80007ee: 0015 movs r5, r2
|
|
80007f0: e749 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
80007f2: 2d00 cmp r5, #0
|
|
80007f4: d146 bne.n 8000884 <__aeabi_fadd+0x3b0>
|
|
80007f6: 2a00 cmp r2, #0
|
|
80007f8: d166 bne.n 80008c8 <__aeabi_fadd+0x3f4>
|
|
80007fa: 2380 movs r3, #128 @ 0x80
|
|
80007fc: 2400 movs r4, #0
|
|
80007fe: 20ff movs r0, #255 @ 0xff
|
|
8000800: 03db lsls r3, r3, #15
|
|
8000802: e6af b.n 8000564 <__aeabi_fadd+0x90>
|
|
8000804: 18aa adds r2, r5, r2
|
|
8000806: 0153 lsls r3, r2, #5
|
|
8000808: d513 bpl.n 8000832 <__aeabi_fadd+0x35e>
|
|
800080a: 4f07 ldr r7, [pc, #28] @ (8000828 <__aeabi_fadd+0x354>)
|
|
800080c: 0852 lsrs r2, r2, #1
|
|
800080e: 4017 ands r7, r2
|
|
8000810: 0753 lsls r3, r2, #29
|
|
8000812: d044 beq.n 800089e <__aeabi_fadd+0x3ca>
|
|
8000814: 230f movs r3, #15
|
|
8000816: 4013 ands r3, r2
|
|
8000818: 2b04 cmp r3, #4
|
|
800081a: d040 beq.n 800089e <__aeabi_fadd+0x3ca>
|
|
800081c: 2102 movs r1, #2
|
|
800081e: 1d3d adds r5, r7, #4
|
|
8000820: e731 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
8000822: 46c0 nop @ (mov r8, r8)
|
|
8000824: fbffffff .word 0xfbffffff
|
|
8000828: 7dffffff .word 0x7dffffff
|
|
800082c: 4644 mov r4, r8
|
|
800082e: 464f mov r7, r9
|
|
8000830: e72c b.n 800068c <__aeabi_fadd+0x1b8>
|
|
8000832: 2101 movs r1, #1
|
|
8000834: 08d7 lsrs r7, r2, #3
|
|
8000836: e711 b.n 800065c <__aeabi_fadd+0x188>
|
|
8000838: 3205 adds r2, #5
|
|
800083a: 0019 movs r1, r3
|
|
800083c: 08d7 lsrs r7, r2, #3
|
|
800083e: e70d b.n 800065c <__aeabi_fadd+0x188>
|
|
8000840: 1b57 subs r7, r2, r5
|
|
8000842: 017b lsls r3, r7, #5
|
|
8000844: d537 bpl.n 80008b6 <__aeabi_fadd+0x3e2>
|
|
8000846: 01bf lsls r7, r7, #6
|
|
8000848: 09bf lsrs r7, r7, #6
|
|
800084a: 0038 movs r0, r7
|
|
800084c: f001 fe10 bl 8002470 <__clzsi2>
|
|
8000850: 003b movs r3, r7
|
|
8000852: 3805 subs r0, #5
|
|
8000854: 4083 lsls r3, r0
|
|
8000856: 4644 mov r4, r8
|
|
8000858: 3601 adds r6, #1
|
|
800085a: e743 b.n 80006e4 <__aeabi_fadd+0x210>
|
|
800085c: 2a00 cmp r2, #0
|
|
800085e: d100 bne.n 8000862 <__aeabi_fadd+0x38e>
|
|
8000860: e775 b.n 800074e <__aeabi_fadd+0x27a>
|
|
8000862: 4644 mov r4, r8
|
|
8000864: 464f mov r7, r9
|
|
8000866: e6f9 b.n 800065c <__aeabi_fadd+0x188>
|
|
8000868: 2d00 cmp r5, #0
|
|
800086a: d0e0 beq.n 800082e <__aeabi_fadd+0x35a>
|
|
800086c: 2380 movs r3, #128 @ 0x80
|
|
800086e: 03db lsls r3, r3, #15
|
|
8000870: 2a00 cmp r2, #0
|
|
8000872: d017 beq.n 80008a4 <__aeabi_fadd+0x3d0>
|
|
8000874: 429f cmp r7, r3
|
|
8000876: d200 bcs.n 800087a <__aeabi_fadd+0x3a6>
|
|
8000878: e70b b.n 8000692 <__aeabi_fadd+0x1be>
|
|
800087a: 4599 cmp r9, r3
|
|
800087c: d300 bcc.n 8000880 <__aeabi_fadd+0x3ac>
|
|
800087e: e708 b.n 8000692 <__aeabi_fadd+0x1be>
|
|
8000880: 464f mov r7, r9
|
|
8000882: e706 b.n 8000692 <__aeabi_fadd+0x1be>
|
|
8000884: 2380 movs r3, #128 @ 0x80
|
|
8000886: 03db lsls r3, r3, #15
|
|
8000888: 2a00 cmp r2, #0
|
|
800088a: d00b beq.n 80008a4 <__aeabi_fadd+0x3d0>
|
|
800088c: 429f cmp r7, r3
|
|
800088e: d200 bcs.n 8000892 <__aeabi_fadd+0x3be>
|
|
8000890: e6ff b.n 8000692 <__aeabi_fadd+0x1be>
|
|
8000892: 4599 cmp r9, r3
|
|
8000894: d300 bcc.n 8000898 <__aeabi_fadd+0x3c4>
|
|
8000896: e6fc b.n 8000692 <__aeabi_fadd+0x1be>
|
|
8000898: 4644 mov r4, r8
|
|
800089a: 464f mov r7, r9
|
|
800089c: e6f9 b.n 8000692 <__aeabi_fadd+0x1be>
|
|
800089e: 2102 movs r1, #2
|
|
80008a0: 08ff lsrs r7, r7, #3
|
|
80008a2: e6db b.n 800065c <__aeabi_fadd+0x188>
|
|
80008a4: 20ff movs r0, #255 @ 0xff
|
|
80008a6: 433b orrs r3, r7
|
|
80008a8: e65c b.n 8000564 <__aeabi_fadd+0x90>
|
|
80008aa: 2a00 cmp r2, #0
|
|
80008ac: d100 bne.n 80008b0 <__aeabi_fadd+0x3dc>
|
|
80008ae: e74f b.n 8000750 <__aeabi_fadd+0x27c>
|
|
80008b0: 2100 movs r1, #0
|
|
80008b2: 08d7 lsrs r7, r2, #3
|
|
80008b4: e6d2 b.n 800065c <__aeabi_fadd+0x188>
|
|
80008b6: 4644 mov r4, r8
|
|
80008b8: 2101 movs r1, #1
|
|
80008ba: 08ff lsrs r7, r7, #3
|
|
80008bc: e6ce b.n 800065c <__aeabi_fadd+0x188>
|
|
80008be: 2f00 cmp r7, #0
|
|
80008c0: d000 beq.n 80008c4 <__aeabi_fadd+0x3f0>
|
|
80008c2: e77b b.n 80007bc <__aeabi_fadd+0x2e8>
|
|
80008c4: 2400 movs r4, #0
|
|
80008c6: e743 b.n 8000750 <__aeabi_fadd+0x27c>
|
|
80008c8: 2380 movs r3, #128 @ 0x80
|
|
80008ca: 464a mov r2, r9
|
|
80008cc: 03db lsls r3, r3, #15
|
|
80008ce: 4644 mov r4, r8
|
|
80008d0: 20ff movs r0, #255 @ 0xff
|
|
80008d2: 4313 orrs r3, r2
|
|
80008d4: e646 b.n 8000564 <__aeabi_fadd+0x90>
|
|
80008d6: 2100 movs r1, #0
|
|
80008d8: e6c0 b.n 800065c <__aeabi_fadd+0x188>
|
|
80008da: 2100 movs r1, #0
|
|
80008dc: 08df lsrs r7, r3, #3
|
|
80008de: e6bd b.n 800065c <__aeabi_fadd+0x188>
|
|
80008e0: 0031 movs r1, r6
|
|
80008e2: e6d0 b.n 8000686 <__aeabi_fadd+0x1b2>
|
|
80008e4: 2001 movs r0, #1
|
|
80008e6: 016a lsls r2, r5, #5
|
|
80008e8: d500 bpl.n 80008ec <__aeabi_fadd+0x418>
|
|
80008ea: e68b b.n 8000604 <__aeabi_fadd+0x130>
|
|
80008ec: 002a movs r2, r5
|
|
80008ee: e7df b.n 80008b0 <__aeabi_fadd+0x3dc>
|
|
|
|
080008f0 <__aeabi_fdiv>:
|
|
80008f0: b5f0 push {r4, r5, r6, r7, lr}
|
|
80008f2: 4646 mov r6, r8
|
|
80008f4: 464f mov r7, r9
|
|
80008f6: 46d6 mov lr, sl
|
|
80008f8: 0245 lsls r5, r0, #9
|
|
80008fa: b5c0 push {r6, r7, lr}
|
|
80008fc: 0fc3 lsrs r3, r0, #31
|
|
80008fe: 0047 lsls r7, r0, #1
|
|
8000900: 4698 mov r8, r3
|
|
8000902: 1c0e adds r6, r1, #0
|
|
8000904: 0a6d lsrs r5, r5, #9
|
|
8000906: 0e3f lsrs r7, r7, #24
|
|
8000908: d05b beq.n 80009c2 <__aeabi_fdiv+0xd2>
|
|
800090a: 2fff cmp r7, #255 @ 0xff
|
|
800090c: d021 beq.n 8000952 <__aeabi_fdiv+0x62>
|
|
800090e: 2380 movs r3, #128 @ 0x80
|
|
8000910: 00ed lsls r5, r5, #3
|
|
8000912: 04db lsls r3, r3, #19
|
|
8000914: 431d orrs r5, r3
|
|
8000916: 2300 movs r3, #0
|
|
8000918: 4699 mov r9, r3
|
|
800091a: 469a mov sl, r3
|
|
800091c: 3f7f subs r7, #127 @ 0x7f
|
|
800091e: 0274 lsls r4, r6, #9
|
|
8000920: 0073 lsls r3, r6, #1
|
|
8000922: 0a64 lsrs r4, r4, #9
|
|
8000924: 0e1b lsrs r3, r3, #24
|
|
8000926: 0ff6 lsrs r6, r6, #31
|
|
8000928: 2b00 cmp r3, #0
|
|
800092a: d020 beq.n 800096e <__aeabi_fdiv+0x7e>
|
|
800092c: 2bff cmp r3, #255 @ 0xff
|
|
800092e: d043 beq.n 80009b8 <__aeabi_fdiv+0xc8>
|
|
8000930: 2280 movs r2, #128 @ 0x80
|
|
8000932: 2000 movs r0, #0
|
|
8000934: 00e4 lsls r4, r4, #3
|
|
8000936: 04d2 lsls r2, r2, #19
|
|
8000938: 4314 orrs r4, r2
|
|
800093a: 3b7f subs r3, #127 @ 0x7f
|
|
800093c: 4642 mov r2, r8
|
|
800093e: 1aff subs r7, r7, r3
|
|
8000940: 464b mov r3, r9
|
|
8000942: 4072 eors r2, r6
|
|
8000944: 2b0f cmp r3, #15
|
|
8000946: d900 bls.n 800094a <__aeabi_fdiv+0x5a>
|
|
8000948: e09d b.n 8000a86 <__aeabi_fdiv+0x196>
|
|
800094a: 4971 ldr r1, [pc, #452] @ (8000b10 <__aeabi_fdiv+0x220>)
|
|
800094c: 009b lsls r3, r3, #2
|
|
800094e: 58cb ldr r3, [r1, r3]
|
|
8000950: 469f mov pc, r3
|
|
8000952: 2d00 cmp r5, #0
|
|
8000954: d15a bne.n 8000a0c <__aeabi_fdiv+0x11c>
|
|
8000956: 2308 movs r3, #8
|
|
8000958: 4699 mov r9, r3
|
|
800095a: 3b06 subs r3, #6
|
|
800095c: 0274 lsls r4, r6, #9
|
|
800095e: 469a mov sl, r3
|
|
8000960: 0073 lsls r3, r6, #1
|
|
8000962: 27ff movs r7, #255 @ 0xff
|
|
8000964: 0a64 lsrs r4, r4, #9
|
|
8000966: 0e1b lsrs r3, r3, #24
|
|
8000968: 0ff6 lsrs r6, r6, #31
|
|
800096a: 2b00 cmp r3, #0
|
|
800096c: d1de bne.n 800092c <__aeabi_fdiv+0x3c>
|
|
800096e: 2c00 cmp r4, #0
|
|
8000970: d13b bne.n 80009ea <__aeabi_fdiv+0xfa>
|
|
8000972: 2301 movs r3, #1
|
|
8000974: 4642 mov r2, r8
|
|
8000976: 4649 mov r1, r9
|
|
8000978: 4072 eors r2, r6
|
|
800097a: 4319 orrs r1, r3
|
|
800097c: 290e cmp r1, #14
|
|
800097e: d818 bhi.n 80009b2 <__aeabi_fdiv+0xc2>
|
|
8000980: 4864 ldr r0, [pc, #400] @ (8000b14 <__aeabi_fdiv+0x224>)
|
|
8000982: 0089 lsls r1, r1, #2
|
|
8000984: 5841 ldr r1, [r0, r1]
|
|
8000986: 468f mov pc, r1
|
|
8000988: 4653 mov r3, sl
|
|
800098a: 2b02 cmp r3, #2
|
|
800098c: d100 bne.n 8000990 <__aeabi_fdiv+0xa0>
|
|
800098e: e0b8 b.n 8000b02 <__aeabi_fdiv+0x212>
|
|
8000990: 2b03 cmp r3, #3
|
|
8000992: d06e beq.n 8000a72 <__aeabi_fdiv+0x182>
|
|
8000994: 4642 mov r2, r8
|
|
8000996: 002c movs r4, r5
|
|
8000998: 2b01 cmp r3, #1
|
|
800099a: d140 bne.n 8000a1e <__aeabi_fdiv+0x12e>
|
|
800099c: 2000 movs r0, #0
|
|
800099e: 2400 movs r4, #0
|
|
80009a0: 05c0 lsls r0, r0, #23
|
|
80009a2: 4320 orrs r0, r4
|
|
80009a4: 07d2 lsls r2, r2, #31
|
|
80009a6: 4310 orrs r0, r2
|
|
80009a8: bce0 pop {r5, r6, r7}
|
|
80009aa: 46ba mov sl, r7
|
|
80009ac: 46b1 mov r9, r6
|
|
80009ae: 46a8 mov r8, r5
|
|
80009b0: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80009b2: 20ff movs r0, #255 @ 0xff
|
|
80009b4: 2400 movs r4, #0
|
|
80009b6: e7f3 b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
80009b8: 2c00 cmp r4, #0
|
|
80009ba: d120 bne.n 80009fe <__aeabi_fdiv+0x10e>
|
|
80009bc: 2302 movs r3, #2
|
|
80009be: 3fff subs r7, #255 @ 0xff
|
|
80009c0: e7d8 b.n 8000974 <__aeabi_fdiv+0x84>
|
|
80009c2: 2d00 cmp r5, #0
|
|
80009c4: d105 bne.n 80009d2 <__aeabi_fdiv+0xe2>
|
|
80009c6: 2304 movs r3, #4
|
|
80009c8: 4699 mov r9, r3
|
|
80009ca: 3b03 subs r3, #3
|
|
80009cc: 2700 movs r7, #0
|
|
80009ce: 469a mov sl, r3
|
|
80009d0: e7a5 b.n 800091e <__aeabi_fdiv+0x2e>
|
|
80009d2: 0028 movs r0, r5
|
|
80009d4: f001 fd4c bl 8002470 <__clzsi2>
|
|
80009d8: 2776 movs r7, #118 @ 0x76
|
|
80009da: 1f43 subs r3, r0, #5
|
|
80009dc: 409d lsls r5, r3
|
|
80009de: 2300 movs r3, #0
|
|
80009e0: 427f negs r7, r7
|
|
80009e2: 4699 mov r9, r3
|
|
80009e4: 469a mov sl, r3
|
|
80009e6: 1a3f subs r7, r7, r0
|
|
80009e8: e799 b.n 800091e <__aeabi_fdiv+0x2e>
|
|
80009ea: 0020 movs r0, r4
|
|
80009ec: f001 fd40 bl 8002470 <__clzsi2>
|
|
80009f0: 1f43 subs r3, r0, #5
|
|
80009f2: 409c lsls r4, r3
|
|
80009f4: 2376 movs r3, #118 @ 0x76
|
|
80009f6: 425b negs r3, r3
|
|
80009f8: 1a1b subs r3, r3, r0
|
|
80009fa: 2000 movs r0, #0
|
|
80009fc: e79e b.n 800093c <__aeabi_fdiv+0x4c>
|
|
80009fe: 2303 movs r3, #3
|
|
8000a00: 464a mov r2, r9
|
|
8000a02: 431a orrs r2, r3
|
|
8000a04: 4691 mov r9, r2
|
|
8000a06: 2003 movs r0, #3
|
|
8000a08: 33fc adds r3, #252 @ 0xfc
|
|
8000a0a: e797 b.n 800093c <__aeabi_fdiv+0x4c>
|
|
8000a0c: 230c movs r3, #12
|
|
8000a0e: 4699 mov r9, r3
|
|
8000a10: 3b09 subs r3, #9
|
|
8000a12: 27ff movs r7, #255 @ 0xff
|
|
8000a14: 469a mov sl, r3
|
|
8000a16: e782 b.n 800091e <__aeabi_fdiv+0x2e>
|
|
8000a18: 2803 cmp r0, #3
|
|
8000a1a: d02c beq.n 8000a76 <__aeabi_fdiv+0x186>
|
|
8000a1c: 0032 movs r2, r6
|
|
8000a1e: 0038 movs r0, r7
|
|
8000a20: 307f adds r0, #127 @ 0x7f
|
|
8000a22: 2800 cmp r0, #0
|
|
8000a24: dd47 ble.n 8000ab6 <__aeabi_fdiv+0x1c6>
|
|
8000a26: 0763 lsls r3, r4, #29
|
|
8000a28: d004 beq.n 8000a34 <__aeabi_fdiv+0x144>
|
|
8000a2a: 230f movs r3, #15
|
|
8000a2c: 4023 ands r3, r4
|
|
8000a2e: 2b04 cmp r3, #4
|
|
8000a30: d000 beq.n 8000a34 <__aeabi_fdiv+0x144>
|
|
8000a32: 3404 adds r4, #4
|
|
8000a34: 0123 lsls r3, r4, #4
|
|
8000a36: d503 bpl.n 8000a40 <__aeabi_fdiv+0x150>
|
|
8000a38: 0038 movs r0, r7
|
|
8000a3a: 4b37 ldr r3, [pc, #220] @ (8000b18 <__aeabi_fdiv+0x228>)
|
|
8000a3c: 3080 adds r0, #128 @ 0x80
|
|
8000a3e: 401c ands r4, r3
|
|
8000a40: 28fe cmp r0, #254 @ 0xfe
|
|
8000a42: dcb6 bgt.n 80009b2 <__aeabi_fdiv+0xc2>
|
|
8000a44: 01a4 lsls r4, r4, #6
|
|
8000a46: 0a64 lsrs r4, r4, #9
|
|
8000a48: b2c0 uxtb r0, r0
|
|
8000a4a: e7a9 b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000a4c: 2480 movs r4, #128 @ 0x80
|
|
8000a4e: 2200 movs r2, #0
|
|
8000a50: 20ff movs r0, #255 @ 0xff
|
|
8000a52: 03e4 lsls r4, r4, #15
|
|
8000a54: e7a4 b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000a56: 2380 movs r3, #128 @ 0x80
|
|
8000a58: 03db lsls r3, r3, #15
|
|
8000a5a: 421d tst r5, r3
|
|
8000a5c: d001 beq.n 8000a62 <__aeabi_fdiv+0x172>
|
|
8000a5e: 421c tst r4, r3
|
|
8000a60: d00b beq.n 8000a7a <__aeabi_fdiv+0x18a>
|
|
8000a62: 2480 movs r4, #128 @ 0x80
|
|
8000a64: 03e4 lsls r4, r4, #15
|
|
8000a66: 432c orrs r4, r5
|
|
8000a68: 0264 lsls r4, r4, #9
|
|
8000a6a: 4642 mov r2, r8
|
|
8000a6c: 20ff movs r0, #255 @ 0xff
|
|
8000a6e: 0a64 lsrs r4, r4, #9
|
|
8000a70: e796 b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000a72: 4646 mov r6, r8
|
|
8000a74: 002c movs r4, r5
|
|
8000a76: 2380 movs r3, #128 @ 0x80
|
|
8000a78: 03db lsls r3, r3, #15
|
|
8000a7a: 431c orrs r4, r3
|
|
8000a7c: 0264 lsls r4, r4, #9
|
|
8000a7e: 0032 movs r2, r6
|
|
8000a80: 20ff movs r0, #255 @ 0xff
|
|
8000a82: 0a64 lsrs r4, r4, #9
|
|
8000a84: e78c b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000a86: 016d lsls r5, r5, #5
|
|
8000a88: 0160 lsls r0, r4, #5
|
|
8000a8a: 4285 cmp r5, r0
|
|
8000a8c: d22d bcs.n 8000aea <__aeabi_fdiv+0x1fa>
|
|
8000a8e: 231b movs r3, #27
|
|
8000a90: 2400 movs r4, #0
|
|
8000a92: 3f01 subs r7, #1
|
|
8000a94: 2601 movs r6, #1
|
|
8000a96: 0029 movs r1, r5
|
|
8000a98: 0064 lsls r4, r4, #1
|
|
8000a9a: 006d lsls r5, r5, #1
|
|
8000a9c: 2900 cmp r1, #0
|
|
8000a9e: db01 blt.n 8000aa4 <__aeabi_fdiv+0x1b4>
|
|
8000aa0: 4285 cmp r5, r0
|
|
8000aa2: d301 bcc.n 8000aa8 <__aeabi_fdiv+0x1b8>
|
|
8000aa4: 1a2d subs r5, r5, r0
|
|
8000aa6: 4334 orrs r4, r6
|
|
8000aa8: 3b01 subs r3, #1
|
|
8000aaa: 2b00 cmp r3, #0
|
|
8000aac: d1f3 bne.n 8000a96 <__aeabi_fdiv+0x1a6>
|
|
8000aae: 1e6b subs r3, r5, #1
|
|
8000ab0: 419d sbcs r5, r3
|
|
8000ab2: 432c orrs r4, r5
|
|
8000ab4: e7b3 b.n 8000a1e <__aeabi_fdiv+0x12e>
|
|
8000ab6: 2301 movs r3, #1
|
|
8000ab8: 1a1b subs r3, r3, r0
|
|
8000aba: 2b1b cmp r3, #27
|
|
8000abc: dd00 ble.n 8000ac0 <__aeabi_fdiv+0x1d0>
|
|
8000abe: e76d b.n 800099c <__aeabi_fdiv+0xac>
|
|
8000ac0: 0021 movs r1, r4
|
|
8000ac2: 379e adds r7, #158 @ 0x9e
|
|
8000ac4: 40d9 lsrs r1, r3
|
|
8000ac6: 40bc lsls r4, r7
|
|
8000ac8: 000b movs r3, r1
|
|
8000aca: 1e61 subs r1, r4, #1
|
|
8000acc: 418c sbcs r4, r1
|
|
8000ace: 4323 orrs r3, r4
|
|
8000ad0: 0759 lsls r1, r3, #29
|
|
8000ad2: d004 beq.n 8000ade <__aeabi_fdiv+0x1ee>
|
|
8000ad4: 210f movs r1, #15
|
|
8000ad6: 4019 ands r1, r3
|
|
8000ad8: 2904 cmp r1, #4
|
|
8000ada: d000 beq.n 8000ade <__aeabi_fdiv+0x1ee>
|
|
8000adc: 3304 adds r3, #4
|
|
8000ade: 0159 lsls r1, r3, #5
|
|
8000ae0: d413 bmi.n 8000b0a <__aeabi_fdiv+0x21a>
|
|
8000ae2: 019b lsls r3, r3, #6
|
|
8000ae4: 2000 movs r0, #0
|
|
8000ae6: 0a5c lsrs r4, r3, #9
|
|
8000ae8: e75a b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000aea: 231a movs r3, #26
|
|
8000aec: 2401 movs r4, #1
|
|
8000aee: 1a2d subs r5, r5, r0
|
|
8000af0: e7d0 b.n 8000a94 <__aeabi_fdiv+0x1a4>
|
|
8000af2: 1e98 subs r0, r3, #2
|
|
8000af4: 4243 negs r3, r0
|
|
8000af6: 4158 adcs r0, r3
|
|
8000af8: 4240 negs r0, r0
|
|
8000afa: 0032 movs r2, r6
|
|
8000afc: 2400 movs r4, #0
|
|
8000afe: b2c0 uxtb r0, r0
|
|
8000b00: e74e b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000b02: 4642 mov r2, r8
|
|
8000b04: 20ff movs r0, #255 @ 0xff
|
|
8000b06: 2400 movs r4, #0
|
|
8000b08: e74a b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000b0a: 2001 movs r0, #1
|
|
8000b0c: 2400 movs r4, #0
|
|
8000b0e: e747 b.n 80009a0 <__aeabi_fdiv+0xb0>
|
|
8000b10: 080089b4 .word 0x080089b4
|
|
8000b14: 080089f4 .word 0x080089f4
|
|
8000b18: f7ffffff .word 0xf7ffffff
|
|
|
|
08000b1c <__eqsf2>:
|
|
8000b1c: b570 push {r4, r5, r6, lr}
|
|
8000b1e: 0042 lsls r2, r0, #1
|
|
8000b20: 024e lsls r6, r1, #9
|
|
8000b22: 004c lsls r4, r1, #1
|
|
8000b24: 0245 lsls r5, r0, #9
|
|
8000b26: 0a6d lsrs r5, r5, #9
|
|
8000b28: 0e12 lsrs r2, r2, #24
|
|
8000b2a: 0fc3 lsrs r3, r0, #31
|
|
8000b2c: 0a76 lsrs r6, r6, #9
|
|
8000b2e: 0e24 lsrs r4, r4, #24
|
|
8000b30: 0fc9 lsrs r1, r1, #31
|
|
8000b32: 2aff cmp r2, #255 @ 0xff
|
|
8000b34: d010 beq.n 8000b58 <__eqsf2+0x3c>
|
|
8000b36: 2cff cmp r4, #255 @ 0xff
|
|
8000b38: d00c beq.n 8000b54 <__eqsf2+0x38>
|
|
8000b3a: 2001 movs r0, #1
|
|
8000b3c: 42a2 cmp r2, r4
|
|
8000b3e: d10a bne.n 8000b56 <__eqsf2+0x3a>
|
|
8000b40: 42b5 cmp r5, r6
|
|
8000b42: d108 bne.n 8000b56 <__eqsf2+0x3a>
|
|
8000b44: 428b cmp r3, r1
|
|
8000b46: d00f beq.n 8000b68 <__eqsf2+0x4c>
|
|
8000b48: 2a00 cmp r2, #0
|
|
8000b4a: d104 bne.n 8000b56 <__eqsf2+0x3a>
|
|
8000b4c: 0028 movs r0, r5
|
|
8000b4e: 1e43 subs r3, r0, #1
|
|
8000b50: 4198 sbcs r0, r3
|
|
8000b52: e000 b.n 8000b56 <__eqsf2+0x3a>
|
|
8000b54: 2001 movs r0, #1
|
|
8000b56: bd70 pop {r4, r5, r6, pc}
|
|
8000b58: 2001 movs r0, #1
|
|
8000b5a: 2cff cmp r4, #255 @ 0xff
|
|
8000b5c: d1fb bne.n 8000b56 <__eqsf2+0x3a>
|
|
8000b5e: 4335 orrs r5, r6
|
|
8000b60: d1f9 bne.n 8000b56 <__eqsf2+0x3a>
|
|
8000b62: 404b eors r3, r1
|
|
8000b64: 0018 movs r0, r3
|
|
8000b66: e7f6 b.n 8000b56 <__eqsf2+0x3a>
|
|
8000b68: 2000 movs r0, #0
|
|
8000b6a: e7f4 b.n 8000b56 <__eqsf2+0x3a>
|
|
|
|
08000b6c <__gesf2>:
|
|
8000b6c: b530 push {r4, r5, lr}
|
|
8000b6e: 0042 lsls r2, r0, #1
|
|
8000b70: 0244 lsls r4, r0, #9
|
|
8000b72: 024d lsls r5, r1, #9
|
|
8000b74: 0fc3 lsrs r3, r0, #31
|
|
8000b76: 0048 lsls r0, r1, #1
|
|
8000b78: 0a64 lsrs r4, r4, #9
|
|
8000b7a: 0e12 lsrs r2, r2, #24
|
|
8000b7c: 0a6d lsrs r5, r5, #9
|
|
8000b7e: 0e00 lsrs r0, r0, #24
|
|
8000b80: 0fc9 lsrs r1, r1, #31
|
|
8000b82: 2aff cmp r2, #255 @ 0xff
|
|
8000b84: d018 beq.n 8000bb8 <__gesf2+0x4c>
|
|
8000b86: 28ff cmp r0, #255 @ 0xff
|
|
8000b88: d00a beq.n 8000ba0 <__gesf2+0x34>
|
|
8000b8a: 2a00 cmp r2, #0
|
|
8000b8c: d11e bne.n 8000bcc <__gesf2+0x60>
|
|
8000b8e: 2800 cmp r0, #0
|
|
8000b90: d10a bne.n 8000ba8 <__gesf2+0x3c>
|
|
8000b92: 2d00 cmp r5, #0
|
|
8000b94: d029 beq.n 8000bea <__gesf2+0x7e>
|
|
8000b96: 2c00 cmp r4, #0
|
|
8000b98: d12d bne.n 8000bf6 <__gesf2+0x8a>
|
|
8000b9a: 0048 lsls r0, r1, #1
|
|
8000b9c: 3801 subs r0, #1
|
|
8000b9e: bd30 pop {r4, r5, pc}
|
|
8000ba0: 2d00 cmp r5, #0
|
|
8000ba2: d125 bne.n 8000bf0 <__gesf2+0x84>
|
|
8000ba4: 2a00 cmp r2, #0
|
|
8000ba6: d101 bne.n 8000bac <__gesf2+0x40>
|
|
8000ba8: 2c00 cmp r4, #0
|
|
8000baa: d0f6 beq.n 8000b9a <__gesf2+0x2e>
|
|
8000bac: 428b cmp r3, r1
|
|
8000bae: d019 beq.n 8000be4 <__gesf2+0x78>
|
|
8000bb0: 2001 movs r0, #1
|
|
8000bb2: 425b negs r3, r3
|
|
8000bb4: 4318 orrs r0, r3
|
|
8000bb6: e7f2 b.n 8000b9e <__gesf2+0x32>
|
|
8000bb8: 2c00 cmp r4, #0
|
|
8000bba: d119 bne.n 8000bf0 <__gesf2+0x84>
|
|
8000bbc: 28ff cmp r0, #255 @ 0xff
|
|
8000bbe: d1f7 bne.n 8000bb0 <__gesf2+0x44>
|
|
8000bc0: 2d00 cmp r5, #0
|
|
8000bc2: d115 bne.n 8000bf0 <__gesf2+0x84>
|
|
8000bc4: 2000 movs r0, #0
|
|
8000bc6: 428b cmp r3, r1
|
|
8000bc8: d1f2 bne.n 8000bb0 <__gesf2+0x44>
|
|
8000bca: e7e8 b.n 8000b9e <__gesf2+0x32>
|
|
8000bcc: 2800 cmp r0, #0
|
|
8000bce: d0ef beq.n 8000bb0 <__gesf2+0x44>
|
|
8000bd0: 428b cmp r3, r1
|
|
8000bd2: d1ed bne.n 8000bb0 <__gesf2+0x44>
|
|
8000bd4: 4282 cmp r2, r0
|
|
8000bd6: dceb bgt.n 8000bb0 <__gesf2+0x44>
|
|
8000bd8: db04 blt.n 8000be4 <__gesf2+0x78>
|
|
8000bda: 42ac cmp r4, r5
|
|
8000bdc: d8e8 bhi.n 8000bb0 <__gesf2+0x44>
|
|
8000bde: 2000 movs r0, #0
|
|
8000be0: 42ac cmp r4, r5
|
|
8000be2: d2dc bcs.n 8000b9e <__gesf2+0x32>
|
|
8000be4: 0058 lsls r0, r3, #1
|
|
8000be6: 3801 subs r0, #1
|
|
8000be8: e7d9 b.n 8000b9e <__gesf2+0x32>
|
|
8000bea: 2c00 cmp r4, #0
|
|
8000bec: d0d7 beq.n 8000b9e <__gesf2+0x32>
|
|
8000bee: e7df b.n 8000bb0 <__gesf2+0x44>
|
|
8000bf0: 2002 movs r0, #2
|
|
8000bf2: 4240 negs r0, r0
|
|
8000bf4: e7d3 b.n 8000b9e <__gesf2+0x32>
|
|
8000bf6: 428b cmp r3, r1
|
|
8000bf8: d1da bne.n 8000bb0 <__gesf2+0x44>
|
|
8000bfa: e7ee b.n 8000bda <__gesf2+0x6e>
|
|
|
|
08000bfc <__lesf2>:
|
|
8000bfc: b530 push {r4, r5, lr}
|
|
8000bfe: 0042 lsls r2, r0, #1
|
|
8000c00: 0244 lsls r4, r0, #9
|
|
8000c02: 024d lsls r5, r1, #9
|
|
8000c04: 0fc3 lsrs r3, r0, #31
|
|
8000c06: 0048 lsls r0, r1, #1
|
|
8000c08: 0a64 lsrs r4, r4, #9
|
|
8000c0a: 0e12 lsrs r2, r2, #24
|
|
8000c0c: 0a6d lsrs r5, r5, #9
|
|
8000c0e: 0e00 lsrs r0, r0, #24
|
|
8000c10: 0fc9 lsrs r1, r1, #31
|
|
8000c12: 2aff cmp r2, #255 @ 0xff
|
|
8000c14: d017 beq.n 8000c46 <__lesf2+0x4a>
|
|
8000c16: 28ff cmp r0, #255 @ 0xff
|
|
8000c18: d00a beq.n 8000c30 <__lesf2+0x34>
|
|
8000c1a: 2a00 cmp r2, #0
|
|
8000c1c: d11b bne.n 8000c56 <__lesf2+0x5a>
|
|
8000c1e: 2800 cmp r0, #0
|
|
8000c20: d10a bne.n 8000c38 <__lesf2+0x3c>
|
|
8000c22: 2d00 cmp r5, #0
|
|
8000c24: d01d beq.n 8000c62 <__lesf2+0x66>
|
|
8000c26: 2c00 cmp r4, #0
|
|
8000c28: d12d bne.n 8000c86 <__lesf2+0x8a>
|
|
8000c2a: 0048 lsls r0, r1, #1
|
|
8000c2c: 3801 subs r0, #1
|
|
8000c2e: e011 b.n 8000c54 <__lesf2+0x58>
|
|
8000c30: 2d00 cmp r5, #0
|
|
8000c32: d10e bne.n 8000c52 <__lesf2+0x56>
|
|
8000c34: 2a00 cmp r2, #0
|
|
8000c36: d101 bne.n 8000c3c <__lesf2+0x40>
|
|
8000c38: 2c00 cmp r4, #0
|
|
8000c3a: d0f6 beq.n 8000c2a <__lesf2+0x2e>
|
|
8000c3c: 428b cmp r3, r1
|
|
8000c3e: d10c bne.n 8000c5a <__lesf2+0x5e>
|
|
8000c40: 0058 lsls r0, r3, #1
|
|
8000c42: 3801 subs r0, #1
|
|
8000c44: e006 b.n 8000c54 <__lesf2+0x58>
|
|
8000c46: 2c00 cmp r4, #0
|
|
8000c48: d103 bne.n 8000c52 <__lesf2+0x56>
|
|
8000c4a: 28ff cmp r0, #255 @ 0xff
|
|
8000c4c: d105 bne.n 8000c5a <__lesf2+0x5e>
|
|
8000c4e: 2d00 cmp r5, #0
|
|
8000c50: d015 beq.n 8000c7e <__lesf2+0x82>
|
|
8000c52: 2002 movs r0, #2
|
|
8000c54: bd30 pop {r4, r5, pc}
|
|
8000c56: 2800 cmp r0, #0
|
|
8000c58: d106 bne.n 8000c68 <__lesf2+0x6c>
|
|
8000c5a: 2001 movs r0, #1
|
|
8000c5c: 425b negs r3, r3
|
|
8000c5e: 4318 orrs r0, r3
|
|
8000c60: e7f8 b.n 8000c54 <__lesf2+0x58>
|
|
8000c62: 2c00 cmp r4, #0
|
|
8000c64: d0f6 beq.n 8000c54 <__lesf2+0x58>
|
|
8000c66: e7f8 b.n 8000c5a <__lesf2+0x5e>
|
|
8000c68: 428b cmp r3, r1
|
|
8000c6a: d1f6 bne.n 8000c5a <__lesf2+0x5e>
|
|
8000c6c: 4282 cmp r2, r0
|
|
8000c6e: dcf4 bgt.n 8000c5a <__lesf2+0x5e>
|
|
8000c70: dbe6 blt.n 8000c40 <__lesf2+0x44>
|
|
8000c72: 42ac cmp r4, r5
|
|
8000c74: d8f1 bhi.n 8000c5a <__lesf2+0x5e>
|
|
8000c76: 2000 movs r0, #0
|
|
8000c78: 42ac cmp r4, r5
|
|
8000c7a: d2eb bcs.n 8000c54 <__lesf2+0x58>
|
|
8000c7c: e7e0 b.n 8000c40 <__lesf2+0x44>
|
|
8000c7e: 2000 movs r0, #0
|
|
8000c80: 428b cmp r3, r1
|
|
8000c82: d1ea bne.n 8000c5a <__lesf2+0x5e>
|
|
8000c84: e7e6 b.n 8000c54 <__lesf2+0x58>
|
|
8000c86: 428b cmp r3, r1
|
|
8000c88: d1e7 bne.n 8000c5a <__lesf2+0x5e>
|
|
8000c8a: e7f2 b.n 8000c72 <__lesf2+0x76>
|
|
|
|
08000c8c <__aeabi_fmul>:
|
|
8000c8c: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000c8e: 464f mov r7, r9
|
|
8000c90: 4646 mov r6, r8
|
|
8000c92: 46d6 mov lr, sl
|
|
8000c94: 0245 lsls r5, r0, #9
|
|
8000c96: b5c0 push {r6, r7, lr}
|
|
8000c98: 0046 lsls r6, r0, #1
|
|
8000c9a: 1c0f adds r7, r1, #0
|
|
8000c9c: 0a6d lsrs r5, r5, #9
|
|
8000c9e: 0e36 lsrs r6, r6, #24
|
|
8000ca0: 0fc4 lsrs r4, r0, #31
|
|
8000ca2: 2e00 cmp r6, #0
|
|
8000ca4: d100 bne.n 8000ca8 <__aeabi_fmul+0x1c>
|
|
8000ca6: e0cd b.n 8000e44 <__aeabi_fmul+0x1b8>
|
|
8000ca8: 2eff cmp r6, #255 @ 0xff
|
|
8000caa: d072 beq.n 8000d92 <__aeabi_fmul+0x106>
|
|
8000cac: 2380 movs r3, #128 @ 0x80
|
|
8000cae: 00ed lsls r5, r5, #3
|
|
8000cb0: 04db lsls r3, r3, #19
|
|
8000cb2: 431d orrs r5, r3
|
|
8000cb4: 2300 movs r3, #0
|
|
8000cb6: 4699 mov r9, r3
|
|
8000cb8: 469a mov sl, r3
|
|
8000cba: 3e7f subs r6, #127 @ 0x7f
|
|
8000cbc: 027b lsls r3, r7, #9
|
|
8000cbe: 0a5b lsrs r3, r3, #9
|
|
8000cc0: 4698 mov r8, r3
|
|
8000cc2: 007b lsls r3, r7, #1
|
|
8000cc4: 0e1b lsrs r3, r3, #24
|
|
8000cc6: 0fff lsrs r7, r7, #31
|
|
8000cc8: 2b00 cmp r3, #0
|
|
8000cca: d072 beq.n 8000db2 <__aeabi_fmul+0x126>
|
|
8000ccc: 2bff cmp r3, #255 @ 0xff
|
|
8000cce: d100 bne.n 8000cd2 <__aeabi_fmul+0x46>
|
|
8000cd0: e0a9 b.n 8000e26 <__aeabi_fmul+0x19a>
|
|
8000cd2: 3b7f subs r3, #127 @ 0x7f
|
|
8000cd4: 18f6 adds r6, r6, r3
|
|
8000cd6: 464b mov r3, r9
|
|
8000cd8: 2b0a cmp r3, #10
|
|
8000cda: dd00 ble.n 8000cde <__aeabi_fmul+0x52>
|
|
8000cdc: e085 b.n 8000dea <__aeabi_fmul+0x15e>
|
|
8000cde: 4643 mov r3, r8
|
|
8000ce0: 2280 movs r2, #128 @ 0x80
|
|
8000ce2: 00db lsls r3, r3, #3
|
|
8000ce4: 04d2 lsls r2, r2, #19
|
|
8000ce6: 431a orrs r2, r3
|
|
8000ce8: 464b mov r3, r9
|
|
8000cea: 4690 mov r8, r2
|
|
8000cec: 407c eors r4, r7
|
|
8000cee: 2200 movs r2, #0
|
|
8000cf0: 2b02 cmp r3, #2
|
|
8000cf2: dd0f ble.n 8000d14 <__aeabi_fmul+0x88>
|
|
8000cf4: 4649 mov r1, r9
|
|
8000cf6: 2301 movs r3, #1
|
|
8000cf8: 408b lsls r3, r1
|
|
8000cfa: 21a6 movs r1, #166 @ 0xa6
|
|
8000cfc: 00c9 lsls r1, r1, #3
|
|
8000cfe: 420b tst r3, r1
|
|
8000d00: d000 beq.n 8000d04 <__aeabi_fmul+0x78>
|
|
8000d02: e072 b.n 8000dea <__aeabi_fmul+0x15e>
|
|
8000d04: 2190 movs r1, #144 @ 0x90
|
|
8000d06: 0089 lsls r1, r1, #2
|
|
8000d08: 420b tst r3, r1
|
|
8000d0a: d000 beq.n 8000d0e <__aeabi_fmul+0x82>
|
|
8000d0c: e0da b.n 8000ec4 <__aeabi_fmul+0x238>
|
|
8000d0e: 2188 movs r1, #136 @ 0x88
|
|
8000d10: 4219 tst r1, r3
|
|
8000d12: d167 bne.n 8000de4 <__aeabi_fmul+0x158>
|
|
8000d14: 0c28 lsrs r0, r5, #16
|
|
8000d16: 4642 mov r2, r8
|
|
8000d18: 042d lsls r5, r5, #16
|
|
8000d1a: 0c2d lsrs r5, r5, #16
|
|
8000d1c: 4643 mov r3, r8
|
|
8000d1e: 0029 movs r1, r5
|
|
8000d20: 0412 lsls r2, r2, #16
|
|
8000d22: 0c1b lsrs r3, r3, #16
|
|
8000d24: 0c12 lsrs r2, r2, #16
|
|
8000d26: 4351 muls r1, r2
|
|
8000d28: 435d muls r5, r3
|
|
8000d2a: 4342 muls r2, r0
|
|
8000d2c: 4358 muls r0, r3
|
|
8000d2e: 18ad adds r5, r5, r2
|
|
8000d30: 0c0b lsrs r3, r1, #16
|
|
8000d32: 195b adds r3, r3, r5
|
|
8000d34: 429a cmp r2, r3
|
|
8000d36: d903 bls.n 8000d40 <__aeabi_fmul+0xb4>
|
|
8000d38: 2280 movs r2, #128 @ 0x80
|
|
8000d3a: 0252 lsls r2, r2, #9
|
|
8000d3c: 4694 mov ip, r2
|
|
8000d3e: 4460 add r0, ip
|
|
8000d40: 0409 lsls r1, r1, #16
|
|
8000d42: 041a lsls r2, r3, #16
|
|
8000d44: 0c09 lsrs r1, r1, #16
|
|
8000d46: 1852 adds r2, r2, r1
|
|
8000d48: 0195 lsls r5, r2, #6
|
|
8000d4a: 1e69 subs r1, r5, #1
|
|
8000d4c: 418d sbcs r5, r1
|
|
8000d4e: 0c1b lsrs r3, r3, #16
|
|
8000d50: 0e92 lsrs r2, r2, #26
|
|
8000d52: 181b adds r3, r3, r0
|
|
8000d54: 4315 orrs r5, r2
|
|
8000d56: 019b lsls r3, r3, #6
|
|
8000d58: 431d orrs r5, r3
|
|
8000d5a: 011b lsls r3, r3, #4
|
|
8000d5c: d500 bpl.n 8000d60 <__aeabi_fmul+0xd4>
|
|
8000d5e: e0cf b.n 8000f00 <__aeabi_fmul+0x274>
|
|
8000d60: 0030 movs r0, r6
|
|
8000d62: 307f adds r0, #127 @ 0x7f
|
|
8000d64: 2800 cmp r0, #0
|
|
8000d66: dc00 bgt.n 8000d6a <__aeabi_fmul+0xde>
|
|
8000d68: e0b1 b.n 8000ece <__aeabi_fmul+0x242>
|
|
8000d6a: 076b lsls r3, r5, #29
|
|
8000d6c: d00b beq.n 8000d86 <__aeabi_fmul+0xfa>
|
|
8000d6e: 230f movs r3, #15
|
|
8000d70: 0032 movs r2, r6
|
|
8000d72: 402b ands r3, r5
|
|
8000d74: 2b04 cmp r3, #4
|
|
8000d76: d006 beq.n 8000d86 <__aeabi_fmul+0xfa>
|
|
8000d78: 3504 adds r5, #4
|
|
8000d7a: 012b lsls r3, r5, #4
|
|
8000d7c: d503 bpl.n 8000d86 <__aeabi_fmul+0xfa>
|
|
8000d7e: 3280 adds r2, #128 @ 0x80
|
|
8000d80: 0010 movs r0, r2
|
|
8000d82: 4b6a ldr r3, [pc, #424] @ (8000f2c <__aeabi_fmul+0x2a0>)
|
|
8000d84: 401d ands r5, r3
|
|
8000d86: 28fe cmp r0, #254 @ 0xfe
|
|
8000d88: dc64 bgt.n 8000e54 <__aeabi_fmul+0x1c8>
|
|
8000d8a: 01ab lsls r3, r5, #6
|
|
8000d8c: 0a5b lsrs r3, r3, #9
|
|
8000d8e: b2c0 uxtb r0, r0
|
|
8000d90: e01f b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000d92: 2d00 cmp r5, #0
|
|
8000d94: d000 beq.n 8000d98 <__aeabi_fmul+0x10c>
|
|
8000d96: e08f b.n 8000eb8 <__aeabi_fmul+0x22c>
|
|
8000d98: 2308 movs r3, #8
|
|
8000d9a: 4699 mov r9, r3
|
|
8000d9c: 3b06 subs r3, #6
|
|
8000d9e: 469a mov sl, r3
|
|
8000da0: 027b lsls r3, r7, #9
|
|
8000da2: 0a5b lsrs r3, r3, #9
|
|
8000da4: 4698 mov r8, r3
|
|
8000da6: 007b lsls r3, r7, #1
|
|
8000da8: 26ff movs r6, #255 @ 0xff
|
|
8000daa: 0e1b lsrs r3, r3, #24
|
|
8000dac: 0fff lsrs r7, r7, #31
|
|
8000dae: 2b00 cmp r3, #0
|
|
8000db0: d18c bne.n 8000ccc <__aeabi_fmul+0x40>
|
|
8000db2: 4643 mov r3, r8
|
|
8000db4: 2b00 cmp r3, #0
|
|
8000db6: d15c bne.n 8000e72 <__aeabi_fmul+0x1e6>
|
|
8000db8: 464a mov r2, r9
|
|
8000dba: 3301 adds r3, #1
|
|
8000dbc: 431a orrs r2, r3
|
|
8000dbe: 4691 mov r9, r2
|
|
8000dc0: 0013 movs r3, r2
|
|
8000dc2: 2a0a cmp r2, #10
|
|
8000dc4: dc11 bgt.n 8000dea <__aeabi_fmul+0x15e>
|
|
8000dc6: 2201 movs r2, #1
|
|
8000dc8: 407c eors r4, r7
|
|
8000dca: 2b02 cmp r3, #2
|
|
8000dcc: dc92 bgt.n 8000cf4 <__aeabi_fmul+0x68>
|
|
8000dce: 2000 movs r0, #0
|
|
8000dd0: 2300 movs r3, #0
|
|
8000dd2: 05c0 lsls r0, r0, #23
|
|
8000dd4: 4318 orrs r0, r3
|
|
8000dd6: 07e4 lsls r4, r4, #31
|
|
8000dd8: 4320 orrs r0, r4
|
|
8000dda: bce0 pop {r5, r6, r7}
|
|
8000ddc: 46ba mov sl, r7
|
|
8000dde: 46b1 mov r9, r6
|
|
8000de0: 46a8 mov r8, r5
|
|
8000de2: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8000de4: 003c movs r4, r7
|
|
8000de6: 4645 mov r5, r8
|
|
8000de8: 4692 mov sl, r2
|
|
8000dea: 4653 mov r3, sl
|
|
8000dec: 2b02 cmp r3, #2
|
|
8000dee: d031 beq.n 8000e54 <__aeabi_fmul+0x1c8>
|
|
8000df0: 2b03 cmp r3, #3
|
|
8000df2: d011 beq.n 8000e18 <__aeabi_fmul+0x18c>
|
|
8000df4: 2b01 cmp r3, #1
|
|
8000df6: d0ea beq.n 8000dce <__aeabi_fmul+0x142>
|
|
8000df8: 0030 movs r0, r6
|
|
8000dfa: 3080 adds r0, #128 @ 0x80
|
|
8000dfc: 1c72 adds r2, r6, #1
|
|
8000dfe: 2800 cmp r0, #0
|
|
8000e00: dd66 ble.n 8000ed0 <__aeabi_fmul+0x244>
|
|
8000e02: 076b lsls r3, r5, #29
|
|
8000e04: d0b9 beq.n 8000d7a <__aeabi_fmul+0xee>
|
|
8000e06: 230f movs r3, #15
|
|
8000e08: 402b ands r3, r5
|
|
8000e0a: 2b04 cmp r3, #4
|
|
8000e0c: d1b4 bne.n 8000d78 <__aeabi_fmul+0xec>
|
|
8000e0e: e7b4 b.n 8000d7a <__aeabi_fmul+0xee>
|
|
8000e10: 2a0f cmp r2, #15
|
|
8000e12: d07a beq.n 8000f0a <__aeabi_fmul+0x27e>
|
|
8000e14: 003c movs r4, r7
|
|
8000e16: 4645 mov r5, r8
|
|
8000e18: 2380 movs r3, #128 @ 0x80
|
|
8000e1a: 03db lsls r3, r3, #15
|
|
8000e1c: 432b orrs r3, r5
|
|
8000e1e: 025b lsls r3, r3, #9
|
|
8000e20: 20ff movs r0, #255 @ 0xff
|
|
8000e22: 0a5b lsrs r3, r3, #9
|
|
8000e24: e7d5 b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000e26: 4643 mov r3, r8
|
|
8000e28: 36ff adds r6, #255 @ 0xff
|
|
8000e2a: 2b00 cmp r3, #0
|
|
8000e2c: d134 bne.n 8000e98 <__aeabi_fmul+0x20c>
|
|
8000e2e: 464a mov r2, r9
|
|
8000e30: 3302 adds r3, #2
|
|
8000e32: 4313 orrs r3, r2
|
|
8000e34: 2b0a cmp r3, #10
|
|
8000e36: dcd8 bgt.n 8000dea <__aeabi_fmul+0x15e>
|
|
8000e38: 407c eors r4, r7
|
|
8000e3a: 2a00 cmp r2, #0
|
|
8000e3c: d00a beq.n 8000e54 <__aeabi_fmul+0x1c8>
|
|
8000e3e: 4699 mov r9, r3
|
|
8000e40: 2202 movs r2, #2
|
|
8000e42: e757 b.n 8000cf4 <__aeabi_fmul+0x68>
|
|
8000e44: 2d00 cmp r5, #0
|
|
8000e46: d108 bne.n 8000e5a <__aeabi_fmul+0x1ce>
|
|
8000e48: 2304 movs r3, #4
|
|
8000e4a: 4699 mov r9, r3
|
|
8000e4c: 3b03 subs r3, #3
|
|
8000e4e: 2600 movs r6, #0
|
|
8000e50: 469a mov sl, r3
|
|
8000e52: e733 b.n 8000cbc <__aeabi_fmul+0x30>
|
|
8000e54: 20ff movs r0, #255 @ 0xff
|
|
8000e56: 2300 movs r3, #0
|
|
8000e58: e7bb b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000e5a: 0028 movs r0, r5
|
|
8000e5c: f001 fb08 bl 8002470 <__clzsi2>
|
|
8000e60: 2676 movs r6, #118 @ 0x76
|
|
8000e62: 1f43 subs r3, r0, #5
|
|
8000e64: 409d lsls r5, r3
|
|
8000e66: 2300 movs r3, #0
|
|
8000e68: 4276 negs r6, r6
|
|
8000e6a: 4699 mov r9, r3
|
|
8000e6c: 469a mov sl, r3
|
|
8000e6e: 1a36 subs r6, r6, r0
|
|
8000e70: e724 b.n 8000cbc <__aeabi_fmul+0x30>
|
|
8000e72: 4640 mov r0, r8
|
|
8000e74: f001 fafc bl 8002470 <__clzsi2>
|
|
8000e78: 464b mov r3, r9
|
|
8000e7a: 1a36 subs r6, r6, r0
|
|
8000e7c: 3e76 subs r6, #118 @ 0x76
|
|
8000e7e: 2b0a cmp r3, #10
|
|
8000e80: dcb3 bgt.n 8000dea <__aeabi_fmul+0x15e>
|
|
8000e82: 4643 mov r3, r8
|
|
8000e84: 3805 subs r0, #5
|
|
8000e86: 4083 lsls r3, r0
|
|
8000e88: 4698 mov r8, r3
|
|
8000e8a: 464b mov r3, r9
|
|
8000e8c: 2200 movs r2, #0
|
|
8000e8e: 407c eors r4, r7
|
|
8000e90: 2b02 cmp r3, #2
|
|
8000e92: dd00 ble.n 8000e96 <__aeabi_fmul+0x20a>
|
|
8000e94: e72e b.n 8000cf4 <__aeabi_fmul+0x68>
|
|
8000e96: e73d b.n 8000d14 <__aeabi_fmul+0x88>
|
|
8000e98: 2303 movs r3, #3
|
|
8000e9a: 464a mov r2, r9
|
|
8000e9c: 431a orrs r2, r3
|
|
8000e9e: 0013 movs r3, r2
|
|
8000ea0: 2a0a cmp r2, #10
|
|
8000ea2: dcb5 bgt.n 8000e10 <__aeabi_fmul+0x184>
|
|
8000ea4: 2201 movs r2, #1
|
|
8000ea6: 409a lsls r2, r3
|
|
8000ea8: 2188 movs r1, #136 @ 0x88
|
|
8000eaa: 0013 movs r3, r2
|
|
8000eac: 407c eors r4, r7
|
|
8000eae: 2203 movs r2, #3
|
|
8000eb0: 4219 tst r1, r3
|
|
8000eb2: d100 bne.n 8000eb6 <__aeabi_fmul+0x22a>
|
|
8000eb4: e72e b.n 8000d14 <__aeabi_fmul+0x88>
|
|
8000eb6: e795 b.n 8000de4 <__aeabi_fmul+0x158>
|
|
8000eb8: 230c movs r3, #12
|
|
8000eba: 4699 mov r9, r3
|
|
8000ebc: 3b09 subs r3, #9
|
|
8000ebe: 26ff movs r6, #255 @ 0xff
|
|
8000ec0: 469a mov sl, r3
|
|
8000ec2: e6fb b.n 8000cbc <__aeabi_fmul+0x30>
|
|
8000ec4: 2380 movs r3, #128 @ 0x80
|
|
8000ec6: 2400 movs r4, #0
|
|
8000ec8: 20ff movs r0, #255 @ 0xff
|
|
8000eca: 03db lsls r3, r3, #15
|
|
8000ecc: e781 b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000ece: 0032 movs r2, r6
|
|
8000ed0: 2301 movs r3, #1
|
|
8000ed2: 1a1b subs r3, r3, r0
|
|
8000ed4: 2b1b cmp r3, #27
|
|
8000ed6: dd00 ble.n 8000eda <__aeabi_fmul+0x24e>
|
|
8000ed8: e779 b.n 8000dce <__aeabi_fmul+0x142>
|
|
8000eda: 329e adds r2, #158 @ 0x9e
|
|
8000edc: 0029 movs r1, r5
|
|
8000ede: 4095 lsls r5, r2
|
|
8000ee0: 40d9 lsrs r1, r3
|
|
8000ee2: 1e6a subs r2, r5, #1
|
|
8000ee4: 4195 sbcs r5, r2
|
|
8000ee6: 430d orrs r5, r1
|
|
8000ee8: 076b lsls r3, r5, #29
|
|
8000eea: d004 beq.n 8000ef6 <__aeabi_fmul+0x26a>
|
|
8000eec: 230f movs r3, #15
|
|
8000eee: 402b ands r3, r5
|
|
8000ef0: 2b04 cmp r3, #4
|
|
8000ef2: d000 beq.n 8000ef6 <__aeabi_fmul+0x26a>
|
|
8000ef4: 3504 adds r5, #4
|
|
8000ef6: 016b lsls r3, r5, #5
|
|
8000ef8: d513 bpl.n 8000f22 <__aeabi_fmul+0x296>
|
|
8000efa: 2001 movs r0, #1
|
|
8000efc: 2300 movs r3, #0
|
|
8000efe: e768 b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000f00: 2301 movs r3, #1
|
|
8000f02: 086a lsrs r2, r5, #1
|
|
8000f04: 401d ands r5, r3
|
|
8000f06: 4315 orrs r5, r2
|
|
8000f08: e776 b.n 8000df8 <__aeabi_fmul+0x16c>
|
|
8000f0a: 2380 movs r3, #128 @ 0x80
|
|
8000f0c: 03db lsls r3, r3, #15
|
|
8000f0e: 421d tst r5, r3
|
|
8000f10: d082 beq.n 8000e18 <__aeabi_fmul+0x18c>
|
|
8000f12: 4642 mov r2, r8
|
|
8000f14: 421a tst r2, r3
|
|
8000f16: d000 beq.n 8000f1a <__aeabi_fmul+0x28e>
|
|
8000f18: e77e b.n 8000e18 <__aeabi_fmul+0x18c>
|
|
8000f1a: 003c movs r4, r7
|
|
8000f1c: 20ff movs r0, #255 @ 0xff
|
|
8000f1e: 4313 orrs r3, r2
|
|
8000f20: e757 b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000f22: 01ab lsls r3, r5, #6
|
|
8000f24: 2000 movs r0, #0
|
|
8000f26: 0a5b lsrs r3, r3, #9
|
|
8000f28: e753 b.n 8000dd2 <__aeabi_fmul+0x146>
|
|
8000f2a: 46c0 nop @ (mov r8, r8)
|
|
8000f2c: f7ffffff .word 0xf7ffffff
|
|
|
|
08000f30 <__aeabi_fsub>:
|
|
8000f30: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8000f32: 4647 mov r7, r8
|
|
8000f34: 46ce mov lr, r9
|
|
8000f36: 024b lsls r3, r1, #9
|
|
8000f38: 0046 lsls r6, r0, #1
|
|
8000f3a: b580 push {r7, lr}
|
|
8000f3c: 0fc4 lsrs r4, r0, #31
|
|
8000f3e: 0247 lsls r7, r0, #9
|
|
8000f40: 0a58 lsrs r0, r3, #9
|
|
8000f42: 4684 mov ip, r0
|
|
8000f44: 0048 lsls r0, r1, #1
|
|
8000f46: 0a7a lsrs r2, r7, #9
|
|
8000f48: 0e36 lsrs r6, r6, #24
|
|
8000f4a: 09bf lsrs r7, r7, #6
|
|
8000f4c: 0e00 lsrs r0, r0, #24
|
|
8000f4e: 0fcd lsrs r5, r1, #31
|
|
8000f50: 099b lsrs r3, r3, #6
|
|
8000f52: 28ff cmp r0, #255 @ 0xff
|
|
8000f54: d06d beq.n 8001032 <__aeabi_fsub+0x102>
|
|
8000f56: 2101 movs r1, #1
|
|
8000f58: 404d eors r5, r1
|
|
8000f5a: 1a31 subs r1, r6, r0
|
|
8000f5c: 42ac cmp r4, r5
|
|
8000f5e: d03a beq.n 8000fd6 <__aeabi_fsub+0xa6>
|
|
8000f60: 2900 cmp r1, #0
|
|
8000f62: dc00 bgt.n 8000f66 <__aeabi_fsub+0x36>
|
|
8000f64: e19c b.n 80012a0 <__aeabi_fsub+0x370>
|
|
8000f66: 2800 cmp r0, #0
|
|
8000f68: d100 bne.n 8000f6c <__aeabi_fsub+0x3c>
|
|
8000f6a: e09e b.n 80010aa <__aeabi_fsub+0x17a>
|
|
8000f6c: 2eff cmp r6, #255 @ 0xff
|
|
8000f6e: d100 bne.n 8000f72 <__aeabi_fsub+0x42>
|
|
8000f70: e088 b.n 8001084 <__aeabi_fsub+0x154>
|
|
8000f72: 2280 movs r2, #128 @ 0x80
|
|
8000f74: 04d2 lsls r2, r2, #19
|
|
8000f76: 4313 orrs r3, r2
|
|
8000f78: 291b cmp r1, #27
|
|
8000f7a: dc00 bgt.n 8000f7e <__aeabi_fsub+0x4e>
|
|
8000f7c: e0f6 b.n 800116c <__aeabi_fsub+0x23c>
|
|
8000f7e: 3f01 subs r7, #1
|
|
8000f80: 017a lsls r2, r7, #5
|
|
8000f82: d400 bmi.n 8000f86 <__aeabi_fsub+0x56>
|
|
8000f84: e079 b.n 800107a <__aeabi_fsub+0x14a>
|
|
8000f86: 2701 movs r7, #1
|
|
8000f88: 427f negs r7, r7
|
|
8000f8a: 01bf lsls r7, r7, #6
|
|
8000f8c: 09bb lsrs r3, r7, #6
|
|
8000f8e: 4698 mov r8, r3
|
|
8000f90: 4640 mov r0, r8
|
|
8000f92: f001 fa6d bl 8002470 <__clzsi2>
|
|
8000f96: 4643 mov r3, r8
|
|
8000f98: 3805 subs r0, #5
|
|
8000f9a: 4083 lsls r3, r0
|
|
8000f9c: 4286 cmp r6, r0
|
|
8000f9e: dc00 bgt.n 8000fa2 <__aeabi_fsub+0x72>
|
|
8000fa0: e0cc b.n 800113c <__aeabi_fsub+0x20c>
|
|
8000fa2: 4fb4 ldr r7, [pc, #720] @ (8001274 <__aeabi_fsub+0x344>)
|
|
8000fa4: 1a31 subs r1, r6, r0
|
|
8000fa6: 401f ands r7, r3
|
|
8000fa8: 075a lsls r2, r3, #29
|
|
8000faa: d068 beq.n 800107e <__aeabi_fsub+0x14e>
|
|
8000fac: 220f movs r2, #15
|
|
8000fae: 4013 ands r3, r2
|
|
8000fb0: 2b04 cmp r3, #4
|
|
8000fb2: d064 beq.n 800107e <__aeabi_fsub+0x14e>
|
|
8000fb4: 3704 adds r7, #4
|
|
8000fb6: 017b lsls r3, r7, #5
|
|
8000fb8: d561 bpl.n 800107e <__aeabi_fsub+0x14e>
|
|
8000fba: 1c48 adds r0, r1, #1
|
|
8000fbc: 29fe cmp r1, #254 @ 0xfe
|
|
8000fbe: d000 beq.n 8000fc2 <__aeabi_fsub+0x92>
|
|
8000fc0: e081 b.n 80010c6 <__aeabi_fsub+0x196>
|
|
8000fc2: 20ff movs r0, #255 @ 0xff
|
|
8000fc4: 2300 movs r3, #0
|
|
8000fc6: 05c0 lsls r0, r0, #23
|
|
8000fc8: 4318 orrs r0, r3
|
|
8000fca: 07e4 lsls r4, r4, #31
|
|
8000fcc: 4320 orrs r0, r4
|
|
8000fce: bcc0 pop {r6, r7}
|
|
8000fd0: 46b9 mov r9, r7
|
|
8000fd2: 46b0 mov r8, r6
|
|
8000fd4: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
8000fd6: 2900 cmp r1, #0
|
|
8000fd8: dc00 bgt.n 8000fdc <__aeabi_fsub+0xac>
|
|
8000fda: e179 b.n 80012d0 <__aeabi_fsub+0x3a0>
|
|
8000fdc: 2800 cmp r0, #0
|
|
8000fde: d176 bne.n 80010ce <__aeabi_fsub+0x19e>
|
|
8000fe0: 2b00 cmp r3, #0
|
|
8000fe2: d04c beq.n 800107e <__aeabi_fsub+0x14e>
|
|
8000fe4: 1e48 subs r0, r1, #1
|
|
8000fe6: 2901 cmp r1, #1
|
|
8000fe8: d100 bne.n 8000fec <__aeabi_fsub+0xbc>
|
|
8000fea: e147 b.n 800127c <__aeabi_fsub+0x34c>
|
|
8000fec: 29ff cmp r1, #255 @ 0xff
|
|
8000fee: d049 beq.n 8001084 <__aeabi_fsub+0x154>
|
|
8000ff0: 281b cmp r0, #27
|
|
8000ff2: dc71 bgt.n 80010d8 <__aeabi_fsub+0x1a8>
|
|
8000ff4: 0001 movs r1, r0
|
|
8000ff6: 001a movs r2, r3
|
|
8000ff8: 2020 movs r0, #32
|
|
8000ffa: 40ca lsrs r2, r1
|
|
8000ffc: 1a41 subs r1, r0, r1
|
|
8000ffe: 408b lsls r3, r1
|
|
8001000: 1e59 subs r1, r3, #1
|
|
8001002: 418b sbcs r3, r1
|
|
8001004: 4313 orrs r3, r2
|
|
8001006: 18ff adds r7, r7, r3
|
|
8001008: 2380 movs r3, #128 @ 0x80
|
|
800100a: 04db lsls r3, r3, #19
|
|
800100c: 421f tst r7, r3
|
|
800100e: d100 bne.n 8001012 <__aeabi_fsub+0xe2>
|
|
8001010: e0b8 b.n 8001184 <__aeabi_fsub+0x254>
|
|
8001012: 1c71 adds r1, r6, #1
|
|
8001014: 2efe cmp r6, #254 @ 0xfe
|
|
8001016: d0d4 beq.n 8000fc2 <__aeabi_fsub+0x92>
|
|
8001018: 2201 movs r2, #1
|
|
800101a: 4897 ldr r0, [pc, #604] @ (8001278 <__aeabi_fsub+0x348>)
|
|
800101c: 403a ands r2, r7
|
|
800101e: 087f lsrs r7, r7, #1
|
|
8001020: 4007 ands r7, r0
|
|
8001022: 4317 orrs r7, r2
|
|
8001024: 077a lsls r2, r7, #29
|
|
8001026: d000 beq.n 800102a <__aeabi_fsub+0xfa>
|
|
8001028: e096 b.n 8001158 <__aeabi_fsub+0x228>
|
|
800102a: 421f tst r7, r3
|
|
800102c: d1c5 bne.n 8000fba <__aeabi_fsub+0x8a>
|
|
800102e: 08fa lsrs r2, r7, #3
|
|
8001030: e055 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001032: 0031 movs r1, r6
|
|
8001034: 39ff subs r1, #255 @ 0xff
|
|
8001036: 4689 mov r9, r1
|
|
8001038: 2b00 cmp r3, #0
|
|
800103a: d12c bne.n 8001096 <__aeabi_fsub+0x166>
|
|
800103c: 2101 movs r1, #1
|
|
800103e: 404d eors r5, r1
|
|
8001040: 42ac cmp r4, r5
|
|
8001042: d100 bne.n 8001046 <__aeabi_fsub+0x116>
|
|
8001044: e0b4 b.n 80011b0 <__aeabi_fsub+0x280>
|
|
8001046: 4649 mov r1, r9
|
|
8001048: 2900 cmp r1, #0
|
|
800104a: d04c beq.n 80010e6 <__aeabi_fsub+0x1b6>
|
|
800104c: 2e00 cmp r6, #0
|
|
800104e: d000 beq.n 8001052 <__aeabi_fsub+0x122>
|
|
8001050: e0f9 b.n 8001246 <__aeabi_fsub+0x316>
|
|
8001052: 21ff movs r1, #255 @ 0xff
|
|
8001054: 2f00 cmp r7, #0
|
|
8001056: d100 bne.n 800105a <__aeabi_fsub+0x12a>
|
|
8001058: e108 b.n 800126c <__aeabi_fsub+0x33c>
|
|
800105a: 1e4a subs r2, r1, #1
|
|
800105c: 2901 cmp r1, #1
|
|
800105e: d100 bne.n 8001062 <__aeabi_fsub+0x132>
|
|
8001060: e156 b.n 8001310 <__aeabi_fsub+0x3e0>
|
|
8001062: 29ff cmp r1, #255 @ 0xff
|
|
8001064: d100 bne.n 8001068 <__aeabi_fsub+0x138>
|
|
8001066: e142 b.n 80012ee <__aeabi_fsub+0x3be>
|
|
8001068: 2a1b cmp r2, #27
|
|
800106a: dc00 bgt.n 800106e <__aeabi_fsub+0x13e>
|
|
800106c: e124 b.n 80012b8 <__aeabi_fsub+0x388>
|
|
800106e: 1e5f subs r7, r3, #1
|
|
8001070: 002c movs r4, r5
|
|
8001072: 0006 movs r6, r0
|
|
8001074: 017a lsls r2, r7, #5
|
|
8001076: d500 bpl.n 800107a <__aeabi_fsub+0x14a>
|
|
8001078: e785 b.n 8000f86 <__aeabi_fsub+0x56>
|
|
800107a: 0031 movs r1, r6
|
|
800107c: 3704 adds r7, #4
|
|
800107e: 08fa lsrs r2, r7, #3
|
|
8001080: 29ff cmp r1, #255 @ 0xff
|
|
8001082: d12c bne.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001084: 2a00 cmp r2, #0
|
|
8001086: d09c beq.n 8000fc2 <__aeabi_fsub+0x92>
|
|
8001088: 2380 movs r3, #128 @ 0x80
|
|
800108a: 03db lsls r3, r3, #15
|
|
800108c: 4313 orrs r3, r2
|
|
800108e: 025b lsls r3, r3, #9
|
|
8001090: 20ff movs r0, #255 @ 0xff
|
|
8001092: 0a5b lsrs r3, r3, #9
|
|
8001094: e797 b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
8001096: 42ac cmp r4, r5
|
|
8001098: d100 bne.n 800109c <__aeabi_fsub+0x16c>
|
|
800109a: e0a7 b.n 80011ec <__aeabi_fsub+0x2bc>
|
|
800109c: 2900 cmp r1, #0
|
|
800109e: d022 beq.n 80010e6 <__aeabi_fsub+0x1b6>
|
|
80010a0: 2e00 cmp r6, #0
|
|
80010a2: d0d6 beq.n 8001052 <__aeabi_fsub+0x122>
|
|
80010a4: 4662 mov r2, ip
|
|
80010a6: 002c movs r4, r5
|
|
80010a8: e7ee b.n 8001088 <__aeabi_fsub+0x158>
|
|
80010aa: 2b00 cmp r3, #0
|
|
80010ac: d0e7 beq.n 800107e <__aeabi_fsub+0x14e>
|
|
80010ae: 1e48 subs r0, r1, #1
|
|
80010b0: 2901 cmp r1, #1
|
|
80010b2: d036 beq.n 8001122 <__aeabi_fsub+0x1f2>
|
|
80010b4: 29ff cmp r1, #255 @ 0xff
|
|
80010b6: d0e5 beq.n 8001084 <__aeabi_fsub+0x154>
|
|
80010b8: 0001 movs r1, r0
|
|
80010ba: e75d b.n 8000f78 <__aeabi_fsub+0x48>
|
|
80010bc: 2001 movs r0, #1
|
|
80010be: 003b movs r3, r7
|
|
80010c0: 017a lsls r2, r7, #5
|
|
80010c2: d400 bmi.n 80010c6 <__aeabi_fsub+0x196>
|
|
80010c4: e157 b.n 8001376 <__aeabi_fsub+0x446>
|
|
80010c6: b2c0 uxtb r0, r0
|
|
80010c8: 01bb lsls r3, r7, #6
|
|
80010ca: 0a5b lsrs r3, r3, #9
|
|
80010cc: e77b b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
80010ce: 2eff cmp r6, #255 @ 0xff
|
|
80010d0: d0d8 beq.n 8001084 <__aeabi_fsub+0x154>
|
|
80010d2: 291b cmp r1, #27
|
|
80010d4: dc00 bgt.n 80010d8 <__aeabi_fsub+0x1a8>
|
|
80010d6: e09f b.n 8001218 <__aeabi_fsub+0x2e8>
|
|
80010d8: 0031 movs r1, r6
|
|
80010da: 3705 adds r7, #5
|
|
80010dc: 08fa lsrs r2, r7, #3
|
|
80010de: 0253 lsls r3, r2, #9
|
|
80010e0: 0a5b lsrs r3, r3, #9
|
|
80010e2: b2c8 uxtb r0, r1
|
|
80010e4: e76f b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
80010e6: 20fe movs r0, #254 @ 0xfe
|
|
80010e8: 1c71 adds r1, r6, #1
|
|
80010ea: 4208 tst r0, r1
|
|
80010ec: d154 bne.n 8001198 <__aeabi_fsub+0x268>
|
|
80010ee: 2e00 cmp r6, #0
|
|
80010f0: d000 beq.n 80010f4 <__aeabi_fsub+0x1c4>
|
|
80010f2: e0b1 b.n 8001258 <__aeabi_fsub+0x328>
|
|
80010f4: 2f00 cmp r7, #0
|
|
80010f6: d100 bne.n 80010fa <__aeabi_fsub+0x1ca>
|
|
80010f8: e102 b.n 8001300 <__aeabi_fsub+0x3d0>
|
|
80010fa: 2b00 cmp r3, #0
|
|
80010fc: d100 bne.n 8001100 <__aeabi_fsub+0x1d0>
|
|
80010fe: e0f9 b.n 80012f4 <__aeabi_fsub+0x3c4>
|
|
8001100: 2180 movs r1, #128 @ 0x80
|
|
8001102: 1afa subs r2, r7, r3
|
|
8001104: 04c9 lsls r1, r1, #19
|
|
8001106: 420a tst r2, r1
|
|
8001108: d100 bne.n 800110c <__aeabi_fsub+0x1dc>
|
|
800110a: e13b b.n 8001384 <__aeabi_fsub+0x454>
|
|
800110c: 2401 movs r4, #1
|
|
800110e: 1bdf subs r7, r3, r7
|
|
8001110: 402c ands r4, r5
|
|
8001112: 2f00 cmp r7, #0
|
|
8001114: d049 beq.n 80011aa <__aeabi_fsub+0x27a>
|
|
8001116: 2001 movs r0, #1
|
|
8001118: 420f tst r7, r1
|
|
800111a: d1d5 bne.n 80010c8 <__aeabi_fsub+0x198>
|
|
800111c: 2100 movs r1, #0
|
|
800111e: 08fa lsrs r2, r7, #3
|
|
8001120: e7dd b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001122: 1aff subs r7, r7, r3
|
|
8001124: 017b lsls r3, r7, #5
|
|
8001126: d400 bmi.n 800112a <__aeabi_fsub+0x1fa>
|
|
8001128: e0de b.n 80012e8 <__aeabi_fsub+0x3b8>
|
|
800112a: 01bd lsls r5, r7, #6
|
|
800112c: 09ad lsrs r5, r5, #6
|
|
800112e: 0028 movs r0, r5
|
|
8001130: f001 f99e bl 8002470 <__clzsi2>
|
|
8001134: 002b movs r3, r5
|
|
8001136: 3805 subs r0, #5
|
|
8001138: 4083 lsls r3, r0
|
|
800113a: 2601 movs r6, #1
|
|
800113c: 2220 movs r2, #32
|
|
800113e: 1b81 subs r1, r0, r6
|
|
8001140: 3101 adds r1, #1
|
|
8001142: 1a52 subs r2, r2, r1
|
|
8001144: 001f movs r7, r3
|
|
8001146: 4093 lsls r3, r2
|
|
8001148: 40cf lsrs r7, r1
|
|
800114a: 1e5a subs r2, r3, #1
|
|
800114c: 4193 sbcs r3, r2
|
|
800114e: 431f orrs r7, r3
|
|
8001150: d02b beq.n 80011aa <__aeabi_fsub+0x27a>
|
|
8001152: 2100 movs r1, #0
|
|
8001154: 077b lsls r3, r7, #29
|
|
8001156: d0b1 beq.n 80010bc <__aeabi_fsub+0x18c>
|
|
8001158: 230f movs r3, #15
|
|
800115a: 403b ands r3, r7
|
|
800115c: 2b04 cmp r3, #4
|
|
800115e: d000 beq.n 8001162 <__aeabi_fsub+0x232>
|
|
8001160: e728 b.n 8000fb4 <__aeabi_fsub+0x84>
|
|
8001162: 017b lsls r3, r7, #5
|
|
8001164: d500 bpl.n 8001168 <__aeabi_fsub+0x238>
|
|
8001166: e728 b.n 8000fba <__aeabi_fsub+0x8a>
|
|
8001168: 08fa lsrs r2, r7, #3
|
|
800116a: e7b8 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
800116c: 001a movs r2, r3
|
|
800116e: 2020 movs r0, #32
|
|
8001170: 40ca lsrs r2, r1
|
|
8001172: 1a41 subs r1, r0, r1
|
|
8001174: 408b lsls r3, r1
|
|
8001176: 1e59 subs r1, r3, #1
|
|
8001178: 418b sbcs r3, r1
|
|
800117a: 4313 orrs r3, r2
|
|
800117c: 1aff subs r7, r7, r3
|
|
800117e: 017b lsls r3, r7, #5
|
|
8001180: d500 bpl.n 8001184 <__aeabi_fsub+0x254>
|
|
8001182: e702 b.n 8000f8a <__aeabi_fsub+0x5a>
|
|
8001184: 077b lsls r3, r7, #29
|
|
8001186: d100 bne.n 800118a <__aeabi_fsub+0x25a>
|
|
8001188: e10d b.n 80013a6 <__aeabi_fsub+0x476>
|
|
800118a: 230f movs r3, #15
|
|
800118c: 0031 movs r1, r6
|
|
800118e: 403b ands r3, r7
|
|
8001190: 2b04 cmp r3, #4
|
|
8001192: d000 beq.n 8001196 <__aeabi_fsub+0x266>
|
|
8001194: e70e b.n 8000fb4 <__aeabi_fsub+0x84>
|
|
8001196: e772 b.n 800107e <__aeabi_fsub+0x14e>
|
|
8001198: 1afa subs r2, r7, r3
|
|
800119a: 4690 mov r8, r2
|
|
800119c: 0152 lsls r2, r2, #5
|
|
800119e: d456 bmi.n 800124e <__aeabi_fsub+0x31e>
|
|
80011a0: 4643 mov r3, r8
|
|
80011a2: 2b00 cmp r3, #0
|
|
80011a4: d000 beq.n 80011a8 <__aeabi_fsub+0x278>
|
|
80011a6: e6f3 b.n 8000f90 <__aeabi_fsub+0x60>
|
|
80011a8: 2400 movs r4, #0
|
|
80011aa: 2000 movs r0, #0
|
|
80011ac: 2300 movs r3, #0
|
|
80011ae: e70a b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
80011b0: 4649 mov r1, r9
|
|
80011b2: 2900 cmp r1, #0
|
|
80011b4: d01c beq.n 80011f0 <__aeabi_fsub+0x2c0>
|
|
80011b6: 2e00 cmp r6, #0
|
|
80011b8: d000 beq.n 80011bc <__aeabi_fsub+0x28c>
|
|
80011ba: e702 b.n 8000fc2 <__aeabi_fsub+0x92>
|
|
80011bc: 21ff movs r1, #255 @ 0xff
|
|
80011be: 2f00 cmp r7, #0
|
|
80011c0: d055 beq.n 800126e <__aeabi_fsub+0x33e>
|
|
80011c2: 1e4a subs r2, r1, #1
|
|
80011c4: 2901 cmp r1, #1
|
|
80011c6: d059 beq.n 800127c <__aeabi_fsub+0x34c>
|
|
80011c8: 29ff cmp r1, #255 @ 0xff
|
|
80011ca: d100 bne.n 80011ce <__aeabi_fsub+0x29e>
|
|
80011cc: e090 b.n 80012f0 <__aeabi_fsub+0x3c0>
|
|
80011ce: 2a1b cmp r2, #27
|
|
80011d0: dd00 ble.n 80011d4 <__aeabi_fsub+0x2a4>
|
|
80011d2: e091 b.n 80012f8 <__aeabi_fsub+0x3c8>
|
|
80011d4: 0011 movs r1, r2
|
|
80011d6: 003a movs r2, r7
|
|
80011d8: 2520 movs r5, #32
|
|
80011da: 40ca lsrs r2, r1
|
|
80011dc: 1a69 subs r1, r5, r1
|
|
80011de: 408f lsls r7, r1
|
|
80011e0: 1e79 subs r1, r7, #1
|
|
80011e2: 418f sbcs r7, r1
|
|
80011e4: 4317 orrs r7, r2
|
|
80011e6: 0006 movs r6, r0
|
|
80011e8: 18ff adds r7, r7, r3
|
|
80011ea: e70d b.n 8001008 <__aeabi_fsub+0xd8>
|
|
80011ec: 2900 cmp r1, #0
|
|
80011ee: d126 bne.n 800123e <__aeabi_fsub+0x30e>
|
|
80011f0: 20fe movs r0, #254 @ 0xfe
|
|
80011f2: 1c71 adds r1, r6, #1
|
|
80011f4: 4208 tst r0, r1
|
|
80011f6: d113 bne.n 8001220 <__aeabi_fsub+0x2f0>
|
|
80011f8: 2e00 cmp r6, #0
|
|
80011fa: d000 beq.n 80011fe <__aeabi_fsub+0x2ce>
|
|
80011fc: e096 b.n 800132c <__aeabi_fsub+0x3fc>
|
|
80011fe: 2f00 cmp r7, #0
|
|
8001200: d100 bne.n 8001204 <__aeabi_fsub+0x2d4>
|
|
8001202: e0b4 b.n 800136e <__aeabi_fsub+0x43e>
|
|
8001204: 2b00 cmp r3, #0
|
|
8001206: d075 beq.n 80012f4 <__aeabi_fsub+0x3c4>
|
|
8001208: 18fb adds r3, r7, r3
|
|
800120a: 015a lsls r2, r3, #5
|
|
800120c: d400 bmi.n 8001210 <__aeabi_fsub+0x2e0>
|
|
800120e: e0b2 b.n 8001376 <__aeabi_fsub+0x446>
|
|
8001210: 019b lsls r3, r3, #6
|
|
8001212: 0a5b lsrs r3, r3, #9
|
|
8001214: 38fd subs r0, #253 @ 0xfd
|
|
8001216: e6d6 b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
8001218: 2280 movs r2, #128 @ 0x80
|
|
800121a: 04d2 lsls r2, r2, #19
|
|
800121c: 4313 orrs r3, r2
|
|
800121e: e6ea b.n 8000ff6 <__aeabi_fsub+0xc6>
|
|
8001220: 29ff cmp r1, #255 @ 0xff
|
|
8001222: d100 bne.n 8001226 <__aeabi_fsub+0x2f6>
|
|
8001224: e6cd b.n 8000fc2 <__aeabi_fsub+0x92>
|
|
8001226: 18fa adds r2, r7, r3
|
|
8001228: 0852 lsrs r2, r2, #1
|
|
800122a: 0753 lsls r3, r2, #29
|
|
800122c: d005 beq.n 800123a <__aeabi_fsub+0x30a>
|
|
800122e: 230f movs r3, #15
|
|
8001230: 1d17 adds r7, r2, #4
|
|
8001232: 4013 ands r3, r2
|
|
8001234: 2b04 cmp r3, #4
|
|
8001236: d000 beq.n 800123a <__aeabi_fsub+0x30a>
|
|
8001238: e721 b.n 800107e <__aeabi_fsub+0x14e>
|
|
800123a: 08d2 lsrs r2, r2, #3
|
|
800123c: e74f b.n 80010de <__aeabi_fsub+0x1ae>
|
|
800123e: 2e00 cmp r6, #0
|
|
8001240: d0bc beq.n 80011bc <__aeabi_fsub+0x28c>
|
|
8001242: 4662 mov r2, ip
|
|
8001244: e720 b.n 8001088 <__aeabi_fsub+0x158>
|
|
8001246: 002c movs r4, r5
|
|
8001248: 20ff movs r0, #255 @ 0xff
|
|
800124a: 2300 movs r3, #0
|
|
800124c: e6bb b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
800124e: 2401 movs r4, #1
|
|
8001250: 1bdb subs r3, r3, r7
|
|
8001252: 4698 mov r8, r3
|
|
8001254: 402c ands r4, r5
|
|
8001256: e69b b.n 8000f90 <__aeabi_fsub+0x60>
|
|
8001258: 2f00 cmp r7, #0
|
|
800125a: d175 bne.n 8001348 <__aeabi_fsub+0x418>
|
|
800125c: 2b00 cmp r3, #0
|
|
800125e: d000 beq.n 8001262 <__aeabi_fsub+0x332>
|
|
8001260: e096 b.n 8001390 <__aeabi_fsub+0x460>
|
|
8001262: 2380 movs r3, #128 @ 0x80
|
|
8001264: 2400 movs r4, #0
|
|
8001266: 20ff movs r0, #255 @ 0xff
|
|
8001268: 03db lsls r3, r3, #15
|
|
800126a: e6ac b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
800126c: 002c movs r4, r5
|
|
800126e: 001f movs r7, r3
|
|
8001270: e705 b.n 800107e <__aeabi_fsub+0x14e>
|
|
8001272: 46c0 nop @ (mov r8, r8)
|
|
8001274: fbffffff .word 0xfbffffff
|
|
8001278: 7dffffff .word 0x7dffffff
|
|
800127c: 18fb adds r3, r7, r3
|
|
800127e: 015a lsls r2, r3, #5
|
|
8001280: d400 bmi.n 8001284 <__aeabi_fsub+0x354>
|
|
8001282: e08d b.n 80013a0 <__aeabi_fsub+0x470>
|
|
8001284: 4a4a ldr r2, [pc, #296] @ (80013b0 <__aeabi_fsub+0x480>)
|
|
8001286: 085b lsrs r3, r3, #1
|
|
8001288: 401a ands r2, r3
|
|
800128a: 0759 lsls r1, r3, #29
|
|
800128c: d100 bne.n 8001290 <__aeabi_fsub+0x360>
|
|
800128e: e08c b.n 80013aa <__aeabi_fsub+0x47a>
|
|
8001290: 210f movs r1, #15
|
|
8001292: 400b ands r3, r1
|
|
8001294: 390d subs r1, #13
|
|
8001296: 2b04 cmp r3, #4
|
|
8001298: d0cf beq.n 800123a <__aeabi_fsub+0x30a>
|
|
800129a: 2102 movs r1, #2
|
|
800129c: 1d17 adds r7, r2, #4
|
|
800129e: e6ee b.n 800107e <__aeabi_fsub+0x14e>
|
|
80012a0: 2900 cmp r1, #0
|
|
80012a2: d100 bne.n 80012a6 <__aeabi_fsub+0x376>
|
|
80012a4: e71f b.n 80010e6 <__aeabi_fsub+0x1b6>
|
|
80012a6: 1b82 subs r2, r0, r6
|
|
80012a8: 0011 movs r1, r2
|
|
80012aa: 2e00 cmp r6, #0
|
|
80012ac: d100 bne.n 80012b0 <__aeabi_fsub+0x380>
|
|
80012ae: e6d1 b.n 8001054 <__aeabi_fsub+0x124>
|
|
80012b0: 2180 movs r1, #128 @ 0x80
|
|
80012b2: 04c9 lsls r1, r1, #19
|
|
80012b4: 430f orrs r7, r1
|
|
80012b6: e6d7 b.n 8001068 <__aeabi_fsub+0x138>
|
|
80012b8: 0039 movs r1, r7
|
|
80012ba: 2420 movs r4, #32
|
|
80012bc: 40d1 lsrs r1, r2
|
|
80012be: 1aa2 subs r2, r4, r2
|
|
80012c0: 4097 lsls r7, r2
|
|
80012c2: 1e7a subs r2, r7, #1
|
|
80012c4: 4197 sbcs r7, r2
|
|
80012c6: 430f orrs r7, r1
|
|
80012c8: 002c movs r4, r5
|
|
80012ca: 0006 movs r6, r0
|
|
80012cc: 1bdf subs r7, r3, r7
|
|
80012ce: e756 b.n 800117e <__aeabi_fsub+0x24e>
|
|
80012d0: 2900 cmp r1, #0
|
|
80012d2: d08d beq.n 80011f0 <__aeabi_fsub+0x2c0>
|
|
80012d4: 1b81 subs r1, r0, r6
|
|
80012d6: 2e00 cmp r6, #0
|
|
80012d8: d100 bne.n 80012dc <__aeabi_fsub+0x3ac>
|
|
80012da: e770 b.n 80011be <__aeabi_fsub+0x28e>
|
|
80012dc: 291b cmp r1, #27
|
|
80012de: dc0b bgt.n 80012f8 <__aeabi_fsub+0x3c8>
|
|
80012e0: 2280 movs r2, #128 @ 0x80
|
|
80012e2: 04d2 lsls r2, r2, #19
|
|
80012e4: 4317 orrs r7, r2
|
|
80012e6: e776 b.n 80011d6 <__aeabi_fsub+0x2a6>
|
|
80012e8: 2101 movs r1, #1
|
|
80012ea: 08fa lsrs r2, r7, #3
|
|
80012ec: e6f7 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
80012ee: 002c movs r4, r5
|
|
80012f0: 4662 mov r2, ip
|
|
80012f2: e6c7 b.n 8001084 <__aeabi_fsub+0x154>
|
|
80012f4: 2100 movs r1, #0
|
|
80012f6: e6f2 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
80012f8: 3305 adds r3, #5
|
|
80012fa: 0001 movs r1, r0
|
|
80012fc: 08da lsrs r2, r3, #3
|
|
80012fe: e6ee b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001300: 2b00 cmp r3, #0
|
|
8001302: d100 bne.n 8001306 <__aeabi_fsub+0x3d6>
|
|
8001304: e750 b.n 80011a8 <__aeabi_fsub+0x278>
|
|
8001306: 2401 movs r4, #1
|
|
8001308: 2100 movs r1, #0
|
|
800130a: 4662 mov r2, ip
|
|
800130c: 402c ands r4, r5
|
|
800130e: e6e6 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001310: 1bda subs r2, r3, r7
|
|
8001312: 0153 lsls r3, r2, #5
|
|
8001314: d532 bpl.n 800137c <__aeabi_fsub+0x44c>
|
|
8001316: 0192 lsls r2, r2, #6
|
|
8001318: 0994 lsrs r4, r2, #6
|
|
800131a: 0020 movs r0, r4
|
|
800131c: f001 f8a8 bl 8002470 <__clzsi2>
|
|
8001320: 0023 movs r3, r4
|
|
8001322: 3805 subs r0, #5
|
|
8001324: 4083 lsls r3, r0
|
|
8001326: 002c movs r4, r5
|
|
8001328: 2601 movs r6, #1
|
|
800132a: e707 b.n 800113c <__aeabi_fsub+0x20c>
|
|
800132c: 2f00 cmp r7, #0
|
|
800132e: d0df beq.n 80012f0 <__aeabi_fsub+0x3c0>
|
|
8001330: 2b00 cmp r3, #0
|
|
8001332: d017 beq.n 8001364 <__aeabi_fsub+0x434>
|
|
8001334: 2380 movs r3, #128 @ 0x80
|
|
8001336: 03db lsls r3, r3, #15
|
|
8001338: 429a cmp r2, r3
|
|
800133a: d200 bcs.n 800133e <__aeabi_fsub+0x40e>
|
|
800133c: e6a4 b.n 8001088 <__aeabi_fsub+0x158>
|
|
800133e: 459c cmp ip, r3
|
|
8001340: d300 bcc.n 8001344 <__aeabi_fsub+0x414>
|
|
8001342: e6a1 b.n 8001088 <__aeabi_fsub+0x158>
|
|
8001344: 4662 mov r2, ip
|
|
8001346: e69f b.n 8001088 <__aeabi_fsub+0x158>
|
|
8001348: 2b00 cmp r3, #0
|
|
800134a: d00b beq.n 8001364 <__aeabi_fsub+0x434>
|
|
800134c: 2380 movs r3, #128 @ 0x80
|
|
800134e: 03db lsls r3, r3, #15
|
|
8001350: 429a cmp r2, r3
|
|
8001352: d200 bcs.n 8001356 <__aeabi_fsub+0x426>
|
|
8001354: e698 b.n 8001088 <__aeabi_fsub+0x158>
|
|
8001356: 459c cmp ip, r3
|
|
8001358: d300 bcc.n 800135c <__aeabi_fsub+0x42c>
|
|
800135a: e695 b.n 8001088 <__aeabi_fsub+0x158>
|
|
800135c: 2401 movs r4, #1
|
|
800135e: 4662 mov r2, ip
|
|
8001360: 402c ands r4, r5
|
|
8001362: e691 b.n 8001088 <__aeabi_fsub+0x158>
|
|
8001364: 2380 movs r3, #128 @ 0x80
|
|
8001366: 03db lsls r3, r3, #15
|
|
8001368: 20ff movs r0, #255 @ 0xff
|
|
800136a: 4313 orrs r3, r2
|
|
800136c: e62b b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
800136e: 2000 movs r0, #0
|
|
8001370: 2b00 cmp r3, #0
|
|
8001372: d100 bne.n 8001376 <__aeabi_fsub+0x446>
|
|
8001374: e627 b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
8001376: 2100 movs r1, #0
|
|
8001378: 08da lsrs r2, r3, #3
|
|
800137a: e6b0 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
800137c: 002c movs r4, r5
|
|
800137e: 2101 movs r1, #1
|
|
8001380: 08d2 lsrs r2, r2, #3
|
|
8001382: e6ac b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001384: 2a00 cmp r2, #0
|
|
8001386: d100 bne.n 800138a <__aeabi_fsub+0x45a>
|
|
8001388: e70e b.n 80011a8 <__aeabi_fsub+0x278>
|
|
800138a: 2100 movs r1, #0
|
|
800138c: 08d2 lsrs r2, r2, #3
|
|
800138e: e6a6 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
8001390: 2380 movs r3, #128 @ 0x80
|
|
8001392: 4662 mov r2, ip
|
|
8001394: 2401 movs r4, #1
|
|
8001396: 03db lsls r3, r3, #15
|
|
8001398: 20ff movs r0, #255 @ 0xff
|
|
800139a: 4313 orrs r3, r2
|
|
800139c: 402c ands r4, r5
|
|
800139e: e612 b.n 8000fc6 <__aeabi_fsub+0x96>
|
|
80013a0: 2101 movs r1, #1
|
|
80013a2: 08da lsrs r2, r3, #3
|
|
80013a4: e69b b.n 80010de <__aeabi_fsub+0x1ae>
|
|
80013a6: 0031 movs r1, r6
|
|
80013a8: e669 b.n 800107e <__aeabi_fsub+0x14e>
|
|
80013aa: 2102 movs r1, #2
|
|
80013ac: 08d2 lsrs r2, r2, #3
|
|
80013ae: e696 b.n 80010de <__aeabi_fsub+0x1ae>
|
|
80013b0: 7dffffff .word 0x7dffffff
|
|
|
|
080013b4 <__aeabi_f2iz>:
|
|
80013b4: 0241 lsls r1, r0, #9
|
|
80013b6: 0042 lsls r2, r0, #1
|
|
80013b8: 0fc3 lsrs r3, r0, #31
|
|
80013ba: 0a49 lsrs r1, r1, #9
|
|
80013bc: 2000 movs r0, #0
|
|
80013be: 0e12 lsrs r2, r2, #24
|
|
80013c0: 2a7e cmp r2, #126 @ 0x7e
|
|
80013c2: dd03 ble.n 80013cc <__aeabi_f2iz+0x18>
|
|
80013c4: 2a9d cmp r2, #157 @ 0x9d
|
|
80013c6: dd02 ble.n 80013ce <__aeabi_f2iz+0x1a>
|
|
80013c8: 4a09 ldr r2, [pc, #36] @ (80013f0 <__aeabi_f2iz+0x3c>)
|
|
80013ca: 1898 adds r0, r3, r2
|
|
80013cc: 4770 bx lr
|
|
80013ce: 2080 movs r0, #128 @ 0x80
|
|
80013d0: 0400 lsls r0, r0, #16
|
|
80013d2: 4301 orrs r1, r0
|
|
80013d4: 2a95 cmp r2, #149 @ 0x95
|
|
80013d6: dc07 bgt.n 80013e8 <__aeabi_f2iz+0x34>
|
|
80013d8: 2096 movs r0, #150 @ 0x96
|
|
80013da: 1a82 subs r2, r0, r2
|
|
80013dc: 40d1 lsrs r1, r2
|
|
80013de: 4248 negs r0, r1
|
|
80013e0: 2b00 cmp r3, #0
|
|
80013e2: d1f3 bne.n 80013cc <__aeabi_f2iz+0x18>
|
|
80013e4: 0008 movs r0, r1
|
|
80013e6: e7f1 b.n 80013cc <__aeabi_f2iz+0x18>
|
|
80013e8: 3a96 subs r2, #150 @ 0x96
|
|
80013ea: 4091 lsls r1, r2
|
|
80013ec: e7f7 b.n 80013de <__aeabi_f2iz+0x2a>
|
|
80013ee: 46c0 nop @ (mov r8, r8)
|
|
80013f0: 7fffffff .word 0x7fffffff
|
|
|
|
080013f4 <__aeabi_i2f>:
|
|
80013f4: b570 push {r4, r5, r6, lr}
|
|
80013f6: 2800 cmp r0, #0
|
|
80013f8: d012 beq.n 8001420 <__aeabi_i2f+0x2c>
|
|
80013fa: 17c3 asrs r3, r0, #31
|
|
80013fc: 18c5 adds r5, r0, r3
|
|
80013fe: 405d eors r5, r3
|
|
8001400: 0fc4 lsrs r4, r0, #31
|
|
8001402: 0028 movs r0, r5
|
|
8001404: f001 f834 bl 8002470 <__clzsi2>
|
|
8001408: 239e movs r3, #158 @ 0x9e
|
|
800140a: 1a1b subs r3, r3, r0
|
|
800140c: 2b96 cmp r3, #150 @ 0x96
|
|
800140e: dc0f bgt.n 8001430 <__aeabi_i2f+0x3c>
|
|
8001410: 2808 cmp r0, #8
|
|
8001412: d038 beq.n 8001486 <__aeabi_i2f+0x92>
|
|
8001414: 3808 subs r0, #8
|
|
8001416: 4085 lsls r5, r0
|
|
8001418: 026d lsls r5, r5, #9
|
|
800141a: 0a6d lsrs r5, r5, #9
|
|
800141c: b2d8 uxtb r0, r3
|
|
800141e: e002 b.n 8001426 <__aeabi_i2f+0x32>
|
|
8001420: 2400 movs r4, #0
|
|
8001422: 2000 movs r0, #0
|
|
8001424: 2500 movs r5, #0
|
|
8001426: 05c0 lsls r0, r0, #23
|
|
8001428: 4328 orrs r0, r5
|
|
800142a: 07e4 lsls r4, r4, #31
|
|
800142c: 4320 orrs r0, r4
|
|
800142e: bd70 pop {r4, r5, r6, pc}
|
|
8001430: 2b99 cmp r3, #153 @ 0x99
|
|
8001432: dc14 bgt.n 800145e <__aeabi_i2f+0x6a>
|
|
8001434: 1f42 subs r2, r0, #5
|
|
8001436: 4095 lsls r5, r2
|
|
8001438: 002a movs r2, r5
|
|
800143a: 4915 ldr r1, [pc, #84] @ (8001490 <__aeabi_i2f+0x9c>)
|
|
800143c: 4011 ands r1, r2
|
|
800143e: 0755 lsls r5, r2, #29
|
|
8001440: d01c beq.n 800147c <__aeabi_i2f+0x88>
|
|
8001442: 250f movs r5, #15
|
|
8001444: 402a ands r2, r5
|
|
8001446: 2a04 cmp r2, #4
|
|
8001448: d018 beq.n 800147c <__aeabi_i2f+0x88>
|
|
800144a: 3104 adds r1, #4
|
|
800144c: 08ca lsrs r2, r1, #3
|
|
800144e: 0149 lsls r1, r1, #5
|
|
8001450: d515 bpl.n 800147e <__aeabi_i2f+0x8a>
|
|
8001452: 239f movs r3, #159 @ 0x9f
|
|
8001454: 0252 lsls r2, r2, #9
|
|
8001456: 1a18 subs r0, r3, r0
|
|
8001458: 0a55 lsrs r5, r2, #9
|
|
800145a: b2c0 uxtb r0, r0
|
|
800145c: e7e3 b.n 8001426 <__aeabi_i2f+0x32>
|
|
800145e: 0002 movs r2, r0
|
|
8001460: 0029 movs r1, r5
|
|
8001462: 321b adds r2, #27
|
|
8001464: 4091 lsls r1, r2
|
|
8001466: 1e4a subs r2, r1, #1
|
|
8001468: 4191 sbcs r1, r2
|
|
800146a: 2205 movs r2, #5
|
|
800146c: 1a12 subs r2, r2, r0
|
|
800146e: 40d5 lsrs r5, r2
|
|
8001470: 002a movs r2, r5
|
|
8001472: 430a orrs r2, r1
|
|
8001474: 4906 ldr r1, [pc, #24] @ (8001490 <__aeabi_i2f+0x9c>)
|
|
8001476: 4011 ands r1, r2
|
|
8001478: 0755 lsls r5, r2, #29
|
|
800147a: d1e2 bne.n 8001442 <__aeabi_i2f+0x4e>
|
|
800147c: 08ca lsrs r2, r1, #3
|
|
800147e: 0252 lsls r2, r2, #9
|
|
8001480: 0a55 lsrs r5, r2, #9
|
|
8001482: b2d8 uxtb r0, r3
|
|
8001484: e7cf b.n 8001426 <__aeabi_i2f+0x32>
|
|
8001486: 026d lsls r5, r5, #9
|
|
8001488: 0a6d lsrs r5, r5, #9
|
|
800148a: 308e adds r0, #142 @ 0x8e
|
|
800148c: e7cb b.n 8001426 <__aeabi_i2f+0x32>
|
|
800148e: 46c0 nop @ (mov r8, r8)
|
|
8001490: fbffffff .word 0xfbffffff
|
|
|
|
08001494 <__aeabi_ui2f>:
|
|
8001494: b510 push {r4, lr}
|
|
8001496: 1e04 subs r4, r0, #0
|
|
8001498: d00d beq.n 80014b6 <__aeabi_ui2f+0x22>
|
|
800149a: f000 ffe9 bl 8002470 <__clzsi2>
|
|
800149e: 239e movs r3, #158 @ 0x9e
|
|
80014a0: 1a1b subs r3, r3, r0
|
|
80014a2: 2b96 cmp r3, #150 @ 0x96
|
|
80014a4: dc0c bgt.n 80014c0 <__aeabi_ui2f+0x2c>
|
|
80014a6: 2808 cmp r0, #8
|
|
80014a8: d034 beq.n 8001514 <__aeabi_ui2f+0x80>
|
|
80014aa: 3808 subs r0, #8
|
|
80014ac: 4084 lsls r4, r0
|
|
80014ae: 0264 lsls r4, r4, #9
|
|
80014b0: 0a64 lsrs r4, r4, #9
|
|
80014b2: b2d8 uxtb r0, r3
|
|
80014b4: e001 b.n 80014ba <__aeabi_ui2f+0x26>
|
|
80014b6: 2000 movs r0, #0
|
|
80014b8: 2400 movs r4, #0
|
|
80014ba: 05c0 lsls r0, r0, #23
|
|
80014bc: 4320 orrs r0, r4
|
|
80014be: bd10 pop {r4, pc}
|
|
80014c0: 2b99 cmp r3, #153 @ 0x99
|
|
80014c2: dc13 bgt.n 80014ec <__aeabi_ui2f+0x58>
|
|
80014c4: 1f42 subs r2, r0, #5
|
|
80014c6: 4094 lsls r4, r2
|
|
80014c8: 4a14 ldr r2, [pc, #80] @ (800151c <__aeabi_ui2f+0x88>)
|
|
80014ca: 4022 ands r2, r4
|
|
80014cc: 0761 lsls r1, r4, #29
|
|
80014ce: d01c beq.n 800150a <__aeabi_ui2f+0x76>
|
|
80014d0: 210f movs r1, #15
|
|
80014d2: 4021 ands r1, r4
|
|
80014d4: 2904 cmp r1, #4
|
|
80014d6: d018 beq.n 800150a <__aeabi_ui2f+0x76>
|
|
80014d8: 3204 adds r2, #4
|
|
80014da: 08d4 lsrs r4, r2, #3
|
|
80014dc: 0152 lsls r2, r2, #5
|
|
80014de: d515 bpl.n 800150c <__aeabi_ui2f+0x78>
|
|
80014e0: 239f movs r3, #159 @ 0x9f
|
|
80014e2: 0264 lsls r4, r4, #9
|
|
80014e4: 1a18 subs r0, r3, r0
|
|
80014e6: 0a64 lsrs r4, r4, #9
|
|
80014e8: b2c0 uxtb r0, r0
|
|
80014ea: e7e6 b.n 80014ba <__aeabi_ui2f+0x26>
|
|
80014ec: 0002 movs r2, r0
|
|
80014ee: 0021 movs r1, r4
|
|
80014f0: 321b adds r2, #27
|
|
80014f2: 4091 lsls r1, r2
|
|
80014f4: 000a movs r2, r1
|
|
80014f6: 1e51 subs r1, r2, #1
|
|
80014f8: 418a sbcs r2, r1
|
|
80014fa: 2105 movs r1, #5
|
|
80014fc: 1a09 subs r1, r1, r0
|
|
80014fe: 40cc lsrs r4, r1
|
|
8001500: 4314 orrs r4, r2
|
|
8001502: 4a06 ldr r2, [pc, #24] @ (800151c <__aeabi_ui2f+0x88>)
|
|
8001504: 4022 ands r2, r4
|
|
8001506: 0761 lsls r1, r4, #29
|
|
8001508: d1e2 bne.n 80014d0 <__aeabi_ui2f+0x3c>
|
|
800150a: 08d4 lsrs r4, r2, #3
|
|
800150c: 0264 lsls r4, r4, #9
|
|
800150e: 0a64 lsrs r4, r4, #9
|
|
8001510: b2d8 uxtb r0, r3
|
|
8001512: e7d2 b.n 80014ba <__aeabi_ui2f+0x26>
|
|
8001514: 0264 lsls r4, r4, #9
|
|
8001516: 0a64 lsrs r4, r4, #9
|
|
8001518: 308e adds r0, #142 @ 0x8e
|
|
800151a: e7ce b.n 80014ba <__aeabi_ui2f+0x26>
|
|
800151c: fbffffff .word 0xfbffffff
|
|
|
|
08001520 <__aeabi_dmul>:
|
|
8001520: b5f0 push {r4, r5, r6, r7, lr}
|
|
8001522: 4657 mov r7, sl
|
|
8001524: 464e mov r6, r9
|
|
8001526: 4645 mov r5, r8
|
|
8001528: 46de mov lr, fp
|
|
800152a: b5e0 push {r5, r6, r7, lr}
|
|
800152c: 001f movs r7, r3
|
|
800152e: 030b lsls r3, r1, #12
|
|
8001530: 0b1b lsrs r3, r3, #12
|
|
8001532: 0016 movs r6, r2
|
|
8001534: 4698 mov r8, r3
|
|
8001536: 0fca lsrs r2, r1, #31
|
|
8001538: 004b lsls r3, r1, #1
|
|
800153a: 0004 movs r4, r0
|
|
800153c: 4692 mov sl, r2
|
|
800153e: b085 sub sp, #20
|
|
8001540: 0d5b lsrs r3, r3, #21
|
|
8001542: d100 bne.n 8001546 <__aeabi_dmul+0x26>
|
|
8001544: e1c2 b.n 80018cc <__aeabi_dmul+0x3ac>
|
|
8001546: 4acc ldr r2, [pc, #816] @ (8001878 <__aeabi_dmul+0x358>)
|
|
8001548: 4293 cmp r3, r2
|
|
800154a: d100 bne.n 800154e <__aeabi_dmul+0x2e>
|
|
800154c: e128 b.n 80017a0 <__aeabi_dmul+0x280>
|
|
800154e: 4641 mov r1, r8
|
|
8001550: 0f42 lsrs r2, r0, #29
|
|
8001552: 00c9 lsls r1, r1, #3
|
|
8001554: 430a orrs r2, r1
|
|
8001556: 2180 movs r1, #128 @ 0x80
|
|
8001558: 0409 lsls r1, r1, #16
|
|
800155a: 4311 orrs r1, r2
|
|
800155c: 00c2 lsls r2, r0, #3
|
|
800155e: 4691 mov r9, r2
|
|
8001560: 4ac6 ldr r2, [pc, #792] @ (800187c <__aeabi_dmul+0x35c>)
|
|
8001562: 4688 mov r8, r1
|
|
8001564: 4693 mov fp, r2
|
|
8001566: 449b add fp, r3
|
|
8001568: 2300 movs r3, #0
|
|
800156a: 2500 movs r5, #0
|
|
800156c: 9301 str r3, [sp, #4]
|
|
800156e: 033c lsls r4, r7, #12
|
|
8001570: 007a lsls r2, r7, #1
|
|
8001572: 0ffb lsrs r3, r7, #31
|
|
8001574: 0030 movs r0, r6
|
|
8001576: 0b24 lsrs r4, r4, #12
|
|
8001578: 0d52 lsrs r2, r2, #21
|
|
800157a: 9300 str r3, [sp, #0]
|
|
800157c: d100 bne.n 8001580 <__aeabi_dmul+0x60>
|
|
800157e: e185 b.n 800188c <__aeabi_dmul+0x36c>
|
|
8001580: 4bbd ldr r3, [pc, #756] @ (8001878 <__aeabi_dmul+0x358>)
|
|
8001582: 429a cmp r2, r3
|
|
8001584: d100 bne.n 8001588 <__aeabi_dmul+0x68>
|
|
8001586: e160 b.n 800184a <__aeabi_dmul+0x32a>
|
|
8001588: 4bbc ldr r3, [pc, #752] @ (800187c <__aeabi_dmul+0x35c>)
|
|
800158a: 469c mov ip, r3
|
|
800158c: 4462 add r2, ip
|
|
800158e: 4493 add fp, r2
|
|
8001590: 2d0a cmp r5, #10
|
|
8001592: dd00 ble.n 8001596 <__aeabi_dmul+0x76>
|
|
8001594: e114 b.n 80017c0 <__aeabi_dmul+0x2a0>
|
|
8001596: 0f73 lsrs r3, r6, #29
|
|
8001598: 00e4 lsls r4, r4, #3
|
|
800159a: 431c orrs r4, r3
|
|
800159c: 2380 movs r3, #128 @ 0x80
|
|
800159e: 041b lsls r3, r3, #16
|
|
80015a0: 4323 orrs r3, r4
|
|
80015a2: 00f0 lsls r0, r6, #3
|
|
80015a4: 4652 mov r2, sl
|
|
80015a6: 9900 ldr r1, [sp, #0]
|
|
80015a8: 2600 movs r6, #0
|
|
80015aa: 404a eors r2, r1
|
|
80015ac: 4692 mov sl, r2
|
|
80015ae: 2d02 cmp r5, #2
|
|
80015b0: dd11 ble.n 80015d6 <__aeabi_dmul+0xb6>
|
|
80015b2: 2201 movs r2, #1
|
|
80015b4: 40aa lsls r2, r5
|
|
80015b6: 21a6 movs r1, #166 @ 0xa6
|
|
80015b8: 0014 movs r4, r2
|
|
80015ba: 00c9 lsls r1, r1, #3
|
|
80015bc: 400c ands r4, r1
|
|
80015be: 420a tst r2, r1
|
|
80015c0: d000 beq.n 80015c4 <__aeabi_dmul+0xa4>
|
|
80015c2: e0fd b.n 80017c0 <__aeabi_dmul+0x2a0>
|
|
80015c4: 2190 movs r1, #144 @ 0x90
|
|
80015c6: 0089 lsls r1, r1, #2
|
|
80015c8: 420a tst r2, r1
|
|
80015ca: d000 beq.n 80015ce <__aeabi_dmul+0xae>
|
|
80015cc: e1d4 b.n 8001978 <__aeabi_dmul+0x458>
|
|
80015ce: 2188 movs r1, #136 @ 0x88
|
|
80015d0: 4211 tst r1, r2
|
|
80015d2: d000 beq.n 80015d6 <__aeabi_dmul+0xb6>
|
|
80015d4: e0ef b.n 80017b6 <__aeabi_dmul+0x296>
|
|
80015d6: 4649 mov r1, r9
|
|
80015d8: 464a mov r2, r9
|
|
80015da: 0409 lsls r1, r1, #16
|
|
80015dc: 0c14 lsrs r4, r2, #16
|
|
80015de: 0c09 lsrs r1, r1, #16
|
|
80015e0: 0c02 lsrs r2, r0, #16
|
|
80015e2: 000f movs r7, r1
|
|
80015e4: 0015 movs r5, r2
|
|
80015e6: 0400 lsls r0, r0, #16
|
|
80015e8: 0c00 lsrs r0, r0, #16
|
|
80015ea: 4365 muls r5, r4
|
|
80015ec: 4347 muls r7, r0
|
|
80015ee: 9501 str r5, [sp, #4]
|
|
80015f0: 46b9 mov r9, r7
|
|
80015f2: 002f movs r7, r5
|
|
80015f4: 000d movs r5, r1
|
|
80015f6: 0006 movs r6, r0
|
|
80015f8: 4355 muls r5, r2
|
|
80015fa: 46ac mov ip, r5
|
|
80015fc: 464d mov r5, r9
|
|
80015fe: 4366 muls r6, r4
|
|
8001600: 0c2d lsrs r5, r5, #16
|
|
8001602: 44b4 add ip, r6
|
|
8001604: 4465 add r5, ip
|
|
8001606: 42ae cmp r6, r5
|
|
8001608: d905 bls.n 8001616 <__aeabi_dmul+0xf6>
|
|
800160a: 003e movs r6, r7
|
|
800160c: 2780 movs r7, #128 @ 0x80
|
|
800160e: 027f lsls r7, r7, #9
|
|
8001610: 46bc mov ip, r7
|
|
8001612: 4466 add r6, ip
|
|
8001614: 9601 str r6, [sp, #4]
|
|
8001616: 464f mov r7, r9
|
|
8001618: 043f lsls r7, r7, #16
|
|
800161a: 0c3f lsrs r7, r7, #16
|
|
800161c: 0c2e lsrs r6, r5, #16
|
|
800161e: 042d lsls r5, r5, #16
|
|
8001620: 19ed adds r5, r5, r7
|
|
8001622: 9502 str r5, [sp, #8]
|
|
8001624: 0c1d lsrs r5, r3, #16
|
|
8001626: 041b lsls r3, r3, #16
|
|
8001628: 0c1b lsrs r3, r3, #16
|
|
800162a: 9500 str r5, [sp, #0]
|
|
800162c: 001d movs r5, r3
|
|
800162e: 001f movs r7, r3
|
|
8001630: 4365 muls r5, r4
|
|
8001632: 434f muls r7, r1
|
|
8001634: 46ac mov ip, r5
|
|
8001636: 9d00 ldr r5, [sp, #0]
|
|
8001638: 4369 muls r1, r5
|
|
800163a: 436c muls r4, r5
|
|
800163c: 0c3d lsrs r5, r7, #16
|
|
800163e: 46a9 mov r9, r5
|
|
8001640: 4461 add r1, ip
|
|
8001642: 4449 add r1, r9
|
|
8001644: 458c cmp ip, r1
|
|
8001646: d903 bls.n 8001650 <__aeabi_dmul+0x130>
|
|
8001648: 2580 movs r5, #128 @ 0x80
|
|
800164a: 026d lsls r5, r5, #9
|
|
800164c: 46ac mov ip, r5
|
|
800164e: 4464 add r4, ip
|
|
8001650: 043f lsls r7, r7, #16
|
|
8001652: 0c0d lsrs r5, r1, #16
|
|
8001654: 0c3f lsrs r7, r7, #16
|
|
8001656: 0409 lsls r1, r1, #16
|
|
8001658: 19c9 adds r1, r1, r7
|
|
800165a: 46ac mov ip, r5
|
|
800165c: 1875 adds r5, r6, r1
|
|
800165e: 9503 str r5, [sp, #12]
|
|
8001660: 4645 mov r5, r8
|
|
8001662: 042e lsls r6, r5, #16
|
|
8001664: 0c36 lsrs r6, r6, #16
|
|
8001666: 0c2f lsrs r7, r5, #16
|
|
8001668: 0035 movs r5, r6
|
|
800166a: 4345 muls r5, r0
|
|
800166c: 4378 muls r0, r7
|
|
800166e: 4680 mov r8, r0
|
|
8001670: 0038 movs r0, r7
|
|
8001672: 4464 add r4, ip
|
|
8001674: 46ac mov ip, r5
|
|
8001676: 0c2d lsrs r5, r5, #16
|
|
8001678: 46a9 mov r9, r5
|
|
800167a: 4350 muls r0, r2
|
|
800167c: 4372 muls r2, r6
|
|
800167e: 4442 add r2, r8
|
|
8001680: 444a add r2, r9
|
|
8001682: 4590 cmp r8, r2
|
|
8001684: d903 bls.n 800168e <__aeabi_dmul+0x16e>
|
|
8001686: 2580 movs r5, #128 @ 0x80
|
|
8001688: 026d lsls r5, r5, #9
|
|
800168a: 46a8 mov r8, r5
|
|
800168c: 4440 add r0, r8
|
|
800168e: 0c15 lsrs r5, r2, #16
|
|
8001690: 46a8 mov r8, r5
|
|
8001692: 4665 mov r5, ip
|
|
8001694: 042d lsls r5, r5, #16
|
|
8001696: 0c2d lsrs r5, r5, #16
|
|
8001698: 46ac mov ip, r5
|
|
800169a: 0035 movs r5, r6
|
|
800169c: 435d muls r5, r3
|
|
800169e: 0412 lsls r2, r2, #16
|
|
80016a0: 4462 add r2, ip
|
|
80016a2: 46ac mov ip, r5
|
|
80016a4: 437b muls r3, r7
|
|
80016a6: 9d00 ldr r5, [sp, #0]
|
|
80016a8: 4440 add r0, r8
|
|
80016aa: 4698 mov r8, r3
|
|
80016ac: 002b movs r3, r5
|
|
80016ae: 436e muls r6, r5
|
|
80016b0: 4665 mov r5, ip
|
|
80016b2: 437b muls r3, r7
|
|
80016b4: 4446 add r6, r8
|
|
80016b6: 0c2d lsrs r5, r5, #16
|
|
80016b8: 19ad adds r5, r5, r6
|
|
80016ba: 001f movs r7, r3
|
|
80016bc: 9300 str r3, [sp, #0]
|
|
80016be: 45a8 cmp r8, r5
|
|
80016c0: d904 bls.n 80016cc <__aeabi_dmul+0x1ac>
|
|
80016c2: 2380 movs r3, #128 @ 0x80
|
|
80016c4: 025b lsls r3, r3, #9
|
|
80016c6: 4698 mov r8, r3
|
|
80016c8: 4447 add r7, r8
|
|
80016ca: 9700 str r7, [sp, #0]
|
|
80016cc: 9b03 ldr r3, [sp, #12]
|
|
80016ce: 9e01 ldr r6, [sp, #4]
|
|
80016d0: 4698 mov r8, r3
|
|
80016d2: 042b lsls r3, r5, #16
|
|
80016d4: 4446 add r6, r8
|
|
80016d6: 4698 mov r8, r3
|
|
80016d8: 4663 mov r3, ip
|
|
80016da: 428e cmp r6, r1
|
|
80016dc: 4189 sbcs r1, r1
|
|
80016de: 041b lsls r3, r3, #16
|
|
80016e0: 0c1b lsrs r3, r3, #16
|
|
80016e2: 4443 add r3, r8
|
|
80016e4: 18b6 adds r6, r6, r2
|
|
80016e6: 4249 negs r1, r1
|
|
80016e8: 191b adds r3, r3, r4
|
|
80016ea: 185f adds r7, r3, r1
|
|
80016ec: 4296 cmp r6, r2
|
|
80016ee: 4192 sbcs r2, r2
|
|
80016f0: 46bc mov ip, r7
|
|
80016f2: 4252 negs r2, r2
|
|
80016f4: 4680 mov r8, r0
|
|
80016f6: 4691 mov r9, r2
|
|
80016f8: 458c cmp ip, r1
|
|
80016fa: 4189 sbcs r1, r1
|
|
80016fc: 42a3 cmp r3, r4
|
|
80016fe: 419b sbcs r3, r3
|
|
8001700: 44e0 add r8, ip
|
|
8001702: 44c1 add r9, r8
|
|
8001704: 4249 negs r1, r1
|
|
8001706: 425b negs r3, r3
|
|
8001708: 4591 cmp r9, r2
|
|
800170a: 4192 sbcs r2, r2
|
|
800170c: 430b orrs r3, r1
|
|
800170e: 4580 cmp r8, r0
|
|
8001710: 4189 sbcs r1, r1
|
|
8001712: 0c2d lsrs r5, r5, #16
|
|
8001714: 4249 negs r1, r1
|
|
8001716: 4252 negs r2, r2
|
|
8001718: 430a orrs r2, r1
|
|
800171a: 195b adds r3, r3, r5
|
|
800171c: 189b adds r3, r3, r2
|
|
800171e: 9a00 ldr r2, [sp, #0]
|
|
8001720: 9902 ldr r1, [sp, #8]
|
|
8001722: 4694 mov ip, r2
|
|
8001724: 464a mov r2, r9
|
|
8001726: 4463 add r3, ip
|
|
8001728: 025b lsls r3, r3, #9
|
|
800172a: 0dd2 lsrs r2, r2, #23
|
|
800172c: 431a orrs r2, r3
|
|
800172e: 4690 mov r8, r2
|
|
8001730: 0272 lsls r2, r6, #9
|
|
8001732: 430a orrs r2, r1
|
|
8001734: 1e51 subs r1, r2, #1
|
|
8001736: 418a sbcs r2, r1
|
|
8001738: 0df6 lsrs r6, r6, #23
|
|
800173a: 4316 orrs r6, r2
|
|
800173c: 464a mov r2, r9
|
|
800173e: 0252 lsls r2, r2, #9
|
|
8001740: 4316 orrs r6, r2
|
|
8001742: 46b1 mov r9, r6
|
|
8001744: 01db lsls r3, r3, #7
|
|
8001746: d454 bmi.n 80017f2 <__aeabi_dmul+0x2d2>
|
|
8001748: 4a4d ldr r2, [pc, #308] @ (8001880 <__aeabi_dmul+0x360>)
|
|
800174a: 445a add r2, fp
|
|
800174c: 2a00 cmp r2, #0
|
|
800174e: dc00 bgt.n 8001752 <__aeabi_dmul+0x232>
|
|
8001750: e118 b.n 8001984 <__aeabi_dmul+0x464>
|
|
8001752: 0033 movs r3, r6
|
|
8001754: 075b lsls r3, r3, #29
|
|
8001756: d015 beq.n 8001784 <__aeabi_dmul+0x264>
|
|
8001758: 210f movs r1, #15
|
|
800175a: 465b mov r3, fp
|
|
800175c: 4031 ands r1, r6
|
|
800175e: 2904 cmp r1, #4
|
|
8001760: d010 beq.n 8001784 <__aeabi_dmul+0x264>
|
|
8001762: 4649 mov r1, r9
|
|
8001764: 1d08 adds r0, r1, #4
|
|
8001766: 4548 cmp r0, r9
|
|
8001768: 4189 sbcs r1, r1
|
|
800176a: 4681 mov r9, r0
|
|
800176c: 4249 negs r1, r1
|
|
800176e: 4488 add r8, r1
|
|
8001770: 4641 mov r1, r8
|
|
8001772: 01c9 lsls r1, r1, #7
|
|
8001774: d506 bpl.n 8001784 <__aeabi_dmul+0x264>
|
|
8001776: 4641 mov r1, r8
|
|
8001778: 4a42 ldr r2, [pc, #264] @ (8001884 <__aeabi_dmul+0x364>)
|
|
800177a: 4011 ands r1, r2
|
|
800177c: 2280 movs r2, #128 @ 0x80
|
|
800177e: 4688 mov r8, r1
|
|
8001780: 00d2 lsls r2, r2, #3
|
|
8001782: 189a adds r2, r3, r2
|
|
8001784: 4b40 ldr r3, [pc, #256] @ (8001888 <__aeabi_dmul+0x368>)
|
|
8001786: 429a cmp r2, r3
|
|
8001788: dd00 ble.n 800178c <__aeabi_dmul+0x26c>
|
|
800178a: e12b b.n 80019e4 <__aeabi_dmul+0x4c4>
|
|
800178c: 4641 mov r1, r8
|
|
800178e: 464b mov r3, r9
|
|
8001790: 074c lsls r4, r1, #29
|
|
8001792: 08db lsrs r3, r3, #3
|
|
8001794: 431c orrs r4, r3
|
|
8001796: 0552 lsls r2, r2, #21
|
|
8001798: 024b lsls r3, r1, #9
|
|
800179a: 0b1b lsrs r3, r3, #12
|
|
800179c: 0d52 lsrs r2, r2, #21
|
|
800179e: e01a b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
80017a0: 4642 mov r2, r8
|
|
80017a2: 4302 orrs r2, r0
|
|
80017a4: 4691 mov r9, r2
|
|
80017a6: d000 beq.n 80017aa <__aeabi_dmul+0x28a>
|
|
80017a8: e0e0 b.n 800196c <__aeabi_dmul+0x44c>
|
|
80017aa: 469b mov fp, r3
|
|
80017ac: 2302 movs r3, #2
|
|
80017ae: 4690 mov r8, r2
|
|
80017b0: 2508 movs r5, #8
|
|
80017b2: 9301 str r3, [sp, #4]
|
|
80017b4: e6db b.n 800156e <__aeabi_dmul+0x4e>
|
|
80017b6: 9a00 ldr r2, [sp, #0]
|
|
80017b8: 4698 mov r8, r3
|
|
80017ba: 4692 mov sl, r2
|
|
80017bc: 4681 mov r9, r0
|
|
80017be: 9601 str r6, [sp, #4]
|
|
80017c0: 9b01 ldr r3, [sp, #4]
|
|
80017c2: 2b02 cmp r3, #2
|
|
80017c4: d100 bne.n 80017c8 <__aeabi_dmul+0x2a8>
|
|
80017c6: e10d b.n 80019e4 <__aeabi_dmul+0x4c4>
|
|
80017c8: 2b03 cmp r3, #3
|
|
80017ca: d035 beq.n 8001838 <__aeabi_dmul+0x318>
|
|
80017cc: 2b01 cmp r3, #1
|
|
80017ce: d11b bne.n 8001808 <__aeabi_dmul+0x2e8>
|
|
80017d0: 2200 movs r2, #0
|
|
80017d2: 2300 movs r3, #0
|
|
80017d4: 2400 movs r4, #0
|
|
80017d6: 0512 lsls r2, r2, #20
|
|
80017d8: 431a orrs r2, r3
|
|
80017da: 4653 mov r3, sl
|
|
80017dc: 07db lsls r3, r3, #31
|
|
80017de: 431a orrs r2, r3
|
|
80017e0: 0020 movs r0, r4
|
|
80017e2: 0011 movs r1, r2
|
|
80017e4: b005 add sp, #20
|
|
80017e6: bcf0 pop {r4, r5, r6, r7}
|
|
80017e8: 46bb mov fp, r7
|
|
80017ea: 46b2 mov sl, r6
|
|
80017ec: 46a9 mov r9, r5
|
|
80017ee: 46a0 mov r8, r4
|
|
80017f0: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80017f2: 2201 movs r2, #1
|
|
80017f4: 0873 lsrs r3, r6, #1
|
|
80017f6: 4032 ands r2, r6
|
|
80017f8: 4313 orrs r3, r2
|
|
80017fa: 4642 mov r2, r8
|
|
80017fc: 07d2 lsls r2, r2, #31
|
|
80017fe: 4313 orrs r3, r2
|
|
8001800: 4699 mov r9, r3
|
|
8001802: 4643 mov r3, r8
|
|
8001804: 085b lsrs r3, r3, #1
|
|
8001806: 4698 mov r8, r3
|
|
8001808: 2280 movs r2, #128 @ 0x80
|
|
800180a: 465b mov r3, fp
|
|
800180c: 00d2 lsls r2, r2, #3
|
|
800180e: 445a add r2, fp
|
|
8001810: 3301 adds r3, #1
|
|
8001812: 2a00 cmp r2, #0
|
|
8001814: dc00 bgt.n 8001818 <__aeabi_dmul+0x2f8>
|
|
8001816: e0b6 b.n 8001986 <__aeabi_dmul+0x466>
|
|
8001818: 4649 mov r1, r9
|
|
800181a: 0749 lsls r1, r1, #29
|
|
800181c: d0a8 beq.n 8001770 <__aeabi_dmul+0x250>
|
|
800181e: 210f movs r1, #15
|
|
8001820: 4648 mov r0, r9
|
|
8001822: 4001 ands r1, r0
|
|
8001824: 2904 cmp r1, #4
|
|
8001826: d19c bne.n 8001762 <__aeabi_dmul+0x242>
|
|
8001828: e7a2 b.n 8001770 <__aeabi_dmul+0x250>
|
|
800182a: 2d0f cmp r5, #15
|
|
800182c: d100 bne.n 8001830 <__aeabi_dmul+0x310>
|
|
800182e: e0fd b.n 8001a2c <__aeabi_dmul+0x50c>
|
|
8001830: 9b00 ldr r3, [sp, #0]
|
|
8001832: 46a0 mov r8, r4
|
|
8001834: 469a mov sl, r3
|
|
8001836: 46b1 mov r9, r6
|
|
8001838: 2380 movs r3, #128 @ 0x80
|
|
800183a: 4642 mov r2, r8
|
|
800183c: 031b lsls r3, r3, #12
|
|
800183e: 4313 orrs r3, r2
|
|
8001840: 031b lsls r3, r3, #12
|
|
8001842: 464c mov r4, r9
|
|
8001844: 4a0c ldr r2, [pc, #48] @ (8001878 <__aeabi_dmul+0x358>)
|
|
8001846: 0b1b lsrs r3, r3, #12
|
|
8001848: e7c5 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
800184a: 490b ldr r1, [pc, #44] @ (8001878 <__aeabi_dmul+0x358>)
|
|
800184c: 0033 movs r3, r6
|
|
800184e: 468c mov ip, r1
|
|
8001850: 4323 orrs r3, r4
|
|
8001852: 44e3 add fp, ip
|
|
8001854: 2b00 cmp r3, #0
|
|
8001856: d177 bne.n 8001948 <__aeabi_dmul+0x428>
|
|
8001858: 2102 movs r1, #2
|
|
800185a: 4329 orrs r1, r5
|
|
800185c: 290a cmp r1, #10
|
|
800185e: dcaf bgt.n 80017c0 <__aeabi_dmul+0x2a0>
|
|
8001860: 4650 mov r0, sl
|
|
8001862: 9c00 ldr r4, [sp, #0]
|
|
8001864: 4060 eors r0, r4
|
|
8001866: 4682 mov sl, r0
|
|
8001868: 2d00 cmp r5, #0
|
|
800186a: d100 bne.n 800186e <__aeabi_dmul+0x34e>
|
|
800186c: e10e b.n 8001a8c <__aeabi_dmul+0x56c>
|
|
800186e: 000d movs r5, r1
|
|
8001870: 2000 movs r0, #0
|
|
8001872: 2602 movs r6, #2
|
|
8001874: e69d b.n 80015b2 <__aeabi_dmul+0x92>
|
|
8001876: 46c0 nop @ (mov r8, r8)
|
|
8001878: 000007ff .word 0x000007ff
|
|
800187c: fffffc01 .word 0xfffffc01
|
|
8001880: 000003ff .word 0x000003ff
|
|
8001884: feffffff .word 0xfeffffff
|
|
8001888: 000007fe .word 0x000007fe
|
|
800188c: 0023 movs r3, r4
|
|
800188e: 4333 orrs r3, r6
|
|
8001890: d04b beq.n 800192a <__aeabi_dmul+0x40a>
|
|
8001892: 2c00 cmp r4, #0
|
|
8001894: d100 bne.n 8001898 <__aeabi_dmul+0x378>
|
|
8001896: e0bb b.n 8001a10 <__aeabi_dmul+0x4f0>
|
|
8001898: 0020 movs r0, r4
|
|
800189a: f000 fde9 bl 8002470 <__clzsi2>
|
|
800189e: 0003 movs r3, r0
|
|
80018a0: 0002 movs r2, r0
|
|
80018a2: 3b0b subs r3, #11
|
|
80018a4: 201d movs r0, #29
|
|
80018a6: 1ac3 subs r3, r0, r3
|
|
80018a8: 0030 movs r0, r6
|
|
80018aa: 40d8 lsrs r0, r3
|
|
80018ac: 0011 movs r1, r2
|
|
80018ae: 0003 movs r3, r0
|
|
80018b0: 0030 movs r0, r6
|
|
80018b2: 3908 subs r1, #8
|
|
80018b4: 408c lsls r4, r1
|
|
80018b6: 4088 lsls r0, r1
|
|
80018b8: 4323 orrs r3, r4
|
|
80018ba: 4659 mov r1, fp
|
|
80018bc: 1a8a subs r2, r1, r2
|
|
80018be: 4978 ldr r1, [pc, #480] @ (8001aa0 <__aeabi_dmul+0x580>)
|
|
80018c0: 468b mov fp, r1
|
|
80018c2: 4493 add fp, r2
|
|
80018c4: 2d0a cmp r5, #10
|
|
80018c6: dc00 bgt.n 80018ca <__aeabi_dmul+0x3aa>
|
|
80018c8: e66c b.n 80015a4 <__aeabi_dmul+0x84>
|
|
80018ca: e779 b.n 80017c0 <__aeabi_dmul+0x2a0>
|
|
80018cc: 4643 mov r3, r8
|
|
80018ce: 4303 orrs r3, r0
|
|
80018d0: 4699 mov r9, r3
|
|
80018d2: d023 beq.n 800191c <__aeabi_dmul+0x3fc>
|
|
80018d4: 4643 mov r3, r8
|
|
80018d6: 2b00 cmp r3, #0
|
|
80018d8: d100 bne.n 80018dc <__aeabi_dmul+0x3bc>
|
|
80018da: e087 b.n 80019ec <__aeabi_dmul+0x4cc>
|
|
80018dc: 4640 mov r0, r8
|
|
80018de: f000 fdc7 bl 8002470 <__clzsi2>
|
|
80018e2: 230b movs r3, #11
|
|
80018e4: 425b negs r3, r3
|
|
80018e6: 469c mov ip, r3
|
|
80018e8: 0002 movs r2, r0
|
|
80018ea: 4484 add ip, r0
|
|
80018ec: 0011 movs r1, r2
|
|
80018ee: 4640 mov r0, r8
|
|
80018f0: 3908 subs r1, #8
|
|
80018f2: 4088 lsls r0, r1
|
|
80018f4: 231d movs r3, #29
|
|
80018f6: 4680 mov r8, r0
|
|
80018f8: 4660 mov r0, ip
|
|
80018fa: 1a1b subs r3, r3, r0
|
|
80018fc: 0020 movs r0, r4
|
|
80018fe: 40d8 lsrs r0, r3
|
|
8001900: 0003 movs r3, r0
|
|
8001902: 4640 mov r0, r8
|
|
8001904: 4303 orrs r3, r0
|
|
8001906: 4698 mov r8, r3
|
|
8001908: 0023 movs r3, r4
|
|
800190a: 408b lsls r3, r1
|
|
800190c: 4699 mov r9, r3
|
|
800190e: 4b64 ldr r3, [pc, #400] @ (8001aa0 <__aeabi_dmul+0x580>)
|
|
8001910: 2500 movs r5, #0
|
|
8001912: 1a9b subs r3, r3, r2
|
|
8001914: 469b mov fp, r3
|
|
8001916: 2300 movs r3, #0
|
|
8001918: 9301 str r3, [sp, #4]
|
|
800191a: e628 b.n 800156e <__aeabi_dmul+0x4e>
|
|
800191c: 2300 movs r3, #0
|
|
800191e: 4698 mov r8, r3
|
|
8001920: 469b mov fp, r3
|
|
8001922: 3301 adds r3, #1
|
|
8001924: 2504 movs r5, #4
|
|
8001926: 9301 str r3, [sp, #4]
|
|
8001928: e621 b.n 800156e <__aeabi_dmul+0x4e>
|
|
800192a: 2201 movs r2, #1
|
|
800192c: 4315 orrs r5, r2
|
|
800192e: 2d0a cmp r5, #10
|
|
8001930: dd00 ble.n 8001934 <__aeabi_dmul+0x414>
|
|
8001932: e745 b.n 80017c0 <__aeabi_dmul+0x2a0>
|
|
8001934: 4652 mov r2, sl
|
|
8001936: 9900 ldr r1, [sp, #0]
|
|
8001938: 404a eors r2, r1
|
|
800193a: 4692 mov sl, r2
|
|
800193c: 2d02 cmp r5, #2
|
|
800193e: dc00 bgt.n 8001942 <__aeabi_dmul+0x422>
|
|
8001940: e746 b.n 80017d0 <__aeabi_dmul+0x2b0>
|
|
8001942: 2000 movs r0, #0
|
|
8001944: 2601 movs r6, #1
|
|
8001946: e634 b.n 80015b2 <__aeabi_dmul+0x92>
|
|
8001948: 2303 movs r3, #3
|
|
800194a: 431d orrs r5, r3
|
|
800194c: 2d0a cmp r5, #10
|
|
800194e: dd00 ble.n 8001952 <__aeabi_dmul+0x432>
|
|
8001950: e76b b.n 800182a <__aeabi_dmul+0x30a>
|
|
8001952: 4653 mov r3, sl
|
|
8001954: 9a00 ldr r2, [sp, #0]
|
|
8001956: 2188 movs r1, #136 @ 0x88
|
|
8001958: 4053 eors r3, r2
|
|
800195a: 2201 movs r2, #1
|
|
800195c: 40aa lsls r2, r5
|
|
800195e: 469a mov sl, r3
|
|
8001960: 2603 movs r6, #3
|
|
8001962: 0023 movs r3, r4
|
|
8001964: 4211 tst r1, r2
|
|
8001966: d100 bne.n 800196a <__aeabi_dmul+0x44a>
|
|
8001968: e635 b.n 80015d6 <__aeabi_dmul+0xb6>
|
|
800196a: e724 b.n 80017b6 <__aeabi_dmul+0x296>
|
|
800196c: 469b mov fp, r3
|
|
800196e: 2303 movs r3, #3
|
|
8001970: 4681 mov r9, r0
|
|
8001972: 250c movs r5, #12
|
|
8001974: 9301 str r3, [sp, #4]
|
|
8001976: e5fa b.n 800156e <__aeabi_dmul+0x4e>
|
|
8001978: 2300 movs r3, #0
|
|
800197a: 469a mov sl, r3
|
|
800197c: 2380 movs r3, #128 @ 0x80
|
|
800197e: 4a49 ldr r2, [pc, #292] @ (8001aa4 <__aeabi_dmul+0x584>)
|
|
8001980: 031b lsls r3, r3, #12
|
|
8001982: e728 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
8001984: 465b mov r3, fp
|
|
8001986: 2101 movs r1, #1
|
|
8001988: 1a89 subs r1, r1, r2
|
|
800198a: 2938 cmp r1, #56 @ 0x38
|
|
800198c: dd00 ble.n 8001990 <__aeabi_dmul+0x470>
|
|
800198e: e71f b.n 80017d0 <__aeabi_dmul+0x2b0>
|
|
8001990: 291f cmp r1, #31
|
|
8001992: dd5a ble.n 8001a4a <__aeabi_dmul+0x52a>
|
|
8001994: 201f movs r0, #31
|
|
8001996: 4240 negs r0, r0
|
|
8001998: 1a82 subs r2, r0, r2
|
|
800199a: 4640 mov r0, r8
|
|
800199c: 40d0 lsrs r0, r2
|
|
800199e: 2920 cmp r1, #32
|
|
80019a0: d008 beq.n 80019b4 <__aeabi_dmul+0x494>
|
|
80019a2: 4a41 ldr r2, [pc, #260] @ (8001aa8 <__aeabi_dmul+0x588>)
|
|
80019a4: 4694 mov ip, r2
|
|
80019a6: 4642 mov r2, r8
|
|
80019a8: 4463 add r3, ip
|
|
80019aa: 409a lsls r2, r3
|
|
80019ac: 0013 movs r3, r2
|
|
80019ae: 464a mov r2, r9
|
|
80019b0: 431a orrs r2, r3
|
|
80019b2: 4691 mov r9, r2
|
|
80019b4: 464a mov r2, r9
|
|
80019b6: 2107 movs r1, #7
|
|
80019b8: 1e53 subs r3, r2, #1
|
|
80019ba: 419a sbcs r2, r3
|
|
80019bc: 000c movs r4, r1
|
|
80019be: 4302 orrs r2, r0
|
|
80019c0: 2300 movs r3, #0
|
|
80019c2: 4014 ands r4, r2
|
|
80019c4: 4211 tst r1, r2
|
|
80019c6: d009 beq.n 80019dc <__aeabi_dmul+0x4bc>
|
|
80019c8: 3108 adds r1, #8
|
|
80019ca: 4011 ands r1, r2
|
|
80019cc: 2904 cmp r1, #4
|
|
80019ce: d060 beq.n 8001a92 <__aeabi_dmul+0x572>
|
|
80019d0: 1d11 adds r1, r2, #4
|
|
80019d2: 4291 cmp r1, r2
|
|
80019d4: 41a4 sbcs r4, r4
|
|
80019d6: 000a movs r2, r1
|
|
80019d8: 4264 negs r4, r4
|
|
80019da: 0764 lsls r4, r4, #29
|
|
80019dc: 08d2 lsrs r2, r2, #3
|
|
80019de: 4314 orrs r4, r2
|
|
80019e0: 2200 movs r2, #0
|
|
80019e2: e6f8 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
80019e4: 2300 movs r3, #0
|
|
80019e6: 2400 movs r4, #0
|
|
80019e8: 4a2e ldr r2, [pc, #184] @ (8001aa4 <__aeabi_dmul+0x584>)
|
|
80019ea: e6f4 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
80019ec: f000 fd40 bl 8002470 <__clzsi2>
|
|
80019f0: 2315 movs r3, #21
|
|
80019f2: 469c mov ip, r3
|
|
80019f4: 4484 add ip, r0
|
|
80019f6: 0002 movs r2, r0
|
|
80019f8: 4663 mov r3, ip
|
|
80019fa: 3220 adds r2, #32
|
|
80019fc: 2b1c cmp r3, #28
|
|
80019fe: dc00 bgt.n 8001a02 <__aeabi_dmul+0x4e2>
|
|
8001a00: e774 b.n 80018ec <__aeabi_dmul+0x3cc>
|
|
8001a02: 2300 movs r3, #0
|
|
8001a04: 4699 mov r9, r3
|
|
8001a06: 0023 movs r3, r4
|
|
8001a08: 3808 subs r0, #8
|
|
8001a0a: 4083 lsls r3, r0
|
|
8001a0c: 4698 mov r8, r3
|
|
8001a0e: e77e b.n 800190e <__aeabi_dmul+0x3ee>
|
|
8001a10: f000 fd2e bl 8002470 <__clzsi2>
|
|
8001a14: 0003 movs r3, r0
|
|
8001a16: 0002 movs r2, r0
|
|
8001a18: 3315 adds r3, #21
|
|
8001a1a: 3220 adds r2, #32
|
|
8001a1c: 2b1c cmp r3, #28
|
|
8001a1e: dc00 bgt.n 8001a22 <__aeabi_dmul+0x502>
|
|
8001a20: e740 b.n 80018a4 <__aeabi_dmul+0x384>
|
|
8001a22: 0033 movs r3, r6
|
|
8001a24: 3808 subs r0, #8
|
|
8001a26: 4083 lsls r3, r0
|
|
8001a28: 2000 movs r0, #0
|
|
8001a2a: e746 b.n 80018ba <__aeabi_dmul+0x39a>
|
|
8001a2c: 2380 movs r3, #128 @ 0x80
|
|
8001a2e: 4642 mov r2, r8
|
|
8001a30: 031b lsls r3, r3, #12
|
|
8001a32: 421a tst r2, r3
|
|
8001a34: d100 bne.n 8001a38 <__aeabi_dmul+0x518>
|
|
8001a36: e6ff b.n 8001838 <__aeabi_dmul+0x318>
|
|
8001a38: 421c tst r4, r3
|
|
8001a3a: d000 beq.n 8001a3e <__aeabi_dmul+0x51e>
|
|
8001a3c: e6fc b.n 8001838 <__aeabi_dmul+0x318>
|
|
8001a3e: 9a00 ldr r2, [sp, #0]
|
|
8001a40: 4323 orrs r3, r4
|
|
8001a42: 4692 mov sl, r2
|
|
8001a44: 0034 movs r4, r6
|
|
8001a46: 4a17 ldr r2, [pc, #92] @ (8001aa4 <__aeabi_dmul+0x584>)
|
|
8001a48: e6c5 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
8001a4a: 4a18 ldr r2, [pc, #96] @ (8001aac <__aeabi_dmul+0x58c>)
|
|
8001a4c: 4640 mov r0, r8
|
|
8001a4e: 4694 mov ip, r2
|
|
8001a50: 464a mov r2, r9
|
|
8001a52: 4463 add r3, ip
|
|
8001a54: 4098 lsls r0, r3
|
|
8001a56: 40ca lsrs r2, r1
|
|
8001a58: 4310 orrs r0, r2
|
|
8001a5a: 464a mov r2, r9
|
|
8001a5c: 409a lsls r2, r3
|
|
8001a5e: 1e53 subs r3, r2, #1
|
|
8001a60: 419a sbcs r2, r3
|
|
8001a62: 4643 mov r3, r8
|
|
8001a64: 4302 orrs r2, r0
|
|
8001a66: 40cb lsrs r3, r1
|
|
8001a68: 0751 lsls r1, r2, #29
|
|
8001a6a: d009 beq.n 8001a80 <__aeabi_dmul+0x560>
|
|
8001a6c: 210f movs r1, #15
|
|
8001a6e: 4011 ands r1, r2
|
|
8001a70: 2904 cmp r1, #4
|
|
8001a72: d005 beq.n 8001a80 <__aeabi_dmul+0x560>
|
|
8001a74: 1d11 adds r1, r2, #4
|
|
8001a76: 4291 cmp r1, r2
|
|
8001a78: 4192 sbcs r2, r2
|
|
8001a7a: 4252 negs r2, r2
|
|
8001a7c: 189b adds r3, r3, r2
|
|
8001a7e: 000a movs r2, r1
|
|
8001a80: 0219 lsls r1, r3, #8
|
|
8001a82: d508 bpl.n 8001a96 <__aeabi_dmul+0x576>
|
|
8001a84: 2201 movs r2, #1
|
|
8001a86: 2300 movs r3, #0
|
|
8001a88: 2400 movs r4, #0
|
|
8001a8a: e6a4 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
8001a8c: 2300 movs r3, #0
|
|
8001a8e: 2400 movs r4, #0
|
|
8001a90: e6a1 b.n 80017d6 <__aeabi_dmul+0x2b6>
|
|
8001a92: 2400 movs r4, #0
|
|
8001a94: e7a2 b.n 80019dc <__aeabi_dmul+0x4bc>
|
|
8001a96: 075c lsls r4, r3, #29
|
|
8001a98: 025b lsls r3, r3, #9
|
|
8001a9a: 0b1b lsrs r3, r3, #12
|
|
8001a9c: e79e b.n 80019dc <__aeabi_dmul+0x4bc>
|
|
8001a9e: 46c0 nop @ (mov r8, r8)
|
|
8001aa0: fffffc0d .word 0xfffffc0d
|
|
8001aa4: 000007ff .word 0x000007ff
|
|
8001aa8: 0000043e .word 0x0000043e
|
|
8001aac: 0000041e .word 0x0000041e
|
|
|
|
08001ab0 <__aeabi_dsub>:
|
|
8001ab0: b5f0 push {r4, r5, r6, r7, lr}
|
|
8001ab2: 464e mov r6, r9
|
|
8001ab4: 4645 mov r5, r8
|
|
8001ab6: 46de mov lr, fp
|
|
8001ab8: 4657 mov r7, sl
|
|
8001aba: b5e0 push {r5, r6, r7, lr}
|
|
8001abc: b083 sub sp, #12
|
|
8001abe: 9000 str r0, [sp, #0]
|
|
8001ac0: 9101 str r1, [sp, #4]
|
|
8001ac2: 030d lsls r5, r1, #12
|
|
8001ac4: 004e lsls r6, r1, #1
|
|
8001ac6: 9901 ldr r1, [sp, #4]
|
|
8001ac8: 0d76 lsrs r6, r6, #21
|
|
8001aca: 0fcc lsrs r4, r1, #31
|
|
8001acc: 0a69 lsrs r1, r5, #9
|
|
8001ace: 9d00 ldr r5, [sp, #0]
|
|
8001ad0: 0f6d lsrs r5, r5, #29
|
|
8001ad2: 430d orrs r5, r1
|
|
8001ad4: 9900 ldr r1, [sp, #0]
|
|
8001ad6: 9200 str r2, [sp, #0]
|
|
8001ad8: 9301 str r3, [sp, #4]
|
|
8001ada: 00c8 lsls r0, r1, #3
|
|
8001adc: 0319 lsls r1, r3, #12
|
|
8001ade: 9b01 ldr r3, [sp, #4]
|
|
8001ae0: 4acb ldr r2, [pc, #812] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001ae2: 005b lsls r3, r3, #1
|
|
8001ae4: 0d5b lsrs r3, r3, #21
|
|
8001ae6: 4699 mov r9, r3
|
|
8001ae8: 9b01 ldr r3, [sp, #4]
|
|
8001aea: 4683 mov fp, r0
|
|
8001aec: 0fdb lsrs r3, r3, #31
|
|
8001aee: 4698 mov r8, r3
|
|
8001af0: 0a4b lsrs r3, r1, #9
|
|
8001af2: 9900 ldr r1, [sp, #0]
|
|
8001af4: 0f49 lsrs r1, r1, #29
|
|
8001af6: 4319 orrs r1, r3
|
|
8001af8: 9b00 ldr r3, [sp, #0]
|
|
8001afa: 00db lsls r3, r3, #3
|
|
8001afc: 469c mov ip, r3
|
|
8001afe: 469a mov sl, r3
|
|
8001b00: 4591 cmp r9, r2
|
|
8001b02: d100 bne.n 8001b06 <__aeabi_dsub+0x56>
|
|
8001b04: e073 b.n 8001bee <__aeabi_dsub+0x13e>
|
|
8001b06: 2301 movs r3, #1
|
|
8001b08: 4647 mov r7, r8
|
|
8001b0a: 405f eors r7, r3
|
|
8001b0c: 464b mov r3, r9
|
|
8001b0e: 46b8 mov r8, r7
|
|
8001b10: 1af3 subs r3, r6, r3
|
|
8001b12: 42bc cmp r4, r7
|
|
8001b14: d016 beq.n 8001b44 <__aeabi_dsub+0x94>
|
|
8001b16: 2b00 cmp r3, #0
|
|
8001b18: dc00 bgt.n 8001b1c <__aeabi_dsub+0x6c>
|
|
8001b1a: e29a b.n 8002052 <__aeabi_dsub+0x5a2>
|
|
8001b1c: 464f mov r7, r9
|
|
8001b1e: 2f00 cmp r7, #0
|
|
8001b20: d000 beq.n 8001b24 <__aeabi_dsub+0x74>
|
|
8001b22: e082 b.n 8001c2a <__aeabi_dsub+0x17a>
|
|
8001b24: 4667 mov r7, ip
|
|
8001b26: 430f orrs r7, r1
|
|
8001b28: d100 bne.n 8001b2c <__aeabi_dsub+0x7c>
|
|
8001b2a: e13a b.n 8001da2 <__aeabi_dsub+0x2f2>
|
|
8001b2c: 1e5f subs r7, r3, #1
|
|
8001b2e: 2b01 cmp r3, #1
|
|
8001b30: d100 bne.n 8001b34 <__aeabi_dsub+0x84>
|
|
8001b32: e2a4 b.n 800207e <__aeabi_dsub+0x5ce>
|
|
8001b34: 4293 cmp r3, r2
|
|
8001b36: d100 bne.n 8001b3a <__aeabi_dsub+0x8a>
|
|
8001b38: e12e b.n 8001d98 <__aeabi_dsub+0x2e8>
|
|
8001b3a: 2f38 cmp r7, #56 @ 0x38
|
|
8001b3c: dd00 ble.n 8001b40 <__aeabi_dsub+0x90>
|
|
8001b3e: e243 b.n 8001fc8 <__aeabi_dsub+0x518>
|
|
8001b40: 003b movs r3, r7
|
|
8001b42: e13e b.n 8001dc2 <__aeabi_dsub+0x312>
|
|
8001b44: 2b00 cmp r3, #0
|
|
8001b46: dc00 bgt.n 8001b4a <__aeabi_dsub+0x9a>
|
|
8001b48: e2d7 b.n 80020fa <__aeabi_dsub+0x64a>
|
|
8001b4a: 464f mov r7, r9
|
|
8001b4c: 2f00 cmp r7, #0
|
|
8001b4e: d000 beq.n 8001b52 <__aeabi_dsub+0xa2>
|
|
8001b50: e0f8 b.n 8001d44 <__aeabi_dsub+0x294>
|
|
8001b52: 4667 mov r7, ip
|
|
8001b54: 430f orrs r7, r1
|
|
8001b56: d100 bne.n 8001b5a <__aeabi_dsub+0xaa>
|
|
8001b58: e123 b.n 8001da2 <__aeabi_dsub+0x2f2>
|
|
8001b5a: 1e5f subs r7, r3, #1
|
|
8001b5c: 2b01 cmp r3, #1
|
|
8001b5e: d100 bne.n 8001b62 <__aeabi_dsub+0xb2>
|
|
8001b60: e257 b.n 8002012 <__aeabi_dsub+0x562>
|
|
8001b62: 4293 cmp r3, r2
|
|
8001b64: d100 bne.n 8001b68 <__aeabi_dsub+0xb8>
|
|
8001b66: e117 b.n 8001d98 <__aeabi_dsub+0x2e8>
|
|
8001b68: 2f38 cmp r7, #56 @ 0x38
|
|
8001b6a: dc00 bgt.n 8001b6e <__aeabi_dsub+0xbe>
|
|
8001b6c: e304 b.n 8002178 <__aeabi_dsub+0x6c8>
|
|
8001b6e: 2280 movs r2, #128 @ 0x80
|
|
8001b70: 0412 lsls r2, r2, #16
|
|
8001b72: 4215 tst r5, r2
|
|
8001b74: d100 bne.n 8001b78 <__aeabi_dsub+0xc8>
|
|
8001b76: e3aa b.n 80022ce <__aeabi_dsub+0x81e>
|
|
8001b78: 001e movs r6, r3
|
|
8001b7a: 0015 movs r5, r2
|
|
8001b7c: 2700 movs r7, #0
|
|
8001b7e: 4ba4 ldr r3, [pc, #656] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001b80: 3601 adds r6, #1
|
|
8001b82: 429e cmp r6, r3
|
|
8001b84: d100 bne.n 8001b88 <__aeabi_dsub+0xd8>
|
|
8001b86: e103 b.n 8001d90 <__aeabi_dsub+0x2e0>
|
|
8001b88: 2201 movs r2, #1
|
|
8001b8a: 4ba2 ldr r3, [pc, #648] @ (8001e14 <__aeabi_dsub+0x364>)
|
|
8001b8c: 403a ands r2, r7
|
|
8001b8e: 401d ands r5, r3
|
|
8001b90: 0879 lsrs r1, r7, #1
|
|
8001b92: 4311 orrs r1, r2
|
|
8001b94: 07ea lsls r2, r5, #31
|
|
8001b96: 430a orrs r2, r1
|
|
8001b98: 086d lsrs r5, r5, #1
|
|
8001b9a: 0753 lsls r3, r2, #29
|
|
8001b9c: d009 beq.n 8001bb2 <__aeabi_dsub+0x102>
|
|
8001b9e: 230f movs r3, #15
|
|
8001ba0: 4013 ands r3, r2
|
|
8001ba2: 2b04 cmp r3, #4
|
|
8001ba4: d005 beq.n 8001bb2 <__aeabi_dsub+0x102>
|
|
8001ba6: 0017 movs r7, r2
|
|
8001ba8: 1d3a adds r2, r7, #4
|
|
8001baa: 42ba cmp r2, r7
|
|
8001bac: 41bf sbcs r7, r7
|
|
8001bae: 427f negs r7, r7
|
|
8001bb0: 19ed adds r5, r5, r7
|
|
8001bb2: 022b lsls r3, r5, #8
|
|
8001bb4: d400 bmi.n 8001bb8 <__aeabi_dsub+0x108>
|
|
8001bb6: e377 b.n 80022a8 <__aeabi_dsub+0x7f8>
|
|
8001bb8: 4995 ldr r1, [pc, #596] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001bba: 3601 adds r6, #1
|
|
8001bbc: 428e cmp r6, r1
|
|
8001bbe: d100 bne.n 8001bc2 <__aeabi_dsub+0x112>
|
|
8001bc0: e0e6 b.n 8001d90 <__aeabi_dsub+0x2e0>
|
|
8001bc2: 4994 ldr r1, [pc, #592] @ (8001e14 <__aeabi_dsub+0x364>)
|
|
8001bc4: 0573 lsls r3, r6, #21
|
|
8001bc6: 400d ands r5, r1
|
|
8001bc8: 0d5b lsrs r3, r3, #21
|
|
8001bca: 0769 lsls r1, r5, #29
|
|
8001bcc: 08d2 lsrs r2, r2, #3
|
|
8001bce: 026d lsls r5, r5, #9
|
|
8001bd0: 430a orrs r2, r1
|
|
8001bd2: 0b2d lsrs r5, r5, #12
|
|
8001bd4: 051b lsls r3, r3, #20
|
|
8001bd6: 432b orrs r3, r5
|
|
8001bd8: 07e4 lsls r4, r4, #31
|
|
8001bda: 4323 orrs r3, r4
|
|
8001bdc: 0010 movs r0, r2
|
|
8001bde: 0019 movs r1, r3
|
|
8001be0: b003 add sp, #12
|
|
8001be2: bcf0 pop {r4, r5, r6, r7}
|
|
8001be4: 46bb mov fp, r7
|
|
8001be6: 46b2 mov sl, r6
|
|
8001be8: 46a9 mov r9, r5
|
|
8001bea: 46a0 mov r8, r4
|
|
8001bec: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8001bee: 4b8a ldr r3, [pc, #552] @ (8001e18 <__aeabi_dsub+0x368>)
|
|
8001bf0: 18f2 adds r2, r6, r3
|
|
8001bf2: 4663 mov r3, ip
|
|
8001bf4: 430b orrs r3, r1
|
|
8001bf6: d04c beq.n 8001c92 <__aeabi_dsub+0x1e2>
|
|
8001bf8: 4544 cmp r4, r8
|
|
8001bfa: d050 beq.n 8001c9e <__aeabi_dsub+0x1ee>
|
|
8001bfc: 2a00 cmp r2, #0
|
|
8001bfe: d06c beq.n 8001cda <__aeabi_dsub+0x22a>
|
|
8001c00: 2e00 cmp r6, #0
|
|
8001c02: d100 bne.n 8001c06 <__aeabi_dsub+0x156>
|
|
8001c04: e17d b.n 8001f02 <__aeabi_dsub+0x452>
|
|
8001c06: 4663 mov r3, ip
|
|
8001c08: 4644 mov r4, r8
|
|
8001c0a: 074f lsls r7, r1, #29
|
|
8001c0c: 08da lsrs r2, r3, #3
|
|
8001c0e: 4317 orrs r7, r2
|
|
8001c10: 08c8 lsrs r0, r1, #3
|
|
8001c12: 003a movs r2, r7
|
|
8001c14: 4302 orrs r2, r0
|
|
8001c16: d100 bne.n 8001c1a <__aeabi_dsub+0x16a>
|
|
8001c18: e0cd b.n 8001db6 <__aeabi_dsub+0x306>
|
|
8001c1a: 2580 movs r5, #128 @ 0x80
|
|
8001c1c: 032d lsls r5, r5, #12
|
|
8001c1e: 4305 orrs r5, r0
|
|
8001c20: 032d lsls r5, r5, #12
|
|
8001c22: 003a movs r2, r7
|
|
8001c24: 4b7a ldr r3, [pc, #488] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001c26: 0b2d lsrs r5, r5, #12
|
|
8001c28: e7d4 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001c2a: 4296 cmp r6, r2
|
|
8001c2c: d100 bne.n 8001c30 <__aeabi_dsub+0x180>
|
|
8001c2e: e0b3 b.n 8001d98 <__aeabi_dsub+0x2e8>
|
|
8001c30: 2b38 cmp r3, #56 @ 0x38
|
|
8001c32: dc00 bgt.n 8001c36 <__aeabi_dsub+0x186>
|
|
8001c34: e0c2 b.n 8001dbc <__aeabi_dsub+0x30c>
|
|
8001c36: 1e47 subs r7, r0, #1
|
|
8001c38: 42b8 cmp r0, r7
|
|
8001c3a: 4180 sbcs r0, r0
|
|
8001c3c: 4240 negs r0, r0
|
|
8001c3e: 1a2d subs r5, r5, r0
|
|
8001c40: 022b lsls r3, r5, #8
|
|
8001c42: d5b1 bpl.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8001c44: 2701 movs r7, #1
|
|
8001c46: 4d75 ldr r5, [pc, #468] @ (8001e1c <__aeabi_dsub+0x36c>)
|
|
8001c48: 427f negs r7, r7
|
|
8001c4a: 0028 movs r0, r5
|
|
8001c4c: f000 fc10 bl 8002470 <__clzsi2>
|
|
8001c50: 3808 subs r0, #8
|
|
8001c52: 2320 movs r3, #32
|
|
8001c54: 0039 movs r1, r7
|
|
8001c56: 1a1a subs r2, r3, r0
|
|
8001c58: 4085 lsls r5, r0
|
|
8001c5a: 40d1 lsrs r1, r2
|
|
8001c5c: 4087 lsls r7, r0
|
|
8001c5e: 4329 orrs r1, r5
|
|
8001c60: 42b0 cmp r0, r6
|
|
8001c62: da00 bge.n 8001c66 <__aeabi_dsub+0x1b6>
|
|
8001c64: e145 b.n 8001ef2 <__aeabi_dsub+0x442>
|
|
8001c66: 1b80 subs r0, r0, r6
|
|
8001c68: 3001 adds r0, #1
|
|
8001c6a: 1a1b subs r3, r3, r0
|
|
8001c6c: 003d movs r5, r7
|
|
8001c6e: 409f lsls r7, r3
|
|
8001c70: 40c5 lsrs r5, r0
|
|
8001c72: 1e7a subs r2, r7, #1
|
|
8001c74: 4197 sbcs r7, r2
|
|
8001c76: 000a movs r2, r1
|
|
8001c78: 409a lsls r2, r3
|
|
8001c7a: 432f orrs r7, r5
|
|
8001c7c: 433a orrs r2, r7
|
|
8001c7e: 40c1 lsrs r1, r0
|
|
8001c80: 0013 movs r3, r2
|
|
8001c82: 000d movs r5, r1
|
|
8001c84: 2600 movs r6, #0
|
|
8001c86: 430b orrs r3, r1
|
|
8001c88: d000 beq.n 8001c8c <__aeabi_dsub+0x1dc>
|
|
8001c8a: e786 b.n 8001b9a <__aeabi_dsub+0xea>
|
|
8001c8c: 2200 movs r2, #0
|
|
8001c8e: 2500 movs r5, #0
|
|
8001c90: e7a0 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001c92: 4647 mov r7, r8
|
|
8001c94: 2301 movs r3, #1
|
|
8001c96: 405f eors r7, r3
|
|
8001c98: 46b8 mov r8, r7
|
|
8001c9a: 4544 cmp r4, r8
|
|
8001c9c: d1ae bne.n 8001bfc <__aeabi_dsub+0x14c>
|
|
8001c9e: 2a00 cmp r2, #0
|
|
8001ca0: d100 bne.n 8001ca4 <__aeabi_dsub+0x1f4>
|
|
8001ca2: e0ef b.n 8001e84 <__aeabi_dsub+0x3d4>
|
|
8001ca4: 2e00 cmp r6, #0
|
|
8001ca6: d000 beq.n 8001caa <__aeabi_dsub+0x1fa>
|
|
8001ca8: e188 b.n 8001fbc <__aeabi_dsub+0x50c>
|
|
8001caa: 464b mov r3, r9
|
|
8001cac: 002a movs r2, r5
|
|
8001cae: 4302 orrs r2, r0
|
|
8001cb0: d100 bne.n 8001cb4 <__aeabi_dsub+0x204>
|
|
8001cb2: e2a0 b.n 80021f6 <__aeabi_dsub+0x746>
|
|
8001cb4: 1e5a subs r2, r3, #1
|
|
8001cb6: 2b01 cmp r3, #1
|
|
8001cb8: d100 bne.n 8001cbc <__aeabi_dsub+0x20c>
|
|
8001cba: e2b7 b.n 800222c <__aeabi_dsub+0x77c>
|
|
8001cbc: 4e54 ldr r6, [pc, #336] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001cbe: 42b3 cmp r3, r6
|
|
8001cc0: d100 bne.n 8001cc4 <__aeabi_dsub+0x214>
|
|
8001cc2: e17b b.n 8001fbc <__aeabi_dsub+0x50c>
|
|
8001cc4: 2a38 cmp r2, #56 @ 0x38
|
|
8001cc6: dc00 bgt.n 8001cca <__aeabi_dsub+0x21a>
|
|
8001cc8: e312 b.n 80022f0 <__aeabi_dsub+0x840>
|
|
8001cca: 2580 movs r5, #128 @ 0x80
|
|
8001ccc: 042d lsls r5, r5, #16
|
|
8001cce: 4229 tst r1, r5
|
|
8001cd0: d100 bne.n 8001cd4 <__aeabi_dsub+0x224>
|
|
8001cd2: e312 b.n 80022fa <__aeabi_dsub+0x84a>
|
|
8001cd4: 001e movs r6, r3
|
|
8001cd6: 2700 movs r7, #0
|
|
8001cd8: e751 b.n 8001b7e <__aeabi_dsub+0xce>
|
|
8001cda: 4a51 ldr r2, [pc, #324] @ (8001e20 <__aeabi_dsub+0x370>)
|
|
8001cdc: 1c73 adds r3, r6, #1
|
|
8001cde: 4213 tst r3, r2
|
|
8001ce0: d000 beq.n 8001ce4 <__aeabi_dsub+0x234>
|
|
8001ce2: e0f4 b.n 8001ece <__aeabi_dsub+0x41e>
|
|
8001ce4: 4662 mov r2, ip
|
|
8001ce6: 002b movs r3, r5
|
|
8001ce8: 430a orrs r2, r1
|
|
8001cea: 4303 orrs r3, r0
|
|
8001cec: 2e00 cmp r6, #0
|
|
8001cee: d000 beq.n 8001cf2 <__aeabi_dsub+0x242>
|
|
8001cf0: e174 b.n 8001fdc <__aeabi_dsub+0x52c>
|
|
8001cf2: 2b00 cmp r3, #0
|
|
8001cf4: d100 bne.n 8001cf8 <__aeabi_dsub+0x248>
|
|
8001cf6: e223 b.n 8002140 <__aeabi_dsub+0x690>
|
|
8001cf8: 2a00 cmp r2, #0
|
|
8001cfa: d100 bne.n 8001cfe <__aeabi_dsub+0x24e>
|
|
8001cfc: e0e0 b.n 8001ec0 <__aeabi_dsub+0x410>
|
|
8001cfe: 4663 mov r3, ip
|
|
8001d00: 1ac7 subs r7, r0, r3
|
|
8001d02: 42b8 cmp r0, r7
|
|
8001d04: 4192 sbcs r2, r2
|
|
8001d06: 2680 movs r6, #128 @ 0x80
|
|
8001d08: 1a6b subs r3, r5, r1
|
|
8001d0a: 4252 negs r2, r2
|
|
8001d0c: 1a9b subs r3, r3, r2
|
|
8001d0e: 0436 lsls r6, r6, #16
|
|
8001d10: 4233 tst r3, r6
|
|
8001d12: d100 bne.n 8001d16 <__aeabi_dsub+0x266>
|
|
8001d14: e2c1 b.n 800229a <__aeabi_dsub+0x7ea>
|
|
8001d16: 4663 mov r3, ip
|
|
8001d18: 1a18 subs r0, r3, r0
|
|
8001d1a: 4584 cmp ip, r0
|
|
8001d1c: 4192 sbcs r2, r2
|
|
8001d1e: 1b4d subs r5, r1, r5
|
|
8001d20: 4252 negs r2, r2
|
|
8001d22: 1aad subs r5, r5, r2
|
|
8001d24: 2401 movs r4, #1
|
|
8001d26: 0002 movs r2, r0
|
|
8001d28: 4643 mov r3, r8
|
|
8001d2a: 432a orrs r2, r5
|
|
8001d2c: 401c ands r4, r3
|
|
8001d2e: 2a00 cmp r2, #0
|
|
8001d30: d100 bne.n 8001d34 <__aeabi_dsub+0x284>
|
|
8001d32: e0db b.n 8001eec <__aeabi_dsub+0x43c>
|
|
8001d34: 4235 tst r5, r6
|
|
8001d36: d100 bne.n 8001d3a <__aeabi_dsub+0x28a>
|
|
8001d38: e2e9 b.n 800230e <__aeabi_dsub+0x85e>
|
|
8001d3a: 4b36 ldr r3, [pc, #216] @ (8001e14 <__aeabi_dsub+0x364>)
|
|
8001d3c: 0002 movs r2, r0
|
|
8001d3e: 401d ands r5, r3
|
|
8001d40: 2301 movs r3, #1
|
|
8001d42: e742 b.n 8001bca <__aeabi_dsub+0x11a>
|
|
8001d44: 4296 cmp r6, r2
|
|
8001d46: d027 beq.n 8001d98 <__aeabi_dsub+0x2e8>
|
|
8001d48: 2b38 cmp r3, #56 @ 0x38
|
|
8001d4a: dd00 ble.n 8001d4e <__aeabi_dsub+0x29e>
|
|
8001d4c: e111 b.n 8001f72 <__aeabi_dsub+0x4c2>
|
|
8001d4e: 2280 movs r2, #128 @ 0x80
|
|
8001d50: 0412 lsls r2, r2, #16
|
|
8001d52: 4311 orrs r1, r2
|
|
8001d54: 2b1f cmp r3, #31
|
|
8001d56: dd00 ble.n 8001d5a <__aeabi_dsub+0x2aa>
|
|
8001d58: e1a1 b.n 800209e <__aeabi_dsub+0x5ee>
|
|
8001d5a: 2220 movs r2, #32
|
|
8001d5c: 000f movs r7, r1
|
|
8001d5e: 1ad2 subs r2, r2, r3
|
|
8001d60: 4691 mov r9, r2
|
|
8001d62: 4097 lsls r7, r2
|
|
8001d64: 4662 mov r2, ip
|
|
8001d66: 40da lsrs r2, r3
|
|
8001d68: 4317 orrs r7, r2
|
|
8001d6a: 46b8 mov r8, r7
|
|
8001d6c: 4662 mov r2, ip
|
|
8001d6e: 464f mov r7, r9
|
|
8001d70: 40ba lsls r2, r7
|
|
8001d72: 40d9 lsrs r1, r3
|
|
8001d74: 1e57 subs r7, r2, #1
|
|
8001d76: 41ba sbcs r2, r7
|
|
8001d78: 4647 mov r7, r8
|
|
8001d7a: 186d adds r5, r5, r1
|
|
8001d7c: 4317 orrs r7, r2
|
|
8001d7e: 183f adds r7, r7, r0
|
|
8001d80: 4287 cmp r7, r0
|
|
8001d82: 4180 sbcs r0, r0
|
|
8001d84: 4240 negs r0, r0
|
|
8001d86: 182d adds r5, r5, r0
|
|
8001d88: 022b lsls r3, r5, #8
|
|
8001d8a: d500 bpl.n 8001d8e <__aeabi_dsub+0x2de>
|
|
8001d8c: e6f7 b.n 8001b7e <__aeabi_dsub+0xce>
|
|
8001d8e: e034 b.n 8001dfa <__aeabi_dsub+0x34a>
|
|
8001d90: 0033 movs r3, r6
|
|
8001d92: 2500 movs r5, #0
|
|
8001d94: 2200 movs r2, #0
|
|
8001d96: e71d b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001d98: 08c0 lsrs r0, r0, #3
|
|
8001d9a: 076f lsls r7, r5, #29
|
|
8001d9c: 4307 orrs r7, r0
|
|
8001d9e: 08e8 lsrs r0, r5, #3
|
|
8001da0: e737 b.n 8001c12 <__aeabi_dsub+0x162>
|
|
8001da2: 08c7 lsrs r7, r0, #3
|
|
8001da4: 076a lsls r2, r5, #29
|
|
8001da6: 4317 orrs r7, r2
|
|
8001da8: 4a19 ldr r2, [pc, #100] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001daa: 08e8 lsrs r0, r5, #3
|
|
8001dac: 4293 cmp r3, r2
|
|
8001dae: d100 bne.n 8001db2 <__aeabi_dsub+0x302>
|
|
8001db0: e72f b.n 8001c12 <__aeabi_dsub+0x162>
|
|
8001db2: 003a movs r2, r7
|
|
8001db4: e0d8 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
8001db6: 4b16 ldr r3, [pc, #88] @ (8001e10 <__aeabi_dsub+0x360>)
|
|
8001db8: 2500 movs r5, #0
|
|
8001dba: e70b b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001dbc: 2280 movs r2, #128 @ 0x80
|
|
8001dbe: 0412 lsls r2, r2, #16
|
|
8001dc0: 4311 orrs r1, r2
|
|
8001dc2: 2b1f cmp r3, #31
|
|
8001dc4: dd00 ble.n 8001dc8 <__aeabi_dsub+0x318>
|
|
8001dc6: e0b7 b.n 8001f38 <__aeabi_dsub+0x488>
|
|
8001dc8: 2220 movs r2, #32
|
|
8001dca: 000f movs r7, r1
|
|
8001dcc: 1ad2 subs r2, r2, r3
|
|
8001dce: 4691 mov r9, r2
|
|
8001dd0: 4097 lsls r7, r2
|
|
8001dd2: 4662 mov r2, ip
|
|
8001dd4: 40da lsrs r2, r3
|
|
8001dd6: 4317 orrs r7, r2
|
|
8001dd8: 46b8 mov r8, r7
|
|
8001dda: 4662 mov r2, ip
|
|
8001ddc: 464f mov r7, r9
|
|
8001dde: 40ba lsls r2, r7
|
|
8001de0: 40d9 lsrs r1, r3
|
|
8001de2: 1e57 subs r7, r2, #1
|
|
8001de4: 41ba sbcs r2, r7
|
|
8001de6: 4647 mov r7, r8
|
|
8001de8: 1a6d subs r5, r5, r1
|
|
8001dea: 4317 orrs r7, r2
|
|
8001dec: 1bc7 subs r7, r0, r7
|
|
8001dee: 42b8 cmp r0, r7
|
|
8001df0: 4180 sbcs r0, r0
|
|
8001df2: 4240 negs r0, r0
|
|
8001df4: 1a2d subs r5, r5, r0
|
|
8001df6: 022b lsls r3, r5, #8
|
|
8001df8: d416 bmi.n 8001e28 <__aeabi_dsub+0x378>
|
|
8001dfa: 077b lsls r3, r7, #29
|
|
8001dfc: d100 bne.n 8001e00 <__aeabi_dsub+0x350>
|
|
8001dfe: e279 b.n 80022f4 <__aeabi_dsub+0x844>
|
|
8001e00: 230f movs r3, #15
|
|
8001e02: 403b ands r3, r7
|
|
8001e04: 2b04 cmp r3, #4
|
|
8001e06: d000 beq.n 8001e0a <__aeabi_dsub+0x35a>
|
|
8001e08: e6ce b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8001e0a: 0033 movs r3, r6
|
|
8001e0c: 08ff lsrs r7, r7, #3
|
|
8001e0e: e7c9 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
8001e10: 000007ff .word 0x000007ff
|
|
8001e14: ff7fffff .word 0xff7fffff
|
|
8001e18: fffff801 .word 0xfffff801
|
|
8001e1c: 007fffff .word 0x007fffff
|
|
8001e20: 000007fe .word 0x000007fe
|
|
8001e24: 4644 mov r4, r8
|
|
8001e26: 2601 movs r6, #1
|
|
8001e28: 026d lsls r5, r5, #9
|
|
8001e2a: 0a6d lsrs r5, r5, #9
|
|
8001e2c: 2d00 cmp r5, #0
|
|
8001e2e: d000 beq.n 8001e32 <__aeabi_dsub+0x382>
|
|
8001e30: e70b b.n 8001c4a <__aeabi_dsub+0x19a>
|
|
8001e32: 0038 movs r0, r7
|
|
8001e34: f000 fb1c bl 8002470 <__clzsi2>
|
|
8001e38: 0003 movs r3, r0
|
|
8001e3a: 3018 adds r0, #24
|
|
8001e3c: 281f cmp r0, #31
|
|
8001e3e: dc00 bgt.n 8001e42 <__aeabi_dsub+0x392>
|
|
8001e40: e707 b.n 8001c52 <__aeabi_dsub+0x1a2>
|
|
8001e42: 0039 movs r1, r7
|
|
8001e44: 3b08 subs r3, #8
|
|
8001e46: 4099 lsls r1, r3
|
|
8001e48: 4286 cmp r6, r0
|
|
8001e4a: dd00 ble.n 8001e4e <__aeabi_dsub+0x39e>
|
|
8001e4c: e087 b.n 8001f5e <__aeabi_dsub+0x4ae>
|
|
8001e4e: 1b83 subs r3, r0, r6
|
|
8001e50: 1c58 adds r0, r3, #1
|
|
8001e52: 281f cmp r0, #31
|
|
8001e54: dc00 bgt.n 8001e58 <__aeabi_dsub+0x3a8>
|
|
8001e56: e214 b.n 8002282 <__aeabi_dsub+0x7d2>
|
|
8001e58: 000a movs r2, r1
|
|
8001e5a: 3b1f subs r3, #31
|
|
8001e5c: 40da lsrs r2, r3
|
|
8001e5e: 2820 cmp r0, #32
|
|
8001e60: d005 beq.n 8001e6e <__aeabi_dsub+0x3be>
|
|
8001e62: 2340 movs r3, #64 @ 0x40
|
|
8001e64: 1a1b subs r3, r3, r0
|
|
8001e66: 4099 lsls r1, r3
|
|
8001e68: 1e4b subs r3, r1, #1
|
|
8001e6a: 4199 sbcs r1, r3
|
|
8001e6c: 430a orrs r2, r1
|
|
8001e6e: 2a00 cmp r2, #0
|
|
8001e70: d03c beq.n 8001eec <__aeabi_dsub+0x43c>
|
|
8001e72: 2600 movs r6, #0
|
|
8001e74: 0753 lsls r3, r2, #29
|
|
8001e76: d000 beq.n 8001e7a <__aeabi_dsub+0x3ca>
|
|
8001e78: e691 b.n 8001b9e <__aeabi_dsub+0xee>
|
|
8001e7a: 0017 movs r7, r2
|
|
8001e7c: 0035 movs r5, r6
|
|
8001e7e: 0033 movs r3, r6
|
|
8001e80: 08ff lsrs r7, r7, #3
|
|
8001e82: e78f b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
8001e84: 4aca ldr r2, [pc, #808] @ (80021b0 <__aeabi_dsub+0x700>)
|
|
8001e86: 1c73 adds r3, r6, #1
|
|
8001e88: 4213 tst r3, r2
|
|
8001e8a: d17a bne.n 8001f82 <__aeabi_dsub+0x4d2>
|
|
8001e8c: 002b movs r3, r5
|
|
8001e8e: 4303 orrs r3, r0
|
|
8001e90: 2e00 cmp r6, #0
|
|
8001e92: d000 beq.n 8001e96 <__aeabi_dsub+0x3e6>
|
|
8001e94: e192 b.n 80021bc <__aeabi_dsub+0x70c>
|
|
8001e96: 4662 mov r2, ip
|
|
8001e98: 430a orrs r2, r1
|
|
8001e9a: 2b00 cmp r3, #0
|
|
8001e9c: d100 bne.n 8001ea0 <__aeabi_dsub+0x3f0>
|
|
8001e9e: e1f4 b.n 800228a <__aeabi_dsub+0x7da>
|
|
8001ea0: 2a00 cmp r2, #0
|
|
8001ea2: d00d beq.n 8001ec0 <__aeabi_dsub+0x410>
|
|
8001ea4: 4663 mov r3, ip
|
|
8001ea6: 18c7 adds r7, r0, r3
|
|
8001ea8: 4287 cmp r7, r0
|
|
8001eaa: 4180 sbcs r0, r0
|
|
8001eac: 186d adds r5, r5, r1
|
|
8001eae: 4240 negs r0, r0
|
|
8001eb0: 182d adds r5, r5, r0
|
|
8001eb2: 022b lsls r3, r5, #8
|
|
8001eb4: d500 bpl.n 8001eb8 <__aeabi_dsub+0x408>
|
|
8001eb6: e212 b.n 80022de <__aeabi_dsub+0x82e>
|
|
8001eb8: 003a movs r2, r7
|
|
8001eba: 46bb mov fp, r7
|
|
8001ebc: 432a orrs r2, r5
|
|
8001ebe: d015 beq.n 8001eec <__aeabi_dsub+0x43c>
|
|
8001ec0: 465b mov r3, fp
|
|
8001ec2: 076a lsls r2, r5, #29
|
|
8001ec4: 08df lsrs r7, r3, #3
|
|
8001ec6: 433a orrs r2, r7
|
|
8001ec8: 2300 movs r3, #0
|
|
8001eca: 08e8 lsrs r0, r5, #3
|
|
8001ecc: e04c b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
8001ece: 4663 mov r3, ip
|
|
8001ed0: 1ac7 subs r7, r0, r3
|
|
8001ed2: 42b8 cmp r0, r7
|
|
8001ed4: 4192 sbcs r2, r2
|
|
8001ed6: 1a6b subs r3, r5, r1
|
|
8001ed8: 4252 negs r2, r2
|
|
8001eda: 1a9b subs r3, r3, r2
|
|
8001edc: 021a lsls r2, r3, #8
|
|
8001ede: d500 bpl.n 8001ee2 <__aeabi_dsub+0x432>
|
|
8001ee0: e087 b.n 8001ff2 <__aeabi_dsub+0x542>
|
|
8001ee2: 003a movs r2, r7
|
|
8001ee4: 001d movs r5, r3
|
|
8001ee6: 431a orrs r2, r3
|
|
8001ee8: d1a0 bne.n 8001e2c <__aeabi_dsub+0x37c>
|
|
8001eea: 2400 movs r4, #0
|
|
8001eec: 2300 movs r3, #0
|
|
8001eee: 2500 movs r5, #0
|
|
8001ef0: e670 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001ef2: 4db0 ldr r5, [pc, #704] @ (80021b4 <__aeabi_dsub+0x704>)
|
|
8001ef4: 1a36 subs r6, r6, r0
|
|
8001ef6: 400d ands r5, r1
|
|
8001ef8: 077b lsls r3, r7, #29
|
|
8001efa: d000 beq.n 8001efe <__aeabi_dsub+0x44e>
|
|
8001efc: e780 b.n 8001e00 <__aeabi_dsub+0x350>
|
|
8001efe: 0033 movs r3, r6
|
|
8001f00: e784 b.n 8001e0c <__aeabi_dsub+0x35c>
|
|
8001f02: 464b mov r3, r9
|
|
8001f04: 002a movs r2, r5
|
|
8001f06: 4302 orrs r2, r0
|
|
8001f08: d07e beq.n 8002008 <__aeabi_dsub+0x558>
|
|
8001f0a: 1e5a subs r2, r3, #1
|
|
8001f0c: 2b01 cmp r3, #1
|
|
8001f0e: d100 bne.n 8001f12 <__aeabi_dsub+0x462>
|
|
8001f10: e11f b.n 8002152 <__aeabi_dsub+0x6a2>
|
|
8001f12: 4ca9 ldr r4, [pc, #676] @ (80021b8 <__aeabi_dsub+0x708>)
|
|
8001f14: 42a3 cmp r3, r4
|
|
8001f16: d100 bne.n 8001f1a <__aeabi_dsub+0x46a>
|
|
8001f18: e198 b.n 800224c <__aeabi_dsub+0x79c>
|
|
8001f1a: 2a38 cmp r2, #56 @ 0x38
|
|
8001f1c: dc00 bgt.n 8001f20 <__aeabi_dsub+0x470>
|
|
8001f1e: e19c b.n 800225a <__aeabi_dsub+0x7aa>
|
|
8001f20: 4662 mov r2, ip
|
|
8001f22: 1e57 subs r7, r2, #1
|
|
8001f24: 45bc cmp ip, r7
|
|
8001f26: 4192 sbcs r2, r2
|
|
8001f28: 4252 negs r2, r2
|
|
8001f2a: 1a8d subs r5, r1, r2
|
|
8001f2c: 4644 mov r4, r8
|
|
8001f2e: 001e movs r6, r3
|
|
8001f30: 022a lsls r2, r5, #8
|
|
8001f32: d500 bpl.n 8001f36 <__aeabi_dsub+0x486>
|
|
8001f34: e686 b.n 8001c44 <__aeabi_dsub+0x194>
|
|
8001f36: e637 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8001f38: 001a movs r2, r3
|
|
8001f3a: 000f movs r7, r1
|
|
8001f3c: 3a20 subs r2, #32
|
|
8001f3e: 40d7 lsrs r7, r2
|
|
8001f40: 46b8 mov r8, r7
|
|
8001f42: 2b20 cmp r3, #32
|
|
8001f44: d005 beq.n 8001f52 <__aeabi_dsub+0x4a2>
|
|
8001f46: 2240 movs r2, #64 @ 0x40
|
|
8001f48: 1ad3 subs r3, r2, r3
|
|
8001f4a: 4099 lsls r1, r3
|
|
8001f4c: 4663 mov r3, ip
|
|
8001f4e: 430b orrs r3, r1
|
|
8001f50: 469a mov sl, r3
|
|
8001f52: 4657 mov r7, sl
|
|
8001f54: 1e7b subs r3, r7, #1
|
|
8001f56: 419f sbcs r7, r3
|
|
8001f58: 4643 mov r3, r8
|
|
8001f5a: 431f orrs r7, r3
|
|
8001f5c: e746 b.n 8001dec <__aeabi_dsub+0x33c>
|
|
8001f5e: 4a95 ldr r2, [pc, #596] @ (80021b4 <__aeabi_dsub+0x704>)
|
|
8001f60: 1a33 subs r3, r6, r0
|
|
8001f62: 4011 ands r1, r2
|
|
8001f64: 074a lsls r2, r1, #29
|
|
8001f66: 08c8 lsrs r0, r1, #3
|
|
8001f68: 0305 lsls r5, r0, #12
|
|
8001f6a: 055b lsls r3, r3, #21
|
|
8001f6c: 0b2d lsrs r5, r5, #12
|
|
8001f6e: 0d5b lsrs r3, r3, #21
|
|
8001f70: e630 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001f72: 2380 movs r3, #128 @ 0x80
|
|
8001f74: 041b lsls r3, r3, #16
|
|
8001f76: 421d tst r5, r3
|
|
8001f78: d100 bne.n 8001f7c <__aeabi_dsub+0x4cc>
|
|
8001f7a: e0fb b.n 8002174 <__aeabi_dsub+0x6c4>
|
|
8001f7c: 001d movs r5, r3
|
|
8001f7e: 2700 movs r7, #0
|
|
8001f80: e5fd b.n 8001b7e <__aeabi_dsub+0xce>
|
|
8001f82: 4a8d ldr r2, [pc, #564] @ (80021b8 <__aeabi_dsub+0x708>)
|
|
8001f84: 4293 cmp r3, r2
|
|
8001f86: d100 bne.n 8001f8a <__aeabi_dsub+0x4da>
|
|
8001f88: e703 b.n 8001d92 <__aeabi_dsub+0x2e2>
|
|
8001f8a: 4662 mov r2, ip
|
|
8001f8c: 1882 adds r2, r0, r2
|
|
8001f8e: 4282 cmp r2, r0
|
|
8001f90: 4180 sbcs r0, r0
|
|
8001f92: 1869 adds r1, r5, r1
|
|
8001f94: 4240 negs r0, r0
|
|
8001f96: 1808 adds r0, r1, r0
|
|
8001f98: 07c7 lsls r7, r0, #31
|
|
8001f9a: 0852 lsrs r2, r2, #1
|
|
8001f9c: 4317 orrs r7, r2
|
|
8001f9e: 0845 lsrs r5, r0, #1
|
|
8001fa0: 0752 lsls r2, r2, #29
|
|
8001fa2: d400 bmi.n 8001fa6 <__aeabi_dsub+0x4f6>
|
|
8001fa4: e1ae b.n 8002304 <__aeabi_dsub+0x854>
|
|
8001fa6: 220f movs r2, #15
|
|
8001fa8: 001e movs r6, r3
|
|
8001faa: 403a ands r2, r7
|
|
8001fac: 2a04 cmp r2, #4
|
|
8001fae: d000 beq.n 8001fb2 <__aeabi_dsub+0x502>
|
|
8001fb0: e5fa b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8001fb2: 08ff lsrs r7, r7, #3
|
|
8001fb4: 076a lsls r2, r5, #29
|
|
8001fb6: 433a orrs r2, r7
|
|
8001fb8: 0900 lsrs r0, r0, #4
|
|
8001fba: e7d5 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
8001fbc: 4663 mov r3, ip
|
|
8001fbe: 074f lsls r7, r1, #29
|
|
8001fc0: 08da lsrs r2, r3, #3
|
|
8001fc2: 4317 orrs r7, r2
|
|
8001fc4: 08c8 lsrs r0, r1, #3
|
|
8001fc6: e624 b.n 8001c12 <__aeabi_dsub+0x162>
|
|
8001fc8: 1e47 subs r7, r0, #1
|
|
8001fca: 42b8 cmp r0, r7
|
|
8001fcc: 4180 sbcs r0, r0
|
|
8001fce: 4240 negs r0, r0
|
|
8001fd0: 1a2d subs r5, r5, r0
|
|
8001fd2: 001e movs r6, r3
|
|
8001fd4: 022a lsls r2, r5, #8
|
|
8001fd6: d500 bpl.n 8001fda <__aeabi_dsub+0x52a>
|
|
8001fd8: e634 b.n 8001c44 <__aeabi_dsub+0x194>
|
|
8001fda: e5e5 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8001fdc: 2b00 cmp r3, #0
|
|
8001fde: d000 beq.n 8001fe2 <__aeabi_dsub+0x532>
|
|
8001fe0: e10d b.n 80021fe <__aeabi_dsub+0x74e>
|
|
8001fe2: 2a00 cmp r2, #0
|
|
8001fe4: d000 beq.n 8001fe8 <__aeabi_dsub+0x538>
|
|
8001fe6: e169 b.n 80022bc <__aeabi_dsub+0x80c>
|
|
8001fe8: 2580 movs r5, #128 @ 0x80
|
|
8001fea: 2400 movs r4, #0
|
|
8001fec: 4b72 ldr r3, [pc, #456] @ (80021b8 <__aeabi_dsub+0x708>)
|
|
8001fee: 032d lsls r5, r5, #12
|
|
8001ff0: e5f0 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
8001ff2: 4663 mov r3, ip
|
|
8001ff4: 1a1f subs r7, r3, r0
|
|
8001ff6: 45bc cmp ip, r7
|
|
8001ff8: 4192 sbcs r2, r2
|
|
8001ffa: 2401 movs r4, #1
|
|
8001ffc: 4643 mov r3, r8
|
|
8001ffe: 1b4d subs r5, r1, r5
|
|
8002000: 4252 negs r2, r2
|
|
8002002: 1aad subs r5, r5, r2
|
|
8002004: 401c ands r4, r3
|
|
8002006: e711 b.n 8001e2c <__aeabi_dsub+0x37c>
|
|
8002008: 4662 mov r2, ip
|
|
800200a: 4644 mov r4, r8
|
|
800200c: 000d movs r5, r1
|
|
800200e: 08d7 lsrs r7, r2, #3
|
|
8002010: e6c8 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
8002012: 4663 mov r3, ip
|
|
8002014: 18c6 adds r6, r0, r3
|
|
8002016: 4286 cmp r6, r0
|
|
8002018: 4180 sbcs r0, r0
|
|
800201a: 1869 adds r1, r5, r1
|
|
800201c: 4240 negs r0, r0
|
|
800201e: 1809 adds r1, r1, r0
|
|
8002020: 020b lsls r3, r1, #8
|
|
8002022: d400 bmi.n 8002026 <__aeabi_dsub+0x576>
|
|
8002024: e10c b.n 8002240 <__aeabi_dsub+0x790>
|
|
8002026: 4b63 ldr r3, [pc, #396] @ (80021b4 <__aeabi_dsub+0x704>)
|
|
8002028: 0870 lsrs r0, r6, #1
|
|
800202a: 4019 ands r1, r3
|
|
800202c: 07cb lsls r3, r1, #31
|
|
800202e: 4303 orrs r3, r0
|
|
8002030: 084a lsrs r2, r1, #1
|
|
8002032: 0740 lsls r0, r0, #29
|
|
8002034: d400 bmi.n 8002038 <__aeabi_dsub+0x588>
|
|
8002036: e13b b.n 80022b0 <__aeabi_dsub+0x800>
|
|
8002038: 200f movs r0, #15
|
|
800203a: 4018 ands r0, r3
|
|
800203c: 2804 cmp r0, #4
|
|
800203e: d100 bne.n 8002042 <__aeabi_dsub+0x592>
|
|
8002040: e136 b.n 80022b0 <__aeabi_dsub+0x800>
|
|
8002042: 1d1f adds r7, r3, #4
|
|
8002044: 429f cmp r7, r3
|
|
8002046: 41ad sbcs r5, r5
|
|
8002048: 426d negs r5, r5
|
|
800204a: 2302 movs r3, #2
|
|
800204c: 18ad adds r5, r5, r2
|
|
800204e: 08ff lsrs r7, r7, #3
|
|
8002050: e6a8 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
8002052: 2b00 cmp r3, #0
|
|
8002054: d100 bne.n 8002058 <__aeabi_dsub+0x5a8>
|
|
8002056: e640 b.n 8001cda <__aeabi_dsub+0x22a>
|
|
8002058: 464b mov r3, r9
|
|
800205a: 1b9b subs r3, r3, r6
|
|
800205c: 2e00 cmp r6, #0
|
|
800205e: d100 bne.n 8002062 <__aeabi_dsub+0x5b2>
|
|
8002060: e750 b.n 8001f04 <__aeabi_dsub+0x454>
|
|
8002062: 2b38 cmp r3, #56 @ 0x38
|
|
8002064: dd2e ble.n 80020c4 <__aeabi_dsub+0x614>
|
|
8002066: 4663 mov r3, ip
|
|
8002068: 1e5f subs r7, r3, #1
|
|
800206a: 45bc cmp ip, r7
|
|
800206c: 4192 sbcs r2, r2
|
|
800206e: 4252 negs r2, r2
|
|
8002070: 1a8d subs r5, r1, r2
|
|
8002072: 4644 mov r4, r8
|
|
8002074: 464e mov r6, r9
|
|
8002076: 022b lsls r3, r5, #8
|
|
8002078: d500 bpl.n 800207c <__aeabi_dsub+0x5cc>
|
|
800207a: e5e3 b.n 8001c44 <__aeabi_dsub+0x194>
|
|
800207c: e594 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
800207e: 4663 mov r3, ip
|
|
8002080: 1ac7 subs r7, r0, r3
|
|
8002082: 42b8 cmp r0, r7
|
|
8002084: 4180 sbcs r0, r0
|
|
8002086: 1a6d subs r5, r5, r1
|
|
8002088: 4240 negs r0, r0
|
|
800208a: 1a2d subs r5, r5, r0
|
|
800208c: 022b lsls r3, r5, #8
|
|
800208e: d500 bpl.n 8002092 <__aeabi_dsub+0x5e2>
|
|
8002090: e6c9 b.n 8001e26 <__aeabi_dsub+0x376>
|
|
8002092: 076a lsls r2, r5, #29
|
|
8002094: 08ff lsrs r7, r7, #3
|
|
8002096: 2301 movs r3, #1
|
|
8002098: 433a orrs r2, r7
|
|
800209a: 08e8 lsrs r0, r5, #3
|
|
800209c: e764 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
800209e: 001a movs r2, r3
|
|
80020a0: 000f movs r7, r1
|
|
80020a2: 3a20 subs r2, #32
|
|
80020a4: 40d7 lsrs r7, r2
|
|
80020a6: 46b8 mov r8, r7
|
|
80020a8: 2b20 cmp r3, #32
|
|
80020aa: d005 beq.n 80020b8 <__aeabi_dsub+0x608>
|
|
80020ac: 2240 movs r2, #64 @ 0x40
|
|
80020ae: 1ad3 subs r3, r2, r3
|
|
80020b0: 4099 lsls r1, r3
|
|
80020b2: 4663 mov r3, ip
|
|
80020b4: 430b orrs r3, r1
|
|
80020b6: 469a mov sl, r3
|
|
80020b8: 4657 mov r7, sl
|
|
80020ba: 1e7b subs r3, r7, #1
|
|
80020bc: 419f sbcs r7, r3
|
|
80020be: 4643 mov r3, r8
|
|
80020c0: 431f orrs r7, r3
|
|
80020c2: e65c b.n 8001d7e <__aeabi_dsub+0x2ce>
|
|
80020c4: 2280 movs r2, #128 @ 0x80
|
|
80020c6: 003c movs r4, r7
|
|
80020c8: 0412 lsls r2, r2, #16
|
|
80020ca: 4315 orrs r5, r2
|
|
80020cc: 2b1f cmp r3, #31
|
|
80020ce: dc26 bgt.n 800211e <__aeabi_dsub+0x66e>
|
|
80020d0: 2220 movs r2, #32
|
|
80020d2: 002f movs r7, r5
|
|
80020d4: 1ad2 subs r2, r2, r3
|
|
80020d6: 0006 movs r6, r0
|
|
80020d8: 4090 lsls r0, r2
|
|
80020da: 4097 lsls r7, r2
|
|
80020dc: 40de lsrs r6, r3
|
|
80020de: 1e42 subs r2, r0, #1
|
|
80020e0: 4190 sbcs r0, r2
|
|
80020e2: 40dd lsrs r5, r3
|
|
80020e4: 4337 orrs r7, r6
|
|
80020e6: 4307 orrs r7, r0
|
|
80020e8: 1b49 subs r1, r1, r5
|
|
80020ea: 4663 mov r3, ip
|
|
80020ec: 1bdf subs r7, r3, r7
|
|
80020ee: 45bc cmp ip, r7
|
|
80020f0: 4192 sbcs r2, r2
|
|
80020f2: 4252 negs r2, r2
|
|
80020f4: 464e mov r6, r9
|
|
80020f6: 1a8d subs r5, r1, r2
|
|
80020f8: e67d b.n 8001df6 <__aeabi_dsub+0x346>
|
|
80020fa: 2b00 cmp r3, #0
|
|
80020fc: d100 bne.n 8002100 <__aeabi_dsub+0x650>
|
|
80020fe: e6c1 b.n 8001e84 <__aeabi_dsub+0x3d4>
|
|
8002100: 464b mov r3, r9
|
|
8002102: 1b9b subs r3, r3, r6
|
|
8002104: 2e00 cmp r6, #0
|
|
8002106: d100 bne.n 800210a <__aeabi_dsub+0x65a>
|
|
8002108: e5d0 b.n 8001cac <__aeabi_dsub+0x1fc>
|
|
800210a: 2b38 cmp r3, #56 @ 0x38
|
|
800210c: dd36 ble.n 800217c <__aeabi_dsub+0x6cc>
|
|
800210e: 2580 movs r5, #128 @ 0x80
|
|
8002110: 042d lsls r5, r5, #16
|
|
8002112: 4229 tst r1, r5
|
|
8002114: d100 bne.n 8002118 <__aeabi_dsub+0x668>
|
|
8002116: e0dd b.n 80022d4 <__aeabi_dsub+0x824>
|
|
8002118: 464e mov r6, r9
|
|
800211a: 2700 movs r7, #0
|
|
800211c: e52f b.n 8001b7e <__aeabi_dsub+0xce>
|
|
800211e: 001a movs r2, r3
|
|
8002120: 002e movs r6, r5
|
|
8002122: 3a20 subs r2, #32
|
|
8002124: 40d6 lsrs r6, r2
|
|
8002126: 2b20 cmp r3, #32
|
|
8002128: d005 beq.n 8002136 <__aeabi_dsub+0x686>
|
|
800212a: 2240 movs r2, #64 @ 0x40
|
|
800212c: 1ad3 subs r3, r2, r3
|
|
800212e: 409d lsls r5, r3
|
|
8002130: 002f movs r7, r5
|
|
8002132: 4307 orrs r7, r0
|
|
8002134: 46bb mov fp, r7
|
|
8002136: 465f mov r7, fp
|
|
8002138: 1e7b subs r3, r7, #1
|
|
800213a: 419f sbcs r7, r3
|
|
800213c: 4337 orrs r7, r6
|
|
800213e: e7d4 b.n 80020ea <__aeabi_dsub+0x63a>
|
|
8002140: 2a00 cmp r2, #0
|
|
8002142: d100 bne.n 8002146 <__aeabi_dsub+0x696>
|
|
8002144: e6d1 b.n 8001eea <__aeabi_dsub+0x43a>
|
|
8002146: 2401 movs r4, #1
|
|
8002148: 4643 mov r3, r8
|
|
800214a: 000d movs r5, r1
|
|
800214c: 46e3 mov fp, ip
|
|
800214e: 401c ands r4, r3
|
|
8002150: e6b6 b.n 8001ec0 <__aeabi_dsub+0x410>
|
|
8002152: 4663 mov r3, ip
|
|
8002154: 1a1f subs r7, r3, r0
|
|
8002156: 45bc cmp ip, r7
|
|
8002158: 4192 sbcs r2, r2
|
|
800215a: 1b4d subs r5, r1, r5
|
|
800215c: 4252 negs r2, r2
|
|
800215e: 1aad subs r5, r5, r2
|
|
8002160: 022b lsls r3, r5, #8
|
|
8002162: d500 bpl.n 8002166 <__aeabi_dsub+0x6b6>
|
|
8002164: e65e b.n 8001e24 <__aeabi_dsub+0x374>
|
|
8002166: 076a lsls r2, r5, #29
|
|
8002168: 08ff lsrs r7, r7, #3
|
|
800216a: 4644 mov r4, r8
|
|
800216c: 2301 movs r3, #1
|
|
800216e: 433a orrs r2, r7
|
|
8002170: 08e8 lsrs r0, r5, #3
|
|
8002172: e6f9 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
8002174: 1c47 adds r7, r0, #1
|
|
8002176: e517 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8002178: 003b movs r3, r7
|
|
800217a: e5eb b.n 8001d54 <__aeabi_dsub+0x2a4>
|
|
800217c: 2280 movs r2, #128 @ 0x80
|
|
800217e: 0412 lsls r2, r2, #16
|
|
8002180: 4315 orrs r5, r2
|
|
8002182: 2b1f cmp r3, #31
|
|
8002184: dc6c bgt.n 8002260 <__aeabi_dsub+0x7b0>
|
|
8002186: 2220 movs r2, #32
|
|
8002188: 002f movs r7, r5
|
|
800218a: 1ad2 subs r2, r2, r3
|
|
800218c: 0006 movs r6, r0
|
|
800218e: 4090 lsls r0, r2
|
|
8002190: 4097 lsls r7, r2
|
|
8002192: 40de lsrs r6, r3
|
|
8002194: 1e42 subs r2, r0, #1
|
|
8002196: 4190 sbcs r0, r2
|
|
8002198: 40dd lsrs r5, r3
|
|
800219a: 4337 orrs r7, r6
|
|
800219c: 4307 orrs r7, r0
|
|
800219e: 1949 adds r1, r1, r5
|
|
80021a0: 4467 add r7, ip
|
|
80021a2: 4567 cmp r7, ip
|
|
80021a4: 4192 sbcs r2, r2
|
|
80021a6: 4252 negs r2, r2
|
|
80021a8: 464e mov r6, r9
|
|
80021aa: 1855 adds r5, r2, r1
|
|
80021ac: e5ec b.n 8001d88 <__aeabi_dsub+0x2d8>
|
|
80021ae: 46c0 nop @ (mov r8, r8)
|
|
80021b0: 000007fe .word 0x000007fe
|
|
80021b4: ff7fffff .word 0xff7fffff
|
|
80021b8: 000007ff .word 0x000007ff
|
|
80021bc: 2b00 cmp r3, #0
|
|
80021be: d100 bne.n 80021c2 <__aeabi_dsub+0x712>
|
|
80021c0: e6fc b.n 8001fbc <__aeabi_dsub+0x50c>
|
|
80021c2: 08c7 lsrs r7, r0, #3
|
|
80021c4: 076b lsls r3, r5, #29
|
|
80021c6: 431f orrs r7, r3
|
|
80021c8: 4663 mov r3, ip
|
|
80021ca: 08e8 lsrs r0, r5, #3
|
|
80021cc: 430b orrs r3, r1
|
|
80021ce: d100 bne.n 80021d2 <__aeabi_dsub+0x722>
|
|
80021d0: e51f b.n 8001c12 <__aeabi_dsub+0x162>
|
|
80021d2: 2380 movs r3, #128 @ 0x80
|
|
80021d4: 031b lsls r3, r3, #12
|
|
80021d6: 4218 tst r0, r3
|
|
80021d8: d007 beq.n 80021ea <__aeabi_dsub+0x73a>
|
|
80021da: 08ca lsrs r2, r1, #3
|
|
80021dc: 421a tst r2, r3
|
|
80021de: d104 bne.n 80021ea <__aeabi_dsub+0x73a>
|
|
80021e0: 4663 mov r3, ip
|
|
80021e2: 0010 movs r0, r2
|
|
80021e4: 08df lsrs r7, r3, #3
|
|
80021e6: 0749 lsls r1, r1, #29
|
|
80021e8: 430f orrs r7, r1
|
|
80021ea: 0f7b lsrs r3, r7, #29
|
|
80021ec: 00ff lsls r7, r7, #3
|
|
80021ee: 08ff lsrs r7, r7, #3
|
|
80021f0: 075b lsls r3, r3, #29
|
|
80021f2: 431f orrs r7, r3
|
|
80021f4: e50d b.n 8001c12 <__aeabi_dsub+0x162>
|
|
80021f6: 4662 mov r2, ip
|
|
80021f8: 000d movs r5, r1
|
|
80021fa: 08d7 lsrs r7, r2, #3
|
|
80021fc: e5d2 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
80021fe: 08c7 lsrs r7, r0, #3
|
|
8002200: 076b lsls r3, r5, #29
|
|
8002202: 431f orrs r7, r3
|
|
8002204: 08e8 lsrs r0, r5, #3
|
|
8002206: 2a00 cmp r2, #0
|
|
8002208: d100 bne.n 800220c <__aeabi_dsub+0x75c>
|
|
800220a: e502 b.n 8001c12 <__aeabi_dsub+0x162>
|
|
800220c: 2380 movs r3, #128 @ 0x80
|
|
800220e: 031b lsls r3, r3, #12
|
|
8002210: 4218 tst r0, r3
|
|
8002212: d0ea beq.n 80021ea <__aeabi_dsub+0x73a>
|
|
8002214: 08ca lsrs r2, r1, #3
|
|
8002216: 421a tst r2, r3
|
|
8002218: d1e7 bne.n 80021ea <__aeabi_dsub+0x73a>
|
|
800221a: 4663 mov r3, ip
|
|
800221c: 2401 movs r4, #1
|
|
800221e: 08df lsrs r7, r3, #3
|
|
8002220: 4643 mov r3, r8
|
|
8002222: 0749 lsls r1, r1, #29
|
|
8002224: 0010 movs r0, r2
|
|
8002226: 430f orrs r7, r1
|
|
8002228: 401c ands r4, r3
|
|
800222a: e7de b.n 80021ea <__aeabi_dsub+0x73a>
|
|
800222c: 4460 add r0, ip
|
|
800222e: 4560 cmp r0, ip
|
|
8002230: 4192 sbcs r2, r2
|
|
8002232: 1869 adds r1, r5, r1
|
|
8002234: 4252 negs r2, r2
|
|
8002236: 1889 adds r1, r1, r2
|
|
8002238: 0006 movs r6, r0
|
|
800223a: 020b lsls r3, r1, #8
|
|
800223c: d500 bpl.n 8002240 <__aeabi_dsub+0x790>
|
|
800223e: e6f2 b.n 8002026 <__aeabi_dsub+0x576>
|
|
8002240: 074a lsls r2, r1, #29
|
|
8002242: 08f6 lsrs r6, r6, #3
|
|
8002244: 2301 movs r3, #1
|
|
8002246: 4332 orrs r2, r6
|
|
8002248: 08c8 lsrs r0, r1, #3
|
|
800224a: e68d b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
800224c: 4663 mov r3, ip
|
|
800224e: 08df lsrs r7, r3, #3
|
|
8002250: 074b lsls r3, r1, #29
|
|
8002252: 4644 mov r4, r8
|
|
8002254: 431f orrs r7, r3
|
|
8002256: 08c8 lsrs r0, r1, #3
|
|
8002258: e4db b.n 8001c12 <__aeabi_dsub+0x162>
|
|
800225a: 4644 mov r4, r8
|
|
800225c: 0013 movs r3, r2
|
|
800225e: e735 b.n 80020cc <__aeabi_dsub+0x61c>
|
|
8002260: 001a movs r2, r3
|
|
8002262: 002e movs r6, r5
|
|
8002264: 3a20 subs r2, #32
|
|
8002266: 40d6 lsrs r6, r2
|
|
8002268: 2b20 cmp r3, #32
|
|
800226a: d005 beq.n 8002278 <__aeabi_dsub+0x7c8>
|
|
800226c: 2240 movs r2, #64 @ 0x40
|
|
800226e: 1ad3 subs r3, r2, r3
|
|
8002270: 409d lsls r5, r3
|
|
8002272: 002f movs r7, r5
|
|
8002274: 4307 orrs r7, r0
|
|
8002276: 46bb mov fp, r7
|
|
8002278: 465f mov r7, fp
|
|
800227a: 1e7b subs r3, r7, #1
|
|
800227c: 419f sbcs r7, r3
|
|
800227e: 4337 orrs r7, r6
|
|
8002280: e78e b.n 80021a0 <__aeabi_dsub+0x6f0>
|
|
8002282: 2320 movs r3, #32
|
|
8002284: 2700 movs r7, #0
|
|
8002286: 1a1b subs r3, r3, r0
|
|
8002288: e4f5 b.n 8001c76 <__aeabi_dsub+0x1c6>
|
|
800228a: 2300 movs r3, #0
|
|
800228c: 2a00 cmp r2, #0
|
|
800228e: d100 bne.n 8002292 <__aeabi_dsub+0x7e2>
|
|
8002290: e592 b.n 8001db8 <__aeabi_dsub+0x308>
|
|
8002292: 4667 mov r7, ip
|
|
8002294: 000d movs r5, r1
|
|
8002296: 08ff lsrs r7, r7, #3
|
|
8002298: e584 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
800229a: 003a movs r2, r7
|
|
800229c: 431a orrs r2, r3
|
|
800229e: d100 bne.n 80022a2 <__aeabi_dsub+0x7f2>
|
|
80022a0: e623 b.n 8001eea <__aeabi_dsub+0x43a>
|
|
80022a2: 001d movs r5, r3
|
|
80022a4: 46bb mov fp, r7
|
|
80022a6: e60b b.n 8001ec0 <__aeabi_dsub+0x410>
|
|
80022a8: 0017 movs r7, r2
|
|
80022aa: 0033 movs r3, r6
|
|
80022ac: 08ff lsrs r7, r7, #3
|
|
80022ae: e579 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
80022b0: 08db lsrs r3, r3, #3
|
|
80022b2: 0752 lsls r2, r2, #29
|
|
80022b4: 431a orrs r2, r3
|
|
80022b6: 0908 lsrs r0, r1, #4
|
|
80022b8: 2302 movs r3, #2
|
|
80022ba: e655 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
80022bc: 4663 mov r3, ip
|
|
80022be: 2401 movs r4, #1
|
|
80022c0: 08da lsrs r2, r3, #3
|
|
80022c2: 4643 mov r3, r8
|
|
80022c4: 074f lsls r7, r1, #29
|
|
80022c6: 4317 orrs r7, r2
|
|
80022c8: 08c8 lsrs r0, r1, #3
|
|
80022ca: 401c ands r4, r3
|
|
80022cc: e4a1 b.n 8001c12 <__aeabi_dsub+0x162>
|
|
80022ce: 001e movs r6, r3
|
|
80022d0: 1c47 adds r7, r0, #1
|
|
80022d2: e469 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
80022d4: 4667 mov r7, ip
|
|
80022d6: 000d movs r5, r1
|
|
80022d8: 464e mov r6, r9
|
|
80022da: 3701 adds r7, #1
|
|
80022dc: e464 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
80022de: 4b0f ldr r3, [pc, #60] @ (800231c <__aeabi_dsub+0x86c>)
|
|
80022e0: 08ff lsrs r7, r7, #3
|
|
80022e2: 401d ands r5, r3
|
|
80022e4: 076a lsls r2, r5, #29
|
|
80022e6: 026d lsls r5, r5, #9
|
|
80022e8: 2301 movs r3, #1
|
|
80022ea: 433a orrs r2, r7
|
|
80022ec: 0b2d lsrs r5, r5, #12
|
|
80022ee: e471 b.n 8001bd4 <__aeabi_dsub+0x124>
|
|
80022f0: 0013 movs r3, r2
|
|
80022f2: e746 b.n 8002182 <__aeabi_dsub+0x6d2>
|
|
80022f4: 0033 movs r3, r6
|
|
80022f6: 08ff lsrs r7, r7, #3
|
|
80022f8: e554 b.n 8001da4 <__aeabi_dsub+0x2f4>
|
|
80022fa: 4667 mov r7, ip
|
|
80022fc: 000d movs r5, r1
|
|
80022fe: 001e movs r6, r3
|
|
8002300: 3701 adds r7, #1
|
|
8002302: e451 b.n 8001ba8 <__aeabi_dsub+0xf8>
|
|
8002304: 076a lsls r2, r5, #29
|
|
8002306: 08ff lsrs r7, r7, #3
|
|
8002308: 433a orrs r2, r7
|
|
800230a: 0900 lsrs r0, r0, #4
|
|
800230c: e62c b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
800230e: 08c0 lsrs r0, r0, #3
|
|
8002310: 076a lsls r2, r5, #29
|
|
8002312: 4302 orrs r2, r0
|
|
8002314: 2300 movs r3, #0
|
|
8002316: 08e8 lsrs r0, r5, #3
|
|
8002318: e626 b.n 8001f68 <__aeabi_dsub+0x4b8>
|
|
800231a: 46c0 nop @ (mov r8, r8)
|
|
800231c: ff7fffff .word 0xff7fffff
|
|
|
|
08002320 <__aeabi_d2iz>:
|
|
8002320: 000b movs r3, r1
|
|
8002322: 0002 movs r2, r0
|
|
8002324: b570 push {r4, r5, r6, lr}
|
|
8002326: 4d16 ldr r5, [pc, #88] @ (8002380 <__aeabi_d2iz+0x60>)
|
|
8002328: 030c lsls r4, r1, #12
|
|
800232a: b082 sub sp, #8
|
|
800232c: 0049 lsls r1, r1, #1
|
|
800232e: 2000 movs r0, #0
|
|
8002330: 9200 str r2, [sp, #0]
|
|
8002332: 9301 str r3, [sp, #4]
|
|
8002334: 0b24 lsrs r4, r4, #12
|
|
8002336: 0d49 lsrs r1, r1, #21
|
|
8002338: 0fde lsrs r6, r3, #31
|
|
800233a: 42a9 cmp r1, r5
|
|
800233c: dd04 ble.n 8002348 <__aeabi_d2iz+0x28>
|
|
800233e: 4811 ldr r0, [pc, #68] @ (8002384 <__aeabi_d2iz+0x64>)
|
|
8002340: 4281 cmp r1, r0
|
|
8002342: dd03 ble.n 800234c <__aeabi_d2iz+0x2c>
|
|
8002344: 4b10 ldr r3, [pc, #64] @ (8002388 <__aeabi_d2iz+0x68>)
|
|
8002346: 18f0 adds r0, r6, r3
|
|
8002348: b002 add sp, #8
|
|
800234a: bd70 pop {r4, r5, r6, pc}
|
|
800234c: 2080 movs r0, #128 @ 0x80
|
|
800234e: 0340 lsls r0, r0, #13
|
|
8002350: 4320 orrs r0, r4
|
|
8002352: 4c0e ldr r4, [pc, #56] @ (800238c <__aeabi_d2iz+0x6c>)
|
|
8002354: 1a64 subs r4, r4, r1
|
|
8002356: 2c1f cmp r4, #31
|
|
8002358: dd08 ble.n 800236c <__aeabi_d2iz+0x4c>
|
|
800235a: 4b0d ldr r3, [pc, #52] @ (8002390 <__aeabi_d2iz+0x70>)
|
|
800235c: 1a5b subs r3, r3, r1
|
|
800235e: 40d8 lsrs r0, r3
|
|
8002360: 0003 movs r3, r0
|
|
8002362: 4258 negs r0, r3
|
|
8002364: 2e00 cmp r6, #0
|
|
8002366: d1ef bne.n 8002348 <__aeabi_d2iz+0x28>
|
|
8002368: 0018 movs r0, r3
|
|
800236a: e7ed b.n 8002348 <__aeabi_d2iz+0x28>
|
|
800236c: 4b09 ldr r3, [pc, #36] @ (8002394 <__aeabi_d2iz+0x74>)
|
|
800236e: 9a00 ldr r2, [sp, #0]
|
|
8002370: 469c mov ip, r3
|
|
8002372: 0003 movs r3, r0
|
|
8002374: 4461 add r1, ip
|
|
8002376: 408b lsls r3, r1
|
|
8002378: 40e2 lsrs r2, r4
|
|
800237a: 4313 orrs r3, r2
|
|
800237c: e7f1 b.n 8002362 <__aeabi_d2iz+0x42>
|
|
800237e: 46c0 nop @ (mov r8, r8)
|
|
8002380: 000003fe .word 0x000003fe
|
|
8002384: 0000041d .word 0x0000041d
|
|
8002388: 7fffffff .word 0x7fffffff
|
|
800238c: 00000433 .word 0x00000433
|
|
8002390: 00000413 .word 0x00000413
|
|
8002394: fffffbed .word 0xfffffbed
|
|
|
|
08002398 <__aeabi_i2d>:
|
|
8002398: b570 push {r4, r5, r6, lr}
|
|
800239a: 2800 cmp r0, #0
|
|
800239c: d016 beq.n 80023cc <__aeabi_i2d+0x34>
|
|
800239e: 17c3 asrs r3, r0, #31
|
|
80023a0: 18c5 adds r5, r0, r3
|
|
80023a2: 405d eors r5, r3
|
|
80023a4: 0fc4 lsrs r4, r0, #31
|
|
80023a6: 0028 movs r0, r5
|
|
80023a8: f000 f862 bl 8002470 <__clzsi2>
|
|
80023ac: 4b10 ldr r3, [pc, #64] @ (80023f0 <__aeabi_i2d+0x58>)
|
|
80023ae: 1a1b subs r3, r3, r0
|
|
80023b0: 055b lsls r3, r3, #21
|
|
80023b2: 0d5b lsrs r3, r3, #21
|
|
80023b4: 280a cmp r0, #10
|
|
80023b6: dc14 bgt.n 80023e2 <__aeabi_i2d+0x4a>
|
|
80023b8: 0002 movs r2, r0
|
|
80023ba: 002e movs r6, r5
|
|
80023bc: 3215 adds r2, #21
|
|
80023be: 4096 lsls r6, r2
|
|
80023c0: 220b movs r2, #11
|
|
80023c2: 1a12 subs r2, r2, r0
|
|
80023c4: 40d5 lsrs r5, r2
|
|
80023c6: 032d lsls r5, r5, #12
|
|
80023c8: 0b2d lsrs r5, r5, #12
|
|
80023ca: e003 b.n 80023d4 <__aeabi_i2d+0x3c>
|
|
80023cc: 2400 movs r4, #0
|
|
80023ce: 2300 movs r3, #0
|
|
80023d0: 2500 movs r5, #0
|
|
80023d2: 2600 movs r6, #0
|
|
80023d4: 051b lsls r3, r3, #20
|
|
80023d6: 432b orrs r3, r5
|
|
80023d8: 07e4 lsls r4, r4, #31
|
|
80023da: 4323 orrs r3, r4
|
|
80023dc: 0030 movs r0, r6
|
|
80023de: 0019 movs r1, r3
|
|
80023e0: bd70 pop {r4, r5, r6, pc}
|
|
80023e2: 380b subs r0, #11
|
|
80023e4: 4085 lsls r5, r0
|
|
80023e6: 032d lsls r5, r5, #12
|
|
80023e8: 2600 movs r6, #0
|
|
80023ea: 0b2d lsrs r5, r5, #12
|
|
80023ec: e7f2 b.n 80023d4 <__aeabi_i2d+0x3c>
|
|
80023ee: 46c0 nop @ (mov r8, r8)
|
|
80023f0: 0000041e .word 0x0000041e
|
|
|
|
080023f4 <__aeabi_cdrcmple>:
|
|
80023f4: 4684 mov ip, r0
|
|
80023f6: 0010 movs r0, r2
|
|
80023f8: 4662 mov r2, ip
|
|
80023fa: 468c mov ip, r1
|
|
80023fc: 0019 movs r1, r3
|
|
80023fe: 4663 mov r3, ip
|
|
8002400: e000 b.n 8002404 <__aeabi_cdcmpeq>
|
|
8002402: 46c0 nop @ (mov r8, r8)
|
|
|
|
08002404 <__aeabi_cdcmpeq>:
|
|
8002404: b51f push {r0, r1, r2, r3, r4, lr}
|
|
8002406: f000 f907 bl 8002618 <__ledf2>
|
|
800240a: 2800 cmp r0, #0
|
|
800240c: d401 bmi.n 8002412 <__aeabi_cdcmpeq+0xe>
|
|
800240e: 2100 movs r1, #0
|
|
8002410: 42c8 cmn r0, r1
|
|
8002412: bd1f pop {r0, r1, r2, r3, r4, pc}
|
|
|
|
08002414 <__aeabi_dcmpeq>:
|
|
8002414: b510 push {r4, lr}
|
|
8002416: f000 f849 bl 80024ac <__eqdf2>
|
|
800241a: 4240 negs r0, r0
|
|
800241c: 3001 adds r0, #1
|
|
800241e: bd10 pop {r4, pc}
|
|
|
|
08002420 <__aeabi_dcmplt>:
|
|
8002420: b510 push {r4, lr}
|
|
8002422: f000 f8f9 bl 8002618 <__ledf2>
|
|
8002426: 2800 cmp r0, #0
|
|
8002428: db01 blt.n 800242e <__aeabi_dcmplt+0xe>
|
|
800242a: 2000 movs r0, #0
|
|
800242c: bd10 pop {r4, pc}
|
|
800242e: 2001 movs r0, #1
|
|
8002430: bd10 pop {r4, pc}
|
|
8002432: 46c0 nop @ (mov r8, r8)
|
|
|
|
08002434 <__aeabi_dcmple>:
|
|
8002434: b510 push {r4, lr}
|
|
8002436: f000 f8ef bl 8002618 <__ledf2>
|
|
800243a: 2800 cmp r0, #0
|
|
800243c: dd01 ble.n 8002442 <__aeabi_dcmple+0xe>
|
|
800243e: 2000 movs r0, #0
|
|
8002440: bd10 pop {r4, pc}
|
|
8002442: 2001 movs r0, #1
|
|
8002444: bd10 pop {r4, pc}
|
|
8002446: 46c0 nop @ (mov r8, r8)
|
|
|
|
08002448 <__aeabi_dcmpgt>:
|
|
8002448: b510 push {r4, lr}
|
|
800244a: f000 f875 bl 8002538 <__gedf2>
|
|
800244e: 2800 cmp r0, #0
|
|
8002450: dc01 bgt.n 8002456 <__aeabi_dcmpgt+0xe>
|
|
8002452: 2000 movs r0, #0
|
|
8002454: bd10 pop {r4, pc}
|
|
8002456: 2001 movs r0, #1
|
|
8002458: bd10 pop {r4, pc}
|
|
800245a: 46c0 nop @ (mov r8, r8)
|
|
|
|
0800245c <__aeabi_dcmpge>:
|
|
800245c: b510 push {r4, lr}
|
|
800245e: f000 f86b bl 8002538 <__gedf2>
|
|
8002462: 2800 cmp r0, #0
|
|
8002464: da01 bge.n 800246a <__aeabi_dcmpge+0xe>
|
|
8002466: 2000 movs r0, #0
|
|
8002468: bd10 pop {r4, pc}
|
|
800246a: 2001 movs r0, #1
|
|
800246c: bd10 pop {r4, pc}
|
|
800246e: 46c0 nop @ (mov r8, r8)
|
|
|
|
08002470 <__clzsi2>:
|
|
8002470: 211c movs r1, #28
|
|
8002472: 2301 movs r3, #1
|
|
8002474: 041b lsls r3, r3, #16
|
|
8002476: 4298 cmp r0, r3
|
|
8002478: d301 bcc.n 800247e <__clzsi2+0xe>
|
|
800247a: 0c00 lsrs r0, r0, #16
|
|
800247c: 3910 subs r1, #16
|
|
800247e: 0a1b lsrs r3, r3, #8
|
|
8002480: 4298 cmp r0, r3
|
|
8002482: d301 bcc.n 8002488 <__clzsi2+0x18>
|
|
8002484: 0a00 lsrs r0, r0, #8
|
|
8002486: 3908 subs r1, #8
|
|
8002488: 091b lsrs r3, r3, #4
|
|
800248a: 4298 cmp r0, r3
|
|
800248c: d301 bcc.n 8002492 <__clzsi2+0x22>
|
|
800248e: 0900 lsrs r0, r0, #4
|
|
8002490: 3904 subs r1, #4
|
|
8002492: a202 add r2, pc, #8 @ (adr r2, 800249c <__clzsi2+0x2c>)
|
|
8002494: 5c10 ldrb r0, [r2, r0]
|
|
8002496: 1840 adds r0, r0, r1
|
|
8002498: 4770 bx lr
|
|
800249a: 46c0 nop @ (mov r8, r8)
|
|
800249c: 02020304 .word 0x02020304
|
|
80024a0: 01010101 .word 0x01010101
|
|
...
|
|
|
|
080024ac <__eqdf2>:
|
|
80024ac: b5f0 push {r4, r5, r6, r7, lr}
|
|
80024ae: 4657 mov r7, sl
|
|
80024b0: 46de mov lr, fp
|
|
80024b2: 464e mov r6, r9
|
|
80024b4: 4645 mov r5, r8
|
|
80024b6: b5e0 push {r5, r6, r7, lr}
|
|
80024b8: 000d movs r5, r1
|
|
80024ba: 0004 movs r4, r0
|
|
80024bc: 0fe8 lsrs r0, r5, #31
|
|
80024be: 4683 mov fp, r0
|
|
80024c0: 0309 lsls r1, r1, #12
|
|
80024c2: 0fd8 lsrs r0, r3, #31
|
|
80024c4: 0b09 lsrs r1, r1, #12
|
|
80024c6: 4682 mov sl, r0
|
|
80024c8: 481a ldr r0, [pc, #104] @ (8002534 <__eqdf2+0x88>)
|
|
80024ca: 468c mov ip, r1
|
|
80024cc: 031f lsls r7, r3, #12
|
|
80024ce: 0069 lsls r1, r5, #1
|
|
80024d0: 005e lsls r6, r3, #1
|
|
80024d2: 0d49 lsrs r1, r1, #21
|
|
80024d4: 0b3f lsrs r7, r7, #12
|
|
80024d6: 0d76 lsrs r6, r6, #21
|
|
80024d8: 4281 cmp r1, r0
|
|
80024da: d01a beq.n 8002512 <__eqdf2+0x66>
|
|
80024dc: 4286 cmp r6, r0
|
|
80024de: d011 beq.n 8002504 <__eqdf2+0x58>
|
|
80024e0: 2001 movs r0, #1
|
|
80024e2: 42b1 cmp r1, r6
|
|
80024e4: d10f bne.n 8002506 <__eqdf2+0x5a>
|
|
80024e6: 45bc cmp ip, r7
|
|
80024e8: d10d bne.n 8002506 <__eqdf2+0x5a>
|
|
80024ea: 42a2 cmp r2, r4
|
|
80024ec: d10b bne.n 8002506 <__eqdf2+0x5a>
|
|
80024ee: 45d3 cmp fp, sl
|
|
80024f0: d01e beq.n 8002530 <__eqdf2+0x84>
|
|
80024f2: 2900 cmp r1, #0
|
|
80024f4: d107 bne.n 8002506 <__eqdf2+0x5a>
|
|
80024f6: 4661 mov r1, ip
|
|
80024f8: 4311 orrs r1, r2
|
|
80024fa: 000a movs r2, r1
|
|
80024fc: 1e53 subs r3, r2, #1
|
|
80024fe: 419a sbcs r2, r3
|
|
8002500: 0010 movs r0, r2
|
|
8002502: e000 b.n 8002506 <__eqdf2+0x5a>
|
|
8002504: 2001 movs r0, #1
|
|
8002506: bcf0 pop {r4, r5, r6, r7}
|
|
8002508: 46bb mov fp, r7
|
|
800250a: 46b2 mov sl, r6
|
|
800250c: 46a9 mov r9, r5
|
|
800250e: 46a0 mov r8, r4
|
|
8002510: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8002512: 2001 movs r0, #1
|
|
8002514: 428e cmp r6, r1
|
|
8002516: d1f6 bne.n 8002506 <__eqdf2+0x5a>
|
|
8002518: 4661 mov r1, ip
|
|
800251a: 4339 orrs r1, r7
|
|
800251c: 000f movs r7, r1
|
|
800251e: 4317 orrs r7, r2
|
|
8002520: 4327 orrs r7, r4
|
|
8002522: d1f0 bne.n 8002506 <__eqdf2+0x5a>
|
|
8002524: 465b mov r3, fp
|
|
8002526: 4652 mov r2, sl
|
|
8002528: 1a98 subs r0, r3, r2
|
|
800252a: 1e43 subs r3, r0, #1
|
|
800252c: 4198 sbcs r0, r3
|
|
800252e: e7ea b.n 8002506 <__eqdf2+0x5a>
|
|
8002530: 2000 movs r0, #0
|
|
8002532: e7e8 b.n 8002506 <__eqdf2+0x5a>
|
|
8002534: 000007ff .word 0x000007ff
|
|
|
|
08002538 <__gedf2>:
|
|
8002538: b5f0 push {r4, r5, r6, r7, lr}
|
|
800253a: 4657 mov r7, sl
|
|
800253c: 464e mov r6, r9
|
|
800253e: 4645 mov r5, r8
|
|
8002540: 46de mov lr, fp
|
|
8002542: b5e0 push {r5, r6, r7, lr}
|
|
8002544: 000d movs r5, r1
|
|
8002546: 030e lsls r6, r1, #12
|
|
8002548: 0049 lsls r1, r1, #1
|
|
800254a: 0d49 lsrs r1, r1, #21
|
|
800254c: 468a mov sl, r1
|
|
800254e: 0fdf lsrs r7, r3, #31
|
|
8002550: 0fe9 lsrs r1, r5, #31
|
|
8002552: 46bc mov ip, r7
|
|
8002554: b083 sub sp, #12
|
|
8002556: 4f2f ldr r7, [pc, #188] @ (8002614 <__gedf2+0xdc>)
|
|
8002558: 0004 movs r4, r0
|
|
800255a: 4680 mov r8, r0
|
|
800255c: 9101 str r1, [sp, #4]
|
|
800255e: 0058 lsls r0, r3, #1
|
|
8002560: 0319 lsls r1, r3, #12
|
|
8002562: 4691 mov r9, r2
|
|
8002564: 0b36 lsrs r6, r6, #12
|
|
8002566: 0b09 lsrs r1, r1, #12
|
|
8002568: 0d40 lsrs r0, r0, #21
|
|
800256a: 45ba cmp sl, r7
|
|
800256c: d01d beq.n 80025aa <__gedf2+0x72>
|
|
800256e: 42b8 cmp r0, r7
|
|
8002570: d00d beq.n 800258e <__gedf2+0x56>
|
|
8002572: 4657 mov r7, sl
|
|
8002574: 2f00 cmp r7, #0
|
|
8002576: d12a bne.n 80025ce <__gedf2+0x96>
|
|
8002578: 4334 orrs r4, r6
|
|
800257a: 2800 cmp r0, #0
|
|
800257c: d124 bne.n 80025c8 <__gedf2+0x90>
|
|
800257e: 430a orrs r2, r1
|
|
8002580: d036 beq.n 80025f0 <__gedf2+0xb8>
|
|
8002582: 2c00 cmp r4, #0
|
|
8002584: d141 bne.n 800260a <__gedf2+0xd2>
|
|
8002586: 4663 mov r3, ip
|
|
8002588: 0058 lsls r0, r3, #1
|
|
800258a: 3801 subs r0, #1
|
|
800258c: e015 b.n 80025ba <__gedf2+0x82>
|
|
800258e: 4311 orrs r1, r2
|
|
8002590: d138 bne.n 8002604 <__gedf2+0xcc>
|
|
8002592: 4653 mov r3, sl
|
|
8002594: 2b00 cmp r3, #0
|
|
8002596: d101 bne.n 800259c <__gedf2+0x64>
|
|
8002598: 4326 orrs r6, r4
|
|
800259a: d0f4 beq.n 8002586 <__gedf2+0x4e>
|
|
800259c: 9b01 ldr r3, [sp, #4]
|
|
800259e: 4563 cmp r3, ip
|
|
80025a0: d107 bne.n 80025b2 <__gedf2+0x7a>
|
|
80025a2: 9b01 ldr r3, [sp, #4]
|
|
80025a4: 0058 lsls r0, r3, #1
|
|
80025a6: 3801 subs r0, #1
|
|
80025a8: e007 b.n 80025ba <__gedf2+0x82>
|
|
80025aa: 4326 orrs r6, r4
|
|
80025ac: d12a bne.n 8002604 <__gedf2+0xcc>
|
|
80025ae: 4550 cmp r0, sl
|
|
80025b0: d021 beq.n 80025f6 <__gedf2+0xbe>
|
|
80025b2: 2001 movs r0, #1
|
|
80025b4: 9b01 ldr r3, [sp, #4]
|
|
80025b6: 425f negs r7, r3
|
|
80025b8: 4338 orrs r0, r7
|
|
80025ba: b003 add sp, #12
|
|
80025bc: bcf0 pop {r4, r5, r6, r7}
|
|
80025be: 46bb mov fp, r7
|
|
80025c0: 46b2 mov sl, r6
|
|
80025c2: 46a9 mov r9, r5
|
|
80025c4: 46a0 mov r8, r4
|
|
80025c6: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80025c8: 2c00 cmp r4, #0
|
|
80025ca: d0dc beq.n 8002586 <__gedf2+0x4e>
|
|
80025cc: e7e6 b.n 800259c <__gedf2+0x64>
|
|
80025ce: 2800 cmp r0, #0
|
|
80025d0: d0ef beq.n 80025b2 <__gedf2+0x7a>
|
|
80025d2: 9b01 ldr r3, [sp, #4]
|
|
80025d4: 4563 cmp r3, ip
|
|
80025d6: d1ec bne.n 80025b2 <__gedf2+0x7a>
|
|
80025d8: 4582 cmp sl, r0
|
|
80025da: dcea bgt.n 80025b2 <__gedf2+0x7a>
|
|
80025dc: dbe1 blt.n 80025a2 <__gedf2+0x6a>
|
|
80025de: 428e cmp r6, r1
|
|
80025e0: d8e7 bhi.n 80025b2 <__gedf2+0x7a>
|
|
80025e2: d1de bne.n 80025a2 <__gedf2+0x6a>
|
|
80025e4: 45c8 cmp r8, r9
|
|
80025e6: d8e4 bhi.n 80025b2 <__gedf2+0x7a>
|
|
80025e8: 2000 movs r0, #0
|
|
80025ea: 45c8 cmp r8, r9
|
|
80025ec: d2e5 bcs.n 80025ba <__gedf2+0x82>
|
|
80025ee: e7d8 b.n 80025a2 <__gedf2+0x6a>
|
|
80025f0: 2c00 cmp r4, #0
|
|
80025f2: d0e2 beq.n 80025ba <__gedf2+0x82>
|
|
80025f4: e7dd b.n 80025b2 <__gedf2+0x7a>
|
|
80025f6: 4311 orrs r1, r2
|
|
80025f8: d104 bne.n 8002604 <__gedf2+0xcc>
|
|
80025fa: 9b01 ldr r3, [sp, #4]
|
|
80025fc: 4563 cmp r3, ip
|
|
80025fe: d1d8 bne.n 80025b2 <__gedf2+0x7a>
|
|
8002600: 2000 movs r0, #0
|
|
8002602: e7da b.n 80025ba <__gedf2+0x82>
|
|
8002604: 2002 movs r0, #2
|
|
8002606: 4240 negs r0, r0
|
|
8002608: e7d7 b.n 80025ba <__gedf2+0x82>
|
|
800260a: 9b01 ldr r3, [sp, #4]
|
|
800260c: 4563 cmp r3, ip
|
|
800260e: d0e6 beq.n 80025de <__gedf2+0xa6>
|
|
8002610: e7cf b.n 80025b2 <__gedf2+0x7a>
|
|
8002612: 46c0 nop @ (mov r8, r8)
|
|
8002614: 000007ff .word 0x000007ff
|
|
|
|
08002618 <__ledf2>:
|
|
8002618: b5f0 push {r4, r5, r6, r7, lr}
|
|
800261a: 4657 mov r7, sl
|
|
800261c: 464e mov r6, r9
|
|
800261e: 4645 mov r5, r8
|
|
8002620: 46de mov lr, fp
|
|
8002622: b5e0 push {r5, r6, r7, lr}
|
|
8002624: 000d movs r5, r1
|
|
8002626: 030e lsls r6, r1, #12
|
|
8002628: 0049 lsls r1, r1, #1
|
|
800262a: 0d49 lsrs r1, r1, #21
|
|
800262c: 468a mov sl, r1
|
|
800262e: 0fdf lsrs r7, r3, #31
|
|
8002630: 0fe9 lsrs r1, r5, #31
|
|
8002632: 46bc mov ip, r7
|
|
8002634: b083 sub sp, #12
|
|
8002636: 4f2e ldr r7, [pc, #184] @ (80026f0 <__ledf2+0xd8>)
|
|
8002638: 0004 movs r4, r0
|
|
800263a: 4680 mov r8, r0
|
|
800263c: 9101 str r1, [sp, #4]
|
|
800263e: 0058 lsls r0, r3, #1
|
|
8002640: 0319 lsls r1, r3, #12
|
|
8002642: 4691 mov r9, r2
|
|
8002644: 0b36 lsrs r6, r6, #12
|
|
8002646: 0b09 lsrs r1, r1, #12
|
|
8002648: 0d40 lsrs r0, r0, #21
|
|
800264a: 45ba cmp sl, r7
|
|
800264c: d01e beq.n 800268c <__ledf2+0x74>
|
|
800264e: 42b8 cmp r0, r7
|
|
8002650: d00d beq.n 800266e <__ledf2+0x56>
|
|
8002652: 4657 mov r7, sl
|
|
8002654: 2f00 cmp r7, #0
|
|
8002656: d127 bne.n 80026a8 <__ledf2+0x90>
|
|
8002658: 4334 orrs r4, r6
|
|
800265a: 2800 cmp r0, #0
|
|
800265c: d133 bne.n 80026c6 <__ledf2+0xae>
|
|
800265e: 430a orrs r2, r1
|
|
8002660: d034 beq.n 80026cc <__ledf2+0xb4>
|
|
8002662: 2c00 cmp r4, #0
|
|
8002664: d140 bne.n 80026e8 <__ledf2+0xd0>
|
|
8002666: 4663 mov r3, ip
|
|
8002668: 0058 lsls r0, r3, #1
|
|
800266a: 3801 subs r0, #1
|
|
800266c: e015 b.n 800269a <__ledf2+0x82>
|
|
800266e: 4311 orrs r1, r2
|
|
8002670: d112 bne.n 8002698 <__ledf2+0x80>
|
|
8002672: 4653 mov r3, sl
|
|
8002674: 2b00 cmp r3, #0
|
|
8002676: d101 bne.n 800267c <__ledf2+0x64>
|
|
8002678: 4326 orrs r6, r4
|
|
800267a: d0f4 beq.n 8002666 <__ledf2+0x4e>
|
|
800267c: 9b01 ldr r3, [sp, #4]
|
|
800267e: 4563 cmp r3, ip
|
|
8002680: d01d beq.n 80026be <__ledf2+0xa6>
|
|
8002682: 2001 movs r0, #1
|
|
8002684: 9b01 ldr r3, [sp, #4]
|
|
8002686: 425f negs r7, r3
|
|
8002688: 4338 orrs r0, r7
|
|
800268a: e006 b.n 800269a <__ledf2+0x82>
|
|
800268c: 4326 orrs r6, r4
|
|
800268e: d103 bne.n 8002698 <__ledf2+0x80>
|
|
8002690: 4550 cmp r0, sl
|
|
8002692: d1f6 bne.n 8002682 <__ledf2+0x6a>
|
|
8002694: 4311 orrs r1, r2
|
|
8002696: d01c beq.n 80026d2 <__ledf2+0xba>
|
|
8002698: 2002 movs r0, #2
|
|
800269a: b003 add sp, #12
|
|
800269c: bcf0 pop {r4, r5, r6, r7}
|
|
800269e: 46bb mov fp, r7
|
|
80026a0: 46b2 mov sl, r6
|
|
80026a2: 46a9 mov r9, r5
|
|
80026a4: 46a0 mov r8, r4
|
|
80026a6: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80026a8: 2800 cmp r0, #0
|
|
80026aa: d0ea beq.n 8002682 <__ledf2+0x6a>
|
|
80026ac: 9b01 ldr r3, [sp, #4]
|
|
80026ae: 4563 cmp r3, ip
|
|
80026b0: d1e7 bne.n 8002682 <__ledf2+0x6a>
|
|
80026b2: 4582 cmp sl, r0
|
|
80026b4: dce5 bgt.n 8002682 <__ledf2+0x6a>
|
|
80026b6: db02 blt.n 80026be <__ledf2+0xa6>
|
|
80026b8: 428e cmp r6, r1
|
|
80026ba: d8e2 bhi.n 8002682 <__ledf2+0x6a>
|
|
80026bc: d00e beq.n 80026dc <__ledf2+0xc4>
|
|
80026be: 9b01 ldr r3, [sp, #4]
|
|
80026c0: 0058 lsls r0, r3, #1
|
|
80026c2: 3801 subs r0, #1
|
|
80026c4: e7e9 b.n 800269a <__ledf2+0x82>
|
|
80026c6: 2c00 cmp r4, #0
|
|
80026c8: d0cd beq.n 8002666 <__ledf2+0x4e>
|
|
80026ca: e7d7 b.n 800267c <__ledf2+0x64>
|
|
80026cc: 2c00 cmp r4, #0
|
|
80026ce: d0e4 beq.n 800269a <__ledf2+0x82>
|
|
80026d0: e7d7 b.n 8002682 <__ledf2+0x6a>
|
|
80026d2: 9b01 ldr r3, [sp, #4]
|
|
80026d4: 2000 movs r0, #0
|
|
80026d6: 4563 cmp r3, ip
|
|
80026d8: d0df beq.n 800269a <__ledf2+0x82>
|
|
80026da: e7d2 b.n 8002682 <__ledf2+0x6a>
|
|
80026dc: 45c8 cmp r8, r9
|
|
80026de: d8d0 bhi.n 8002682 <__ledf2+0x6a>
|
|
80026e0: 2000 movs r0, #0
|
|
80026e2: 45c8 cmp r8, r9
|
|
80026e4: d2d9 bcs.n 800269a <__ledf2+0x82>
|
|
80026e6: e7ea b.n 80026be <__ledf2+0xa6>
|
|
80026e8: 9b01 ldr r3, [sp, #4]
|
|
80026ea: 4563 cmp r3, ip
|
|
80026ec: d0e4 beq.n 80026b8 <__ledf2+0xa0>
|
|
80026ee: e7c8 b.n 8002682 <__ledf2+0x6a>
|
|
80026f0: 000007ff .word 0x000007ff
|
|
|
|
080026f4 <Adc_Init>:
|
|
* Author: dmitrijs
|
|
*/
|
|
|
|
#include "main.h"
|
|
|
|
void Adc_Init(void) {
|
|
80026f4: b580 push {r7, lr}
|
|
80026f6: af00 add r7, sp, #0
|
|
|
|
RCC->APB2ENR |= RCC_APB2ENR_ADCEN;
|
|
80026f8: 4b28 ldr r3, [pc, #160] @ (800279c <Adc_Init+0xa8>)
|
|
80026fa: 699a ldr r2, [r3, #24]
|
|
80026fc: 4b27 ldr r3, [pc, #156] @ (800279c <Adc_Init+0xa8>)
|
|
80026fe: 2180 movs r1, #128 @ 0x80
|
|
8002700: 0089 lsls r1, r1, #2
|
|
8002702: 430a orrs r2, r1
|
|
8002704: 619a str r2, [r3, #24]
|
|
ADC1->CFGR2 = (0x00000002 << 30); // pclk/4 -> 12Mhz
|
|
8002706: 4b26 ldr r3, [pc, #152] @ (80027a0 <Adc_Init+0xac>)
|
|
8002708: 2280 movs r2, #128 @ 0x80
|
|
800270a: 0612 lsls r2, r2, #24
|
|
800270c: 611a str r2, [r3, #16]
|
|
ADC1->SMPR = 0x00000001; // Sample 7.5 adc cycles
|
|
800270e: 4b24 ldr r3, [pc, #144] @ (80027a0 <Adc_Init+0xac>)
|
|
8002710: 2201 movs r2, #1
|
|
8002712: 615a str r2, [r3, #20]
|
|
ADC1->CFGR1 = 0;
|
|
8002714: 4b22 ldr r3, [pc, #136] @ (80027a0 <Adc_Init+0xac>)
|
|
8002716: 2200 movs r2, #0
|
|
8002718: 60da str r2, [r3, #12]
|
|
/* (1) Ensure that ADEN = 0 */
|
|
/* (2) Clear ADEN by setting ADDIS*/
|
|
/* (3) Clear DMAEN */
|
|
/* (4) Launch the calibration by setting ADCAL */
|
|
/* (5) Wait until ADCAL=0 */
|
|
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */
|
|
800271a: 4b21 ldr r3, [pc, #132] @ (80027a0 <Adc_Init+0xac>)
|
|
800271c: 689b ldr r3, [r3, #8]
|
|
800271e: 2201 movs r2, #1
|
|
8002720: 4013 ands r3, r2
|
|
8002722: d005 beq.n 8002730 <Adc_Init+0x3c>
|
|
{
|
|
ADC1->CR |= ADC_CR_ADDIS; /* (2) */
|
|
8002724: 4b1e ldr r3, [pc, #120] @ (80027a0 <Adc_Init+0xac>)
|
|
8002726: 689a ldr r2, [r3, #8]
|
|
8002728: 4b1d ldr r3, [pc, #116] @ (80027a0 <Adc_Init+0xac>)
|
|
800272a: 2102 movs r1, #2
|
|
800272c: 430a orrs r2, r1
|
|
800272e: 609a str r2, [r3, #8]
|
|
}
|
|
while ((ADC1->CR & ADC_CR_ADEN) != 0) {
|
|
8002730: 46c0 nop @ (mov r8, r8)
|
|
8002732: 4b1b ldr r3, [pc, #108] @ (80027a0 <Adc_Init+0xac>)
|
|
8002734: 689b ldr r3, [r3, #8]
|
|
8002736: 2201 movs r2, #1
|
|
8002738: 4013 ands r3, r2
|
|
800273a: d1fa bne.n 8002732 <Adc_Init+0x3e>
|
|
/* For robust implementation, add here time-out management */
|
|
}
|
|
ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN; /* (3) */
|
|
800273c: 4b18 ldr r3, [pc, #96] @ (80027a0 <Adc_Init+0xac>)
|
|
800273e: 68da ldr r2, [r3, #12]
|
|
8002740: 4b17 ldr r3, [pc, #92] @ (80027a0 <Adc_Init+0xac>)
|
|
8002742: 2101 movs r1, #1
|
|
8002744: 438a bics r2, r1
|
|
8002746: 60da str r2, [r3, #12]
|
|
ADC1->CR |= ADC_CR_ADCAL; /* (4) */
|
|
8002748: 4b15 ldr r3, [pc, #84] @ (80027a0 <Adc_Init+0xac>)
|
|
800274a: 689a ldr r2, [r3, #8]
|
|
800274c: 4b14 ldr r3, [pc, #80] @ (80027a0 <Adc_Init+0xac>)
|
|
800274e: 2180 movs r1, #128 @ 0x80
|
|
8002750: 0609 lsls r1, r1, #24
|
|
8002752: 430a orrs r2, r1
|
|
8002754: 609a str r2, [r3, #8]
|
|
while ((ADC1->CR & ADC_CR_ADCAL) != 0) /* (5) */
|
|
8002756: 46c0 nop @ (mov r8, r8)
|
|
8002758: 4b11 ldr r3, [pc, #68] @ (80027a0 <Adc_Init+0xac>)
|
|
800275a: 689b ldr r3, [r3, #8]
|
|
800275c: 2b00 cmp r3, #0
|
|
800275e: dbfb blt.n 8002758 <Adc_Init+0x64>
|
|
}
|
|
/* (1) Ensure that ADRDY = 0 */
|
|
/* (2) Clear ADRDY */
|
|
/* (3) Enable the ADC */
|
|
/* (4) Wait until ADC ready */
|
|
if ((ADC1->ISR & ADC_ISR_ADRDY) != 0) /* (1) */
|
|
8002760: 4b0f ldr r3, [pc, #60] @ (80027a0 <Adc_Init+0xac>)
|
|
8002762: 681b ldr r3, [r3, #0]
|
|
8002764: 2201 movs r2, #1
|
|
8002766: 4013 ands r3, r2
|
|
8002768: d005 beq.n 8002776 <Adc_Init+0x82>
|
|
{
|
|
ADC1->ISR |= ADC_ISR_ADRDY; /* (2) */
|
|
800276a: 4b0d ldr r3, [pc, #52] @ (80027a0 <Adc_Init+0xac>)
|
|
800276c: 681a ldr r2, [r3, #0]
|
|
800276e: 4b0c ldr r3, [pc, #48] @ (80027a0 <Adc_Init+0xac>)
|
|
8002770: 2101 movs r1, #1
|
|
8002772: 430a orrs r2, r1
|
|
8002774: 601a str r2, [r3, #0]
|
|
}
|
|
ADC1->CR |= ADC_CR_ADEN; /* (3) */
|
|
8002776: 4b0a ldr r3, [pc, #40] @ (80027a0 <Adc_Init+0xac>)
|
|
8002778: 689a ldr r2, [r3, #8]
|
|
800277a: 4b09 ldr r3, [pc, #36] @ (80027a0 <Adc_Init+0xac>)
|
|
800277c: 2101 movs r1, #1
|
|
800277e: 430a orrs r2, r1
|
|
8002780: 609a str r2, [r3, #8]
|
|
while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (4) */
|
|
8002782: 46c0 nop @ (mov r8, r8)
|
|
8002784: 4b06 ldr r3, [pc, #24] @ (80027a0 <Adc_Init+0xac>)
|
|
8002786: 681b ldr r3, [r3, #0]
|
|
8002788: 2201 movs r2, #1
|
|
800278a: 4013 ands r3, r2
|
|
800278c: d0fa beq.n 8002784 <Adc_Init+0x90>
|
|
{
|
|
/*TODO For robust implementation, add here time-out management */
|
|
}
|
|
|
|
ADC1->IER = 0;
|
|
800278e: 4b04 ldr r3, [pc, #16] @ (80027a0 <Adc_Init+0xac>)
|
|
8002790: 2200 movs r2, #0
|
|
8002792: 605a str r2, [r3, #4]
|
|
//NVIC_EnableIRQ(ADC1_IRQn);
|
|
}
|
|
8002794: 46c0 nop @ (mov r8, r8)
|
|
8002796: 46bd mov sp, r7
|
|
8002798: bd80 pop {r7, pc}
|
|
800279a: 46c0 nop @ (mov r8, r8)
|
|
800279c: 40021000 .word 0x40021000
|
|
80027a0: 40012400 .word 0x40012400
|
|
|
|
080027a4 <LPF>:
|
|
|
|
unsigned short LPF(unsigned short lpf_c, unsigned short value,
|
|
unsigned short old_value) {
|
|
80027a4: b590 push {r4, r7, lr}
|
|
80027a6: b085 sub sp, #20
|
|
80027a8: af00 add r7, sp, #0
|
|
80027aa: 0004 movs r4, r0
|
|
80027ac: 0008 movs r0, r1
|
|
80027ae: 0011 movs r1, r2
|
|
80027b0: 1dbb adds r3, r7, #6
|
|
80027b2: 1c22 adds r2, r4, #0
|
|
80027b4: 801a strh r2, [r3, #0]
|
|
80027b6: 1d3b adds r3, r7, #4
|
|
80027b8: 1c02 adds r2, r0, #0
|
|
80027ba: 801a strh r2, [r3, #0]
|
|
80027bc: 1cbb adds r3, r7, #2
|
|
80027be: 1c0a adds r2, r1, #0
|
|
80027c0: 801a strh r2, [r3, #0]
|
|
// Averageing filtering
|
|
|
|
float tmp;
|
|
|
|
tmp = ((float) (value - old_value) * ((float) (lpf_c) / (float) 1000.0)); // filter
|
|
80027c2: 1d3b adds r3, r7, #4
|
|
80027c4: 881a ldrh r2, [r3, #0]
|
|
80027c6: 1cbb adds r3, r7, #2
|
|
80027c8: 881b ldrh r3, [r3, #0]
|
|
80027ca: 1ad3 subs r3, r2, r3
|
|
80027cc: 0018 movs r0, r3
|
|
80027ce: f7fe fe11 bl 80013f4 <__aeabi_i2f>
|
|
80027d2: 1c04 adds r4, r0, #0
|
|
80027d4: 1dbb adds r3, r7, #6
|
|
80027d6: 881b ldrh r3, [r3, #0]
|
|
80027d8: 0018 movs r0, r3
|
|
80027da: f7fe fe5b bl 8001494 <__aeabi_ui2f>
|
|
80027de: 1c03 adds r3, r0, #0
|
|
80027e0: 4916 ldr r1, [pc, #88] @ (800283c <LPF+0x98>)
|
|
80027e2: 1c18 adds r0, r3, #0
|
|
80027e4: f7fe f884 bl 80008f0 <__aeabi_fdiv>
|
|
80027e8: 1c03 adds r3, r0, #0
|
|
80027ea: 1c19 adds r1, r3, #0
|
|
80027ec: 1c20 adds r0, r4, #0
|
|
80027ee: f7fe fa4d bl 8000c8c <__aeabi_fmul>
|
|
80027f2: 1c03 adds r3, r0, #0
|
|
80027f4: 60fb str r3, [r7, #12]
|
|
if (tmp > 0)
|
|
80027f6: 2100 movs r1, #0
|
|
80027f8: 68f8 ldr r0, [r7, #12]
|
|
80027fa: f7fd fe21 bl 8000440 <__aeabi_fcmpgt>
|
|
80027fe: 1e03 subs r3, r0, #0
|
|
8002800: d007 beq.n 8002812 <LPF+0x6e>
|
|
tmp += (float) 0.5; // roundup
|
|
8002802: 21fc movs r1, #252 @ 0xfc
|
|
8002804: 0589 lsls r1, r1, #22
|
|
8002806: 68f8 ldr r0, [r7, #12]
|
|
8002808: f7fd fe64 bl 80004d4 <__aeabi_fadd>
|
|
800280c: 1c03 adds r3, r0, #0
|
|
800280e: 60fb str r3, [r7, #12]
|
|
8002810: e006 b.n 8002820 <LPF+0x7c>
|
|
else
|
|
tmp -= (float) 0.5;
|
|
8002812: 21fc movs r1, #252 @ 0xfc
|
|
8002814: 0589 lsls r1, r1, #22
|
|
8002816: 68f8 ldr r0, [r7, #12]
|
|
8002818: f7fe fb8a bl 8000f30 <__aeabi_fsub>
|
|
800281c: 1c03 adds r3, r0, #0
|
|
800281e: 60fb str r3, [r7, #12]
|
|
|
|
return (unsigned short) ((signed int) old_value + (signed int) tmp);
|
|
8002820: 68f8 ldr r0, [r7, #12]
|
|
8002822: f7fe fdc7 bl 80013b4 <__aeabi_f2iz>
|
|
8002826: 0003 movs r3, r0
|
|
8002828: b29a uxth r2, r3
|
|
800282a: 1cbb adds r3, r7, #2
|
|
800282c: 881b ldrh r3, [r3, #0]
|
|
800282e: 18d3 adds r3, r2, r3
|
|
8002830: b29b uxth r3, r3
|
|
|
|
}
|
|
8002832: 0018 movs r0, r3
|
|
8002834: 46bd mov sp, r7
|
|
8002836: b005 add sp, #20
|
|
8002838: bd90 pop {r4, r7, pc}
|
|
800283a: 46c0 nop @ (mov r8, r8)
|
|
800283c: 447a0000 .word 0x447a0000
|
|
|
|
08002840 <Adc_Read>:
|
|
|
|
unsigned short Adc_Read(unsigned char ch) {
|
|
8002840: b580 push {r7, lr}
|
|
8002842: b084 sub sp, #16
|
|
8002844: af00 add r7, sp, #0
|
|
8002846: 0002 movs r2, r0
|
|
8002848: 1dfb adds r3, r7, #7
|
|
800284a: 701a strb r2, [r3, #0]
|
|
unsigned short tmp;
|
|
if (ADC1->ISR & ADC_ISR_EOC)
|
|
800284c: 4b16 ldr r3, [pc, #88] @ (80028a8 <Adc_Read+0x68>)
|
|
800284e: 681b ldr r3, [r3, #0]
|
|
8002850: 2204 movs r2, #4
|
|
8002852: 4013 ands r3, r2
|
|
8002854: d004 beq.n 8002860 <Adc_Read+0x20>
|
|
tmp = ADC1->DR; //ADC1->ISR |= ADC_ISR_EOC; // clear EOC flag
|
|
8002856: 4b14 ldr r3, [pc, #80] @ (80028a8 <Adc_Read+0x68>)
|
|
8002858: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800285a: 230e movs r3, #14
|
|
800285c: 18fb adds r3, r7, r3
|
|
800285e: 801a strh r2, [r3, #0]
|
|
ADC1->CHSELR = (1 << ch); // select channel
|
|
8002860: 1dfb adds r3, r7, #7
|
|
8002862: 781b ldrb r3, [r3, #0]
|
|
8002864: 2201 movs r2, #1
|
|
8002866: 409a lsls r2, r3
|
|
8002868: 4b0f ldr r3, [pc, #60] @ (80028a8 <Adc_Read+0x68>)
|
|
800286a: 629a str r2, [r3, #40] @ 0x28
|
|
ADC1->CR |= ADC_CR_ADSTART;
|
|
800286c: 4b0e ldr r3, [pc, #56] @ (80028a8 <Adc_Read+0x68>)
|
|
800286e: 689a ldr r2, [r3, #8]
|
|
8002870: 4b0d ldr r3, [pc, #52] @ (80028a8 <Adc_Read+0x68>)
|
|
8002872: 2104 movs r1, #4
|
|
8002874: 430a orrs r2, r1
|
|
8002876: 609a str r2, [r3, #8]
|
|
while ((~ADC1->ISR) & ADC_ISR_EOC)
|
|
8002878: 46c0 nop @ (mov r8, r8)
|
|
800287a: 4b0b ldr r3, [pc, #44] @ (80028a8 <Adc_Read+0x68>)
|
|
800287c: 681b ldr r3, [r3, #0]
|
|
800287e: 2204 movs r2, #4
|
|
8002880: 4013 ands r3, r2
|
|
8002882: d0fa beq.n 800287a <Adc_Read+0x3a>
|
|
;
|
|
ADC1->ISR |= ADC_ISR_EOC;
|
|
8002884: 4b08 ldr r3, [pc, #32] @ (80028a8 <Adc_Read+0x68>)
|
|
8002886: 681a ldr r2, [r3, #0]
|
|
8002888: 4b07 ldr r3, [pc, #28] @ (80028a8 <Adc_Read+0x68>)
|
|
800288a: 2104 movs r1, #4
|
|
800288c: 430a orrs r2, r1
|
|
800288e: 601a str r2, [r3, #0]
|
|
tmp = ADC1->DR;
|
|
8002890: 4b05 ldr r3, [pc, #20] @ (80028a8 <Adc_Read+0x68>)
|
|
8002892: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8002894: 210e movs r1, #14
|
|
8002896: 187b adds r3, r7, r1
|
|
8002898: 801a strh r2, [r3, #0]
|
|
return tmp;
|
|
800289a: 187b adds r3, r7, r1
|
|
800289c: 881b ldrh r3, [r3, #0]
|
|
}
|
|
800289e: 0018 movs r0, r3
|
|
80028a0: 46bd mov sp, r7
|
|
80028a2: b004 add sp, #16
|
|
80028a4: bd80 pop {r7, pc}
|
|
80028a6: 46c0 nop @ (mov r8, r8)
|
|
80028a8: 40012400 .word 0x40012400
|
|
|
|
080028ac <CAN_Send_Msg>:
|
|
}
|
|
CAN_TX_Rdy = 1;
|
|
}
|
|
|
|
// CAN send data
|
|
void CAN_Send_Msg(can_msg_typedef *msg) {
|
|
80028ac: b580 push {r7, lr}
|
|
80028ae: b082 sub sp, #8
|
|
80028b0: af00 add r7, sp, #0
|
|
80028b2: 6078 str r0, [r7, #4]
|
|
CAN_TX_Rdy = 0;
|
|
80028b4: 4b47 ldr r3, [pc, #284] @ (80029d4 <CAN_Send_Msg+0x128>)
|
|
80028b6: 2200 movs r2, #0
|
|
80028b8: 701a strb r2, [r3, #0]
|
|
CAN->sTxMailBox[0].TIR = (uint32_t) 0;
|
|
80028ba: 4a47 ldr r2, [pc, #284] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80028bc: 23c0 movs r3, #192 @ 0xc0
|
|
80028be: 005b lsls r3, r3, #1
|
|
80028c0: 2100 movs r1, #0
|
|
80028c2: 50d1 str r1, [r2, r3]
|
|
if (msg->format == STD_FORMAT) {
|
|
80028c4: 687b ldr r3, [r7, #4]
|
|
80028c6: 7b5b ldrb r3, [r3, #13]
|
|
80028c8: 2b00 cmp r3, #0
|
|
80028ca: d10c bne.n 80028e6 <CAN_Send_Msg+0x3a>
|
|
CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 21) | CAN_ID_STD;
|
|
80028cc: 4a42 ldr r2, [pc, #264] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80028ce: 23c0 movs r3, #192 @ 0xc0
|
|
80028d0: 005b lsls r3, r3, #1
|
|
80028d2: 58d2 ldr r2, [r2, r3]
|
|
80028d4: 687b ldr r3, [r7, #4]
|
|
80028d6: 681b ldr r3, [r3, #0]
|
|
80028d8: 055b lsls r3, r3, #21
|
|
80028da: 493f ldr r1, [pc, #252] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80028dc: 431a orrs r2, r3
|
|
80028de: 23c0 movs r3, #192 @ 0xc0
|
|
80028e0: 005b lsls r3, r3, #1
|
|
80028e2: 50ca str r2, [r1, r3]
|
|
80028e4: e00d b.n 8002902 <CAN_Send_Msg+0x56>
|
|
} else {
|
|
CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 3) | CAN_ID_EXT;
|
|
80028e6: 4a3c ldr r2, [pc, #240] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80028e8: 23c0 movs r3, #192 @ 0xc0
|
|
80028ea: 005b lsls r3, r3, #1
|
|
80028ec: 58d2 ldr r2, [r2, r3]
|
|
80028ee: 687b ldr r3, [r7, #4]
|
|
80028f0: 681b ldr r3, [r3, #0]
|
|
80028f2: 00db lsls r3, r3, #3
|
|
80028f4: 4313 orrs r3, r2
|
|
80028f6: 4938 ldr r1, [pc, #224] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80028f8: 2204 movs r2, #4
|
|
80028fa: 431a orrs r2, r3
|
|
80028fc: 23c0 movs r3, #192 @ 0xc0
|
|
80028fe: 005b lsls r3, r3, #1
|
|
8002900: 50ca str r2, [r1, r3]
|
|
}
|
|
if (msg->frame == DATA_FRAME) {
|
|
8002902: 687b ldr r3, [r7, #4]
|
|
8002904: 7b9b ldrb r3, [r3, #14]
|
|
8002906: 2b00 cmp r3, #0
|
|
8002908: d108 bne.n 800291c <CAN_Send_Msg+0x70>
|
|
CAN->sTxMailBox[0].TIR |= CAN_RTR_DATA;
|
|
800290a: 4a33 ldr r2, [pc, #204] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
800290c: 4932 ldr r1, [pc, #200] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
800290e: 23c0 movs r3, #192 @ 0xc0
|
|
8002910: 005b lsls r3, r3, #1
|
|
8002912: 58d2 ldr r2, [r2, r3]
|
|
8002914: 23c0 movs r3, #192 @ 0xc0
|
|
8002916: 005b lsls r3, r3, #1
|
|
8002918: 50ca str r2, [r1, r3]
|
|
800291a: e009 b.n 8002930 <CAN_Send_Msg+0x84>
|
|
} else {
|
|
CAN->sTxMailBox[0].TIR |= CAN_RTR_REMOTE;
|
|
800291c: 4a2e ldr r2, [pc, #184] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
800291e: 23c0 movs r3, #192 @ 0xc0
|
|
8002920: 005b lsls r3, r3, #1
|
|
8002922: 58d3 ldr r3, [r2, r3]
|
|
8002924: 492c ldr r1, [pc, #176] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
8002926: 2202 movs r2, #2
|
|
8002928: 431a orrs r2, r3
|
|
800292a: 23c0 movs r3, #192 @ 0xc0
|
|
800292c: 005b lsls r3, r3, #1
|
|
800292e: 50ca str r2, [r1, r3]
|
|
}
|
|
CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24)
|
|
8002930: 687b ldr r3, [r7, #4]
|
|
8002932: 79db ldrb r3, [r3, #7]
|
|
8002934: 061a lsls r2, r3, #24
|
|
| ((uint32_t) msg->data[2] << 16) | ((uint32_t) msg->data[1] << 8)
|
|
8002936: 687b ldr r3, [r7, #4]
|
|
8002938: 799b ldrb r3, [r3, #6]
|
|
800293a: 041b lsls r3, r3, #16
|
|
800293c: 431a orrs r2, r3
|
|
800293e: 687b ldr r3, [r7, #4]
|
|
8002940: 795b ldrb r3, [r3, #5]
|
|
8002942: 021b lsls r3, r3, #8
|
|
8002944: 4313 orrs r3, r2
|
|
| ((uint32_t) msg->data[0]));
|
|
8002946: 687a ldr r2, [r7, #4]
|
|
8002948: 7912 ldrb r2, [r2, #4]
|
|
CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24)
|
|
800294a: 4923 ldr r1, [pc, #140] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
| ((uint32_t) msg->data[0]));
|
|
800294c: 431a orrs r2, r3
|
|
CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24)
|
|
800294e: 23c4 movs r3, #196 @ 0xc4
|
|
8002950: 005b lsls r3, r3, #1
|
|
8002952: 50ca str r2, [r1, r3]
|
|
CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24)
|
|
8002954: 687b ldr r3, [r7, #4]
|
|
8002956: 7adb ldrb r3, [r3, #11]
|
|
8002958: 061a lsls r2, r3, #24
|
|
| ((uint32_t) msg->data[6] << 16) | ((uint32_t) msg->data[5] << 8)
|
|
800295a: 687b ldr r3, [r7, #4]
|
|
800295c: 7a9b ldrb r3, [r3, #10]
|
|
800295e: 041b lsls r3, r3, #16
|
|
8002960: 431a orrs r2, r3
|
|
8002962: 687b ldr r3, [r7, #4]
|
|
8002964: 7a5b ldrb r3, [r3, #9]
|
|
8002966: 021b lsls r3, r3, #8
|
|
8002968: 4313 orrs r3, r2
|
|
| ((uint32_t) msg->data[4]));
|
|
800296a: 687a ldr r2, [r7, #4]
|
|
800296c: 7a12 ldrb r2, [r2, #8]
|
|
CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24)
|
|
800296e: 491a ldr r1, [pc, #104] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
| ((uint32_t) msg->data[4]));
|
|
8002970: 431a orrs r2, r3
|
|
CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24)
|
|
8002972: 23c6 movs r3, #198 @ 0xc6
|
|
8002974: 005b lsls r3, r3, #1
|
|
8002976: 50ca str r2, [r1, r3]
|
|
CAN->sTxMailBox[0].TDTR &= ~CAN_TDT0R_DLC;
|
|
8002978: 4a17 ldr r2, [pc, #92] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
800297a: 23c2 movs r3, #194 @ 0xc2
|
|
800297c: 005b lsls r3, r3, #1
|
|
800297e: 58d3 ldr r3, [r2, r3]
|
|
8002980: 4915 ldr r1, [pc, #84] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
8002982: 220f movs r2, #15
|
|
8002984: 4393 bics r3, r2
|
|
8002986: 001a movs r2, r3
|
|
8002988: 23c2 movs r3, #194 @ 0xc2
|
|
800298a: 005b lsls r3, r3, #1
|
|
800298c: 50ca str r2, [r1, r3]
|
|
CAN->sTxMailBox[0].TDTR |= (msg->lenght & CAN_TDT0R_DLC);
|
|
800298e: 4a12 ldr r2, [pc, #72] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
8002990: 23c2 movs r3, #194 @ 0xc2
|
|
8002992: 005b lsls r3, r3, #1
|
|
8002994: 58d2 ldr r2, [r2, r3]
|
|
8002996: 687b ldr r3, [r7, #4]
|
|
8002998: 7b1b ldrb r3, [r3, #12]
|
|
800299a: 0019 movs r1, r3
|
|
800299c: 230f movs r3, #15
|
|
800299e: 400b ands r3, r1
|
|
80029a0: 490d ldr r1, [pc, #52] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80029a2: 431a orrs r2, r3
|
|
80029a4: 23c2 movs r3, #194 @ 0xc2
|
|
80029a6: 005b lsls r3, r3, #1
|
|
80029a8: 50ca str r2, [r1, r3]
|
|
CAN->IER |= CAN_IER_TMEIE;
|
|
80029aa: 4b0b ldr r3, [pc, #44] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80029ac: 695a ldr r2, [r3, #20]
|
|
80029ae: 4b0a ldr r3, [pc, #40] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80029b0: 2101 movs r1, #1
|
|
80029b2: 430a orrs r2, r1
|
|
80029b4: 615a str r2, [r3, #20]
|
|
CAN->sTxMailBox[0].TIR |= CAN_TI0R_TXRQ;
|
|
80029b6: 4a08 ldr r2, [pc, #32] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80029b8: 23c0 movs r3, #192 @ 0xc0
|
|
80029ba: 005b lsls r3, r3, #1
|
|
80029bc: 58d3 ldr r3, [r2, r3]
|
|
80029be: 4906 ldr r1, [pc, #24] @ (80029d8 <CAN_Send_Msg+0x12c>)
|
|
80029c0: 2201 movs r2, #1
|
|
80029c2: 431a orrs r2, r3
|
|
80029c4: 23c0 movs r3, #192 @ 0xc0
|
|
80029c6: 005b lsls r3, r3, #1
|
|
80029c8: 50ca str r2, [r1, r3]
|
|
}
|
|
80029ca: 46c0 nop @ (mov r8, r8)
|
|
80029cc: 46bd mov sp, r7
|
|
80029ce: b002 add sp, #8
|
|
80029d0: bd80 pop {r7, pc}
|
|
80029d2: 46c0 nop @ (mov r8, r8)
|
|
80029d4: 20000434 .word 0x20000434
|
|
80029d8: 40006400 .word 0x40006400
|
|
|
|
080029dc <CEC_CAN_IRQHandler>:
|
|
CAN->FA1R |= (uint32_t) (1 << CAN_Filter_Idx);
|
|
CAN->FMR &= ~CAN_FMR_FINIT;
|
|
CAN_Filter_Idx++;
|
|
}
|
|
//CAN recive/transmit irq handler
|
|
void CEC_CAN_IRQHandler(void) {
|
|
80029dc: b580 push {r7, lr}
|
|
80029de: af00 add r7, sp, #0
|
|
if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
|
|
80029e0: 4b15 ldr r3, [pc, #84] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
80029e2: 689a ldr r2, [r3, #8]
|
|
80029e4: 2380 movs r3, #128 @ 0x80
|
|
80029e6: 04db lsls r3, r3, #19
|
|
80029e8: 401a ands r2, r3
|
|
80029ea: 2380 movs r3, #128 @ 0x80
|
|
80029ec: 04db lsls r3, r3, #19
|
|
80029ee: 429a cmp r2, r3
|
|
80029f0: d10e bne.n 8002a10 <CEC_CAN_IRQHandler+0x34>
|
|
CAN->TSR |= CAN_TSR_RQCP0;
|
|
80029f2: 4b11 ldr r3, [pc, #68] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
80029f4: 689a ldr r2, [r3, #8]
|
|
80029f6: 4b10 ldr r3, [pc, #64] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
80029f8: 2101 movs r1, #1
|
|
80029fa: 430a orrs r2, r1
|
|
80029fc: 609a str r2, [r3, #8]
|
|
CAN->IER &= ~CAN_IER_TMEIE;
|
|
80029fe: 4b0e ldr r3, [pc, #56] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
8002a00: 695a ldr r2, [r3, #20]
|
|
8002a02: 4b0d ldr r3, [pc, #52] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
8002a04: 2101 movs r1, #1
|
|
8002a06: 438a bics r2, r1
|
|
8002a08: 615a str r2, [r3, #20]
|
|
CAN_TX_Rdy = 1;
|
|
8002a0a: 4b0c ldr r3, [pc, #48] @ (8002a3c <CEC_CAN_IRQHandler+0x60>)
|
|
8002a0c: 2201 movs r2, #1
|
|
8002a0e: 701a strb r2, [r3, #0]
|
|
}
|
|
if ((CAN->RF0R & CAN_RF0R_FMP0) != 0) {
|
|
8002a10: 4b09 ldr r3, [pc, #36] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
8002a12: 68db ldr r3, [r3, #12]
|
|
8002a14: 2203 movs r2, #3
|
|
8002a16: 4013 ands r3, r2
|
|
8002a18: d00a beq.n 8002a30 <CEC_CAN_IRQHandler+0x54>
|
|
CAN_Add_RX_Buffer();
|
|
8002a1a: f000 f90d bl 8002c38 <CAN_Add_RX_Buffer>
|
|
// TO DO
|
|
CAN->RF0R |= CAN_RF0R_RFOM0;
|
|
8002a1e: 4b06 ldr r3, [pc, #24] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
8002a20: 68da ldr r2, [r3, #12]
|
|
8002a22: 4b05 ldr r3, [pc, #20] @ (8002a38 <CEC_CAN_IRQHandler+0x5c>)
|
|
8002a24: 2120 movs r1, #32
|
|
8002a26: 430a orrs r2, r1
|
|
8002a28: 60da str r2, [r3, #12]
|
|
CAN_RX_Rdy = 1;
|
|
8002a2a: 4b05 ldr r3, [pc, #20] @ (8002a40 <CEC_CAN_IRQHandler+0x64>)
|
|
8002a2c: 2201 movs r2, #1
|
|
8002a2e: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
8002a30: 46c0 nop @ (mov r8, r8)
|
|
8002a32: 46bd mov sp, r7
|
|
8002a34: bd80 pop {r7, pc}
|
|
8002a36: 46c0 nop @ (mov r8, r8)
|
|
8002a38: 40006400 .word 0x40006400
|
|
8002a3c: 20000434 .word 0x20000434
|
|
8002a40: 20000435 .word 0x20000435
|
|
|
|
08002a44 <CAN_Send_TX_Buffer>:
|
|
void CAN_Send_TX_Buffer(void) {
|
|
8002a44: b580 push {r7, lr}
|
|
8002a46: af00 add r7, sp, #0
|
|
|
|
if (CAN_TX_Rdy) {
|
|
8002a48: 4b18 ldr r3, [pc, #96] @ (8002aac <CAN_Send_TX_Buffer+0x68>)
|
|
8002a4a: 781b ldrb r3, [r3, #0]
|
|
8002a4c: 2b00 cmp r3, #0
|
|
8002a4e: d02a beq.n 8002aa6 <CAN_Send_TX_Buffer+0x62>
|
|
//HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1);
|
|
if (CAN_TX_Buffer.todo > 0) {
|
|
8002a50: 4a17 ldr r2, [pc, #92] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a52: 2380 movs r3, #128 @ 0x80
|
|
8002a54: 005b lsls r3, r3, #1
|
|
8002a56: 5cd3 ldrb r3, [r2, r3]
|
|
8002a58: 2b00 cmp r3, #0
|
|
8002a5a: d024 beq.n 8002aa6 <CAN_Send_TX_Buffer+0x62>
|
|
CAN_TX_Buffer.todo--;
|
|
8002a5c: 4a14 ldr r2, [pc, #80] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a5e: 2380 movs r3, #128 @ 0x80
|
|
8002a60: 005b lsls r3, r3, #1
|
|
8002a62: 5cd3 ldrb r3, [r2, r3]
|
|
8002a64: 3b01 subs r3, #1
|
|
8002a66: b2d9 uxtb r1, r3
|
|
8002a68: 4a11 ldr r2, [pc, #68] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a6a: 2380 movs r3, #128 @ 0x80
|
|
8002a6c: 005b lsls r3, r3, #1
|
|
8002a6e: 54d1 strb r1, [r2, r3]
|
|
//HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1);
|
|
CAN_Send_Msg(&CAN_TX_Buffer.data[CAN_TX_Buffer.done]);
|
|
8002a70: 4a0f ldr r2, [pc, #60] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a72: 2381 movs r3, #129 @ 0x81
|
|
8002a74: 005b lsls r3, r3, #1
|
|
8002a76: 5cd3 ldrb r3, [r2, r3]
|
|
8002a78: 011a lsls r2, r3, #4
|
|
8002a7a: 4b0d ldr r3, [pc, #52] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a7c: 18d3 adds r3, r2, r3
|
|
8002a7e: 0018 movs r0, r3
|
|
8002a80: f7ff ff14 bl 80028ac <CAN_Send_Msg>
|
|
if ((CAN_TX_Buffer.done++) > 14) {
|
|
8002a84: 4a0a ldr r2, [pc, #40] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a86: 2381 movs r3, #129 @ 0x81
|
|
8002a88: 005b lsls r3, r3, #1
|
|
8002a8a: 5cd3 ldrb r3, [r2, r3]
|
|
8002a8c: 1c5a adds r2, r3, #1
|
|
8002a8e: b2d0 uxtb r0, r2
|
|
8002a90: 4907 ldr r1, [pc, #28] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a92: 2281 movs r2, #129 @ 0x81
|
|
8002a94: 0052 lsls r2, r2, #1
|
|
8002a96: 5488 strb r0, [r1, r2]
|
|
8002a98: 2b0e cmp r3, #14
|
|
8002a9a: d904 bls.n 8002aa6 <CAN_Send_TX_Buffer+0x62>
|
|
CAN_TX_Buffer.done = 0;
|
|
8002a9c: 4a04 ldr r2, [pc, #16] @ (8002ab0 <CAN_Send_TX_Buffer+0x6c>)
|
|
8002a9e: 2381 movs r3, #129 @ 0x81
|
|
8002aa0: 005b lsls r3, r3, #1
|
|
8002aa2: 2100 movs r1, #0
|
|
8002aa4: 54d1 strb r1, [r2, r3]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8002aa6: 46c0 nop @ (mov r8, r8)
|
|
8002aa8: 46bd mov sp, r7
|
|
8002aaa: bd80 pop {r7, pc}
|
|
8002aac: 20000434 .word 0x20000434
|
|
8002ab0: 20000438 .word 0x20000438
|
|
|
|
08002ab4 <CAN_Add_TX_Buffer>:
|
|
void CAN_Add_TX_Buffer(can_msg_typedef *data) {
|
|
8002ab4: b580 push {r7, lr}
|
|
8002ab6: b082 sub sp, #8
|
|
8002ab8: af00 add r7, sp, #0
|
|
8002aba: 6078 str r0, [r7, #4]
|
|
if ((CAN_TX_Buffer.todo++) < 15) {
|
|
8002abc: 4a5d ldr r2, [pc, #372] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002abe: 2380 movs r3, #128 @ 0x80
|
|
8002ac0: 005b lsls r3, r3, #1
|
|
8002ac2: 5cd3 ldrb r3, [r2, r3]
|
|
8002ac4: 1c5a adds r2, r3, #1
|
|
8002ac6: b2d0 uxtb r0, r2
|
|
8002ac8: 495a ldr r1, [pc, #360] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002aca: 2280 movs r2, #128 @ 0x80
|
|
8002acc: 0052 lsls r2, r2, #1
|
|
8002ace: 5488 strb r0, [r1, r2]
|
|
8002ad0: 2b0e cmp r3, #14
|
|
8002ad2: d900 bls.n 8002ad6 <CAN_Add_TX_Buffer+0x22>
|
|
8002ad4: e0a9 b.n 8002c2a <CAN_Add_TX_Buffer+0x176>
|
|
if ((CAN_TX_Buffer.corent++) > 14) {
|
|
8002ad6: 4a57 ldr r2, [pc, #348] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002ad8: 2302 movs r3, #2
|
|
8002ada: 33ff adds r3, #255 @ 0xff
|
|
8002adc: 5cd3 ldrb r3, [r2, r3]
|
|
8002ade: 1c5a adds r2, r3, #1
|
|
8002ae0: b2d0 uxtb r0, r2
|
|
8002ae2: 4954 ldr r1, [pc, #336] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002ae4: 2202 movs r2, #2
|
|
8002ae6: 32ff adds r2, #255 @ 0xff
|
|
8002ae8: 5488 strb r0, [r1, r2]
|
|
8002aea: 2b0e cmp r3, #14
|
|
8002aec: d904 bls.n 8002af8 <CAN_Add_TX_Buffer+0x44>
|
|
CAN_TX_Buffer.corent = 0;
|
|
8002aee: 4a51 ldr r2, [pc, #324] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002af0: 2302 movs r3, #2
|
|
8002af2: 33ff adds r3, #255 @ 0xff
|
|
8002af4: 2100 movs r1, #0
|
|
8002af6: 54d1 strb r1, [r2, r3]
|
|
}
|
|
//memcpy((void*) &canTX_buffer.data[canTX_buffer.corent], (void*) &data, sizeof(CAN_msg_typedef));
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].id = data->id;
|
|
8002af8: 4a4e ldr r2, [pc, #312] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002afa: 2302 movs r3, #2
|
|
8002afc: 33ff adds r3, #255 @ 0xff
|
|
8002afe: 5cd3 ldrb r3, [r2, r3]
|
|
8002b00: 001a movs r2, r3
|
|
8002b02: 687b ldr r3, [r7, #4]
|
|
8002b04: 6819 ldr r1, [r3, #0]
|
|
8002b06: 4b4b ldr r3, [pc, #300] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b08: 0112 lsls r2, r2, #4
|
|
8002b0a: 50d1 str r1, [r2, r3]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].format = data->format;
|
|
8002b0c: 4a49 ldr r2, [pc, #292] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b0e: 2302 movs r3, #2
|
|
8002b10: 33ff adds r3, #255 @ 0xff
|
|
8002b12: 5cd3 ldrb r3, [r2, r3]
|
|
8002b14: 0018 movs r0, r3
|
|
8002b16: 687b ldr r3, [r7, #4]
|
|
8002b18: 7b59 ldrb r1, [r3, #13]
|
|
8002b1a: 4a46 ldr r2, [pc, #280] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b1c: 0103 lsls r3, r0, #4
|
|
8002b1e: 18d3 adds r3, r2, r3
|
|
8002b20: 330d adds r3, #13
|
|
8002b22: 1c0a adds r2, r1, #0
|
|
8002b24: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].frame = data->frame;
|
|
8002b26: 4a43 ldr r2, [pc, #268] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b28: 2302 movs r3, #2
|
|
8002b2a: 33ff adds r3, #255 @ 0xff
|
|
8002b2c: 5cd3 ldrb r3, [r2, r3]
|
|
8002b2e: 0018 movs r0, r3
|
|
8002b30: 687b ldr r3, [r7, #4]
|
|
8002b32: 7b99 ldrb r1, [r3, #14]
|
|
8002b34: 4a3f ldr r2, [pc, #252] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b36: 0103 lsls r3, r0, #4
|
|
8002b38: 18d3 adds r3, r2, r3
|
|
8002b3a: 330e adds r3, #14
|
|
8002b3c: 1c0a adds r2, r1, #0
|
|
8002b3e: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].lenght = data->lenght;
|
|
8002b40: 4a3c ldr r2, [pc, #240] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b42: 2302 movs r3, #2
|
|
8002b44: 33ff adds r3, #255 @ 0xff
|
|
8002b46: 5cd3 ldrb r3, [r2, r3]
|
|
8002b48: 0018 movs r0, r3
|
|
8002b4a: 687b ldr r3, [r7, #4]
|
|
8002b4c: 7b19 ldrb r1, [r3, #12]
|
|
8002b4e: 4a39 ldr r2, [pc, #228] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b50: 0103 lsls r3, r0, #4
|
|
8002b52: 18d3 adds r3, r2, r3
|
|
8002b54: 330c adds r3, #12
|
|
8002b56: 1c0a adds r2, r1, #0
|
|
8002b58: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[0] = data->data[0];
|
|
8002b5a: 4a36 ldr r2, [pc, #216] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b5c: 2302 movs r3, #2
|
|
8002b5e: 33ff adds r3, #255 @ 0xff
|
|
8002b60: 5cd3 ldrb r3, [r2, r3]
|
|
8002b62: 0018 movs r0, r3
|
|
8002b64: 687b ldr r3, [r7, #4]
|
|
8002b66: 7919 ldrb r1, [r3, #4]
|
|
8002b68: 4a32 ldr r2, [pc, #200] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b6a: 0103 lsls r3, r0, #4
|
|
8002b6c: 18d3 adds r3, r2, r3
|
|
8002b6e: 3304 adds r3, #4
|
|
8002b70: 1c0a adds r2, r1, #0
|
|
8002b72: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[1] = data->data[1];
|
|
8002b74: 4a2f ldr r2, [pc, #188] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b76: 2302 movs r3, #2
|
|
8002b78: 33ff adds r3, #255 @ 0xff
|
|
8002b7a: 5cd3 ldrb r3, [r2, r3]
|
|
8002b7c: 0018 movs r0, r3
|
|
8002b7e: 687b ldr r3, [r7, #4]
|
|
8002b80: 7959 ldrb r1, [r3, #5]
|
|
8002b82: 4a2c ldr r2, [pc, #176] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b84: 0103 lsls r3, r0, #4
|
|
8002b86: 18d3 adds r3, r2, r3
|
|
8002b88: 3305 adds r3, #5
|
|
8002b8a: 1c0a adds r2, r1, #0
|
|
8002b8c: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[2] = data->data[2];
|
|
8002b8e: 4a29 ldr r2, [pc, #164] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b90: 2302 movs r3, #2
|
|
8002b92: 33ff adds r3, #255 @ 0xff
|
|
8002b94: 5cd3 ldrb r3, [r2, r3]
|
|
8002b96: 0018 movs r0, r3
|
|
8002b98: 687b ldr r3, [r7, #4]
|
|
8002b9a: 7999 ldrb r1, [r3, #6]
|
|
8002b9c: 4a25 ldr r2, [pc, #148] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002b9e: 0103 lsls r3, r0, #4
|
|
8002ba0: 18d3 adds r3, r2, r3
|
|
8002ba2: 3306 adds r3, #6
|
|
8002ba4: 1c0a adds r2, r1, #0
|
|
8002ba6: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[3] = data->data[3];
|
|
8002ba8: 4a22 ldr r2, [pc, #136] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002baa: 2302 movs r3, #2
|
|
8002bac: 33ff adds r3, #255 @ 0xff
|
|
8002bae: 5cd3 ldrb r3, [r2, r3]
|
|
8002bb0: 0018 movs r0, r3
|
|
8002bb2: 687b ldr r3, [r7, #4]
|
|
8002bb4: 79d9 ldrb r1, [r3, #7]
|
|
8002bb6: 4a1f ldr r2, [pc, #124] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bb8: 0103 lsls r3, r0, #4
|
|
8002bba: 18d3 adds r3, r2, r3
|
|
8002bbc: 3307 adds r3, #7
|
|
8002bbe: 1c0a adds r2, r1, #0
|
|
8002bc0: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[4] = data->data[4];
|
|
8002bc2: 4a1c ldr r2, [pc, #112] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bc4: 2302 movs r3, #2
|
|
8002bc6: 33ff adds r3, #255 @ 0xff
|
|
8002bc8: 5cd3 ldrb r3, [r2, r3]
|
|
8002bca: 0018 movs r0, r3
|
|
8002bcc: 687b ldr r3, [r7, #4]
|
|
8002bce: 7a19 ldrb r1, [r3, #8]
|
|
8002bd0: 4a18 ldr r2, [pc, #96] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bd2: 0103 lsls r3, r0, #4
|
|
8002bd4: 18d3 adds r3, r2, r3
|
|
8002bd6: 3308 adds r3, #8
|
|
8002bd8: 1c0a adds r2, r1, #0
|
|
8002bda: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[5] = data->data[5];
|
|
8002bdc: 4a15 ldr r2, [pc, #84] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bde: 2302 movs r3, #2
|
|
8002be0: 33ff adds r3, #255 @ 0xff
|
|
8002be2: 5cd3 ldrb r3, [r2, r3]
|
|
8002be4: 0018 movs r0, r3
|
|
8002be6: 687b ldr r3, [r7, #4]
|
|
8002be8: 7a59 ldrb r1, [r3, #9]
|
|
8002bea: 4a12 ldr r2, [pc, #72] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bec: 0103 lsls r3, r0, #4
|
|
8002bee: 18d3 adds r3, r2, r3
|
|
8002bf0: 3309 adds r3, #9
|
|
8002bf2: 1c0a adds r2, r1, #0
|
|
8002bf4: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[6] = data->data[6];
|
|
8002bf6: 4a0f ldr r2, [pc, #60] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002bf8: 2302 movs r3, #2
|
|
8002bfa: 33ff adds r3, #255 @ 0xff
|
|
8002bfc: 5cd3 ldrb r3, [r2, r3]
|
|
8002bfe: 0018 movs r0, r3
|
|
8002c00: 687b ldr r3, [r7, #4]
|
|
8002c02: 7a99 ldrb r1, [r3, #10]
|
|
8002c04: 4a0b ldr r2, [pc, #44] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002c06: 0103 lsls r3, r0, #4
|
|
8002c08: 18d3 adds r3, r2, r3
|
|
8002c0a: 330a adds r3, #10
|
|
8002c0c: 1c0a adds r2, r1, #0
|
|
8002c0e: 701a strb r2, [r3, #0]
|
|
CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[7] = data->data[7];
|
|
8002c10: 4a08 ldr r2, [pc, #32] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002c12: 2302 movs r3, #2
|
|
8002c14: 33ff adds r3, #255 @ 0xff
|
|
8002c16: 5cd3 ldrb r3, [r2, r3]
|
|
8002c18: 0018 movs r0, r3
|
|
8002c1a: 687b ldr r3, [r7, #4]
|
|
8002c1c: 7ad9 ldrb r1, [r3, #11]
|
|
8002c1e: 4a05 ldr r2, [pc, #20] @ (8002c34 <CAN_Add_TX_Buffer+0x180>)
|
|
8002c20: 0103 lsls r3, r0, #4
|
|
8002c22: 18d3 adds r3, r2, r3
|
|
8002c24: 330b adds r3, #11
|
|
8002c26: 1c0a adds r2, r1, #0
|
|
8002c28: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
8002c2a: 46c0 nop @ (mov r8, r8)
|
|
8002c2c: 46bd mov sp, r7
|
|
8002c2e: b002 add sp, #8
|
|
8002c30: bd80 pop {r7, pc}
|
|
8002c32: 46c0 nop @ (mov r8, r8)
|
|
8002c34: 20000438 .word 0x20000438
|
|
|
|
08002c38 <CAN_Add_RX_Buffer>:
|
|
void CAN_Add_RX_Buffer(void) {
|
|
8002c38: b580 push {r7, lr}
|
|
8002c3a: af00 add r7, sp, #0
|
|
if ((CAN_RX_Buffer.todo) < 16) {
|
|
8002c3c: 4a87 ldr r2, [pc, #540] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c3e: 2380 movs r3, #128 @ 0x80
|
|
8002c40: 005b lsls r3, r3, #1
|
|
8002c42: 5cd3 ldrb r3, [r2, r3]
|
|
8002c44: 2b0f cmp r3, #15
|
|
8002c46: d900 bls.n 8002c4a <CAN_Add_RX_Buffer+0x12>
|
|
8002c48: e0ff b.n 8002e4a <CAN_Add_RX_Buffer+0x212>
|
|
CAN_RX_Buffer.todo++;
|
|
8002c4a: 4a84 ldr r2, [pc, #528] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c4c: 2380 movs r3, #128 @ 0x80
|
|
8002c4e: 005b lsls r3, r3, #1
|
|
8002c50: 5cd3 ldrb r3, [r2, r3]
|
|
8002c52: 3301 adds r3, #1
|
|
8002c54: b2d9 uxtb r1, r3
|
|
8002c56: 4a81 ldr r2, [pc, #516] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c58: 2380 movs r3, #128 @ 0x80
|
|
8002c5a: 005b lsls r3, r3, #1
|
|
8002c5c: 54d1 strb r1, [r2, r3]
|
|
if ((CAN->sFIFOMailBox[0].RIR & CAN_ID_EXT) == 0) {
|
|
8002c5e: 4a80 ldr r2, [pc, #512] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002c60: 23d8 movs r3, #216 @ 0xd8
|
|
8002c62: 005b lsls r3, r3, #1
|
|
8002c64: 58d3 ldr r3, [r2, r3]
|
|
8002c66: 2204 movs r2, #4
|
|
8002c68: 4013 ands r3, r2
|
|
8002c6a: d118 bne.n 8002c9e <CAN_Add_RX_Buffer+0x66>
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = STD_FORMAT;
|
|
8002c6c: 4a7b ldr r2, [pc, #492] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c6e: 2302 movs r3, #2
|
|
8002c70: 33ff adds r3, #255 @ 0xff
|
|
8002c72: 5cd3 ldrb r3, [r2, r3]
|
|
8002c74: 4a79 ldr r2, [pc, #484] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c76: 011b lsls r3, r3, #4
|
|
8002c78: 18d3 adds r3, r2, r3
|
|
8002c7a: 330d adds r3, #13
|
|
8002c7c: 2200 movs r2, #0
|
|
8002c7e: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF
|
|
& (CAN->sFIFOMailBox[0].RIR >> 21);
|
|
8002c80: 4a77 ldr r2, [pc, #476] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002c82: 23d8 movs r3, #216 @ 0xd8
|
|
8002c84: 005b lsls r3, r3, #1
|
|
8002c86: 58d3 ldr r3, [r2, r3]
|
|
8002c88: 0d5b lsrs r3, r3, #21
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF
|
|
8002c8a: 4974 ldr r1, [pc, #464] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c8c: 2202 movs r2, #2
|
|
8002c8e: 32ff adds r2, #255 @ 0xff
|
|
8002c90: 5c8a ldrb r2, [r1, r2]
|
|
& (CAN->sFIFOMailBox[0].RIR >> 21);
|
|
8002c92: 055b lsls r3, r3, #21
|
|
8002c94: 0d59 lsrs r1, r3, #21
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF
|
|
8002c96: 4b71 ldr r3, [pc, #452] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002c98: 0112 lsls r2, r2, #4
|
|
8002c9a: 50d1 str r1, [r2, r3]
|
|
8002c9c: e017 b.n 8002cce <CAN_Add_RX_Buffer+0x96>
|
|
} else {
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = EXTD_FORMAT;
|
|
8002c9e: 4a6f ldr r2, [pc, #444] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002ca0: 2302 movs r3, #2
|
|
8002ca2: 33ff adds r3, #255 @ 0xff
|
|
8002ca4: 5cd3 ldrb r3, [r2, r3]
|
|
8002ca6: 4a6d ldr r2, [pc, #436] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002ca8: 011b lsls r3, r3, #4
|
|
8002caa: 18d3 adds r3, r2, r3
|
|
8002cac: 330d adds r3, #13
|
|
8002cae: 2201 movs r2, #1
|
|
8002cb0: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF
|
|
& (CAN->sFIFOMailBox[0].RIR >> 3);
|
|
8002cb2: 4a6b ldr r2, [pc, #428] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002cb4: 23d8 movs r3, #216 @ 0xd8
|
|
8002cb6: 005b lsls r3, r3, #1
|
|
8002cb8: 58d3 ldr r3, [r2, r3]
|
|
8002cba: 08db lsrs r3, r3, #3
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF
|
|
8002cbc: 4967 ldr r1, [pc, #412] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002cbe: 2202 movs r2, #2
|
|
8002cc0: 32ff adds r2, #255 @ 0xff
|
|
8002cc2: 5c8a ldrb r2, [r1, r2]
|
|
& (CAN->sFIFOMailBox[0].RIR >> 3);
|
|
8002cc4: 039b lsls r3, r3, #14
|
|
8002cc6: 0b99 lsrs r1, r3, #14
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF
|
|
8002cc8: 4b64 ldr r3, [pc, #400] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002cca: 0112 lsls r2, r2, #4
|
|
8002ccc: 50d1 str r1, [r2, r3]
|
|
}
|
|
if ((CAN->sFIFOMailBox[0].RIR & CAN_RTR_REMOTE) == 0) {
|
|
8002cce: 4a64 ldr r2, [pc, #400] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002cd0: 23d8 movs r3, #216 @ 0xd8
|
|
8002cd2: 005b lsls r3, r3, #1
|
|
8002cd4: 58d3 ldr r3, [r2, r3]
|
|
8002cd6: 2202 movs r2, #2
|
|
8002cd8: 4013 ands r3, r2
|
|
8002cda: d10a bne.n 8002cf2 <CAN_Add_RX_Buffer+0xba>
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = DATA_FRAME;
|
|
8002cdc: 4a5f ldr r2, [pc, #380] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002cde: 2302 movs r3, #2
|
|
8002ce0: 33ff adds r3, #255 @ 0xff
|
|
8002ce2: 5cd3 ldrb r3, [r2, r3]
|
|
8002ce4: 4a5d ldr r2, [pc, #372] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002ce6: 011b lsls r3, r3, #4
|
|
8002ce8: 18d3 adds r3, r2, r3
|
|
8002cea: 330e adds r3, #14
|
|
8002cec: 2200 movs r2, #0
|
|
8002cee: 701a strb r2, [r3, #0]
|
|
8002cf0: e009 b.n 8002d06 <CAN_Add_RX_Buffer+0xce>
|
|
} else {
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = REMOTE_FRAME;
|
|
8002cf2: 4a5a ldr r2, [pc, #360] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002cf4: 2302 movs r3, #2
|
|
8002cf6: 33ff adds r3, #255 @ 0xff
|
|
8002cf8: 5cd3 ldrb r3, [r2, r3]
|
|
8002cfa: 4a58 ldr r2, [pc, #352] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002cfc: 011b lsls r3, r3, #4
|
|
8002cfe: 18d3 adds r3, r2, r3
|
|
8002d00: 330e adds r3, #14
|
|
8002d02: 2201 movs r2, #1
|
|
8002d04: 701a strb r2, [r3, #0]
|
|
}
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F
|
|
& CAN->sFIFOMailBox[0].RDTR;
|
|
8002d06: 4a56 ldr r2, [pc, #344] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002d08: 23da movs r3, #218 @ 0xda
|
|
8002d0a: 005b lsls r3, r3, #1
|
|
8002d0c: 58d3 ldr r3, [r2, r3]
|
|
8002d0e: b2db uxtb r3, r3
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F
|
|
8002d10: 4952 ldr r1, [pc, #328] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d12: 2202 movs r2, #2
|
|
8002d14: 32ff adds r2, #255 @ 0xff
|
|
8002d16: 5c8a ldrb r2, [r1, r2]
|
|
8002d18: 0010 movs r0, r2
|
|
& CAN->sFIFOMailBox[0].RDTR;
|
|
8002d1a: 220f movs r2, #15
|
|
8002d1c: 4013 ands r3, r2
|
|
8002d1e: b2d9 uxtb r1, r3
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F
|
|
8002d20: 4a4e ldr r2, [pc, #312] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d22: 0103 lsls r3, r0, #4
|
|
8002d24: 18d3 adds r3, r2, r3
|
|
8002d26: 330c adds r3, #12
|
|
8002d28: 1c0a adds r2, r1, #0
|
|
8002d2a: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[0] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDLR);
|
|
8002d2c: 4a4c ldr r2, [pc, #304] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002d2e: 23dc movs r3, #220 @ 0xdc
|
|
8002d30: 005b lsls r3, r3, #1
|
|
8002d32: 58d1 ldr r1, [r2, r3]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[0] = (uint32_t) 0x000000FF
|
|
8002d34: 4a49 ldr r2, [pc, #292] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d36: 2302 movs r3, #2
|
|
8002d38: 33ff adds r3, #255 @ 0xff
|
|
8002d3a: 5cd3 ldrb r3, [r2, r3]
|
|
8002d3c: b2c9 uxtb r1, r1
|
|
8002d3e: 4a47 ldr r2, [pc, #284] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d40: 011b lsls r3, r3, #4
|
|
8002d42: 18d3 adds r3, r2, r3
|
|
8002d44: 3304 adds r3, #4
|
|
8002d46: 1c0a adds r2, r1, #0
|
|
8002d48: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[1] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDLR >> 8);
|
|
8002d4a: 4a45 ldr r2, [pc, #276] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002d4c: 23dc movs r3, #220 @ 0xdc
|
|
8002d4e: 005b lsls r3, r3, #1
|
|
8002d50: 58d3 ldr r3, [r2, r3]
|
|
8002d52: 0a19 lsrs r1, r3, #8
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[1] = (uint32_t) 0x000000FF
|
|
8002d54: 4a41 ldr r2, [pc, #260] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d56: 2302 movs r3, #2
|
|
8002d58: 33ff adds r3, #255 @ 0xff
|
|
8002d5a: 5cd3 ldrb r3, [r2, r3]
|
|
8002d5c: b2c9 uxtb r1, r1
|
|
8002d5e: 4a3f ldr r2, [pc, #252] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d60: 011b lsls r3, r3, #4
|
|
8002d62: 18d3 adds r3, r2, r3
|
|
8002d64: 3305 adds r3, #5
|
|
8002d66: 1c0a adds r2, r1, #0
|
|
8002d68: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[2] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDLR >> 16);
|
|
8002d6a: 4a3d ldr r2, [pc, #244] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002d6c: 23dc movs r3, #220 @ 0xdc
|
|
8002d6e: 005b lsls r3, r3, #1
|
|
8002d70: 58d3 ldr r3, [r2, r3]
|
|
8002d72: 0c19 lsrs r1, r3, #16
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[2] = (uint32_t) 0x000000FF
|
|
8002d74: 4a39 ldr r2, [pc, #228] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d76: 2302 movs r3, #2
|
|
8002d78: 33ff adds r3, #255 @ 0xff
|
|
8002d7a: 5cd3 ldrb r3, [r2, r3]
|
|
8002d7c: b2c9 uxtb r1, r1
|
|
8002d7e: 4a37 ldr r2, [pc, #220] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d80: 011b lsls r3, r3, #4
|
|
8002d82: 18d3 adds r3, r2, r3
|
|
8002d84: 3306 adds r3, #6
|
|
8002d86: 1c0a adds r2, r1, #0
|
|
8002d88: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[3] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDLR >> 24);
|
|
8002d8a: 4a35 ldr r2, [pc, #212] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002d8c: 23dc movs r3, #220 @ 0xdc
|
|
8002d8e: 005b lsls r3, r3, #1
|
|
8002d90: 58d3 ldr r3, [r2, r3]
|
|
8002d92: 0e19 lsrs r1, r3, #24
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[3] = (uint32_t) 0x000000FF
|
|
8002d94: 4a31 ldr r2, [pc, #196] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002d96: 2302 movs r3, #2
|
|
8002d98: 33ff adds r3, #255 @ 0xff
|
|
8002d9a: 5cd3 ldrb r3, [r2, r3]
|
|
8002d9c: b2c9 uxtb r1, r1
|
|
8002d9e: 4a2f ldr r2, [pc, #188] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002da0: 011b lsls r3, r3, #4
|
|
8002da2: 18d3 adds r3, r2, r3
|
|
8002da4: 3307 adds r3, #7
|
|
8002da6: 1c0a adds r2, r1, #0
|
|
8002da8: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[4] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDHR);
|
|
8002daa: 4a2d ldr r2, [pc, #180] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002dac: 23de movs r3, #222 @ 0xde
|
|
8002dae: 005b lsls r3, r3, #1
|
|
8002db0: 58d1 ldr r1, [r2, r3]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[4] = (uint32_t) 0x000000FF
|
|
8002db2: 4a2a ldr r2, [pc, #168] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002db4: 2302 movs r3, #2
|
|
8002db6: 33ff adds r3, #255 @ 0xff
|
|
8002db8: 5cd3 ldrb r3, [r2, r3]
|
|
8002dba: b2c9 uxtb r1, r1
|
|
8002dbc: 4a27 ldr r2, [pc, #156] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002dbe: 011b lsls r3, r3, #4
|
|
8002dc0: 18d3 adds r3, r2, r3
|
|
8002dc2: 3308 adds r3, #8
|
|
8002dc4: 1c0a adds r2, r1, #0
|
|
8002dc6: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[5] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDHR >> 8);
|
|
8002dc8: 4a25 ldr r2, [pc, #148] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002dca: 23de movs r3, #222 @ 0xde
|
|
8002dcc: 005b lsls r3, r3, #1
|
|
8002dce: 58d3 ldr r3, [r2, r3]
|
|
8002dd0: 0a19 lsrs r1, r3, #8
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[5] = (uint32_t) 0x000000FF
|
|
8002dd2: 4a22 ldr r2, [pc, #136] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002dd4: 2302 movs r3, #2
|
|
8002dd6: 33ff adds r3, #255 @ 0xff
|
|
8002dd8: 5cd3 ldrb r3, [r2, r3]
|
|
8002dda: b2c9 uxtb r1, r1
|
|
8002ddc: 4a1f ldr r2, [pc, #124] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002dde: 011b lsls r3, r3, #4
|
|
8002de0: 18d3 adds r3, r2, r3
|
|
8002de2: 3309 adds r3, #9
|
|
8002de4: 1c0a adds r2, r1, #0
|
|
8002de6: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[6] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDHR >> 16);
|
|
8002de8: 4a1d ldr r2, [pc, #116] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002dea: 23de movs r3, #222 @ 0xde
|
|
8002dec: 005b lsls r3, r3, #1
|
|
8002dee: 58d3 ldr r3, [r2, r3]
|
|
8002df0: 0c19 lsrs r1, r3, #16
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[6] = (uint32_t) 0x000000FF
|
|
8002df2: 4a1a ldr r2, [pc, #104] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002df4: 2302 movs r3, #2
|
|
8002df6: 33ff adds r3, #255 @ 0xff
|
|
8002df8: 5cd3 ldrb r3, [r2, r3]
|
|
8002dfa: b2c9 uxtb r1, r1
|
|
8002dfc: 4a17 ldr r2, [pc, #92] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002dfe: 011b lsls r3, r3, #4
|
|
8002e00: 18d3 adds r3, r2, r3
|
|
8002e02: 330a adds r3, #10
|
|
8002e04: 1c0a adds r2, r1, #0
|
|
8002e06: 701a strb r2, [r3, #0]
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[7] = (uint32_t) 0x000000FF
|
|
& (CAN->sFIFOMailBox[0].RDHR >> 24);
|
|
8002e08: 4a15 ldr r2, [pc, #84] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002e0a: 23de movs r3, #222 @ 0xde
|
|
8002e0c: 005b lsls r3, r3, #1
|
|
8002e0e: 58d3 ldr r3, [r2, r3]
|
|
8002e10: 0e19 lsrs r1, r3, #24
|
|
CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[7] = (uint32_t) 0x000000FF
|
|
8002e12: 4a12 ldr r2, [pc, #72] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002e14: 2302 movs r3, #2
|
|
8002e16: 33ff adds r3, #255 @ 0xff
|
|
8002e18: 5cd3 ldrb r3, [r2, r3]
|
|
8002e1a: b2c9 uxtb r1, r1
|
|
8002e1c: 4a0f ldr r2, [pc, #60] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002e1e: 011b lsls r3, r3, #4
|
|
8002e20: 18d3 adds r3, r2, r3
|
|
8002e22: 330b adds r3, #11
|
|
8002e24: 1c0a adds r2, r1, #0
|
|
8002e26: 701a strb r2, [r3, #0]
|
|
if ((CAN_RX_Buffer.corent++) > 15) {
|
|
8002e28: 4a0c ldr r2, [pc, #48] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002e2a: 2302 movs r3, #2
|
|
8002e2c: 33ff adds r3, #255 @ 0xff
|
|
8002e2e: 5cd3 ldrb r3, [r2, r3]
|
|
8002e30: 1c5a adds r2, r3, #1
|
|
8002e32: b2d0 uxtb r0, r2
|
|
8002e34: 4909 ldr r1, [pc, #36] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002e36: 2202 movs r2, #2
|
|
8002e38: 32ff adds r2, #255 @ 0xff
|
|
8002e3a: 5488 strb r0, [r1, r2]
|
|
8002e3c: 2b0f cmp r3, #15
|
|
8002e3e: d904 bls.n 8002e4a <CAN_Add_RX_Buffer+0x212>
|
|
CAN_RX_Buffer.corent = 0;
|
|
8002e40: 4a06 ldr r2, [pc, #24] @ (8002e5c <CAN_Add_RX_Buffer+0x224>)
|
|
8002e42: 2302 movs r3, #2
|
|
8002e44: 33ff adds r3, #255 @ 0xff
|
|
8002e46: 2100 movs r1, #0
|
|
8002e48: 54d1 strb r1, [r2, r3]
|
|
}
|
|
|
|
//canAddRXBuffer(&canRxMsg); //TO DO not realy working
|
|
}
|
|
CAN->RF0R |= CAN_RF0R_RFOM0;
|
|
8002e4a: 4b05 ldr r3, [pc, #20] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002e4c: 68da ldr r2, [r3, #12]
|
|
8002e4e: 4b04 ldr r3, [pc, #16] @ (8002e60 <CAN_Add_RX_Buffer+0x228>)
|
|
8002e50: 2120 movs r1, #32
|
|
8002e52: 430a orrs r2, r1
|
|
8002e54: 60da str r2, [r3, #12]
|
|
}
|
|
8002e56: 46c0 nop @ (mov r8, r8)
|
|
8002e58: 46bd mov sp, r7
|
|
8002e5a: bd80 pop {r7, pc}
|
|
8002e5c: 2000053c .word 0x2000053c
|
|
8002e60: 40006400 .word 0x40006400
|
|
|
|
08002e64 <CAN_Read_RX_Buffer>:
|
|
void CAN_Read_RX_Buffer(can_msg_typedef *data) {
|
|
8002e64: b580 push {r7, lr}
|
|
8002e66: b082 sub sp, #8
|
|
8002e68: af00 add r7, sp, #0
|
|
8002e6a: 6078 str r0, [r7, #4]
|
|
if (CAN_RX_Buffer.todo > 0) {
|
|
8002e6c: 4a54 ldr r2, [pc, #336] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002e6e: 2380 movs r3, #128 @ 0x80
|
|
8002e70: 005b lsls r3, r3, #1
|
|
8002e72: 5cd3 ldrb r3, [r2, r3]
|
|
8002e74: 2b00 cmp r3, #0
|
|
8002e76: d100 bne.n 8002e7a <CAN_Read_RX_Buffer+0x16>
|
|
8002e78: e09d b.n 8002fb6 <CAN_Read_RX_Buffer+0x152>
|
|
//memcpy((void*) &data, (void*) &canRX_buffer.data[canRX_buffer.done], sizeof(CAN_msg_typedef));
|
|
data->id = CAN_RX_Buffer.data[CAN_RX_Buffer.done].id;
|
|
8002e7a: 4a51 ldr r2, [pc, #324] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002e7c: 2381 movs r3, #129 @ 0x81
|
|
8002e7e: 005b lsls r3, r3, #1
|
|
8002e80: 5cd3 ldrb r3, [r2, r3]
|
|
8002e82: 001a movs r2, r3
|
|
8002e84: 4b4e ldr r3, [pc, #312] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002e86: 0112 lsls r2, r2, #4
|
|
8002e88: 58d2 ldr r2, [r2, r3]
|
|
8002e8a: 687b ldr r3, [r7, #4]
|
|
8002e8c: 601a str r2, [r3, #0]
|
|
data->format = CAN_RX_Buffer.data[CAN_RX_Buffer.done].format;
|
|
8002e8e: 4a4c ldr r2, [pc, #304] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002e90: 2381 movs r3, #129 @ 0x81
|
|
8002e92: 005b lsls r3, r3, #1
|
|
8002e94: 5cd3 ldrb r3, [r2, r3]
|
|
8002e96: 4a4a ldr r2, [pc, #296] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002e98: 011b lsls r3, r3, #4
|
|
8002e9a: 18d3 adds r3, r2, r3
|
|
8002e9c: 330d adds r3, #13
|
|
8002e9e: 781a ldrb r2, [r3, #0]
|
|
8002ea0: 687b ldr r3, [r7, #4]
|
|
8002ea2: 735a strb r2, [r3, #13]
|
|
data->frame = CAN_RX_Buffer.data[CAN_RX_Buffer.done].frame;
|
|
8002ea4: 4a46 ldr r2, [pc, #280] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ea6: 2381 movs r3, #129 @ 0x81
|
|
8002ea8: 005b lsls r3, r3, #1
|
|
8002eaa: 5cd3 ldrb r3, [r2, r3]
|
|
8002eac: 4a44 ldr r2, [pc, #272] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002eae: 011b lsls r3, r3, #4
|
|
8002eb0: 18d3 adds r3, r2, r3
|
|
8002eb2: 330e adds r3, #14
|
|
8002eb4: 781a ldrb r2, [r3, #0]
|
|
8002eb6: 687b ldr r3, [r7, #4]
|
|
8002eb8: 739a strb r2, [r3, #14]
|
|
data->lenght = CAN_RX_Buffer.data[CAN_RX_Buffer.done].lenght;
|
|
8002eba: 4a41 ldr r2, [pc, #260] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ebc: 2381 movs r3, #129 @ 0x81
|
|
8002ebe: 005b lsls r3, r3, #1
|
|
8002ec0: 5cd3 ldrb r3, [r2, r3]
|
|
8002ec2: 4a3f ldr r2, [pc, #252] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ec4: 011b lsls r3, r3, #4
|
|
8002ec6: 18d3 adds r3, r2, r3
|
|
8002ec8: 330c adds r3, #12
|
|
8002eca: 781a ldrb r2, [r3, #0]
|
|
8002ecc: 687b ldr r3, [r7, #4]
|
|
8002ece: 731a strb r2, [r3, #12]
|
|
data->data[0] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[0];
|
|
8002ed0: 4a3b ldr r2, [pc, #236] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ed2: 2381 movs r3, #129 @ 0x81
|
|
8002ed4: 005b lsls r3, r3, #1
|
|
8002ed6: 5cd3 ldrb r3, [r2, r3]
|
|
8002ed8: 4a39 ldr r2, [pc, #228] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002eda: 011b lsls r3, r3, #4
|
|
8002edc: 18d3 adds r3, r2, r3
|
|
8002ede: 3304 adds r3, #4
|
|
8002ee0: 781a ldrb r2, [r3, #0]
|
|
8002ee2: 687b ldr r3, [r7, #4]
|
|
8002ee4: 711a strb r2, [r3, #4]
|
|
data->data[1] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[1];
|
|
8002ee6: 4a36 ldr r2, [pc, #216] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ee8: 2381 movs r3, #129 @ 0x81
|
|
8002eea: 005b lsls r3, r3, #1
|
|
8002eec: 5cd3 ldrb r3, [r2, r3]
|
|
8002eee: 4a34 ldr r2, [pc, #208] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002ef0: 011b lsls r3, r3, #4
|
|
8002ef2: 18d3 adds r3, r2, r3
|
|
8002ef4: 3305 adds r3, #5
|
|
8002ef6: 781a ldrb r2, [r3, #0]
|
|
8002ef8: 687b ldr r3, [r7, #4]
|
|
8002efa: 715a strb r2, [r3, #5]
|
|
data->data[2] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[2];
|
|
8002efc: 4a30 ldr r2, [pc, #192] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002efe: 2381 movs r3, #129 @ 0x81
|
|
8002f00: 005b lsls r3, r3, #1
|
|
8002f02: 5cd3 ldrb r3, [r2, r3]
|
|
8002f04: 4a2e ldr r2, [pc, #184] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f06: 011b lsls r3, r3, #4
|
|
8002f08: 18d3 adds r3, r2, r3
|
|
8002f0a: 3306 adds r3, #6
|
|
8002f0c: 781a ldrb r2, [r3, #0]
|
|
8002f0e: 687b ldr r3, [r7, #4]
|
|
8002f10: 719a strb r2, [r3, #6]
|
|
data->data[3] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[3];
|
|
8002f12: 4a2b ldr r2, [pc, #172] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f14: 2381 movs r3, #129 @ 0x81
|
|
8002f16: 005b lsls r3, r3, #1
|
|
8002f18: 5cd3 ldrb r3, [r2, r3]
|
|
8002f1a: 4a29 ldr r2, [pc, #164] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f1c: 011b lsls r3, r3, #4
|
|
8002f1e: 18d3 adds r3, r2, r3
|
|
8002f20: 3307 adds r3, #7
|
|
8002f22: 781a ldrb r2, [r3, #0]
|
|
8002f24: 687b ldr r3, [r7, #4]
|
|
8002f26: 71da strb r2, [r3, #7]
|
|
data->data[4] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[4];
|
|
8002f28: 4a25 ldr r2, [pc, #148] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f2a: 2381 movs r3, #129 @ 0x81
|
|
8002f2c: 005b lsls r3, r3, #1
|
|
8002f2e: 5cd3 ldrb r3, [r2, r3]
|
|
8002f30: 4a23 ldr r2, [pc, #140] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f32: 011b lsls r3, r3, #4
|
|
8002f34: 18d3 adds r3, r2, r3
|
|
8002f36: 3308 adds r3, #8
|
|
8002f38: 781a ldrb r2, [r3, #0]
|
|
8002f3a: 687b ldr r3, [r7, #4]
|
|
8002f3c: 721a strb r2, [r3, #8]
|
|
data->data[5] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[5];
|
|
8002f3e: 4a20 ldr r2, [pc, #128] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f40: 2381 movs r3, #129 @ 0x81
|
|
8002f42: 005b lsls r3, r3, #1
|
|
8002f44: 5cd3 ldrb r3, [r2, r3]
|
|
8002f46: 4a1e ldr r2, [pc, #120] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f48: 011b lsls r3, r3, #4
|
|
8002f4a: 18d3 adds r3, r2, r3
|
|
8002f4c: 3309 adds r3, #9
|
|
8002f4e: 781a ldrb r2, [r3, #0]
|
|
8002f50: 687b ldr r3, [r7, #4]
|
|
8002f52: 725a strb r2, [r3, #9]
|
|
data->data[6] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[6];
|
|
8002f54: 4a1a ldr r2, [pc, #104] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f56: 2381 movs r3, #129 @ 0x81
|
|
8002f58: 005b lsls r3, r3, #1
|
|
8002f5a: 5cd3 ldrb r3, [r2, r3]
|
|
8002f5c: 4a18 ldr r2, [pc, #96] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f5e: 011b lsls r3, r3, #4
|
|
8002f60: 18d3 adds r3, r2, r3
|
|
8002f62: 330a adds r3, #10
|
|
8002f64: 781a ldrb r2, [r3, #0]
|
|
8002f66: 687b ldr r3, [r7, #4]
|
|
8002f68: 729a strb r2, [r3, #10]
|
|
data->data[7] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[7];
|
|
8002f6a: 4a15 ldr r2, [pc, #84] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f6c: 2381 movs r3, #129 @ 0x81
|
|
8002f6e: 005b lsls r3, r3, #1
|
|
8002f70: 5cd3 ldrb r3, [r2, r3]
|
|
8002f72: 4a13 ldr r2, [pc, #76] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f74: 011b lsls r3, r3, #4
|
|
8002f76: 18d3 adds r3, r2, r3
|
|
8002f78: 330b adds r3, #11
|
|
8002f7a: 781a ldrb r2, [r3, #0]
|
|
8002f7c: 687b ldr r3, [r7, #4]
|
|
8002f7e: 72da strb r2, [r3, #11]
|
|
if ((CAN_RX_Buffer.done++) > 15) {
|
|
8002f80: 4a0f ldr r2, [pc, #60] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f82: 2381 movs r3, #129 @ 0x81
|
|
8002f84: 005b lsls r3, r3, #1
|
|
8002f86: 5cd3 ldrb r3, [r2, r3]
|
|
8002f88: 1c5a adds r2, r3, #1
|
|
8002f8a: b2d0 uxtb r0, r2
|
|
8002f8c: 490c ldr r1, [pc, #48] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f8e: 2281 movs r2, #129 @ 0x81
|
|
8002f90: 0052 lsls r2, r2, #1
|
|
8002f92: 5488 strb r0, [r1, r2]
|
|
8002f94: 2b0f cmp r3, #15
|
|
8002f96: d904 bls.n 8002fa2 <CAN_Read_RX_Buffer+0x13e>
|
|
CAN_RX_Buffer.done = 0;
|
|
8002f98: 4a09 ldr r2, [pc, #36] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002f9a: 2381 movs r3, #129 @ 0x81
|
|
8002f9c: 005b lsls r3, r3, #1
|
|
8002f9e: 2100 movs r1, #0
|
|
8002fa0: 54d1 strb r1, [r2, r3]
|
|
}
|
|
CAN_RX_Buffer.todo--;
|
|
8002fa2: 4a07 ldr r2, [pc, #28] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002fa4: 2380 movs r3, #128 @ 0x80
|
|
8002fa6: 005b lsls r3, r3, #1
|
|
8002fa8: 5cd3 ldrb r3, [r2, r3]
|
|
8002faa: 3b01 subs r3, #1
|
|
8002fac: b2d9 uxtb r1, r3
|
|
8002fae: 4a04 ldr r2, [pc, #16] @ (8002fc0 <CAN_Read_RX_Buffer+0x15c>)
|
|
8002fb0: 2380 movs r3, #128 @ 0x80
|
|
8002fb2: 005b lsls r3, r3, #1
|
|
8002fb4: 54d1 strb r1, [r2, r3]
|
|
}
|
|
}
|
|
8002fb6: 46c0 nop @ (mov r8, r8)
|
|
8002fb8: 46bd mov sp, r7
|
|
8002fba: b002 add sp, #8
|
|
8002fbc: bd80 pop {r7, pc}
|
|
8002fbe: 46c0 nop @ (mov r8, r8)
|
|
8002fc0: 2000053c .word 0x2000053c
|
|
|
|
08002fc4 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8002fc4: b580 push {r7, lr}
|
|
8002fc6: b082 sub sp, #8
|
|
8002fc8: af00 add r7, sp, #0
|
|
8002fca: 0002 movs r2, r0
|
|
8002fcc: 1dfb adds r3, r7, #7
|
|
8002fce: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8002fd0: 1dfb adds r3, r7, #7
|
|
8002fd2: 781b ldrb r3, [r3, #0]
|
|
8002fd4: 2b7f cmp r3, #127 @ 0x7f
|
|
8002fd6: d809 bhi.n 8002fec <__NVIC_EnableIRQ+0x28>
|
|
{
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8002fd8: 1dfb adds r3, r7, #7
|
|
8002fda: 781b ldrb r3, [r3, #0]
|
|
8002fdc: 001a movs r2, r3
|
|
8002fde: 231f movs r3, #31
|
|
8002fe0: 401a ands r2, r3
|
|
8002fe2: 4b04 ldr r3, [pc, #16] @ (8002ff4 <__NVIC_EnableIRQ+0x30>)
|
|
8002fe4: 2101 movs r1, #1
|
|
8002fe6: 4091 lsls r1, r2
|
|
8002fe8: 000a movs r2, r1
|
|
8002fea: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
8002fec: 46c0 nop @ (mov r8, r8)
|
|
8002fee: 46bd mov sp, r7
|
|
8002ff0: b002 add sp, #8
|
|
8002ff2: bd80 pop {r7, pc}
|
|
8002ff4: e000e100 .word 0xe000e100
|
|
|
|
08002ff8 <__NVIC_DisableIRQ>:
|
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8002ff8: b580 push {r7, lr}
|
|
8002ffa: b082 sub sp, #8
|
|
8002ffc: af00 add r7, sp, #0
|
|
8002ffe: 0002 movs r2, r0
|
|
8003000: 1dfb adds r3, r7, #7
|
|
8003002: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8003004: 1dfb adds r3, r7, #7
|
|
8003006: 781b ldrb r3, [r3, #0]
|
|
8003008: 2b7f cmp r3, #127 @ 0x7f
|
|
800300a: d810 bhi.n 800302e <__NVIC_DisableIRQ+0x36>
|
|
{
|
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
800300c: 1dfb adds r3, r7, #7
|
|
800300e: 781b ldrb r3, [r3, #0]
|
|
8003010: 001a movs r2, r3
|
|
8003012: 231f movs r3, #31
|
|
8003014: 4013 ands r3, r2
|
|
8003016: 4908 ldr r1, [pc, #32] @ (8003038 <__NVIC_DisableIRQ+0x40>)
|
|
8003018: 2201 movs r2, #1
|
|
800301a: 409a lsls r2, r3
|
|
800301c: 0013 movs r3, r2
|
|
800301e: 2280 movs r2, #128 @ 0x80
|
|
8003020: 508b str r3, [r1, r2]
|
|
\details Acts as a special kind of Data Memory Barrier.
|
|
It completes when all explicit memory accesses before this instruction complete.
|
|
*/
|
|
__STATIC_FORCEINLINE void __DSB(void)
|
|
{
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
|
8003022: f3bf 8f4f dsb sy
|
|
}
|
|
8003026: 46c0 nop @ (mov r8, r8)
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|
8003028: f3bf 8f6f isb sy
|
|
}
|
|
800302c: 46c0 nop @ (mov r8, r8)
|
|
__DSB();
|
|
__ISB();
|
|
}
|
|
}
|
|
800302e: 46c0 nop @ (mov r8, r8)
|
|
8003030: 46bd mov sp, r7
|
|
8003032: b002 add sp, #8
|
|
8003034: bd80 pop {r7, pc}
|
|
8003036: 46c0 nop @ (mov r8, r8)
|
|
8003038: e000e100 .word 0xe000e100
|
|
|
|
0800303c <Apply_Sensor_Calibration>:
|
|
tps1_offset, tps2_gain, tps2_offset;
|
|
volatile uint16_t dbw_fast_process_timer, dbw_slow_process_timer;
|
|
volatile int32_t vbat_corr, tps_slow_t, p_comp, i_comp, d_comp, tps_error_t,
|
|
can_target, spring_preload, idle_adder;
|
|
|
|
void Apply_Sensor_Calibration(void) {
|
|
800303c: b5b0 push {r4, r5, r7, lr}
|
|
800303e: af00 add r7, sp, #0
|
|
pps1_gain = (1000.0F / (float) (config->pps1_max - config->pps1_min));
|
|
8003040: 4b79 ldr r3, [pc, #484] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003042: 681b ldr r3, [r3, #0]
|
|
8003044: 889b ldrh r3, [r3, #4]
|
|
8003046: b29b uxth r3, r3
|
|
8003048: 001a movs r2, r3
|
|
800304a: 4b77 ldr r3, [pc, #476] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
800304c: 681b ldr r3, [r3, #0]
|
|
800304e: 885b ldrh r3, [r3, #2]
|
|
8003050: b29b uxth r3, r3
|
|
8003052: 1ad3 subs r3, r2, r3
|
|
8003054: 0018 movs r0, r3
|
|
8003056: f7fe f9cd bl 80013f4 <__aeabi_i2f>
|
|
800305a: 1c03 adds r3, r0, #0
|
|
800305c: 1c19 adds r1, r3, #0
|
|
800305e: 4873 ldr r0, [pc, #460] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
8003060: f7fd fc46 bl 80008f0 <__aeabi_fdiv>
|
|
8003064: 1c03 adds r3, r0, #0
|
|
8003066: 1c1a adds r2, r3, #0
|
|
8003068: 4b71 ldr r3, [pc, #452] @ (8003230 <Apply_Sensor_Calibration+0x1f4>)
|
|
800306a: 601a str r2, [r3, #0]
|
|
pps1_offset = (config->pps1_min * 1000.0F
|
|
800306c: 4b6e ldr r3, [pc, #440] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
800306e: 681b ldr r3, [r3, #0]
|
|
8003070: 885b ldrh r3, [r3, #2]
|
|
8003072: b29b uxth r3, r3
|
|
8003074: 0018 movs r0, r3
|
|
8003076: f7fe f9bd bl 80013f4 <__aeabi_i2f>
|
|
800307a: 1c03 adds r3, r0, #0
|
|
800307c: 496b ldr r1, [pc, #428] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
800307e: 1c18 adds r0, r3, #0
|
|
8003080: f7fd fe04 bl 8000c8c <__aeabi_fmul>
|
|
8003084: 1c03 adds r3, r0, #0
|
|
8003086: 1c1c adds r4, r3, #0
|
|
/ (config->pps1_min - config->pps1_max));
|
|
8003088: 4b67 ldr r3, [pc, #412] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
800308a: 681b ldr r3, [r3, #0]
|
|
800308c: 885b ldrh r3, [r3, #2]
|
|
800308e: b29b uxth r3, r3
|
|
8003090: 001a movs r2, r3
|
|
8003092: 4b65 ldr r3, [pc, #404] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003094: 681b ldr r3, [r3, #0]
|
|
8003096: 889b ldrh r3, [r3, #4]
|
|
8003098: b29b uxth r3, r3
|
|
800309a: 1ad3 subs r3, r2, r3
|
|
800309c: 0018 movs r0, r3
|
|
800309e: f7fe f9a9 bl 80013f4 <__aeabi_i2f>
|
|
80030a2: 1c03 adds r3, r0, #0
|
|
80030a4: 1c19 adds r1, r3, #0
|
|
80030a6: 1c20 adds r0, r4, #0
|
|
80030a8: f7fd fc22 bl 80008f0 <__aeabi_fdiv>
|
|
80030ac: 1c03 adds r3, r0, #0
|
|
80030ae: 1c1a adds r2, r3, #0
|
|
pps1_offset = (config->pps1_min * 1000.0F
|
|
80030b0: 4b60 ldr r3, [pc, #384] @ (8003234 <Apply_Sensor_Calibration+0x1f8>)
|
|
80030b2: 601a str r2, [r3, #0]
|
|
|
|
pps2_gain = (1000.0F / (float) (config->pps2_max - config->pps2_min));
|
|
80030b4: 4b5c ldr r3, [pc, #368] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80030b6: 681b ldr r3, [r3, #0]
|
|
80030b8: 899b ldrh r3, [r3, #12]
|
|
80030ba: b29b uxth r3, r3
|
|
80030bc: 001a movs r2, r3
|
|
80030be: 4b5a ldr r3, [pc, #360] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80030c0: 681b ldr r3, [r3, #0]
|
|
80030c2: 88db ldrh r3, [r3, #6]
|
|
80030c4: b29b uxth r3, r3
|
|
80030c6: 1ad3 subs r3, r2, r3
|
|
80030c8: 0018 movs r0, r3
|
|
80030ca: f7fe f993 bl 80013f4 <__aeabi_i2f>
|
|
80030ce: 1c03 adds r3, r0, #0
|
|
80030d0: 1c19 adds r1, r3, #0
|
|
80030d2: 4856 ldr r0, [pc, #344] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
80030d4: f7fd fc0c bl 80008f0 <__aeabi_fdiv>
|
|
80030d8: 1c03 adds r3, r0, #0
|
|
80030da: 1c1a adds r2, r3, #0
|
|
80030dc: 4b56 ldr r3, [pc, #344] @ (8003238 <Apply_Sensor_Calibration+0x1fc>)
|
|
80030de: 601a str r2, [r3, #0]
|
|
pps2_offset = (config->pps2_min * 1000.0F
|
|
80030e0: 4b51 ldr r3, [pc, #324] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80030e2: 681b ldr r3, [r3, #0]
|
|
80030e4: 88db ldrh r3, [r3, #6]
|
|
80030e6: b29b uxth r3, r3
|
|
80030e8: 0018 movs r0, r3
|
|
80030ea: f7fe f983 bl 80013f4 <__aeabi_i2f>
|
|
80030ee: 1c03 adds r3, r0, #0
|
|
80030f0: 494e ldr r1, [pc, #312] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
80030f2: 1c18 adds r0, r3, #0
|
|
80030f4: f7fd fdca bl 8000c8c <__aeabi_fmul>
|
|
80030f8: 1c03 adds r3, r0, #0
|
|
80030fa: 1c1c adds r4, r3, #0
|
|
/ (config->pps2_min - config->pps2_max));
|
|
80030fc: 4b4a ldr r3, [pc, #296] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80030fe: 681b ldr r3, [r3, #0]
|
|
8003100: 88db ldrh r3, [r3, #6]
|
|
8003102: b29b uxth r3, r3
|
|
8003104: 001a movs r2, r3
|
|
8003106: 4b48 ldr r3, [pc, #288] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003108: 681b ldr r3, [r3, #0]
|
|
800310a: 899b ldrh r3, [r3, #12]
|
|
800310c: b29b uxth r3, r3
|
|
800310e: 1ad3 subs r3, r2, r3
|
|
8003110: 0018 movs r0, r3
|
|
8003112: f7fe f96f bl 80013f4 <__aeabi_i2f>
|
|
8003116: 1c03 adds r3, r0, #0
|
|
8003118: 1c19 adds r1, r3, #0
|
|
800311a: 1c20 adds r0, r4, #0
|
|
800311c: f7fd fbe8 bl 80008f0 <__aeabi_fdiv>
|
|
8003120: 1c03 adds r3, r0, #0
|
|
8003122: 1c1a adds r2, r3, #0
|
|
pps2_offset = (config->pps2_min * 1000.0F
|
|
8003124: 4b45 ldr r3, [pc, #276] @ (800323c <Apply_Sensor_Calibration+0x200>)
|
|
8003126: 601a str r2, [r3, #0]
|
|
|
|
tps1_gain = (1000.0F / (float) (config->tps1_max - config->tps1_min));
|
|
8003128: 4b3f ldr r3, [pc, #252] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
800312a: 681b ldr r3, [r3, #0]
|
|
800312c: 8a1b ldrh r3, [r3, #16]
|
|
800312e: b29b uxth r3, r3
|
|
8003130: 001a movs r2, r3
|
|
8003132: 4b3d ldr r3, [pc, #244] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003134: 681b ldr r3, [r3, #0]
|
|
8003136: 89db ldrh r3, [r3, #14]
|
|
8003138: b29b uxth r3, r3
|
|
800313a: 1ad3 subs r3, r2, r3
|
|
800313c: 0018 movs r0, r3
|
|
800313e: f7fe f959 bl 80013f4 <__aeabi_i2f>
|
|
8003142: 1c03 adds r3, r0, #0
|
|
8003144: 1c19 adds r1, r3, #0
|
|
8003146: 4839 ldr r0, [pc, #228] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
8003148: f7fd fbd2 bl 80008f0 <__aeabi_fdiv>
|
|
800314c: 1c03 adds r3, r0, #0
|
|
800314e: 1c1a adds r2, r3, #0
|
|
8003150: 4b3b ldr r3, [pc, #236] @ (8003240 <Apply_Sensor_Calibration+0x204>)
|
|
8003152: 601a str r2, [r3, #0]
|
|
tps1_offset = (short) (config->tps1_min * 1000.0F
|
|
8003154: 4b34 ldr r3, [pc, #208] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003156: 681b ldr r3, [r3, #0]
|
|
8003158: 89db ldrh r3, [r3, #14]
|
|
800315a: b29b uxth r3, r3
|
|
800315c: 0018 movs r0, r3
|
|
800315e: f7fe f949 bl 80013f4 <__aeabi_i2f>
|
|
8003162: 1c03 adds r3, r0, #0
|
|
8003164: 4931 ldr r1, [pc, #196] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
8003166: 1c18 adds r0, r3, #0
|
|
8003168: f7fd fd90 bl 8000c8c <__aeabi_fmul>
|
|
800316c: 1c03 adds r3, r0, #0
|
|
800316e: 1c1c adds r4, r3, #0
|
|
/ (config->tps1_min - config->tps1_max));
|
|
8003170: 4b2d ldr r3, [pc, #180] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003172: 681b ldr r3, [r3, #0]
|
|
8003174: 89db ldrh r3, [r3, #14]
|
|
8003176: b29b uxth r3, r3
|
|
8003178: 001a movs r2, r3
|
|
800317a: 4b2b ldr r3, [pc, #172] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
800317c: 681b ldr r3, [r3, #0]
|
|
800317e: 8a1b ldrh r3, [r3, #16]
|
|
8003180: b29b uxth r3, r3
|
|
8003182: 1ad3 subs r3, r2, r3
|
|
8003184: 0018 movs r0, r3
|
|
8003186: f7fe f935 bl 80013f4 <__aeabi_i2f>
|
|
800318a: 1c03 adds r3, r0, #0
|
|
800318c: 1c19 adds r1, r3, #0
|
|
800318e: 1c20 adds r0, r4, #0
|
|
8003190: f7fd fbae bl 80008f0 <__aeabi_fdiv>
|
|
8003194: 1c03 adds r3, r0, #0
|
|
tps1_offset = (short) (config->tps1_min * 1000.0F
|
|
8003196: 1c18 adds r0, r3, #0
|
|
8003198: f7fe f90c bl 80013b4 <__aeabi_f2iz>
|
|
800319c: 0003 movs r3, r0
|
|
800319e: b21b sxth r3, r3
|
|
80031a0: 0018 movs r0, r3
|
|
80031a2: f7fe f927 bl 80013f4 <__aeabi_i2f>
|
|
80031a6: 1c02 adds r2, r0, #0
|
|
80031a8: 4b26 ldr r3, [pc, #152] @ (8003244 <Apply_Sensor_Calibration+0x208>)
|
|
80031aa: 601a str r2, [r3, #0]
|
|
|
|
tps2_gain = (1000.0F / (float) (config->tps2_max - config->tps2_min));
|
|
80031ac: 4b1e ldr r3, [pc, #120] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80031ae: 681b ldr r3, [r3, #0]
|
|
80031b0: 8b1b ldrh r3, [r3, #24]
|
|
80031b2: b29b uxth r3, r3
|
|
80031b4: 001a movs r2, r3
|
|
80031b6: 4b1c ldr r3, [pc, #112] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80031b8: 681b ldr r3, [r3, #0]
|
|
80031ba: 8a5b ldrh r3, [r3, #18]
|
|
80031bc: b29b uxth r3, r3
|
|
80031be: 1ad3 subs r3, r2, r3
|
|
80031c0: 0018 movs r0, r3
|
|
80031c2: f7fe f917 bl 80013f4 <__aeabi_i2f>
|
|
80031c6: 1c03 adds r3, r0, #0
|
|
80031c8: 1c19 adds r1, r3, #0
|
|
80031ca: 4818 ldr r0, [pc, #96] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
80031cc: f7fd fb90 bl 80008f0 <__aeabi_fdiv>
|
|
80031d0: 1c03 adds r3, r0, #0
|
|
80031d2: 1c1a adds r2, r3, #0
|
|
80031d4: 4b1c ldr r3, [pc, #112] @ (8003248 <Apply_Sensor_Calibration+0x20c>)
|
|
80031d6: 601a str r2, [r3, #0]
|
|
tps2_offset = (config->tps2_min * 1000.0F
|
|
80031d8: 4b13 ldr r3, [pc, #76] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80031da: 681b ldr r3, [r3, #0]
|
|
80031dc: 8a5b ldrh r3, [r3, #18]
|
|
80031de: b29b uxth r3, r3
|
|
80031e0: 0018 movs r0, r3
|
|
80031e2: f7fe f907 bl 80013f4 <__aeabi_i2f>
|
|
80031e6: 1c03 adds r3, r0, #0
|
|
80031e8: 4910 ldr r1, [pc, #64] @ (800322c <Apply_Sensor_Calibration+0x1f0>)
|
|
80031ea: 1c18 adds r0, r3, #0
|
|
80031ec: f7fd fd4e bl 8000c8c <__aeabi_fmul>
|
|
80031f0: 1c03 adds r3, r0, #0
|
|
80031f2: 1c1c adds r4, r3, #0
|
|
/ (config->tps2_min - config->tps2_max));
|
|
80031f4: 4b0c ldr r3, [pc, #48] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
80031f6: 681b ldr r3, [r3, #0]
|
|
80031f8: 8a5b ldrh r3, [r3, #18]
|
|
80031fa: b29b uxth r3, r3
|
|
80031fc: 001a movs r2, r3
|
|
80031fe: 4b0a ldr r3, [pc, #40] @ (8003228 <Apply_Sensor_Calibration+0x1ec>)
|
|
8003200: 681b ldr r3, [r3, #0]
|
|
8003202: 8b1b ldrh r3, [r3, #24]
|
|
8003204: b29b uxth r3, r3
|
|
8003206: 1ad3 subs r3, r2, r3
|
|
8003208: 0018 movs r0, r3
|
|
800320a: f7fe f8f3 bl 80013f4 <__aeabi_i2f>
|
|
800320e: 1c03 adds r3, r0, #0
|
|
8003210: 1c19 adds r1, r3, #0
|
|
8003212: 1c20 adds r0, r4, #0
|
|
8003214: f7fd fb6c bl 80008f0 <__aeabi_fdiv>
|
|
8003218: 1c03 adds r3, r0, #0
|
|
800321a: 1c1a adds r2, r3, #0
|
|
tps2_offset = (config->tps2_min * 1000.0F
|
|
800321c: 4b0b ldr r3, [pc, #44] @ (800324c <Apply_Sensor_Calibration+0x210>)
|
|
800321e: 601a str r2, [r3, #0]
|
|
|
|
}
|
|
8003220: 46c0 nop @ (mov r8, r8)
|
|
8003222: 46bd mov sp, r7
|
|
8003224: bdb0 pop {r4, r5, r7, pc}
|
|
8003226: 46c0 nop @ (mov r8, r8)
|
|
8003228: 200009cc .word 0x200009cc
|
|
800322c: 447a0000 .word 0x447a0000
|
|
8003230: 200009fc .word 0x200009fc
|
|
8003234: 20000a00 .word 0x20000a00
|
|
8003238: 20000a04 .word 0x20000a04
|
|
800323c: 20000a08 .word 0x20000a08
|
|
8003240: 20000a0c .word 0x20000a0c
|
|
8003244: 20000a10 .word 0x20000a10
|
|
8003248: 20000a14 .word 0x20000a14
|
|
800324c: 20000a18 .word 0x20000a18
|
|
|
|
08003250 <DBW_Init>:
|
|
|
|
void DBW_Init(void) {
|
|
8003250: b580 push {r7, lr}
|
|
8003252: af00 add r7, sp, #0
|
|
dbw_fast_process_timer = 1;
|
|
8003254: 4b16 ldr r3, [pc, #88] @ (80032b0 <DBW_Init+0x60>)
|
|
8003256: 2201 movs r2, #1
|
|
8003258: 801a strh r2, [r3, #0]
|
|
dbw_slow_process_timer = config->motor_ctl_period;
|
|
800325a: 4b16 ldr r3, [pc, #88] @ (80032b4 <DBW_Init+0x64>)
|
|
800325c: 681b ldr r3, [r3, #0]
|
|
800325e: 227e movs r2, #126 @ 0x7e
|
|
8003260: 5a9b ldrh r3, [r3, r2]
|
|
8003262: b29a uxth r2, r3
|
|
8003264: 4b14 ldr r3, [pc, #80] @ (80032b8 <DBW_Init+0x68>)
|
|
8003266: 801a strh r2, [r3, #0]
|
|
vbat_corr = 0;
|
|
8003268: 4b14 ldr r3, [pc, #80] @ (80032bc <DBW_Init+0x6c>)
|
|
800326a: 2200 movs r2, #0
|
|
800326c: 601a str r2, [r3, #0]
|
|
tps_slow_t = var.tps;
|
|
800326e: 4b14 ldr r3, [pc, #80] @ (80032c0 <DBW_Init+0x70>)
|
|
8003270: 8c5b ldrh r3, [r3, #34] @ 0x22
|
|
8003272: b21b sxth r3, r3
|
|
8003274: 001a movs r2, r3
|
|
8003276: 4b13 ldr r3, [pc, #76] @ (80032c4 <DBW_Init+0x74>)
|
|
8003278: 601a str r2, [r3, #0]
|
|
p_comp = 0;
|
|
800327a: 4b13 ldr r3, [pc, #76] @ (80032c8 <DBW_Init+0x78>)
|
|
800327c: 2200 movs r2, #0
|
|
800327e: 601a str r2, [r3, #0]
|
|
i_comp = 0;
|
|
8003280: 4b12 ldr r3, [pc, #72] @ (80032cc <DBW_Init+0x7c>)
|
|
8003282: 2200 movs r2, #0
|
|
8003284: 601a str r2, [r3, #0]
|
|
d_comp = 0;
|
|
8003286: 4b12 ldr r3, [pc, #72] @ (80032d0 <DBW_Init+0x80>)
|
|
8003288: 2200 movs r2, #0
|
|
800328a: 601a str r2, [r3, #0]
|
|
tps_error_t = var.tps_error;
|
|
800328c: 4b0c ldr r3, [pc, #48] @ (80032c0 <DBW_Init+0x70>)
|
|
800328e: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8003290: b21b sxth r3, r3
|
|
8003292: 001a movs r2, r3
|
|
8003294: 4b0f ldr r3, [pc, #60] @ (80032d4 <DBW_Init+0x84>)
|
|
8003296: 601a str r2, [r3, #0]
|
|
can_target = 0;
|
|
8003298: 4b0f ldr r3, [pc, #60] @ (80032d8 <DBW_Init+0x88>)
|
|
800329a: 2200 movs r2, #0
|
|
800329c: 601a str r2, [r3, #0]
|
|
spring_preload = 0;
|
|
800329e: 4b0f ldr r3, [pc, #60] @ (80032dc <DBW_Init+0x8c>)
|
|
80032a0: 2200 movs r2, #0
|
|
80032a2: 601a str r2, [r3, #0]
|
|
idle_adder = 0;
|
|
80032a4: 4b0e ldr r3, [pc, #56] @ (80032e0 <DBW_Init+0x90>)
|
|
80032a6: 2200 movs r2, #0
|
|
80032a8: 601a str r2, [r3, #0]
|
|
}
|
|
80032aa: 46c0 nop @ (mov r8, r8)
|
|
80032ac: 46bd mov sp, r7
|
|
80032ae: bd80 pop {r7, pc}
|
|
80032b0: 20000a1c .word 0x20000a1c
|
|
80032b4: 200009cc .word 0x200009cc
|
|
80032b8: 20000a1e .word 0x20000a1e
|
|
80032bc: 20000a20 .word 0x20000a20
|
|
80032c0: 20000998 .word 0x20000998
|
|
80032c4: 20000a24 .word 0x20000a24
|
|
80032c8: 20000a28 .word 0x20000a28
|
|
80032cc: 20000a2c .word 0x20000a2c
|
|
80032d0: 20000a30 .word 0x20000a30
|
|
80032d4: 20000a34 .word 0x20000a34
|
|
80032d8: 20000a38 .word 0x20000a38
|
|
80032dc: 20000a3c .word 0x20000a3c
|
|
80032e0: 20000a40 .word 0x20000a40
|
|
|
|
080032e4 <DBW_Process>:
|
|
|
|
int DBW_Process(void) {
|
|
80032e4: b590 push {r4, r7, lr}
|
|
80032e6: b085 sub sp, #20
|
|
80032e8: af02 add r7, sp, #8
|
|
|
|
int32_t pwm_output = 0;
|
|
80032ea: 2300 movs r3, #0
|
|
80032ec: 607b str r3, [r7, #4]
|
|
int32_t pct = 0;
|
|
80032ee: 2300 movs r3, #0
|
|
80032f0: 603b str r3, [r7, #0]
|
|
if (dbw_fast_process_timer == 0) {
|
|
80032f2: 4ba6 ldr r3, [pc, #664] @ (800358c <DBW_Process+0x2a8>)
|
|
80032f4: 881b ldrh r3, [r3, #0]
|
|
80032f6: b29b uxth r3, r3
|
|
80032f8: 2b00 cmp r3, #0
|
|
80032fa: d000 beq.n 80032fe <DBW_Process+0x1a>
|
|
80032fc: e2f4 b.n 80038e8 <DBW_Process+0x604>
|
|
//process DBW every 1 mS
|
|
dbw_fast_process_timer = 1;
|
|
80032fe: 4ba3 ldr r3, [pc, #652] @ (800358c <DBW_Process+0x2a8>)
|
|
8003300: 2201 movs r2, #1
|
|
8003302: 801a strh r2, [r3, #0]
|
|
|
|
// Read all sensors and calculate error
|
|
// calculate PPS sensor reading
|
|
var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc);
|
|
8003304: 2000 movs r0, #0
|
|
8003306: f7ff fa9b bl 8002840 <Adc_Read>
|
|
800330a: 0003 movs r3, r0
|
|
800330c: 0019 movs r1, r3
|
|
800330e: 4ba0 ldr r3, [pc, #640] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003310: 899b ldrh r3, [r3, #12]
|
|
8003312: b29a uxth r2, r3
|
|
8003314: 23af movs r3, #175 @ 0xaf
|
|
8003316: 009b lsls r3, r3, #2
|
|
8003318: 0018 movs r0, r3
|
|
800331a: f7ff fa43 bl 80027a4 <LPF>
|
|
800331e: 0003 movs r3, r0
|
|
8003320: 001a movs r2, r3
|
|
8003322: 4b9b ldr r3, [pc, #620] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003324: 819a strh r2, [r3, #12]
|
|
var.pps1 = var.pps1_adc * pps1_gain + pps1_offset;
|
|
8003326: 4b9a ldr r3, [pc, #616] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003328: 899b ldrh r3, [r3, #12]
|
|
800332a: b29b uxth r3, r3
|
|
800332c: 0018 movs r0, r3
|
|
800332e: f7fe f861 bl 80013f4 <__aeabi_i2f>
|
|
8003332: 1c02 adds r2, r0, #0
|
|
8003334: 4b97 ldr r3, [pc, #604] @ (8003594 <DBW_Process+0x2b0>)
|
|
8003336: 681b ldr r3, [r3, #0]
|
|
8003338: 1c19 adds r1, r3, #0
|
|
800333a: 1c10 adds r0, r2, #0
|
|
800333c: f7fd fca6 bl 8000c8c <__aeabi_fmul>
|
|
8003340: 1c03 adds r3, r0, #0
|
|
8003342: 1c1a adds r2, r3, #0
|
|
8003344: 4b94 ldr r3, [pc, #592] @ (8003598 <DBW_Process+0x2b4>)
|
|
8003346: 681b ldr r3, [r3, #0]
|
|
8003348: 1c19 adds r1, r3, #0
|
|
800334a: 1c10 adds r0, r2, #0
|
|
800334c: f7fd f8c2 bl 80004d4 <__aeabi_fadd>
|
|
8003350: 1c03 adds r3, r0, #0
|
|
8003352: 1c18 adds r0, r3, #0
|
|
8003354: f7fe f82e bl 80013b4 <__aeabi_f2iz>
|
|
8003358: 0003 movs r3, r0
|
|
800335a: b21a sxth r2, r3
|
|
800335c: 4b8c ldr r3, [pc, #560] @ (8003590 <DBW_Process+0x2ac>)
|
|
800335e: 831a strh r2, [r3, #24]
|
|
|
|
var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); //orig 1
|
|
8003360: 2003 movs r0, #3
|
|
8003362: f7ff fa6d bl 8002840 <Adc_Read>
|
|
8003366: 0003 movs r3, r0
|
|
8003368: 0019 movs r1, r3
|
|
800336a: 4b89 ldr r3, [pc, #548] @ (8003590 <DBW_Process+0x2ac>)
|
|
800336c: 89db ldrh r3, [r3, #14]
|
|
800336e: b29a uxth r2, r3
|
|
8003370: 23af movs r3, #175 @ 0xaf
|
|
8003372: 009b lsls r3, r3, #2
|
|
8003374: 0018 movs r0, r3
|
|
8003376: f7ff fa15 bl 80027a4 <LPF>
|
|
800337a: 0003 movs r3, r0
|
|
800337c: 001a movs r2, r3
|
|
800337e: 4b84 ldr r3, [pc, #528] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003380: 81da strh r2, [r3, #14]
|
|
var.pps2 = var.pps2_adc * pps2_gain + pps2_offset;
|
|
8003382: 4b83 ldr r3, [pc, #524] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003384: 89db ldrh r3, [r3, #14]
|
|
8003386: b29b uxth r3, r3
|
|
8003388: 0018 movs r0, r3
|
|
800338a: f7fe f833 bl 80013f4 <__aeabi_i2f>
|
|
800338e: 1c02 adds r2, r0, #0
|
|
8003390: 4b82 ldr r3, [pc, #520] @ (800359c <DBW_Process+0x2b8>)
|
|
8003392: 681b ldr r3, [r3, #0]
|
|
8003394: 1c19 adds r1, r3, #0
|
|
8003396: 1c10 adds r0, r2, #0
|
|
8003398: f7fd fc78 bl 8000c8c <__aeabi_fmul>
|
|
800339c: 1c03 adds r3, r0, #0
|
|
800339e: 1c1a adds r2, r3, #0
|
|
80033a0: 4b7f ldr r3, [pc, #508] @ (80035a0 <DBW_Process+0x2bc>)
|
|
80033a2: 681b ldr r3, [r3, #0]
|
|
80033a4: 1c19 adds r1, r3, #0
|
|
80033a6: 1c10 adds r0, r2, #0
|
|
80033a8: f7fd f894 bl 80004d4 <__aeabi_fadd>
|
|
80033ac: 1c03 adds r3, r0, #0
|
|
80033ae: 1c18 adds r0, r3, #0
|
|
80033b0: f7fe f800 bl 80013b4 <__aeabi_f2iz>
|
|
80033b4: 0003 movs r3, r0
|
|
80033b6: b21a sxth r2, r3
|
|
80033b8: 4b75 ldr r3, [pc, #468] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033ba: 835a strh r2, [r3, #26]
|
|
|
|
var.pps_delta = var.pps1 - var.pps2;
|
|
80033bc: 4b74 ldr r3, [pc, #464] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033be: 8b1b ldrh r3, [r3, #24]
|
|
80033c0: b21b sxth r3, r3
|
|
80033c2: b29a uxth r2, r3
|
|
80033c4: 4b72 ldr r3, [pc, #456] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033c6: 8b5b ldrh r3, [r3, #26]
|
|
80033c8: b21b sxth r3, r3
|
|
80033ca: b29b uxth r3, r3
|
|
80033cc: 1ad3 subs r3, r2, r3
|
|
80033ce: b29b uxth r3, r3
|
|
80033d0: b21a sxth r2, r3
|
|
80033d2: 4b6f ldr r3, [pc, #444] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033d4: 855a strh r2, [r3, #42] @ 0x2a
|
|
var.pps = (var.pps1 + var.pps2) >> 1;
|
|
80033d6: 4b6e ldr r3, [pc, #440] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033d8: 8b1b ldrh r3, [r3, #24]
|
|
80033da: b21b sxth r3, r3
|
|
80033dc: 001a movs r2, r3
|
|
80033de: 4b6c ldr r3, [pc, #432] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033e0: 8b5b ldrh r3, [r3, #26]
|
|
80033e2: b21b sxth r3, r3
|
|
80033e4: 18d3 adds r3, r2, r3
|
|
80033e6: 105b asrs r3, r3, #1
|
|
80033e8: b21a sxth r2, r3
|
|
80033ea: 4b69 ldr r3, [pc, #420] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033ec: 841a strh r2, [r3, #32]
|
|
|
|
//Calculate TPS sensor reading
|
|
var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc);
|
|
80033ee: 2002 movs r0, #2
|
|
80033f0: f7ff fa26 bl 8002840 <Adc_Read>
|
|
80033f4: 0003 movs r3, r0
|
|
80033f6: 0019 movs r1, r3
|
|
80033f8: 4b65 ldr r3, [pc, #404] @ (8003590 <DBW_Process+0x2ac>)
|
|
80033fa: 8a1b ldrh r3, [r3, #16]
|
|
80033fc: b29a uxth r2, r3
|
|
80033fe: 23af movs r3, #175 @ 0xaf
|
|
8003400: 009b lsls r3, r3, #2
|
|
8003402: 0018 movs r0, r3
|
|
8003404: f7ff f9ce bl 80027a4 <LPF>
|
|
8003408: 0003 movs r3, r0
|
|
800340a: 001a movs r2, r3
|
|
800340c: 4b60 ldr r3, [pc, #384] @ (8003590 <DBW_Process+0x2ac>)
|
|
800340e: 821a strh r2, [r3, #16]
|
|
var.tps1 = var.tps1_adc * tps1_gain + tps1_offset;
|
|
8003410: 4b5f ldr r3, [pc, #380] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003412: 8a1b ldrh r3, [r3, #16]
|
|
8003414: b29b uxth r3, r3
|
|
8003416: 0018 movs r0, r3
|
|
8003418: f7fd ffec bl 80013f4 <__aeabi_i2f>
|
|
800341c: 1c02 adds r2, r0, #0
|
|
800341e: 4b61 ldr r3, [pc, #388] @ (80035a4 <DBW_Process+0x2c0>)
|
|
8003420: 681b ldr r3, [r3, #0]
|
|
8003422: 1c19 adds r1, r3, #0
|
|
8003424: 1c10 adds r0, r2, #0
|
|
8003426: f7fd fc31 bl 8000c8c <__aeabi_fmul>
|
|
800342a: 1c03 adds r3, r0, #0
|
|
800342c: 1c1a adds r2, r3, #0
|
|
800342e: 4b5e ldr r3, [pc, #376] @ (80035a8 <DBW_Process+0x2c4>)
|
|
8003430: 681b ldr r3, [r3, #0]
|
|
8003432: 1c19 adds r1, r3, #0
|
|
8003434: 1c10 adds r0, r2, #0
|
|
8003436: f7fd f84d bl 80004d4 <__aeabi_fadd>
|
|
800343a: 1c03 adds r3, r0, #0
|
|
800343c: 1c18 adds r0, r3, #0
|
|
800343e: f7fd ffb9 bl 80013b4 <__aeabi_f2iz>
|
|
8003442: 0003 movs r3, r0
|
|
8003444: b21a sxth r2, r3
|
|
8003446: 4b52 ldr r3, [pc, #328] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003448: 839a strh r2, [r3, #28]
|
|
|
|
var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //orig 3
|
|
800344a: 2001 movs r0, #1
|
|
800344c: f7ff f9f8 bl 8002840 <Adc_Read>
|
|
8003450: 0003 movs r3, r0
|
|
8003452: 0019 movs r1, r3
|
|
8003454: 4b4e ldr r3, [pc, #312] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003456: 8a5b ldrh r3, [r3, #18]
|
|
8003458: b29a uxth r2, r3
|
|
800345a: 23af movs r3, #175 @ 0xaf
|
|
800345c: 009b lsls r3, r3, #2
|
|
800345e: 0018 movs r0, r3
|
|
8003460: f7ff f9a0 bl 80027a4 <LPF>
|
|
8003464: 0003 movs r3, r0
|
|
8003466: 001a movs r2, r3
|
|
8003468: 4b49 ldr r3, [pc, #292] @ (8003590 <DBW_Process+0x2ac>)
|
|
800346a: 825a strh r2, [r3, #18]
|
|
var.tps2 = var.tps2_adc * tps2_gain + tps2_offset;
|
|
800346c: 4b48 ldr r3, [pc, #288] @ (8003590 <DBW_Process+0x2ac>)
|
|
800346e: 8a5b ldrh r3, [r3, #18]
|
|
8003470: b29b uxth r3, r3
|
|
8003472: 0018 movs r0, r3
|
|
8003474: f7fd ffbe bl 80013f4 <__aeabi_i2f>
|
|
8003478: 1c02 adds r2, r0, #0
|
|
800347a: 4b4c ldr r3, [pc, #304] @ (80035ac <DBW_Process+0x2c8>)
|
|
800347c: 681b ldr r3, [r3, #0]
|
|
800347e: 1c19 adds r1, r3, #0
|
|
8003480: 1c10 adds r0, r2, #0
|
|
8003482: f7fd fc03 bl 8000c8c <__aeabi_fmul>
|
|
8003486: 1c03 adds r3, r0, #0
|
|
8003488: 1c1a adds r2, r3, #0
|
|
800348a: 4b49 ldr r3, [pc, #292] @ (80035b0 <DBW_Process+0x2cc>)
|
|
800348c: 681b ldr r3, [r3, #0]
|
|
800348e: 1c19 adds r1, r3, #0
|
|
8003490: 1c10 adds r0, r2, #0
|
|
8003492: f7fd f81f bl 80004d4 <__aeabi_fadd>
|
|
8003496: 1c03 adds r3, r0, #0
|
|
8003498: 1c18 adds r0, r3, #0
|
|
800349a: f7fd ff8b bl 80013b4 <__aeabi_f2iz>
|
|
800349e: 0003 movs r3, r0
|
|
80034a0: b21a sxth r2, r3
|
|
80034a2: 4b3b ldr r3, [pc, #236] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034a4: 83da strh r2, [r3, #30]
|
|
|
|
// calculate tps and pps delta and values
|
|
var.tps_delta = var.tps1 - var.tps2;
|
|
80034a6: 4b3a ldr r3, [pc, #232] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034a8: 8b9b ldrh r3, [r3, #28]
|
|
80034aa: b21b sxth r3, r3
|
|
80034ac: b29a uxth r2, r3
|
|
80034ae: 4b38 ldr r3, [pc, #224] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034b0: 8bdb ldrh r3, [r3, #30]
|
|
80034b2: b21b sxth r3, r3
|
|
80034b4: b29b uxth r3, r3
|
|
80034b6: 1ad3 subs r3, r2, r3
|
|
80034b8: b29b uxth r3, r3
|
|
80034ba: b21a sxth r2, r3
|
|
80034bc: 4b34 ldr r3, [pc, #208] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034be: 859a strh r2, [r3, #44] @ 0x2c
|
|
var.tps = (var.tps1 + var.tps2) >> 1;
|
|
80034c0: 4b33 ldr r3, [pc, #204] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034c2: 8b9b ldrh r3, [r3, #28]
|
|
80034c4: b21b sxth r3, r3
|
|
80034c6: 001a movs r2, r3
|
|
80034c8: 4b31 ldr r3, [pc, #196] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034ca: 8bdb ldrh r3, [r3, #30]
|
|
80034cc: b21b sxth r3, r3
|
|
80034ce: 18d3 adds r3, r2, r3
|
|
80034d0: 105b asrs r3, r3, #1
|
|
80034d2: b21a sxth r2, r3
|
|
80034d4: 4b2e ldr r3, [pc, #184] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034d6: 845a strh r2, [r3, #34] @ 0x22
|
|
|
|
var.pps_delta = var.pps1 - var.pps2;
|
|
80034d8: 4b2d ldr r3, [pc, #180] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034da: 8b1b ldrh r3, [r3, #24]
|
|
80034dc: b21b sxth r3, r3
|
|
80034de: b29a uxth r2, r3
|
|
80034e0: 4b2b ldr r3, [pc, #172] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034e2: 8b5b ldrh r3, [r3, #26]
|
|
80034e4: b21b sxth r3, r3
|
|
80034e6: b29b uxth r3, r3
|
|
80034e8: 1ad3 subs r3, r2, r3
|
|
80034ea: b29b uxth r3, r3
|
|
80034ec: b21a sxth r2, r3
|
|
80034ee: 4b28 ldr r3, [pc, #160] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034f0: 855a strh r2, [r3, #42] @ 0x2a
|
|
var.pps = (var.pps1 + var.pps2) >> 1;
|
|
80034f2: 4b27 ldr r3, [pc, #156] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034f4: 8b1b ldrh r3, [r3, #24]
|
|
80034f6: b21b sxth r3, r3
|
|
80034f8: 001a movs r2, r3
|
|
80034fa: 4b25 ldr r3, [pc, #148] @ (8003590 <DBW_Process+0x2ac>)
|
|
80034fc: 8b5b ldrh r3, [r3, #26]
|
|
80034fe: b21b sxth r3, r3
|
|
8003500: 18d3 adds r3, r2, r3
|
|
8003502: 105b asrs r3, r3, #1
|
|
8003504: b21a sxth r2, r3
|
|
8003506: 4b22 ldr r3, [pc, #136] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003508: 841a strh r2, [r3, #32]
|
|
|
|
// set tps target
|
|
if (config->pps2tps_option == PPS2TPS_OPTION_CURVE) {
|
|
800350a: 4b2a ldr r3, [pc, #168] @ (80035b4 <DBW_Process+0x2d0>)
|
|
800350c: 681b ldr r3, [r3, #0]
|
|
800350e: 7e9b ldrb r3, [r3, #26]
|
|
8003510: b2db uxtb r3, r3
|
|
8003512: 2b00 cmp r3, #0
|
|
8003514: d113 bne.n 800353e <DBW_Process+0x25a>
|
|
var.tps_target = intrp_1d_ss_table(var.pps, 16,
|
|
8003516: 4b1e ldr r3, [pc, #120] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003518: 8c1b ldrh r3, [r3, #32]
|
|
800351a: b218 sxth r0, r3
|
|
(signed short*) config->pps_bins, 1,
|
|
800351c: 4b25 ldr r3, [pc, #148] @ (80035b4 <DBW_Process+0x2d0>)
|
|
800351e: 681b ldr r3, [r3, #0]
|
|
8003520: 331c adds r3, #28
|
|
8003522: 001a movs r2, r3
|
|
(signed short*) config->tps_bins);
|
|
8003524: 4b23 ldr r3, [pc, #140] @ (80035b4 <DBW_Process+0x2d0>)
|
|
8003526: 681b ldr r3, [r3, #0]
|
|
8003528: 333c adds r3, #60 @ 0x3c
|
|
var.tps_target = intrp_1d_ss_table(var.pps, 16,
|
|
800352a: 9300 str r3, [sp, #0]
|
|
800352c: 2301 movs r3, #1
|
|
800352e: 2110 movs r1, #16
|
|
8003530: f000 fcce bl 8003ed0 <intrp_1d_ss_table>
|
|
8003534: 0003 movs r3, r0
|
|
8003536: 001a movs r2, r3
|
|
8003538: 4b15 ldr r3, [pc, #84] @ (8003590 <DBW_Process+0x2ac>)
|
|
800353a: 85da strh r2, [r3, #46] @ 0x2e
|
|
800353c: e040 b.n 80035c0 <DBW_Process+0x2dc>
|
|
}
|
|
// if MS3 DBW protocol is used
|
|
else if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) {
|
|
800353e: 4b1d ldr r3, [pc, #116] @ (80035b4 <DBW_Process+0x2d0>)
|
|
8003540: 681b ldr r3, [r3, #0]
|
|
8003542: 7e9b ldrb r3, [r3, #26]
|
|
8003544: b2db uxtb r3, r3
|
|
8003546: 2b01 cmp r3, #1
|
|
8003548: d138 bne.n 80035bc <DBW_Process+0x2d8>
|
|
// if no RX errors
|
|
//if(var.status0 & DBW_STATUS0_CAN_MSDBW_F)
|
|
if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) {
|
|
800354a: 4b1a ldr r3, [pc, #104] @ (80035b4 <DBW_Process+0x2d0>)
|
|
800354c: 681b ldr r3, [r3, #0]
|
|
800354e: 7e9b ldrb r3, [r3, #26]
|
|
8003550: b2db uxtb r3, r3
|
|
8003552: 2b01 cmp r3, #1
|
|
8003554: d105 bne.n 8003562 <DBW_Process+0x27e>
|
|
// use MS3 TPS TARGET
|
|
var.tps_target = can_target;
|
|
8003556: 4b18 ldr r3, [pc, #96] @ (80035b8 <DBW_Process+0x2d4>)
|
|
8003558: 681b ldr r3, [r3, #0]
|
|
800355a: b21a sxth r2, r3
|
|
800355c: 4b0c ldr r3, [pc, #48] @ (8003590 <DBW_Process+0x2ac>)
|
|
800355e: 85da strh r2, [r3, #46] @ 0x2e
|
|
8003560: e02e b.n 80035c0 <DBW_Process+0x2dc>
|
|
} else {
|
|
// on CAN error fall back to internal curve
|
|
var.tps_target = intrp_1d_ss_table(var.pps, 16,
|
|
8003562: 4b0b ldr r3, [pc, #44] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003564: 8c1b ldrh r3, [r3, #32]
|
|
8003566: b218 sxth r0, r3
|
|
(signed short*) config->pps_bins, 1,
|
|
8003568: 4b12 ldr r3, [pc, #72] @ (80035b4 <DBW_Process+0x2d0>)
|
|
800356a: 681b ldr r3, [r3, #0]
|
|
800356c: 331c adds r3, #28
|
|
800356e: 001a movs r2, r3
|
|
(signed short*) config->tps_bins);
|
|
8003570: 4b10 ldr r3, [pc, #64] @ (80035b4 <DBW_Process+0x2d0>)
|
|
8003572: 681b ldr r3, [r3, #0]
|
|
8003574: 333c adds r3, #60 @ 0x3c
|
|
var.tps_target = intrp_1d_ss_table(var.pps, 16,
|
|
8003576: 9300 str r3, [sp, #0]
|
|
8003578: 2301 movs r3, #1
|
|
800357a: 2110 movs r1, #16
|
|
800357c: f000 fca8 bl 8003ed0 <intrp_1d_ss_table>
|
|
8003580: 0003 movs r3, r0
|
|
8003582: 001a movs r2, r3
|
|
8003584: 4b02 ldr r3, [pc, #8] @ (8003590 <DBW_Process+0x2ac>)
|
|
8003586: 85da strh r2, [r3, #46] @ 0x2e
|
|
8003588: e01a b.n 80035c0 <DBW_Process+0x2dc>
|
|
800358a: 46c0 nop @ (mov r8, r8)
|
|
800358c: 20000a1c .word 0x20000a1c
|
|
8003590: 20000998 .word 0x20000998
|
|
8003594: 200009fc .word 0x200009fc
|
|
8003598: 20000a00 .word 0x20000a00
|
|
800359c: 20000a04 .word 0x20000a04
|
|
80035a0: 20000a08 .word 0x20000a08
|
|
80035a4: 20000a0c .word 0x20000a0c
|
|
80035a8: 20000a10 .word 0x20000a10
|
|
80035ac: 20000a14 .word 0x20000a14
|
|
80035b0: 20000a18 .word 0x20000a18
|
|
80035b4: 200009cc .word 0x200009cc
|
|
80035b8: 20000a38 .word 0x20000a38
|
|
}
|
|
}
|
|
|
|
else {
|
|
// All other TPS target options are considered as fault
|
|
Error_Handler();
|
|
80035bc: f001 fbb0 bl 8004d20 <Error_Handler>
|
|
}
|
|
|
|
// add idle TPS target adder
|
|
var.tps_target += idle_adder;
|
|
80035c0: 4bcc ldr r3, [pc, #816] @ (80038f4 <DBW_Process+0x610>)
|
|
80035c2: 6819 ldr r1, [r3, #0]
|
|
80035c4: 4bcc ldr r3, [pc, #816] @ (80038f8 <DBW_Process+0x614>)
|
|
80035c6: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
80035c8: b21b sxth r3, r3
|
|
80035ca: b29a uxth r2, r3
|
|
80035cc: b28b uxth r3, r1
|
|
80035ce: 18d3 adds r3, r2, r3
|
|
80035d0: b29b uxth r3, r3
|
|
80035d2: b21a sxth r2, r3
|
|
80035d4: 4bc8 ldr r3, [pc, #800] @ (80038f8 <DBW_Process+0x614>)
|
|
80035d6: 85da strh r2, [r3, #46] @ 0x2e
|
|
//limit TPS target
|
|
if (var.tps_target > 1000)
|
|
80035d8: 4bc7 ldr r3, [pc, #796] @ (80038f8 <DBW_Process+0x614>)
|
|
80035da: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
80035dc: b21a sxth r2, r3
|
|
80035de: 23fa movs r3, #250 @ 0xfa
|
|
80035e0: 009b lsls r3, r3, #2
|
|
80035e2: 429a cmp r2, r3
|
|
80035e4: dd03 ble.n 80035ee <DBW_Process+0x30a>
|
|
var.tps_target = 1000;
|
|
80035e6: 4bc4 ldr r3, [pc, #784] @ (80038f8 <DBW_Process+0x614>)
|
|
80035e8: 22fa movs r2, #250 @ 0xfa
|
|
80035ea: 0092 lsls r2, r2, #2
|
|
80035ec: 85da strh r2, [r3, #46] @ 0x2e
|
|
if (var.tps_target < 0)
|
|
80035ee: 4bc2 ldr r3, [pc, #776] @ (80038f8 <DBW_Process+0x614>)
|
|
80035f0: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
80035f2: b21b sxth r3, r3
|
|
80035f4: 2b00 cmp r3, #0
|
|
80035f6: da02 bge.n 80035fe <DBW_Process+0x31a>
|
|
var.tps_target = 0;
|
|
80035f8: 4bbf ldr r3, [pc, #764] @ (80038f8 <DBW_Process+0x614>)
|
|
80035fa: 2200 movs r2, #0
|
|
80035fc: 85da strh r2, [r3, #46] @ 0x2e
|
|
|
|
//calculate regulation error
|
|
var.tps_error = var.tps_target - var.tps;
|
|
80035fe: 4bbe ldr r3, [pc, #760] @ (80038f8 <DBW_Process+0x614>)
|
|
8003600: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8003602: b21b sxth r3, r3
|
|
8003604: b29a uxth r2, r3
|
|
8003606: 4bbc ldr r3, [pc, #752] @ (80038f8 <DBW_Process+0x614>)
|
|
8003608: 8c5b ldrh r3, [r3, #34] @ 0x22
|
|
800360a: b21b sxth r3, r3
|
|
800360c: b29b uxth r3, r3
|
|
800360e: 1ad3 subs r3, r2, r3
|
|
8003610: b29b uxth r3, r3
|
|
8003612: b21a sxth r2, r3
|
|
8003614: 4bb8 ldr r3, [pc, #736] @ (80038f8 <DBW_Process+0x614>)
|
|
8003616: 849a strh r2, [r3, #36] @ 0x24
|
|
|
|
// Proportional regulator
|
|
p_comp = (((int32_t) var.tps_error) * (int32_t) config->motor_fw_p)
|
|
8003618: 4bb7 ldr r3, [pc, #732] @ (80038f8 <DBW_Process+0x614>)
|
|
800361a: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
800361c: b21b sxth r3, r3
|
|
800361e: 0019 movs r1, r3
|
|
8003620: 4bb6 ldr r3, [pc, #728] @ (80038fc <DBW_Process+0x618>)
|
|
8003622: 681b ldr r3, [r3, #0]
|
|
8003624: 2282 movs r2, #130 @ 0x82
|
|
8003626: 5a9b ldrh r3, [r3, r2]
|
|
8003628: b21b sxth r3, r3
|
|
800362a: 434b muls r3, r1
|
|
/ 10;
|
|
800362c: 210a movs r1, #10
|
|
800362e: 0018 movs r0, r3
|
|
8003630: f7fc fdf4 bl 800021c <__divsi3>
|
|
8003634: 0003 movs r3, r0
|
|
8003636: 001a movs r2, r3
|
|
p_comp = (((int32_t) var.tps_error) * (int32_t) config->motor_fw_p)
|
|
8003638: 4bb1 ldr r3, [pc, #708] @ (8003900 <DBW_Process+0x61c>)
|
|
800363a: 601a str r2, [r3, #0]
|
|
|
|
// calculate spring preload compensation using interpolation
|
|
spring_preload = intrp_1d_ss_table(var.tps_target, 16,
|
|
800363c: 4bae ldr r3, [pc, #696] @ (80038f8 <DBW_Process+0x614>)
|
|
800363e: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8003640: b218 sxth r0, r3
|
|
(signed short*) config->tps_dc_tps_bins, 1,
|
|
8003642: 4bae ldr r3, [pc, #696] @ (80038fc <DBW_Process+0x618>)
|
|
8003644: 681b ldr r3, [r3, #0]
|
|
8003646: 22b5 movs r2, #181 @ 0xb5
|
|
8003648: 0092 lsls r2, r2, #2
|
|
800364a: 189a adds r2, r3, r2
|
|
(signed short*) config->tps_dc_offset_bins);
|
|
800364c: 4bab ldr r3, [pc, #684] @ (80038fc <DBW_Process+0x618>)
|
|
800364e: 681b ldr r3, [r3, #0]
|
|
8003650: 21bd movs r1, #189 @ 0xbd
|
|
8003652: 0089 lsls r1, r1, #2
|
|
8003654: 468c mov ip, r1
|
|
8003656: 4463 add r3, ip
|
|
spring_preload = intrp_1d_ss_table(var.tps_target, 16,
|
|
8003658: 9300 str r3, [sp, #0]
|
|
800365a: 2301 movs r3, #1
|
|
800365c: 2110 movs r1, #16
|
|
800365e: f000 fc37 bl 8003ed0 <intrp_1d_ss_table>
|
|
8003662: 0003 movs r3, r0
|
|
8003664: 001a movs r2, r3
|
|
8003666: 4ba7 ldr r3, [pc, #668] @ (8003904 <DBW_Process+0x620>)
|
|
8003668: 601a str r2, [r3, #0]
|
|
|
|
if (dbw_slow_process_timer > 0) {
|
|
800366a: 4ba7 ldr r3, [pc, #668] @ (8003908 <DBW_Process+0x624>)
|
|
800366c: 881b ldrh r3, [r3, #0]
|
|
800366e: b29b uxth r3, r3
|
|
8003670: 2b00 cmp r3, #0
|
|
8003672: d100 bne.n 8003676 <DBW_Process+0x392>
|
|
8003674: e0ef b.n 8003856 <DBW_Process+0x572>
|
|
dbw_slow_process_timer--;
|
|
8003676: 4ba4 ldr r3, [pc, #656] @ (8003908 <DBW_Process+0x624>)
|
|
8003678: 881b ldrh r3, [r3, #0]
|
|
800367a: b29b uxth r3, r3
|
|
800367c: 3b01 subs r3, #1
|
|
800367e: b29a uxth r2, r3
|
|
8003680: 4ba1 ldr r3, [pc, #644] @ (8003908 <DBW_Process+0x624>)
|
|
8003682: 801a strh r2, [r3, #0]
|
|
if (dbw_slow_process_timer == 0) {
|
|
8003684: 4ba0 ldr r3, [pc, #640] @ (8003908 <DBW_Process+0x624>)
|
|
8003686: 881b ldrh r3, [r3, #0]
|
|
8003688: b29b uxth r3, r3
|
|
800368a: 2b00 cmp r3, #0
|
|
800368c: d000 beq.n 8003690 <DBW_Process+0x3ac>
|
|
800368e: e0e2 b.n 8003856 <DBW_Process+0x572>
|
|
dbw_slow_process_timer = config->motor_ctl_period;
|
|
8003690: 4b9a ldr r3, [pc, #616] @ (80038fc <DBW_Process+0x618>)
|
|
8003692: 681b ldr r3, [r3, #0]
|
|
8003694: 227e movs r2, #126 @ 0x7e
|
|
8003696: 5a9b ldrh r3, [r3, r2]
|
|
8003698: b29a uxth r2, r3
|
|
800369a: 4b9b ldr r3, [pc, #620] @ (8003908 <DBW_Process+0x624>)
|
|
800369c: 801a strh r2, [r3, #0]
|
|
//calculate slow changing thinks
|
|
|
|
//read Battery voltage and apply corrections
|
|
var.vbat_adc = LPF(700, Adc_Read(5), var.vbat_adc);
|
|
800369e: 2005 movs r0, #5
|
|
80036a0: f7ff f8ce bl 8002840 <Adc_Read>
|
|
80036a4: 0003 movs r3, r0
|
|
80036a6: 0019 movs r1, r3
|
|
80036a8: 4b93 ldr r3, [pc, #588] @ (80038f8 <DBW_Process+0x614>)
|
|
80036aa: 8adb ldrh r3, [r3, #22]
|
|
80036ac: b29a uxth r2, r3
|
|
80036ae: 23af movs r3, #175 @ 0xaf
|
|
80036b0: 009b lsls r3, r3, #2
|
|
80036b2: 0018 movs r0, r3
|
|
80036b4: f7ff f876 bl 80027a4 <LPF>
|
|
80036b8: 0003 movs r3, r0
|
|
80036ba: 001a movs r2, r3
|
|
80036bc: 4b8e ldr r3, [pc, #568] @ (80038f8 <DBW_Process+0x614>)
|
|
80036be: 82da strh r2, [r3, #22]
|
|
pct = intrp_1d_ss_table(var.vbat_adc, 8,
|
|
80036c0: 4b8d ldr r3, [pc, #564] @ (80038f8 <DBW_Process+0x614>)
|
|
80036c2: 8adb ldrh r3, [r3, #22]
|
|
80036c4: b29b uxth r3, r3
|
|
80036c6: b218 sxth r0, r3
|
|
(signed short*) config->vbat_bins, 1,
|
|
80036c8: 4b8c ldr r3, [pc, #560] @ (80038fc <DBW_Process+0x618>)
|
|
80036ca: 681b ldr r3, [r3, #0]
|
|
80036cc: 22c5 movs r2, #197 @ 0xc5
|
|
80036ce: 0092 lsls r2, r2, #2
|
|
80036d0: 189a adds r2, r3, r2
|
|
(signed short*) config->motor_pwm_corr_bins);
|
|
80036d2: 4b8a ldr r3, [pc, #552] @ (80038fc <DBW_Process+0x618>)
|
|
80036d4: 681b ldr r3, [r3, #0]
|
|
80036d6: 21c9 movs r1, #201 @ 0xc9
|
|
80036d8: 0089 lsls r1, r1, #2
|
|
80036da: 468c mov ip, r1
|
|
80036dc: 4463 add r3, ip
|
|
pct = intrp_1d_ss_table(var.vbat_adc, 8,
|
|
80036de: 9300 str r3, [sp, #0]
|
|
80036e0: 2301 movs r3, #1
|
|
80036e2: 2108 movs r1, #8
|
|
80036e4: f000 fbf4 bl 8003ed0 <intrp_1d_ss_table>
|
|
80036e8: 0003 movs r3, r0
|
|
80036ea: 603b str r3, [r7, #0]
|
|
|
|
//read motor current
|
|
var.motor_current_adc = LPF(700, Adc_Read(4),
|
|
80036ec: 2004 movs r0, #4
|
|
80036ee: f7ff f8a7 bl 8002840 <Adc_Read>
|
|
80036f2: 0003 movs r3, r0
|
|
80036f4: 0019 movs r1, r3
|
|
var.motor_current_adc);
|
|
80036f6: 4b80 ldr r3, [pc, #512] @ (80038f8 <DBW_Process+0x614>)
|
|
80036f8: 8a9b ldrh r3, [r3, #20]
|
|
80036fa: b29a uxth r2, r3
|
|
var.motor_current_adc = LPF(700, Adc_Read(4),
|
|
80036fc: 23af movs r3, #175 @ 0xaf
|
|
80036fe: 009b lsls r3, r3, #2
|
|
8003700: 0018 movs r0, r3
|
|
8003702: f7ff f84f bl 80027a4 <LPF>
|
|
8003706: 0003 movs r3, r0
|
|
8003708: 001a movs r2, r3
|
|
800370a: 4b7b ldr r3, [pc, #492] @ (80038f8 <DBW_Process+0x614>)
|
|
800370c: 829a strh r2, [r3, #20]
|
|
|
|
// calculate I component
|
|
|
|
i_comp += ((int32_t) var.tps_error
|
|
800370e: 4b7a ldr r3, [pc, #488] @ (80038f8 <DBW_Process+0x614>)
|
|
8003710: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8003712: b21b sxth r3, r3
|
|
8003714: 0019 movs r1, r3
|
|
* (int32_t) config->motor_fw_i) / 100;
|
|
8003716: 4b79 ldr r3, [pc, #484] @ (80038fc <DBW_Process+0x618>)
|
|
8003718: 681b ldr r3, [r3, #0]
|
|
800371a: 2284 movs r2, #132 @ 0x84
|
|
800371c: 5a9b ldrh r3, [r3, r2]
|
|
800371e: b21b sxth r3, r3
|
|
8003720: 434b muls r3, r1
|
|
8003722: 2164 movs r1, #100 @ 0x64
|
|
8003724: 0018 movs r0, r3
|
|
8003726: f7fc fd79 bl 800021c <__divsi3>
|
|
800372a: 0003 movs r3, r0
|
|
800372c: 001a movs r2, r3
|
|
i_comp += ((int32_t) var.tps_error
|
|
800372e: 4b77 ldr r3, [pc, #476] @ (800390c <DBW_Process+0x628>)
|
|
8003730: 681b ldr r3, [r3, #0]
|
|
8003732: 18d2 adds r2, r2, r3
|
|
8003734: 4b75 ldr r3, [pc, #468] @ (800390c <DBW_Process+0x628>)
|
|
8003736: 601a str r2, [r3, #0]
|
|
if (i_comp > config->i_limmit)
|
|
8003738: 4b70 ldr r3, [pc, #448] @ (80038fc <DBW_Process+0x618>)
|
|
800373a: 681b ldr r3, [r3, #0]
|
|
800373c: 4a74 ldr r2, [pc, #464] @ (8003910 <DBW_Process+0x62c>)
|
|
800373e: 5a9b ldrh r3, [r3, r2]
|
|
8003740: b21b sxth r3, r3
|
|
8003742: 001a movs r2, r3
|
|
8003744: 4b71 ldr r3, [pc, #452] @ (800390c <DBW_Process+0x628>)
|
|
8003746: 681b ldr r3, [r3, #0]
|
|
8003748: 429a cmp r2, r3
|
|
800374a: da07 bge.n 800375c <DBW_Process+0x478>
|
|
i_comp = config->i_limmit;
|
|
800374c: 4b6b ldr r3, [pc, #428] @ (80038fc <DBW_Process+0x618>)
|
|
800374e: 681b ldr r3, [r3, #0]
|
|
8003750: 4a6f ldr r2, [pc, #444] @ (8003910 <DBW_Process+0x62c>)
|
|
8003752: 5a9b ldrh r3, [r3, r2]
|
|
8003754: b21b sxth r3, r3
|
|
8003756: 001a movs r2, r3
|
|
8003758: 4b6c ldr r3, [pc, #432] @ (800390c <DBW_Process+0x628>)
|
|
800375a: 601a str r2, [r3, #0]
|
|
if (i_comp < (-config->i_limmit))
|
|
800375c: 4b67 ldr r3, [pc, #412] @ (80038fc <DBW_Process+0x618>)
|
|
800375e: 681b ldr r3, [r3, #0]
|
|
8003760: 4a6b ldr r2, [pc, #428] @ (8003910 <DBW_Process+0x62c>)
|
|
8003762: 5a9b ldrh r3, [r3, r2]
|
|
8003764: b21b sxth r3, r3
|
|
8003766: 425a negs r2, r3
|
|
8003768: 4b68 ldr r3, [pc, #416] @ (800390c <DBW_Process+0x628>)
|
|
800376a: 681b ldr r3, [r3, #0]
|
|
800376c: 429a cmp r2, r3
|
|
800376e: dd07 ble.n 8003780 <DBW_Process+0x49c>
|
|
i_comp = (-config->i_limmit);
|
|
8003770: 4b62 ldr r3, [pc, #392] @ (80038fc <DBW_Process+0x618>)
|
|
8003772: 681b ldr r3, [r3, #0]
|
|
8003774: 4a66 ldr r2, [pc, #408] @ (8003910 <DBW_Process+0x62c>)
|
|
8003776: 5a9b ldrh r3, [r3, r2]
|
|
8003778: b21b sxth r3, r3
|
|
800377a: 425a negs r2, r3
|
|
800377c: 4b63 ldr r3, [pc, #396] @ (800390c <DBW_Process+0x628>)
|
|
800377e: 601a str r2, [r3, #0]
|
|
|
|
// calculate D component
|
|
d_comp = (((int32_t) var.tps_error - tps_error_t)
|
|
8003780: 4b5d ldr r3, [pc, #372] @ (80038f8 <DBW_Process+0x614>)
|
|
8003782: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8003784: b21b sxth r3, r3
|
|
8003786: 001a movs r2, r3
|
|
8003788: 4b62 ldr r3, [pc, #392] @ (8003914 <DBW_Process+0x630>)
|
|
800378a: 681b ldr r3, [r3, #0]
|
|
800378c: 1ad2 subs r2, r2, r3
|
|
* (int32_t) config->motor_fw_d) / 10;
|
|
800378e: 4b5b ldr r3, [pc, #364] @ (80038fc <DBW_Process+0x618>)
|
|
8003790: 681b ldr r3, [r3, #0]
|
|
8003792: 2186 movs r1, #134 @ 0x86
|
|
8003794: 5a5b ldrh r3, [r3, r1]
|
|
8003796: b21b sxth r3, r3
|
|
8003798: 4353 muls r3, r2
|
|
800379a: 210a movs r1, #10
|
|
800379c: 0018 movs r0, r3
|
|
800379e: f7fc fd3d bl 800021c <__divsi3>
|
|
80037a2: 0003 movs r3, r0
|
|
80037a4: 001a movs r2, r3
|
|
d_comp = (((int32_t) var.tps_error - tps_error_t)
|
|
80037a6: 4b5c ldr r3, [pc, #368] @ (8003918 <DBW_Process+0x634>)
|
|
80037a8: 601a str r2, [r3, #0]
|
|
tps_error_t = var.tps_error;
|
|
80037aa: 4b53 ldr r3, [pc, #332] @ (80038f8 <DBW_Process+0x614>)
|
|
80037ac: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
80037ae: b21b sxth r3, r3
|
|
80037b0: 001a movs r2, r3
|
|
80037b2: 4b58 ldr r3, [pc, #352] @ (8003914 <DBW_Process+0x630>)
|
|
80037b4: 601a str r2, [r3, #0]
|
|
|
|
// calculate single shot
|
|
//single_shot = var.tps_error *
|
|
|
|
// Calculate Idle adder
|
|
if (config->idle_input_option == IDLE_OPTION_NO_IDLE_INPUT)
|
|
80037b6: 4b51 ldr r3, [pc, #324] @ (80038fc <DBW_Process+0x618>)
|
|
80037b8: 681b ldr r3, [r3, #0]
|
|
80037ba: 7edb ldrb r3, [r3, #27]
|
|
80037bc: b2db uxtb r3, r3
|
|
80037be: 2b00 cmp r3, #0
|
|
80037c0: d103 bne.n 80037ca <DBW_Process+0x4e6>
|
|
idle_adder = 0;
|
|
80037c2: 4b4c ldr r3, [pc, #304] @ (80038f4 <DBW_Process+0x610>)
|
|
80037c4: 2200 movs r2, #0
|
|
80037c6: 601a str r2, [r3, #0]
|
|
80037c8: e045 b.n 8003856 <DBW_Process+0x572>
|
|
else if (config->idle_input_option == IDLE_OPTION_MS_CAN) {
|
|
80037ca: 4b4c ldr r3, [pc, #304] @ (80038fc <DBW_Process+0x618>)
|
|
80037cc: 681b ldr r3, [r3, #0]
|
|
80037ce: 7edb ldrb r3, [r3, #27]
|
|
80037d0: b2db uxtb r3, r3
|
|
80037d2: 2b03 cmp r3, #3
|
|
80037d4: d114 bne.n 8003800 <DBW_Process+0x51c>
|
|
idle_adder = intrp_1d_ss_table(var.idle_dc, 8,
|
|
80037d6: 4b48 ldr r3, [pc, #288] @ (80038f8 <DBW_Process+0x614>)
|
|
80037d8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
80037da: b29b uxth r3, r3
|
|
80037dc: b218 sxth r0, r3
|
|
(signed short*) config->idle_input_bins, 1,
|
|
80037de: 4b47 ldr r3, [pc, #284] @ (80038fc <DBW_Process+0x618>)
|
|
80037e0: 681b ldr r3, [r3, #0]
|
|
80037e2: 335c adds r3, #92 @ 0x5c
|
|
80037e4: 001a movs r2, r3
|
|
(signed short*) config->idle_tps_adder_bins);
|
|
80037e6: 4b45 ldr r3, [pc, #276] @ (80038fc <DBW_Process+0x618>)
|
|
80037e8: 681b ldr r3, [r3, #0]
|
|
80037ea: 336c adds r3, #108 @ 0x6c
|
|
idle_adder = intrp_1d_ss_table(var.idle_dc, 8,
|
|
80037ec: 9300 str r3, [sp, #0]
|
|
80037ee: 2301 movs r3, #1
|
|
80037f0: 2108 movs r1, #8
|
|
80037f2: f000 fb6d bl 8003ed0 <intrp_1d_ss_table>
|
|
80037f6: 0003 movs r3, r0
|
|
80037f8: 001a movs r2, r3
|
|
80037fa: 4b3e ldr r3, [pc, #248] @ (80038f4 <DBW_Process+0x610>)
|
|
80037fc: 601a str r2, [r3, #0]
|
|
80037fe: e02a b.n 8003856 <DBW_Process+0x572>
|
|
|
|
} else if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) {
|
|
8003800: 4b3e ldr r3, [pc, #248] @ (80038fc <DBW_Process+0x618>)
|
|
8003802: 681b ldr r3, [r3, #0]
|
|
8003804: 7edb ldrb r3, [r3, #27]
|
|
8003806: b2db uxtb r3, r3
|
|
8003808: 2b01 cmp r3, #1
|
|
800380a: d124 bne.n 8003856 <DBW_Process+0x572>
|
|
|
|
idle_adder = intrp_1d_ss_table(var.idle_dc, 8,
|
|
800380c: 4b3a ldr r3, [pc, #232] @ (80038f8 <DBW_Process+0x614>)
|
|
800380e: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003810: b29b uxth r3, r3
|
|
8003812: b218 sxth r0, r3
|
|
(signed short*) config->idle_input_bins, 1,
|
|
8003814: 4b39 ldr r3, [pc, #228] @ (80038fc <DBW_Process+0x618>)
|
|
8003816: 681b ldr r3, [r3, #0]
|
|
8003818: 335c adds r3, #92 @ 0x5c
|
|
800381a: 001a movs r2, r3
|
|
(signed short*) config->idle_tps_adder_bins)
|
|
800381c: 4b37 ldr r3, [pc, #220] @ (80038fc <DBW_Process+0x618>)
|
|
800381e: 681b ldr r3, [r3, #0]
|
|
8003820: 336c adds r3, #108 @ 0x6c
|
|
idle_adder = intrp_1d_ss_table(var.idle_dc, 8,
|
|
8003822: 9300 str r3, [sp, #0]
|
|
8003824: 2301 movs r3, #1
|
|
8003826: 2108 movs r1, #8
|
|
8003828: f000 fb52 bl 8003ed0 <intrp_1d_ss_table>
|
|
800382c: 0003 movs r3, r0
|
|
800382e: 001c movs r4, r3
|
|
- (var.pps / 5);
|
|
8003830: 4b31 ldr r3, [pc, #196] @ (80038f8 <DBW_Process+0x614>)
|
|
8003832: 8c1b ldrh r3, [r3, #32]
|
|
8003834: b21b sxth r3, r3
|
|
8003836: 2105 movs r1, #5
|
|
8003838: 0018 movs r0, r3
|
|
800383a: f7fc fcef bl 800021c <__divsi3>
|
|
800383e: 0003 movs r3, r0
|
|
8003840: b21b sxth r3, r3
|
|
8003842: 1ae2 subs r2, r4, r3
|
|
idle_adder = intrp_1d_ss_table(var.idle_dc, 8,
|
|
8003844: 4b2b ldr r3, [pc, #172] @ (80038f4 <DBW_Process+0x610>)
|
|
8003846: 601a str r2, [r3, #0]
|
|
if (idle_adder < 0) {
|
|
8003848: 4b2a ldr r3, [pc, #168] @ (80038f4 <DBW_Process+0x610>)
|
|
800384a: 681b ldr r3, [r3, #0]
|
|
800384c: 2b00 cmp r3, #0
|
|
800384e: da02 bge.n 8003856 <DBW_Process+0x572>
|
|
idle_adder = 0;
|
|
8003850: 4b28 ldr r3, [pc, #160] @ (80038f4 <DBW_Process+0x610>)
|
|
8003852: 2200 movs r2, #0
|
|
8003854: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
pwm_output = p_comp + i_comp + d_comp + spring_preload;
|
|
8003856: 4b2a ldr r3, [pc, #168] @ (8003900 <DBW_Process+0x61c>)
|
|
8003858: 681a ldr r2, [r3, #0]
|
|
800385a: 4b2c ldr r3, [pc, #176] @ (800390c <DBW_Process+0x628>)
|
|
800385c: 681b ldr r3, [r3, #0]
|
|
800385e: 18d2 adds r2, r2, r3
|
|
8003860: 4b2d ldr r3, [pc, #180] @ (8003918 <DBW_Process+0x634>)
|
|
8003862: 681b ldr r3, [r3, #0]
|
|
8003864: 18d2 adds r2, r2, r3
|
|
8003866: 4b27 ldr r3, [pc, #156] @ (8003904 <DBW_Process+0x620>)
|
|
8003868: 681b ldr r3, [r3, #0]
|
|
800386a: 18d3 adds r3, r2, r3
|
|
800386c: 607b str r3, [r7, #4]
|
|
|
|
vbat_corr = (int16_t) (((int32_t) var.motor_pwm) * vbat_corr / 1000);
|
|
800386e: 4b22 ldr r3, [pc, #136] @ (80038f8 <DBW_Process+0x614>)
|
|
8003870: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8003872: b21b sxth r3, r3
|
|
8003874: 001a movs r2, r3
|
|
8003876: 4b29 ldr r3, [pc, #164] @ (800391c <DBW_Process+0x638>)
|
|
8003878: 681b ldr r3, [r3, #0]
|
|
800387a: 4353 muls r3, r2
|
|
800387c: 22fa movs r2, #250 @ 0xfa
|
|
800387e: 0091 lsls r1, r2, #2
|
|
8003880: 0018 movs r0, r3
|
|
8003882: f7fc fccb bl 800021c <__divsi3>
|
|
8003886: 0003 movs r3, r0
|
|
8003888: b21b sxth r3, r3
|
|
800388a: 001a movs r2, r3
|
|
800388c: 4b23 ldr r3, [pc, #140] @ (800391c <DBW_Process+0x638>)
|
|
800388e: 601a str r2, [r3, #0]
|
|
|
|
pwm_output += pct;
|
|
8003890: 687a ldr r2, [r7, #4]
|
|
8003892: 683b ldr r3, [r7, #0]
|
|
8003894: 18d3 adds r3, r2, r3
|
|
8003896: 607b str r3, [r7, #4]
|
|
|
|
//limmit pwm
|
|
if (pwm_output > config->motor_dc_max)
|
|
8003898: 4b18 ldr r3, [pc, #96] @ (80038fc <DBW_Process+0x618>)
|
|
800389a: 681a ldr r2, [r3, #0]
|
|
800389c: 23b4 movs r3, #180 @ 0xb4
|
|
800389e: 009b lsls r3, r3, #2
|
|
80038a0: 5ad3 ldrh r3, [r2, r3]
|
|
80038a2: b21b sxth r3, r3
|
|
80038a4: 001a movs r2, r3
|
|
80038a6: 687b ldr r3, [r7, #4]
|
|
80038a8: 4293 cmp r3, r2
|
|
80038aa: dd06 ble.n 80038ba <DBW_Process+0x5d6>
|
|
pwm_output = config->motor_dc_max;
|
|
80038ac: 4b13 ldr r3, [pc, #76] @ (80038fc <DBW_Process+0x618>)
|
|
80038ae: 681a ldr r2, [r3, #0]
|
|
80038b0: 23b4 movs r3, #180 @ 0xb4
|
|
80038b2: 009b lsls r3, r3, #2
|
|
80038b4: 5ad3 ldrh r3, [r2, r3]
|
|
80038b6: b21b sxth r3, r3
|
|
80038b8: 607b str r3, [r7, #4]
|
|
if (pwm_output < config->motor_dc_min)
|
|
80038ba: 4b10 ldr r3, [pc, #64] @ (80038fc <DBW_Process+0x618>)
|
|
80038bc: 681b ldr r3, [r3, #0]
|
|
80038be: 4a18 ldr r2, [pc, #96] @ (8003920 <DBW_Process+0x63c>)
|
|
80038c0: 5a9b ldrh r3, [r3, r2]
|
|
80038c2: b21b sxth r3, r3
|
|
80038c4: 001a movs r2, r3
|
|
80038c6: 687b ldr r3, [r7, #4]
|
|
80038c8: 4293 cmp r3, r2
|
|
80038ca: da05 bge.n 80038d8 <DBW_Process+0x5f4>
|
|
pwm_output = config->motor_dc_min;
|
|
80038cc: 4b0b ldr r3, [pc, #44] @ (80038fc <DBW_Process+0x618>)
|
|
80038ce: 681b ldr r3, [r3, #0]
|
|
80038d0: 4a13 ldr r2, [pc, #76] @ (8003920 <DBW_Process+0x63c>)
|
|
80038d2: 5a9b ldrh r3, [r3, r2]
|
|
80038d4: b21b sxth r3, r3
|
|
80038d6: 607b str r3, [r7, #4]
|
|
|
|
//apply pwm
|
|
DBW_Pwm_Set_Duty((signed short) (pwm_output), (pwm_t*) &ttl1_pwm);
|
|
80038d8: 687b ldr r3, [r7, #4]
|
|
80038da: b21b sxth r3, r3
|
|
80038dc: 001a movs r2, r3
|
|
80038de: 4b11 ldr r3, [pc, #68] @ (8003924 <DBW_Process+0x640>)
|
|
80038e0: 0019 movs r1, r3
|
|
80038e2: 0010 movs r0, r2
|
|
80038e4: f000 fa1c bl 8003d20 <DBW_Pwm_Set_Duty>
|
|
|
|
}
|
|
|
|
return 0;
|
|
80038e8: 2300 movs r3, #0
|
|
}
|
|
80038ea: 0018 movs r0, r3
|
|
80038ec: 46bd mov sp, r7
|
|
80038ee: b003 add sp, #12
|
|
80038f0: bd90 pop {r4, r7, pc}
|
|
80038f2: 46c0 nop @ (mov r8, r8)
|
|
80038f4: 20000a40 .word 0x20000a40
|
|
80038f8: 20000998 .word 0x20000998
|
|
80038fc: 200009cc .word 0x200009cc
|
|
8003900: 20000a28 .word 0x20000a28
|
|
8003904: 20000a3c .word 0x20000a3c
|
|
8003908: 20000a1e .word 0x20000a1e
|
|
800390c: 20000a2c .word 0x20000a2c
|
|
8003910: 000002ce .word 0x000002ce
|
|
8003914: 20000a34 .word 0x20000a34
|
|
8003918: 20000a30 .word 0x20000a30
|
|
800391c: 20000a20 .word 0x20000a20
|
|
8003920: 000002d2 .word 0x000002d2
|
|
8003924: 200009d4 .word 0x200009d4
|
|
|
|
08003928 <DBW_Pwm_Init>:
|
|
|
|
void DBW_Pwm_Init(void) {
|
|
8003928: b580 push {r7, lr}
|
|
800392a: af00 add r7, sp, #0
|
|
|
|
// Setup PWM ports
|
|
ttl1_pwm.pos_port = GPIOB;
|
|
800392c: 4b4e ldr r3, [pc, #312] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800392e: 4a4f ldr r2, [pc, #316] @ (8003a6c <DBW_Pwm_Init+0x144>)
|
|
8003930: 605a str r2, [r3, #4]
|
|
ttl1_pwm.pos_pin = 10;
|
|
8003932: 4b4d ldr r3, [pc, #308] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
8003934: 220a movs r2, #10
|
|
8003936: 811a strh r2, [r3, #8]
|
|
|
|
ttl1_pwm.neg_port = GPIOB;
|
|
8003938: 4b4b ldr r3, [pc, #300] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800393a: 4a4c ldr r2, [pc, #304] @ (8003a6c <DBW_Pwm_Init+0x144>)
|
|
800393c: 60da str r2, [r3, #12]
|
|
ttl1_pwm.neg_pin = 11;
|
|
800393e: 4b4a ldr r3, [pc, #296] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
8003940: 220b movs r2, #11
|
|
8003942: 821a strh r2, [r3, #16]
|
|
|
|
// setup pwm status default -> no drive
|
|
ttl1_pwm.status = PWM_STATUS_DEFAULT;
|
|
8003944: 4b48 ldr r3, [pc, #288] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
8003946: 2200 movs r2, #0
|
|
8003948: 701a strb r2, [r3, #0]
|
|
|
|
// calculate how many tick are in given freq period
|
|
ttl1_pwm.period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq;
|
|
800394a: 4b49 ldr r3, [pc, #292] @ (8003a70 <DBW_Pwm_Init+0x148>)
|
|
800394c: 681b ldr r3, [r3, #0]
|
|
800394e: 227c movs r2, #124 @ 0x7c
|
|
8003950: 5a9b ldrh r3, [r3, r2]
|
|
8003952: b29b uxth r3, r3
|
|
8003954: 0019 movs r1, r3
|
|
8003956: 4847 ldr r0, [pc, #284] @ (8003a74 <DBW_Pwm_Init+0x14c>)
|
|
8003958: f7fc fbd6 bl 8000108 <__udivsi3>
|
|
800395c: 0003 movs r3, r0
|
|
800395e: 001a movs r2, r3
|
|
8003960: 4b41 ldr r3, [pc, #260] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
8003962: 615a str r2, [r3, #20]
|
|
|
|
// set initian pwm from current settings
|
|
ttl1_pwm.pwm = var.motor_pwm;
|
|
8003964: 4b44 ldr r3, [pc, #272] @ (8003a78 <DBW_Pwm_Init+0x150>)
|
|
8003966: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8003968: b21b sxth r3, r3
|
|
800396a: 001a movs r2, r3
|
|
800396c: 4b3e ldr r3, [pc, #248] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800396e: 61da str r2, [r3, #28]
|
|
ttl1_pwm.pwm_t = var.motor_pwm;
|
|
8003970: 4b41 ldr r3, [pc, #260] @ (8003a78 <DBW_Pwm_Init+0x150>)
|
|
8003972: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8003974: b21b sxth r3, r3
|
|
8003976: 001a movs r2, r3
|
|
8003978: 4b3b ldr r3, [pc, #236] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800397a: 621a str r2, [r3, #32]
|
|
ttl1_pwm.single_pulse = 0;
|
|
800397c: 4b3a ldr r3, [pc, #232] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800397e: 2200 movs r2, #0
|
|
8003980: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
//tmp = (float)ttl1_pwm.period_ticks * (float)ttl1_pwm.pwm/10000.0F;
|
|
//ttl1_pwm.duty_ticks = (unsigned int) tmp;
|
|
|
|
DBW_Pwm_Set_Duty(var.motor_pwm, (pwm_t*) &ttl1_pwm);
|
|
8003982: 4b3d ldr r3, [pc, #244] @ (8003a78 <DBW_Pwm_Init+0x150>)
|
|
8003984: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8003986: b21b sxth r3, r3
|
|
8003988: 001a movs r2, r3
|
|
800398a: 4b37 ldr r3, [pc, #220] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
800398c: 0019 movs r1, r3
|
|
800398e: 0010 movs r0, r2
|
|
8003990: f000 f9c6 bl 8003d20 <DBW_Pwm_Set_Duty>
|
|
|
|
if (var.motor_pwm < 0)
|
|
8003994: 4b38 ldr r3, [pc, #224] @ (8003a78 <DBW_Pwm_Init+0x150>)
|
|
8003996: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
8003998: b21b sxth r3, r3
|
|
800399a: 2b00 cmp r3, #0
|
|
800399c: da03 bge.n 80039a6 <DBW_Pwm_Init+0x7e>
|
|
ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE;
|
|
800399e: 4b32 ldr r3, [pc, #200] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039a0: 2202 movs r2, #2
|
|
80039a2: 705a strb r2, [r3, #1]
|
|
80039a4: e00b b.n 80039be <DBW_Pwm_Init+0x96>
|
|
else if (var.motor_pwm > 0)
|
|
80039a6: 4b34 ldr r3, [pc, #208] @ (8003a78 <DBW_Pwm_Init+0x150>)
|
|
80039a8: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
80039aa: b21b sxth r3, r3
|
|
80039ac: 2b00 cmp r3, #0
|
|
80039ae: dd03 ble.n 80039b8 <DBW_Pwm_Init+0x90>
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE;
|
|
80039b0: 4b2d ldr r3, [pc, #180] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039b2: 2200 movs r2, #0
|
|
80039b4: 705a strb r2, [r3, #1]
|
|
80039b6: e002 b.n 80039be <DBW_Pwm_Init+0x96>
|
|
else
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE;
|
|
80039b8: 4b2b ldr r3, [pc, #172] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039ba: 2200 movs r2, #0
|
|
80039bc: 705a strb r2, [r3, #1]
|
|
|
|
ttl1_pwm.status = PWM_STATUS_IDLE;
|
|
80039be: 4b2a ldr r3, [pc, #168] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039c0: 2201 movs r2, #1
|
|
80039c2: 701a strb r2, [r3, #0]
|
|
|
|
DBW_Stop();
|
|
80039c4: f000 fb3c bl 8004040 <DBW_Stop>
|
|
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
80039c8: 4b27 ldr r3, [pc, #156] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039ca: 891b ldrh r3, [r3, #8]
|
|
80039cc: b29b uxth r3, r3
|
|
80039ce: 3310 adds r3, #16
|
|
80039d0: 2201 movs r2, #1
|
|
80039d2: 409a lsls r2, r3
|
|
80039d4: 4b24 ldr r3, [pc, #144] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039d6: 685b ldr r3, [r3, #4]
|
|
80039d8: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
80039da: 4b23 ldr r3, [pc, #140] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039dc: 8a1b ldrh r3, [r3, #16]
|
|
80039de: b29b uxth r3, r3
|
|
80039e0: 3310 adds r3, #16
|
|
80039e2: 2201 movs r2, #1
|
|
80039e4: 409a lsls r2, r3
|
|
80039e6: 4b20 ldr r3, [pc, #128] @ (8003a68 <DBW_Pwm_Init+0x140>)
|
|
80039e8: 68db ldr r3, [r3, #12]
|
|
80039ea: 619a str r2, [r3, #24]
|
|
|
|
// configure TIM2 to 1uS / tick timer
|
|
// setup CCR interrupt happen after sturtup delay is over
|
|
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
|
|
80039ec: 4b23 ldr r3, [pc, #140] @ (8003a7c <DBW_Pwm_Init+0x154>)
|
|
80039ee: 69da ldr r2, [r3, #28]
|
|
80039f0: 4b22 ldr r3, [pc, #136] @ (8003a7c <DBW_Pwm_Init+0x154>)
|
|
80039f2: 2101 movs r1, #1
|
|
80039f4: 430a orrs r2, r1
|
|
80039f6: 61da str r2, [r3, #28]
|
|
TIM2->CNT = 0xFFFFFFFE;
|
|
80039f8: 2380 movs r3, #128 @ 0x80
|
|
80039fa: 05db lsls r3, r3, #23
|
|
80039fc: 2202 movs r2, #2
|
|
80039fe: 4252 negs r2, r2
|
|
8003a00: 625a str r2, [r3, #36] @ 0x24
|
|
TIM2->PSC = 48; //2400; // (1uS precision)
|
|
8003a02: 2380 movs r3, #128 @ 0x80
|
|
8003a04: 05db lsls r3, r3, #23
|
|
8003a06: 2230 movs r2, #48 @ 0x30
|
|
8003a08: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
TIM2->ARR = 0xFFFFFFFF;
|
|
8003a0a: 2380 movs r3, #128 @ 0x80
|
|
8003a0c: 05db lsls r3, r3, #23
|
|
8003a0e: 2201 movs r2, #1
|
|
8003a10: 4252 negs r2, r2
|
|
8003a12: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
TIM2->CR1 = (TIM_CR1_URS | TIM_CR1_CEN);
|
|
8003a14: 2380 movs r3, #128 @ 0x80
|
|
8003a16: 05db lsls r3, r3, #23
|
|
8003a18: 2205 movs r2, #5
|
|
8003a1a: 601a str r2, [r3, #0]
|
|
TIM2->CCER = 0x0000;
|
|
8003a1c: 2380 movs r3, #128 @ 0x80
|
|
8003a1e: 05db lsls r3, r3, #23
|
|
8003a20: 2200 movs r2, #0
|
|
8003a22: 621a str r2, [r3, #32]
|
|
TIM2->CCMR1 = 0x0000;
|
|
8003a24: 2380 movs r3, #128 @ 0x80
|
|
8003a26: 05db lsls r3, r3, #23
|
|
8003a28: 2200 movs r2, #0
|
|
8003a2a: 619a str r2, [r3, #24]
|
|
|
|
TIM2->CCR1 = (unsigned int) 20000; // startup delay
|
|
8003a2c: 2380 movs r3, #128 @ 0x80
|
|
8003a2e: 05db lsls r3, r3, #23
|
|
8003a30: 4a13 ldr r2, [pc, #76] @ (8003a80 <DBW_Pwm_Init+0x158>)
|
|
8003a32: 635a str r2, [r3, #52] @ 0x34
|
|
TIM2->CCR2 = 0;
|
|
8003a34: 2380 movs r3, #128 @ 0x80
|
|
8003a36: 05db lsls r3, r3, #23
|
|
8003a38: 2200 movs r2, #0
|
|
8003a3a: 639a str r2, [r3, #56] @ 0x38
|
|
TIM2->SR &= ~TIM_SR_CC1IF;
|
|
8003a3c: 2380 movs r3, #128 @ 0x80
|
|
8003a3e: 05db lsls r3, r3, #23
|
|
8003a40: 691a ldr r2, [r3, #16]
|
|
8003a42: 2380 movs r3, #128 @ 0x80
|
|
8003a44: 05db lsls r3, r3, #23
|
|
8003a46: 2102 movs r1, #2
|
|
8003a48: 438a bics r2, r1
|
|
8003a4a: 611a str r2, [r3, #16]
|
|
TIM2->DIER |= TIM_DIER_CC1IE;
|
|
8003a4c: 2380 movs r3, #128 @ 0x80
|
|
8003a4e: 05db lsls r3, r3, #23
|
|
8003a50: 68da ldr r2, [r3, #12]
|
|
8003a52: 2380 movs r3, #128 @ 0x80
|
|
8003a54: 05db lsls r3, r3, #23
|
|
8003a56: 2102 movs r1, #2
|
|
8003a58: 430a orrs r2, r1
|
|
8003a5a: 60da str r2, [r3, #12]
|
|
NVIC_EnableIRQ(TIM2_IRQn);
|
|
8003a5c: 200f movs r0, #15
|
|
8003a5e: f7ff fab1 bl 8002fc4 <__NVIC_EnableIRQ>
|
|
|
|
}
|
|
8003a62: 46c0 nop @ (mov r8, r8)
|
|
8003a64: 46bd mov sp, r7
|
|
8003a66: bd80 pop {r7, pc}
|
|
8003a68: 200009d4 .word 0x200009d4
|
|
8003a6c: 48000400 .word 0x48000400
|
|
8003a70: 200009cc .word 0x200009cc
|
|
8003a74: 000f4240 .word 0x000f4240
|
|
8003a78: 20000998 .word 0x20000998
|
|
8003a7c: 40021000 .word 0x40021000
|
|
8003a80: 00004e20 .word 0x00004e20
|
|
|
|
08003a84 <TIM2_IRQHandler>:
|
|
|
|
void TIM2_IRQHandler(void) {
|
|
8003a84: b580 push {r7, lr}
|
|
8003a86: af00 add r7, sp, #0
|
|
if (TIM2->SR & TIM_SR_CC1IF) {
|
|
8003a88: 2380 movs r3, #128 @ 0x80
|
|
8003a8a: 05db lsls r3, r3, #23
|
|
8003a8c: 691b ldr r3, [r3, #16]
|
|
8003a8e: 2202 movs r2, #2
|
|
8003a90: 4013 ands r3, r2
|
|
8003a92: d100 bne.n 8003a96 <TIM2_IRQHandler+0x12>
|
|
8003a94: e12f b.n 8003cf6 <TIM2_IRQHandler+0x272>
|
|
// capture compare intrrupt
|
|
TIM2->SR &= ~TIM_SR_CC1IF;
|
|
8003a96: 2380 movs r3, #128 @ 0x80
|
|
8003a98: 05db lsls r3, r3, #23
|
|
8003a9a: 691a ldr r2, [r3, #16]
|
|
8003a9c: 2380 movs r3, #128 @ 0x80
|
|
8003a9e: 05db lsls r3, r3, #23
|
|
8003aa0: 2102 movs r1, #2
|
|
8003aa2: 438a bics r2, r1
|
|
8003aa4: 611a str r2, [r3, #16]
|
|
if (ttl1_pwm.status == PWM_STATUS_DEFAULT) {
|
|
8003aa6: 4b9c ldr r3, [pc, #624] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003aa8: 781b ldrb r3, [r3, #0]
|
|
8003aaa: b2db uxtb r3, r3
|
|
8003aac: 2b00 cmp r3, #0
|
|
8003aae: d102 bne.n 8003ab6 <TIM2_IRQHandler+0x32>
|
|
// here ends startup delay
|
|
// enable drive here
|
|
ttl1_pwm.status = PWM_STATUS_STARTED;
|
|
8003ab0: 4b99 ldr r3, [pc, #612] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ab2: 2202 movs r2, #2
|
|
8003ab4: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
//Set duty
|
|
if (ttl1_pwm.pwm > 0) {
|
|
8003ab6: 4b98 ldr r3, [pc, #608] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ab8: 69db ldr r3, [r3, #28]
|
|
8003aba: 2b00 cmp r3, #0
|
|
8003abc: dc00 bgt.n 8003ac0 <TIM2_IRQHandler+0x3c>
|
|
8003abe: e072 b.n 8003ba6 <TIM2_IRQHandler+0x122>
|
|
// pwm > 0
|
|
if ((ttl1_pwm.pwm > 0) && (ttl1_pwm.pwm_t < 0)) {
|
|
8003ac0: 4b95 ldr r3, [pc, #596] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ac2: 69db ldr r3, [r3, #28]
|
|
8003ac4: 2b00 cmp r3, #0
|
|
8003ac6: dd27 ble.n 8003b18 <TIM2_IRQHandler+0x94>
|
|
8003ac8: 4b93 ldr r3, [pc, #588] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003aca: 6a1b ldr r3, [r3, #32]
|
|
8003acc: 2b00 cmp r3, #0
|
|
8003ace: da23 bge.n 8003b18 <TIM2_IRQHandler+0x94>
|
|
// if changeing PWM polarity insert dead time
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE;
|
|
8003ad0: 4b91 ldr r3, [pc, #580] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ad2: 2200 movs r2, #0
|
|
8003ad4: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003ad6: 4b90 ldr r3, [pc, #576] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ad8: 891b ldrh r3, [r3, #8]
|
|
8003ada: b29b uxth r3, r3
|
|
8003adc: 3310 adds r3, #16
|
|
8003ade: 2201 movs r2, #1
|
|
8003ae0: 409a lsls r2, r3
|
|
8003ae2: 4b8d ldr r3, [pc, #564] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ae4: 685b ldr r3, [r3, #4]
|
|
8003ae6: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003ae8: 4b8b ldr r3, [pc, #556] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003aea: 8a1b ldrh r3, [r3, #16]
|
|
8003aec: b29b uxth r3, r3
|
|
8003aee: 3310 adds r3, #16
|
|
8003af0: 2201 movs r2, #1
|
|
8003af2: 409a lsls r2, r3
|
|
8003af4: 4b88 ldr r3, [pc, #544] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003af6: 68db ldr r3, [r3, #12]
|
|
8003af8: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime;
|
|
8003afa: 2380 movs r3, #128 @ 0x80
|
|
8003afc: 05db lsls r3, r3, #23
|
|
8003afe: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8003b00: 4b86 ldr r3, [pc, #536] @ (8003d1c <TIM2_IRQHandler+0x298>)
|
|
8003b02: 6819 ldr r1, [r3, #0]
|
|
8003b04: 23cd movs r3, #205 @ 0xcd
|
|
8003b06: 009b lsls r3, r3, #2
|
|
8003b08: 5acb ldrh r3, [r1, r3]
|
|
8003b0a: b29b uxth r3, r3
|
|
8003b0c: 0019 movs r1, r3
|
|
8003b0e: 2380 movs r3, #128 @ 0x80
|
|
8003b10: 05db lsls r3, r3, #23
|
|
8003b12: 1852 adds r2, r2, r1
|
|
8003b14: 635a str r2, [r3, #52] @ 0x34
|
|
8003b16: e0ea b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
} else if (ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) {
|
|
8003b18: 4b7f ldr r3, [pc, #508] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b1a: 785b ldrb r3, [r3, #1]
|
|
8003b1c: b2db uxtb r3, r3
|
|
8003b1e: 2b00 cmp r3, #0
|
|
8003b20: d11f bne.n 8003b62 <TIM2_IRQHandler+0xde>
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_ACTIVE;
|
|
8003b22: 4b7d ldr r3, [pc, #500] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b24: 2201 movs r2, #1
|
|
8003b26: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << ttl1_pwm.pos_pin);
|
|
8003b28: 4b7b ldr r3, [pc, #492] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b2a: 891b ldrh r3, [r3, #8]
|
|
8003b2c: b29b uxth r3, r3
|
|
8003b2e: 001a movs r2, r3
|
|
8003b30: 2301 movs r3, #1
|
|
8003b32: 4093 lsls r3, r2
|
|
8003b34: 001a movs r2, r3
|
|
8003b36: 4b78 ldr r3, [pc, #480] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b38: 685b ldr r3, [r3, #4]
|
|
8003b3a: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003b3c: 4b76 ldr r3, [pc, #472] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b3e: 8a1b ldrh r3, [r3, #16]
|
|
8003b40: b29b uxth r3, r3
|
|
8003b42: 3310 adds r3, #16
|
|
8003b44: 2201 movs r2, #1
|
|
8003b46: 409a lsls r2, r3
|
|
8003b48: 4b73 ldr r3, [pc, #460] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b4a: 68db ldr r3, [r3, #12]
|
|
8003b4c: 619a str r2, [r3, #24]
|
|
|
|
TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks;
|
|
8003b4e: 2380 movs r3, #128 @ 0x80
|
|
8003b50: 05db lsls r3, r3, #23
|
|
8003b52: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
8003b54: 4b70 ldr r3, [pc, #448] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b56: 699a ldr r2, [r3, #24]
|
|
8003b58: 2380 movs r3, #128 @ 0x80
|
|
8003b5a: 05db lsls r3, r3, #23
|
|
8003b5c: 188a adds r2, r1, r2
|
|
8003b5e: 635a str r2, [r3, #52] @ 0x34
|
|
8003b60: e0c5 b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
} else {
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE;
|
|
8003b62: 4b6d ldr r3, [pc, #436] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b64: 2200 movs r2, #0
|
|
8003b66: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003b68: 4b6b ldr r3, [pc, #428] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b6a: 891b ldrh r3, [r3, #8]
|
|
8003b6c: b29b uxth r3, r3
|
|
8003b6e: 3310 adds r3, #16
|
|
8003b70: 2201 movs r2, #1
|
|
8003b72: 409a lsls r2, r3
|
|
8003b74: 4b68 ldr r3, [pc, #416] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b76: 685b ldr r3, [r3, #4]
|
|
8003b78: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003b7a: 4b67 ldr r3, [pc, #412] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b7c: 8a1b ldrh r3, [r3, #16]
|
|
8003b7e: b29b uxth r3, r3
|
|
8003b80: 3310 adds r3, #16
|
|
8003b82: 2201 movs r2, #1
|
|
8003b84: 409a lsls r2, r3
|
|
8003b86: 4b64 ldr r3, [pc, #400] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b88: 68db ldr r3, [r3, #12]
|
|
8003b8a: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003b8c: 2380 movs r3, #128 @ 0x80
|
|
8003b8e: 05db lsls r3, r3, #23
|
|
8003b90: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
+ (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks);
|
|
8003b92: 4b61 ldr r3, [pc, #388] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b94: 695a ldr r2, [r3, #20]
|
|
8003b96: 4b60 ldr r3, [pc, #384] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003b98: 699b ldr r3, [r3, #24]
|
|
8003b9a: 1ad2 subs r2, r2, r3
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003b9c: 2380 movs r3, #128 @ 0x80
|
|
8003b9e: 05db lsls r3, r3, #23
|
|
+ (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks);
|
|
8003ba0: 188a adds r2, r1, r2
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003ba2: 635a str r2, [r3, #52] @ 0x34
|
|
8003ba4: e0a3 b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
|
|
}
|
|
} else if (ttl1_pwm.pwm < 0) {
|
|
8003ba6: 4b5c ldr r3, [pc, #368] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ba8: 69db ldr r3, [r3, #28]
|
|
8003baa: 2b00 cmp r3, #0
|
|
8003bac: db00 blt.n 8003bb0 <TIM2_IRQHandler+0x12c>
|
|
8003bae: e072 b.n 8003c96 <TIM2_IRQHandler+0x212>
|
|
//pwm < 0
|
|
//if((ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) && (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE))
|
|
if ((ttl1_pwm.pwm < 0) && (ttl1_pwm.pwm_t > 0)) {
|
|
8003bb0: 4b59 ldr r3, [pc, #356] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bb2: 69db ldr r3, [r3, #28]
|
|
8003bb4: 2b00 cmp r3, #0
|
|
8003bb6: da27 bge.n 8003c08 <TIM2_IRQHandler+0x184>
|
|
8003bb8: 4b57 ldr r3, [pc, #348] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bba: 6a1b ldr r3, [r3, #32]
|
|
8003bbc: 2b00 cmp r3, #0
|
|
8003bbe: dd23 ble.n 8003c08 <TIM2_IRQHandler+0x184>
|
|
// if changeing PWM polarity insert dead time
|
|
ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE;
|
|
8003bc0: 4b55 ldr r3, [pc, #340] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bc2: 2202 movs r2, #2
|
|
8003bc4: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003bc6: 4b54 ldr r3, [pc, #336] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bc8: 891b ldrh r3, [r3, #8]
|
|
8003bca: b29b uxth r3, r3
|
|
8003bcc: 3310 adds r3, #16
|
|
8003bce: 2201 movs r2, #1
|
|
8003bd0: 409a lsls r2, r3
|
|
8003bd2: 4b51 ldr r3, [pc, #324] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bd4: 685b ldr r3, [r3, #4]
|
|
8003bd6: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003bd8: 4b4f ldr r3, [pc, #316] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003bda: 8a1b ldrh r3, [r3, #16]
|
|
8003bdc: b29b uxth r3, r3
|
|
8003bde: 3310 adds r3, #16
|
|
8003be0: 2201 movs r2, #1
|
|
8003be2: 409a lsls r2, r3
|
|
8003be4: 4b4c ldr r3, [pc, #304] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003be6: 68db ldr r3, [r3, #12]
|
|
8003be8: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime;
|
|
8003bea: 2380 movs r3, #128 @ 0x80
|
|
8003bec: 05db lsls r3, r3, #23
|
|
8003bee: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8003bf0: 4b4a ldr r3, [pc, #296] @ (8003d1c <TIM2_IRQHandler+0x298>)
|
|
8003bf2: 6819 ldr r1, [r3, #0]
|
|
8003bf4: 23cd movs r3, #205 @ 0xcd
|
|
8003bf6: 009b lsls r3, r3, #2
|
|
8003bf8: 5acb ldrh r3, [r1, r3]
|
|
8003bfa: b29b uxth r3, r3
|
|
8003bfc: 0019 movs r1, r3
|
|
8003bfe: 2380 movs r3, #128 @ 0x80
|
|
8003c00: 05db lsls r3, r3, #23
|
|
8003c02: 1852 adds r2, r2, r1
|
|
8003c04: 635a str r2, [r3, #52] @ 0x34
|
|
8003c06: e072 b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
} else if (ttl1_pwm.state == PWM_STATE_NEGATIVE_INACTIVE) {
|
|
8003c08: 4b43 ldr r3, [pc, #268] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c0a: 785b ldrb r3, [r3, #1]
|
|
8003c0c: b2db uxtb r3, r3
|
|
8003c0e: 2b02 cmp r3, #2
|
|
8003c10: d11f bne.n 8003c52 <TIM2_IRQHandler+0x1ce>
|
|
ttl1_pwm.state = PWM_STATE_NEGATIVE_ACTIVE;
|
|
8003c12: 4b41 ldr r3, [pc, #260] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c14: 2203 movs r2, #3
|
|
8003c16: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003c18: 4b3f ldr r3, [pc, #252] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c1a: 891b ldrh r3, [r3, #8]
|
|
8003c1c: b29b uxth r3, r3
|
|
8003c1e: 3310 adds r3, #16
|
|
8003c20: 2201 movs r2, #1
|
|
8003c22: 409a lsls r2, r3
|
|
8003c24: 4b3c ldr r3, [pc, #240] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c26: 685b ldr r3, [r3, #4]
|
|
8003c28: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << ttl1_pwm.neg_pin);
|
|
8003c2a: 4b3b ldr r3, [pc, #236] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c2c: 8a1b ldrh r3, [r3, #16]
|
|
8003c2e: b29b uxth r3, r3
|
|
8003c30: 001a movs r2, r3
|
|
8003c32: 2301 movs r3, #1
|
|
8003c34: 4093 lsls r3, r2
|
|
8003c36: 001a movs r2, r3
|
|
8003c38: 4b37 ldr r3, [pc, #220] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c3a: 68db ldr r3, [r3, #12]
|
|
8003c3c: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks;
|
|
8003c3e: 2380 movs r3, #128 @ 0x80
|
|
8003c40: 05db lsls r3, r3, #23
|
|
8003c42: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
8003c44: 4b34 ldr r3, [pc, #208] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c46: 699a ldr r2, [r3, #24]
|
|
8003c48: 2380 movs r3, #128 @ 0x80
|
|
8003c4a: 05db lsls r3, r3, #23
|
|
8003c4c: 188a adds r2, r1, r2
|
|
8003c4e: 635a str r2, [r3, #52] @ 0x34
|
|
8003c50: e04d b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
} else {
|
|
ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE;
|
|
8003c52: 4b31 ldr r3, [pc, #196] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c54: 2202 movs r2, #2
|
|
8003c56: 705a strb r2, [r3, #1]
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003c58: 4b2f ldr r3, [pc, #188] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c5a: 891b ldrh r3, [r3, #8]
|
|
8003c5c: b29b uxth r3, r3
|
|
8003c5e: 3310 adds r3, #16
|
|
8003c60: 2201 movs r2, #1
|
|
8003c62: 409a lsls r2, r3
|
|
8003c64: 4b2c ldr r3, [pc, #176] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c66: 685b ldr r3, [r3, #4]
|
|
8003c68: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003c6a: 4b2b ldr r3, [pc, #172] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c6c: 8a1b ldrh r3, [r3, #16]
|
|
8003c6e: b29b uxth r3, r3
|
|
8003c70: 3310 adds r3, #16
|
|
8003c72: 2201 movs r2, #1
|
|
8003c74: 409a lsls r2, r3
|
|
8003c76: 4b28 ldr r3, [pc, #160] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c78: 68db ldr r3, [r3, #12]
|
|
8003c7a: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003c7c: 2380 movs r3, #128 @ 0x80
|
|
8003c7e: 05db lsls r3, r3, #23
|
|
8003c80: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
+ (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks);
|
|
8003c82: 4b25 ldr r3, [pc, #148] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c84: 695a ldr r2, [r3, #20]
|
|
8003c86: 4b24 ldr r3, [pc, #144] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c88: 699b ldr r3, [r3, #24]
|
|
8003c8a: 1ad2 subs r2, r2, r3
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003c8c: 2380 movs r3, #128 @ 0x80
|
|
8003c8e: 05db lsls r3, r3, #23
|
|
+ (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks);
|
|
8003c90: 188a adds r2, r1, r2
|
|
TIM2->CCR1 = TIM2->CNT
|
|
8003c92: 635a str r2, [r3, #52] @ 0x34
|
|
8003c94: e02b b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
}
|
|
} else {
|
|
// if pwm == 0
|
|
ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin));
|
|
8003c96: 4b20 ldr r3, [pc, #128] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003c98: 891b ldrh r3, [r3, #8]
|
|
8003c9a: b29b uxth r3, r3
|
|
8003c9c: 3310 adds r3, #16
|
|
8003c9e: 2201 movs r2, #1
|
|
8003ca0: 409a lsls r2, r3
|
|
8003ca2: 4b1d ldr r3, [pc, #116] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ca4: 685b ldr r3, [r3, #4]
|
|
8003ca6: 619a str r2, [r3, #24]
|
|
ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin));
|
|
8003ca8: 4b1b ldr r3, [pc, #108] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003caa: 8a1b ldrh r3, [r3, #16]
|
|
8003cac: b29b uxth r3, r3
|
|
8003cae: 3310 adds r3, #16
|
|
8003cb0: 2201 movs r2, #1
|
|
8003cb2: 409a lsls r2, r3
|
|
8003cb4: 4b18 ldr r3, [pc, #96] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cb6: 68db ldr r3, [r3, #12]
|
|
8003cb8: 619a str r2, [r3, #24]
|
|
TIM2->CCR1 = TIM2->CNT + ttl1_pwm.period_ticks;
|
|
8003cba: 2380 movs r3, #128 @ 0x80
|
|
8003cbc: 05db lsls r3, r3, #23
|
|
8003cbe: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
8003cc0: 4b15 ldr r3, [pc, #84] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cc2: 695a ldr r2, [r3, #20]
|
|
8003cc4: 2380 movs r3, #128 @ 0x80
|
|
8003cc6: 05db lsls r3, r3, #23
|
|
8003cc8: 188a adds r2, r1, r2
|
|
8003cca: 635a str r2, [r3, #52] @ 0x34
|
|
if (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE
|
|
8003ccc: 4b12 ldr r3, [pc, #72] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cce: 785b ldrb r3, [r3, #1]
|
|
8003cd0: b2db uxtb r3, r3
|
|
8003cd2: 2b01 cmp r3, #1
|
|
8003cd4: d004 beq.n 8003ce0 <TIM2_IRQHandler+0x25c>
|
|
|| ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) {
|
|
8003cd6: 4b10 ldr r3, [pc, #64] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cd8: 785b ldrb r3, [r3, #1]
|
|
8003cda: b2db uxtb r3, r3
|
|
8003cdc: 2b00 cmp r3, #0
|
|
8003cde: d103 bne.n 8003ce8 <TIM2_IRQHandler+0x264>
|
|
ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE;
|
|
8003ce0: 4b0d ldr r3, [pc, #52] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003ce2: 2200 movs r2, #0
|
|
8003ce4: 705a strb r2, [r3, #1]
|
|
8003ce6: e002 b.n 8003cee <TIM2_IRQHandler+0x26a>
|
|
} else {
|
|
ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE;
|
|
8003ce8: 4b0b ldr r3, [pc, #44] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cea: 2202 movs r2, #2
|
|
8003cec: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
}
|
|
// store new pwm value as old pwm value for the nex iteration
|
|
ttl1_pwm.pwm_t = ttl1_pwm.pwm;
|
|
8003cee: 4b0a ldr r3, [pc, #40] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cf0: 69da ldr r2, [r3, #28]
|
|
8003cf2: 4b09 ldr r3, [pc, #36] @ (8003d18 <TIM2_IRQHandler+0x294>)
|
|
8003cf4: 621a str r2, [r3, #32]
|
|
}
|
|
if (TIM2->SR & TIM_SR_UIF) {
|
|
8003cf6: 2380 movs r3, #128 @ 0x80
|
|
8003cf8: 05db lsls r3, r3, #23
|
|
8003cfa: 691b ldr r3, [r3, #16]
|
|
8003cfc: 2201 movs r2, #1
|
|
8003cfe: 4013 ands r3, r2
|
|
8003d00: d007 beq.n 8003d12 <TIM2_IRQHandler+0x28e>
|
|
//TIM2 overflow interrupt jaust clear update interrupt flag
|
|
TIM2->SR &= ~TIM_SR_UIF;
|
|
8003d02: 2380 movs r3, #128 @ 0x80
|
|
8003d04: 05db lsls r3, r3, #23
|
|
8003d06: 691a ldr r2, [r3, #16]
|
|
8003d08: 2380 movs r3, #128 @ 0x80
|
|
8003d0a: 05db lsls r3, r3, #23
|
|
8003d0c: 2101 movs r1, #1
|
|
8003d0e: 438a bics r2, r1
|
|
8003d10: 611a str r2, [r3, #16]
|
|
|
|
}
|
|
|
|
}
|
|
8003d12: 46c0 nop @ (mov r8, r8)
|
|
8003d14: 46bd mov sp, r7
|
|
8003d16: bd80 pop {r7, pc}
|
|
8003d18: 200009d4 .word 0x200009d4
|
|
8003d1c: 200009cc .word 0x200009cc
|
|
|
|
08003d20 <DBW_Pwm_Set_Duty>:
|
|
void DBW_Pwm_Set_Duty(signed int duty, pwm_t *ttl) {
|
|
8003d20: b590 push {r4, r7, lr}
|
|
8003d22: b085 sub sp, #20
|
|
8003d24: af00 add r7, sp, #0
|
|
8003d26: 6078 str r0, [r7, #4]
|
|
8003d28: 6039 str r1, [r7, #0]
|
|
float tmp;
|
|
unsigned int period_ticks;
|
|
|
|
//check limmits
|
|
if (duty > 10000)
|
|
8003d2a: 687b ldr r3, [r7, #4]
|
|
8003d2c: 4a61 ldr r2, [pc, #388] @ (8003eb4 <DBW_Pwm_Set_Duty+0x194>)
|
|
8003d2e: 4293 cmp r3, r2
|
|
8003d30: dd02 ble.n 8003d38 <DBW_Pwm_Set_Duty+0x18>
|
|
duty = 10000;
|
|
8003d32: 4b60 ldr r3, [pc, #384] @ (8003eb4 <DBW_Pwm_Set_Duty+0x194>)
|
|
8003d34: 607b str r3, [r7, #4]
|
|
8003d36: e005 b.n 8003d44 <DBW_Pwm_Set_Duty+0x24>
|
|
else if (duty < -10000)
|
|
8003d38: 687b ldr r3, [r7, #4]
|
|
8003d3a: 4a5f ldr r2, [pc, #380] @ (8003eb8 <DBW_Pwm_Set_Duty+0x198>)
|
|
8003d3c: 4293 cmp r3, r2
|
|
8003d3e: da01 bge.n 8003d44 <DBW_Pwm_Set_Duty+0x24>
|
|
duty = -10000;
|
|
8003d40: 4b5d ldr r3, [pc, #372] @ (8003eb8 <DBW_Pwm_Set_Duty+0x198>)
|
|
8003d42: 607b str r3, [r7, #4]
|
|
|
|
//calculate period - needed to change frequency on-the-fly
|
|
period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq;
|
|
8003d44: 4b5d ldr r3, [pc, #372] @ (8003ebc <DBW_Pwm_Set_Duty+0x19c>)
|
|
8003d46: 681b ldr r3, [r3, #0]
|
|
8003d48: 227c movs r2, #124 @ 0x7c
|
|
8003d4a: 5a9b ldrh r3, [r3, r2]
|
|
8003d4c: b29b uxth r3, r3
|
|
8003d4e: 0019 movs r1, r3
|
|
8003d50: 485b ldr r0, [pc, #364] @ (8003ec0 <DBW_Pwm_Set_Duty+0x1a0>)
|
|
8003d52: f7fc f9d9 bl 8000108 <__udivsi3>
|
|
8003d56: 0003 movs r3, r0
|
|
8003d58: 60bb str r3, [r7, #8]
|
|
if (duty > 0)
|
|
8003d5a: 687b ldr r3, [r7, #4]
|
|
8003d5c: 2b00 cmp r3, #0
|
|
8003d5e: dd13 ble.n 8003d88 <DBW_Pwm_Set_Duty+0x68>
|
|
tmp = (float) period_ticks * (float) duty / 10000.0F;
|
|
8003d60: 68b8 ldr r0, [r7, #8]
|
|
8003d62: f7fd fb97 bl 8001494 <__aeabi_ui2f>
|
|
8003d66: 1c04 adds r4, r0, #0
|
|
8003d68: 6878 ldr r0, [r7, #4]
|
|
8003d6a: f7fd fb43 bl 80013f4 <__aeabi_i2f>
|
|
8003d6e: 1c03 adds r3, r0, #0
|
|
8003d70: 1c19 adds r1, r3, #0
|
|
8003d72: 1c20 adds r0, r4, #0
|
|
8003d74: f7fc ff8a bl 8000c8c <__aeabi_fmul>
|
|
8003d78: 1c03 adds r3, r0, #0
|
|
8003d7a: 4952 ldr r1, [pc, #328] @ (8003ec4 <DBW_Pwm_Set_Duty+0x1a4>)
|
|
8003d7c: 1c18 adds r0, r3, #0
|
|
8003d7e: f7fc fdb7 bl 80008f0 <__aeabi_fdiv>
|
|
8003d82: 1c03 adds r3, r0, #0
|
|
8003d84: 60fb str r3, [r7, #12]
|
|
8003d86: e01b b.n 8003dc0 <DBW_Pwm_Set_Duty+0xa0>
|
|
else if (duty < 0)
|
|
8003d88: 687b ldr r3, [r7, #4]
|
|
8003d8a: 2b00 cmp r3, #0
|
|
8003d8c: da16 bge.n 8003dbc <DBW_Pwm_Set_Duty+0x9c>
|
|
tmp = (float) period_ticks * (0 - ((float) duty)) / 10000.0F;
|
|
8003d8e: 68b8 ldr r0, [r7, #8]
|
|
8003d90: f7fd fb80 bl 8001494 <__aeabi_ui2f>
|
|
8003d94: 1c04 adds r4, r0, #0
|
|
8003d96: 6878 ldr r0, [r7, #4]
|
|
8003d98: f7fd fb2c bl 80013f4 <__aeabi_i2f>
|
|
8003d9c: 1c02 adds r2, r0, #0
|
|
8003d9e: 2380 movs r3, #128 @ 0x80
|
|
8003da0: 061b lsls r3, r3, #24
|
|
8003da2: 4053 eors r3, r2
|
|
8003da4: 1c19 adds r1, r3, #0
|
|
8003da6: 1c20 adds r0, r4, #0
|
|
8003da8: f7fc ff70 bl 8000c8c <__aeabi_fmul>
|
|
8003dac: 1c03 adds r3, r0, #0
|
|
8003dae: 4945 ldr r1, [pc, #276] @ (8003ec4 <DBW_Pwm_Set_Duty+0x1a4>)
|
|
8003db0: 1c18 adds r0, r3, #0
|
|
8003db2: f7fc fd9d bl 80008f0 <__aeabi_fdiv>
|
|
8003db6: 1c03 adds r3, r0, #0
|
|
8003db8: 60fb str r3, [r7, #12]
|
|
8003dba: e001 b.n 8003dc0 <DBW_Pwm_Set_Duty+0xa0>
|
|
else
|
|
tmp = 20;
|
|
8003dbc: 4b42 ldr r3, [pc, #264] @ (8003ec8 <DBW_Pwm_Set_Duty+0x1a8>)
|
|
8003dbe: 60fb str r3, [r7, #12]
|
|
|
|
// check minimum duty period;
|
|
|
|
// do not allow duty cylce <20uS
|
|
if ((period_ticks - (unsigned int) tmp) < 20) {
|
|
8003dc0: 68f8 ldr r0, [r7, #12]
|
|
8003dc2: f7fc fb51 bl 8000468 <__aeabi_f2uiz>
|
|
8003dc6: 0002 movs r2, r0
|
|
8003dc8: 68bb ldr r3, [r7, #8]
|
|
8003dca: 1a9b subs r3, r3, r2
|
|
8003dcc: 2b13 cmp r3, #19
|
|
8003dce: d84f bhi.n 8003e70 <DBW_Pwm_Set_Duty+0x150>
|
|
tmp = period_ticks - 20;
|
|
8003dd0: 68bb ldr r3, [r7, #8]
|
|
8003dd2: 3b14 subs r3, #20
|
|
8003dd4: 0018 movs r0, r3
|
|
8003dd6: f7fd fb5d bl 8001494 <__aeabi_ui2f>
|
|
8003dda: 1c03 adds r3, r0, #0
|
|
8003ddc: 60fb str r3, [r7, #12]
|
|
if (duty > 0)
|
|
8003dde: 687b ldr r3, [r7, #4]
|
|
8003de0: 2b00 cmp r3, #0
|
|
8003de2: dd1e ble.n 8003e22 <DBW_Pwm_Set_Duty+0x102>
|
|
duty = (signed int) tmp * 10000.0F / ttl->period_ticks;
|
|
8003de4: 68f8 ldr r0, [r7, #12]
|
|
8003de6: f7fd fae5 bl 80013b4 <__aeabi_f2iz>
|
|
8003dea: 0003 movs r3, r0
|
|
8003dec: 0018 movs r0, r3
|
|
8003dee: f7fd fb01 bl 80013f4 <__aeabi_i2f>
|
|
8003df2: 1c03 adds r3, r0, #0
|
|
8003df4: 4933 ldr r1, [pc, #204] @ (8003ec4 <DBW_Pwm_Set_Duty+0x1a4>)
|
|
8003df6: 1c18 adds r0, r3, #0
|
|
8003df8: f7fc ff48 bl 8000c8c <__aeabi_fmul>
|
|
8003dfc: 1c03 adds r3, r0, #0
|
|
8003dfe: 1c1c adds r4, r3, #0
|
|
8003e00: 683b ldr r3, [r7, #0]
|
|
8003e02: 695b ldr r3, [r3, #20]
|
|
8003e04: 0018 movs r0, r3
|
|
8003e06: f7fd fb45 bl 8001494 <__aeabi_ui2f>
|
|
8003e0a: 1c03 adds r3, r0, #0
|
|
8003e0c: 1c19 adds r1, r3, #0
|
|
8003e0e: 1c20 adds r0, r4, #0
|
|
8003e10: f7fc fd6e bl 80008f0 <__aeabi_fdiv>
|
|
8003e14: 1c03 adds r3, r0, #0
|
|
8003e16: 1c18 adds r0, r3, #0
|
|
8003e18: f7fd facc bl 80013b4 <__aeabi_f2iz>
|
|
8003e1c: 0003 movs r3, r0
|
|
8003e1e: 607b str r3, [r7, #4]
|
|
8003e20: e030 b.n 8003e84 <DBW_Pwm_Set_Duty+0x164>
|
|
else if (duty < 0)
|
|
8003e22: 687b ldr r3, [r7, #4]
|
|
8003e24: 2b00 cmp r3, #0
|
|
8003e26: da2d bge.n 8003e84 <DBW_Pwm_Set_Duty+0x164>
|
|
duty = 0 - (signed int) tmp * 10000.0F / ttl->period_ticks;
|
|
8003e28: 68f8 ldr r0, [r7, #12]
|
|
8003e2a: f7fd fac3 bl 80013b4 <__aeabi_f2iz>
|
|
8003e2e: 0003 movs r3, r0
|
|
8003e30: 0018 movs r0, r3
|
|
8003e32: f7fd fadf bl 80013f4 <__aeabi_i2f>
|
|
8003e36: 1c03 adds r3, r0, #0
|
|
8003e38: 4922 ldr r1, [pc, #136] @ (8003ec4 <DBW_Pwm_Set_Duty+0x1a4>)
|
|
8003e3a: 1c18 adds r0, r3, #0
|
|
8003e3c: f7fc ff26 bl 8000c8c <__aeabi_fmul>
|
|
8003e40: 1c03 adds r3, r0, #0
|
|
8003e42: 1c1c adds r4, r3, #0
|
|
8003e44: 683b ldr r3, [r7, #0]
|
|
8003e46: 695b ldr r3, [r3, #20]
|
|
8003e48: 0018 movs r0, r3
|
|
8003e4a: f7fd fb23 bl 8001494 <__aeabi_ui2f>
|
|
8003e4e: 1c03 adds r3, r0, #0
|
|
8003e50: 1c19 adds r1, r3, #0
|
|
8003e52: 1c20 adds r0, r4, #0
|
|
8003e54: f7fc fd4c bl 80008f0 <__aeabi_fdiv>
|
|
8003e58: 1c03 adds r3, r0, #0
|
|
8003e5a: 1c19 adds r1, r3, #0
|
|
8003e5c: 2000 movs r0, #0
|
|
8003e5e: f7fd f867 bl 8000f30 <__aeabi_fsub>
|
|
8003e62: 1c03 adds r3, r0, #0
|
|
8003e64: 1c18 adds r0, r3, #0
|
|
8003e66: f7fd faa5 bl 80013b4 <__aeabi_f2iz>
|
|
8003e6a: 0003 movs r3, r0
|
|
8003e6c: 607b str r3, [r7, #4]
|
|
8003e6e: e009 b.n 8003e84 <DBW_Pwm_Set_Duty+0x164>
|
|
} else if (tmp < 20) {
|
|
8003e70: 4915 ldr r1, [pc, #84] @ (8003ec8 <DBW_Pwm_Set_Duty+0x1a8>)
|
|
8003e72: 68f8 ldr r0, [r7, #12]
|
|
8003e74: f7fc fad0 bl 8000418 <__aeabi_fcmplt>
|
|
8003e78: 1e03 subs r3, r0, #0
|
|
8003e7a: d003 beq.n 8003e84 <DBW_Pwm_Set_Duty+0x164>
|
|
tmp = 20;
|
|
8003e7c: 4b12 ldr r3, [pc, #72] @ (8003ec8 <DBW_Pwm_Set_Duty+0x1a8>)
|
|
8003e7e: 60fb str r3, [r7, #12]
|
|
duty = 0;
|
|
8003e80: 2300 movs r3, #0
|
|
8003e82: 607b str r3, [r7, #4]
|
|
}
|
|
|
|
//update variables
|
|
var.motor_pwm = duty;
|
|
8003e84: 687b ldr r3, [r7, #4]
|
|
8003e86: b21a sxth r2, r3
|
|
8003e88: 4b10 ldr r3, [pc, #64] @ (8003ecc <DBW_Pwm_Set_Duty+0x1ac>)
|
|
8003e8a: 84da strh r2, [r3, #38] @ 0x26
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8003e8c: b672 cpsid i
|
|
}
|
|
8003e8e: 46c0 nop @ (mov r8, r8)
|
|
|
|
//apply new settings
|
|
__disable_irq();
|
|
ttl->duty_ticks = (unsigned int) tmp;
|
|
8003e90: 68f8 ldr r0, [r7, #12]
|
|
8003e92: f7fc fae9 bl 8000468 <__aeabi_f2uiz>
|
|
8003e96: 0002 movs r2, r0
|
|
8003e98: 683b ldr r3, [r7, #0]
|
|
8003e9a: 619a str r2, [r3, #24]
|
|
ttl->period_ticks = period_ticks;
|
|
8003e9c: 683b ldr r3, [r7, #0]
|
|
8003e9e: 68ba ldr r2, [r7, #8]
|
|
8003ea0: 615a str r2, [r3, #20]
|
|
ttl->pwm = duty;
|
|
8003ea2: 683b ldr r3, [r7, #0]
|
|
8003ea4: 687a ldr r2, [r7, #4]
|
|
8003ea6: 61da str r2, [r3, #28]
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8003ea8: b662 cpsie i
|
|
}
|
|
8003eaa: 46c0 nop @ (mov r8, r8)
|
|
__enable_irq();
|
|
|
|
}
|
|
8003eac: 46c0 nop @ (mov r8, r8)
|
|
8003eae: 46bd mov sp, r7
|
|
8003eb0: b005 add sp, #20
|
|
8003eb2: bd90 pop {r4, r7, pc}
|
|
8003eb4: 00002710 .word 0x00002710
|
|
8003eb8: ffffd8f0 .word 0xffffd8f0
|
|
8003ebc: 200009cc .word 0x200009cc
|
|
8003ec0: 000f4240 .word 0x000f4240
|
|
8003ec4: 461c4000 .word 0x461c4000
|
|
8003ec8: 41a00000 .word 0x41a00000
|
|
8003ecc: 20000998 .word 0x20000998
|
|
|
|
08003ed0 <intrp_1d_ss_table>:
|
|
return ((unsigned int) (z_table[ix]
|
|
+ interp * (int) (z_table[ix + 1] - z_table[ix]) / 100));
|
|
}
|
|
|
|
signed short intrp_1d_ss_table(signed short x, unsigned char n,
|
|
signed short *x_table, char sgn, signed short *z_table) {
|
|
8003ed0: b590 push {r4, r7, lr}
|
|
8003ed2: b087 sub sp, #28
|
|
8003ed4: af00 add r7, sp, #0
|
|
8003ed6: 0004 movs r4, r0
|
|
8003ed8: 0008 movs r0, r1
|
|
8003eda: 603a str r2, [r7, #0]
|
|
8003edc: 0019 movs r1, r3
|
|
8003ede: 1dbb adds r3, r7, #6
|
|
8003ee0: 1c22 adds r2, r4, #0
|
|
8003ee2: 801a strh r2, [r3, #0]
|
|
8003ee4: 1d7b adds r3, r7, #5
|
|
8003ee6: 1c02 adds r2, r0, #0
|
|
8003ee8: 701a strb r2, [r3, #0]
|
|
8003eea: 1d3b adds r3, r7, #4
|
|
8003eec: 1c0a adds r2, r1, #0
|
|
8003eee: 701a strb r2, [r3, #0]
|
|
int ix;
|
|
int interp, interp3;
|
|
// bound input arguments
|
|
if (x > x_table[n - 1])
|
|
8003ef0: 1d7b adds r3, r7, #5
|
|
8003ef2: 781b ldrb r3, [r3, #0]
|
|
8003ef4: 4a46 ldr r2, [pc, #280] @ (8004010 <intrp_1d_ss_table+0x140>)
|
|
8003ef6: 4694 mov ip, r2
|
|
8003ef8: 4463 add r3, ip
|
|
8003efa: 005b lsls r3, r3, #1
|
|
8003efc: 683a ldr r2, [r7, #0]
|
|
8003efe: 18d3 adds r3, r2, r3
|
|
8003f00: 2200 movs r2, #0
|
|
8003f02: 5e9b ldrsh r3, [r3, r2]
|
|
8003f04: 1dba adds r2, r7, #6
|
|
8003f06: 2100 movs r1, #0
|
|
8003f08: 5e52 ldrsh r2, [r2, r1]
|
|
8003f0a: 429a cmp r2, r3
|
|
8003f0c: dd0a ble.n 8003f24 <intrp_1d_ss_table+0x54>
|
|
return z_table[n - 1];
|
|
8003f0e: 1d7b adds r3, r7, #5
|
|
8003f10: 781b ldrb r3, [r3, #0]
|
|
8003f12: 4a3f ldr r2, [pc, #252] @ (8004010 <intrp_1d_ss_table+0x140>)
|
|
8003f14: 4694 mov ip, r2
|
|
8003f16: 4463 add r3, ip
|
|
8003f18: 005b lsls r3, r3, #1
|
|
8003f1a: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8003f1c: 18d3 adds r3, r2, r3
|
|
8003f1e: 2200 movs r2, #0
|
|
8003f20: 5e9b ldrsh r3, [r3, r2]
|
|
8003f22: e071 b.n 8004008 <intrp_1d_ss_table+0x138>
|
|
|
|
if (x < x_table[0])
|
|
8003f24: 683b ldr r3, [r7, #0]
|
|
8003f26: 2200 movs r2, #0
|
|
8003f28: 5e9b ldrsh r3, [r3, r2]
|
|
8003f2a: 1dba adds r2, r7, #6
|
|
8003f2c: 2100 movs r1, #0
|
|
8003f2e: 5e52 ldrsh r2, [r2, r1]
|
|
8003f30: 429a cmp r2, r3
|
|
8003f32: da03 bge.n 8003f3c <intrp_1d_ss_table+0x6c>
|
|
return z_table[0];
|
|
8003f34: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003f36: 2200 movs r2, #0
|
|
8003f38: 5e9b ldrsh r3, [r3, r2]
|
|
8003f3a: e065 b.n 8004008 <intrp_1d_ss_table+0x138>
|
|
|
|
for (ix = n - 2; ix > -1; ix--) {
|
|
8003f3c: 1d7b adds r3, r7, #5
|
|
8003f3e: 781b ldrb r3, [r3, #0]
|
|
8003f40: 3b02 subs r3, #2
|
|
8003f42: 617b str r3, [r7, #20]
|
|
8003f44: e00d b.n 8003f62 <intrp_1d_ss_table+0x92>
|
|
if (x > x_table[ix]) {
|
|
8003f46: 697b ldr r3, [r7, #20]
|
|
8003f48: 005b lsls r3, r3, #1
|
|
8003f4a: 683a ldr r2, [r7, #0]
|
|
8003f4c: 18d3 adds r3, r2, r3
|
|
8003f4e: 2200 movs r2, #0
|
|
8003f50: 5e9b ldrsh r3, [r3, r2]
|
|
8003f52: 1dba adds r2, r7, #6
|
|
8003f54: 2100 movs r1, #0
|
|
8003f56: 5e52 ldrsh r2, [r2, r1]
|
|
8003f58: 429a cmp r2, r3
|
|
8003f5a: dc06 bgt.n 8003f6a <intrp_1d_ss_table+0x9a>
|
|
for (ix = n - 2; ix > -1; ix--) {
|
|
8003f5c: 697b ldr r3, [r7, #20]
|
|
8003f5e: 3b01 subs r3, #1
|
|
8003f60: 617b str r3, [r7, #20]
|
|
8003f62: 697b ldr r3, [r7, #20]
|
|
8003f64: 2b00 cmp r3, #0
|
|
8003f66: daee bge.n 8003f46 <intrp_1d_ss_table+0x76>
|
|
8003f68: e000 b.n 8003f6c <intrp_1d_ss_table+0x9c>
|
|
break;
|
|
8003f6a: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
if (ix < 0)
|
|
8003f6c: 697b ldr r3, [r7, #20]
|
|
8003f6e: 2b00 cmp r3, #0
|
|
8003f70: da01 bge.n 8003f76 <intrp_1d_ss_table+0xa6>
|
|
ix = 0;
|
|
8003f72: 2300 movs r3, #0
|
|
8003f74: 617b str r3, [r7, #20]
|
|
|
|
interp = x_table[ix + 1] - x_table[ix];
|
|
8003f76: 697b ldr r3, [r7, #20]
|
|
8003f78: 3301 adds r3, #1
|
|
8003f7a: 005b lsls r3, r3, #1
|
|
8003f7c: 683a ldr r2, [r7, #0]
|
|
8003f7e: 18d3 adds r3, r2, r3
|
|
8003f80: 2200 movs r2, #0
|
|
8003f82: 5e9b ldrsh r3, [r3, r2]
|
|
8003f84: 0019 movs r1, r3
|
|
8003f86: 697b ldr r3, [r7, #20]
|
|
8003f88: 005b lsls r3, r3, #1
|
|
8003f8a: 683a ldr r2, [r7, #0]
|
|
8003f8c: 18d3 adds r3, r2, r3
|
|
8003f8e: 2200 movs r2, #0
|
|
8003f90: 5e9b ldrsh r3, [r3, r2]
|
|
8003f92: 1acb subs r3, r1, r3
|
|
8003f94: 613b str r3, [r7, #16]
|
|
if (interp != 0) {
|
|
8003f96: 693b ldr r3, [r7, #16]
|
|
8003f98: 2b00 cmp r3, #0
|
|
8003f9a: d014 beq.n 8003fc6 <intrp_1d_ss_table+0xf6>
|
|
interp3 = (x - x_table[ix]);
|
|
8003f9c: 1dbb adds r3, r7, #6
|
|
8003f9e: 2200 movs r2, #0
|
|
8003fa0: 5e9b ldrsh r3, [r3, r2]
|
|
8003fa2: 697a ldr r2, [r7, #20]
|
|
8003fa4: 0052 lsls r2, r2, #1
|
|
8003fa6: 6839 ldr r1, [r7, #0]
|
|
8003fa8: 188a adds r2, r1, r2
|
|
8003faa: 2100 movs r1, #0
|
|
8003fac: 5e52 ldrsh r2, [r2, r1]
|
|
8003fae: 1a9b subs r3, r3, r2
|
|
8003fb0: 60fb str r3, [r7, #12]
|
|
interp3 = (100 * interp3);
|
|
8003fb2: 68fb ldr r3, [r7, #12]
|
|
8003fb4: 2264 movs r2, #100 @ 0x64
|
|
8003fb6: 4353 muls r3, r2
|
|
8003fb8: 60fb str r3, [r7, #12]
|
|
interp = interp3 / interp;
|
|
8003fba: 6939 ldr r1, [r7, #16]
|
|
8003fbc: 68f8 ldr r0, [r7, #12]
|
|
8003fbe: f7fc f92d bl 800021c <__divsi3>
|
|
8003fc2: 0003 movs r3, r0
|
|
8003fc4: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
return ((short) ((int) z_table[ix]
|
|
8003fc6: 697b ldr r3, [r7, #20]
|
|
8003fc8: 005b lsls r3, r3, #1
|
|
8003fca: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8003fcc: 18d3 adds r3, r2, r3
|
|
8003fce: 2200 movs r2, #0
|
|
8003fd0: 5e9b ldrsh r3, [r3, r2]
|
|
8003fd2: b29c uxth r4, r3
|
|
+ interp * ((int) z_table[ix + 1] - (int) z_table[ix]) / 100));
|
|
8003fd4: 697b ldr r3, [r7, #20]
|
|
8003fd6: 3301 adds r3, #1
|
|
8003fd8: 005b lsls r3, r3, #1
|
|
8003fda: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8003fdc: 18d3 adds r3, r2, r3
|
|
8003fde: 2200 movs r2, #0
|
|
8003fe0: 5e9b ldrsh r3, [r3, r2]
|
|
8003fe2: 0019 movs r1, r3
|
|
8003fe4: 697b ldr r3, [r7, #20]
|
|
8003fe6: 005b lsls r3, r3, #1
|
|
8003fe8: 6aba ldr r2, [r7, #40] @ 0x28
|
|
8003fea: 18d3 adds r3, r2, r3
|
|
8003fec: 2200 movs r2, #0
|
|
8003fee: 5e9b ldrsh r3, [r3, r2]
|
|
8003ff0: 1acb subs r3, r1, r3
|
|
8003ff2: 693a ldr r2, [r7, #16]
|
|
8003ff4: 4353 muls r3, r2
|
|
8003ff6: 2164 movs r1, #100 @ 0x64
|
|
8003ff8: 0018 movs r0, r3
|
|
8003ffa: f7fc f90f bl 800021c <__divsi3>
|
|
8003ffe: 0003 movs r3, r0
|
|
8004000: b29b uxth r3, r3
|
|
8004002: 18e3 adds r3, r4, r3
|
|
8004004: b29b uxth r3, r3
|
|
return ((short) ((int) z_table[ix]
|
|
8004006: b21b sxth r3, r3
|
|
}
|
|
8004008: 0018 movs r0, r3
|
|
800400a: 46bd mov sp, r7
|
|
800400c: b007 add sp, #28
|
|
800400e: bd90 pop {r4, r7, pc}
|
|
8004010: 7fffffff .word 0x7fffffff
|
|
|
|
08004014 <DBW_Start>:
|
|
+ interp
|
|
* ((signed short) z_table[ix + 1]
|
|
- (signed short) z_table[ix]) / 100));
|
|
}
|
|
|
|
void DBW_Start(void) {
|
|
8004014: b580 push {r7, lr}
|
|
8004016: af00 add r7, sp, #0
|
|
GPIOB->ODR &= ~D1_Pin;
|
|
8004018: 4b07 ldr r3, [pc, #28] @ (8004038 <DBW_Start+0x24>)
|
|
800401a: 695a ldr r2, [r3, #20]
|
|
800401c: 4b06 ldr r3, [pc, #24] @ (8004038 <DBW_Start+0x24>)
|
|
800401e: 4907 ldr r1, [pc, #28] @ (800403c <DBW_Start+0x28>)
|
|
8004020: 400a ands r2, r1
|
|
8004022: 615a str r2, [r3, #20]
|
|
GPIOB->ODR |= D2_Pin;
|
|
8004024: 4b04 ldr r3, [pc, #16] @ (8004038 <DBW_Start+0x24>)
|
|
8004026: 695a ldr r2, [r3, #20]
|
|
8004028: 4b03 ldr r3, [pc, #12] @ (8004038 <DBW_Start+0x24>)
|
|
800402a: 2180 movs r1, #128 @ 0x80
|
|
800402c: 0189 lsls r1, r1, #6
|
|
800402e: 430a orrs r2, r1
|
|
8004030: 615a str r2, [r3, #20]
|
|
}
|
|
8004032: 46c0 nop @ (mov r8, r8)
|
|
8004034: 46bd mov sp, r7
|
|
8004036: bd80 pop {r7, pc}
|
|
8004038: 48000400 .word 0x48000400
|
|
800403c: ffffbfff .word 0xffffbfff
|
|
|
|
08004040 <DBW_Stop>:
|
|
void DBW_Stop(void) {
|
|
8004040: b580 push {r7, lr}
|
|
8004042: af00 add r7, sp, #0
|
|
GPIOB->ODR |= D1_Pin;
|
|
8004044: 4b07 ldr r3, [pc, #28] @ (8004064 <DBW_Stop+0x24>)
|
|
8004046: 695a ldr r2, [r3, #20]
|
|
8004048: 4b06 ldr r3, [pc, #24] @ (8004064 <DBW_Stop+0x24>)
|
|
800404a: 2180 movs r1, #128 @ 0x80
|
|
800404c: 01c9 lsls r1, r1, #7
|
|
800404e: 430a orrs r2, r1
|
|
8004050: 615a str r2, [r3, #20]
|
|
GPIOB->ODR &= ~D2_Pin;
|
|
8004052: 4b04 ldr r3, [pc, #16] @ (8004064 <DBW_Stop+0x24>)
|
|
8004054: 695a ldr r2, [r3, #20]
|
|
8004056: 4b03 ldr r3, [pc, #12] @ (8004064 <DBW_Stop+0x24>)
|
|
8004058: 4903 ldr r1, [pc, #12] @ (8004068 <DBW_Stop+0x28>)
|
|
800405a: 400a ands r2, r1
|
|
800405c: 615a str r2, [r3, #20]
|
|
|
|
}
|
|
800405e: 46c0 nop @ (mov r8, r8)
|
|
8004060: 46bd mov sp, r7
|
|
8004062: bd80 pop {r7, pc}
|
|
8004064: 48000400 .word 0x48000400
|
|
8004068: ffffdfff .word 0xffffdfff
|
|
|
|
0800406c <DBW_TPS_AutoCal>:
|
|
|
|
void DBW_TPS_AutoCal(void) {
|
|
800406c: b580 push {r7, lr}
|
|
800406e: b086 sub sp, #24
|
|
8004070: af00 add r7, sp, #0
|
|
// if time to process autocal
|
|
if ((ac_timer == 0) && (ac_mode != 0)) {
|
|
8004072: 4b77 ldr r3, [pc, #476] @ (8004250 <DBW_TPS_AutoCal+0x1e4>)
|
|
8004074: 681b ldr r3, [r3, #0]
|
|
8004076: 2b00 cmp r3, #0
|
|
8004078: d000 beq.n 800407c <DBW_TPS_AutoCal+0x10>
|
|
800407a: e0e4 b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
800407c: 4b75 ldr r3, [pc, #468] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
800407e: 681b ldr r3, [r3, #0]
|
|
8004080: 2b00 cmp r3, #0
|
|
8004082: d100 bne.n 8004086 <DBW_TPS_AutoCal+0x1a>
|
|
8004084: e0df b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
if (ac_mode == 1) {
|
|
8004086: 4b73 ldr r3, [pc, #460] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004088: 681b ldr r3, [r3, #0]
|
|
800408a: 2b01 cmp r3, #1
|
|
800408c: d117 bne.n 80040be <DBW_TPS_AutoCal+0x52>
|
|
var.status0 |= DBW_STATUS0_PPSTPS_CAL_F;
|
|
800408e: 4b72 ldr r3, [pc, #456] @ (8004258 <DBW_TPS_AutoCal+0x1ec>)
|
|
8004090: 889b ldrh r3, [r3, #4]
|
|
8004092: b29b uxth r3, r3
|
|
8004094: 2280 movs r2, #128 @ 0x80
|
|
8004096: 0112 lsls r2, r2, #4
|
|
8004098: 4313 orrs r3, r2
|
|
800409a: b29a uxth r2, r3
|
|
800409c: 4b6e ldr r3, [pc, #440] @ (8004258 <DBW_TPS_AutoCal+0x1ec>)
|
|
800409e: 809a strh r2, [r3, #4]
|
|
DBW_Pwm_Set_Duty((signed short) (-6000), (pwm_t*) &ttl1_pwm);
|
|
80040a0: 4b6e ldr r3, [pc, #440] @ (800425c <DBW_TPS_AutoCal+0x1f0>)
|
|
80040a2: 4a6f ldr r2, [pc, #444] @ (8004260 <DBW_TPS_AutoCal+0x1f4>)
|
|
80040a4: 0019 movs r1, r3
|
|
80040a6: 0010 movs r0, r2
|
|
80040a8: f7ff fe3a bl 8003d20 <DBW_Pwm_Set_Duty>
|
|
DBW_Start();
|
|
80040ac: f7ff ffb2 bl 8004014 <DBW_Start>
|
|
ac_timer = 1500;
|
|
80040b0: 4b67 ldr r3, [pc, #412] @ (8004250 <DBW_TPS_AutoCal+0x1e4>)
|
|
80040b2: 4a6c ldr r2, [pc, #432] @ (8004264 <DBW_TPS_AutoCal+0x1f8>)
|
|
80040b4: 601a str r2, [r3, #0]
|
|
ac_mode = 2;
|
|
80040b6: 4b67 ldr r3, [pc, #412] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
80040b8: 2202 movs r2, #2
|
|
80040ba: 601a str r2, [r3, #0]
|
|
NVIC_EnableIRQ(USART1_IRQn);
|
|
|
|
}
|
|
}
|
|
|
|
}
|
|
80040bc: e0c3 b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
} else if (ac_mode == 2) {
|
|
80040be: 4b65 ldr r3, [pc, #404] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
80040c0: 681b ldr r3, [r3, #0]
|
|
80040c2: 2b02 cmp r3, #2
|
|
80040c4: d13b bne.n 800413e <DBW_TPS_AutoCal+0xd2>
|
|
uint32_t tmp = 0;
|
|
80040c6: 2300 movs r3, #0
|
|
80040c8: 617b str r3, [r7, #20]
|
|
for (int i = 0; i < 16; i++)
|
|
80040ca: 2300 movs r3, #0
|
|
80040cc: 613b str r3, [r7, #16]
|
|
80040ce: e00a b.n 80040e6 <DBW_TPS_AutoCal+0x7a>
|
|
tmp += Adc_Read(2);
|
|
80040d0: 2002 movs r0, #2
|
|
80040d2: f7fe fbb5 bl 8002840 <Adc_Read>
|
|
80040d6: 0003 movs r3, r0
|
|
80040d8: 001a movs r2, r3
|
|
80040da: 697b ldr r3, [r7, #20]
|
|
80040dc: 189b adds r3, r3, r2
|
|
80040de: 617b str r3, [r7, #20]
|
|
for (int i = 0; i < 16; i++)
|
|
80040e0: 693b ldr r3, [r7, #16]
|
|
80040e2: 3301 adds r3, #1
|
|
80040e4: 613b str r3, [r7, #16]
|
|
80040e6: 693b ldr r3, [r7, #16]
|
|
80040e8: 2b0f cmp r3, #15
|
|
80040ea: ddf1 ble.n 80040d0 <DBW_TPS_AutoCal+0x64>
|
|
config->tps1_min = tmp >> 4;
|
|
80040ec: 697b ldr r3, [r7, #20]
|
|
80040ee: 091a lsrs r2, r3, #4
|
|
80040f0: 4b5d ldr r3, [pc, #372] @ (8004268 <DBW_TPS_AutoCal+0x1fc>)
|
|
80040f2: 681b ldr r3, [r3, #0]
|
|
80040f4: b292 uxth r2, r2
|
|
80040f6: 81da strh r2, [r3, #14]
|
|
tmp = 0;
|
|
80040f8: 2300 movs r3, #0
|
|
80040fa: 617b str r3, [r7, #20]
|
|
for (int i = 0; i < 16; i++)
|
|
80040fc: 2300 movs r3, #0
|
|
80040fe: 60fb str r3, [r7, #12]
|
|
8004100: e00a b.n 8004118 <DBW_TPS_AutoCal+0xac>
|
|
tmp += Adc_Read(3);
|
|
8004102: 2003 movs r0, #3
|
|
8004104: f7fe fb9c bl 8002840 <Adc_Read>
|
|
8004108: 0003 movs r3, r0
|
|
800410a: 001a movs r2, r3
|
|
800410c: 697b ldr r3, [r7, #20]
|
|
800410e: 189b adds r3, r3, r2
|
|
8004110: 617b str r3, [r7, #20]
|
|
for (int i = 0; i < 16; i++)
|
|
8004112: 68fb ldr r3, [r7, #12]
|
|
8004114: 3301 adds r3, #1
|
|
8004116: 60fb str r3, [r7, #12]
|
|
8004118: 68fb ldr r3, [r7, #12]
|
|
800411a: 2b0f cmp r3, #15
|
|
800411c: ddf1 ble.n 8004102 <DBW_TPS_AutoCal+0x96>
|
|
config->tps2_min = tmp >> 4;
|
|
800411e: 697b ldr r3, [r7, #20]
|
|
8004120: 091a lsrs r2, r3, #4
|
|
8004122: 4b51 ldr r3, [pc, #324] @ (8004268 <DBW_TPS_AutoCal+0x1fc>)
|
|
8004124: 681b ldr r3, [r3, #0]
|
|
8004126: b292 uxth r2, r2
|
|
8004128: 825a strh r2, [r3, #18]
|
|
DBW_Stop();
|
|
800412a: f7ff ff89 bl 8004040 <DBW_Stop>
|
|
ac_timer = 2000;
|
|
800412e: 4b48 ldr r3, [pc, #288] @ (8004250 <DBW_TPS_AutoCal+0x1e4>)
|
|
8004130: 22fa movs r2, #250 @ 0xfa
|
|
8004132: 00d2 lsls r2, r2, #3
|
|
8004134: 601a str r2, [r3, #0]
|
|
ac_mode = 3;
|
|
8004136: 4b47 ldr r3, [pc, #284] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004138: 2203 movs r2, #3
|
|
800413a: 601a str r2, [r3, #0]
|
|
}
|
|
800413c: e083 b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
} else if (ac_mode == 3) {
|
|
800413e: 4b45 ldr r3, [pc, #276] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004140: 681b ldr r3, [r3, #0]
|
|
8004142: 2b03 cmp r3, #3
|
|
8004144: d10e bne.n 8004164 <DBW_TPS_AutoCal+0xf8>
|
|
DBW_Pwm_Set_Duty((signed short) (9000), (pwm_t*) &ttl1_pwm);
|
|
8004146: 4b45 ldr r3, [pc, #276] @ (800425c <DBW_TPS_AutoCal+0x1f0>)
|
|
8004148: 4a48 ldr r2, [pc, #288] @ (800426c <DBW_TPS_AutoCal+0x200>)
|
|
800414a: 0019 movs r1, r3
|
|
800414c: 0010 movs r0, r2
|
|
800414e: f7ff fde7 bl 8003d20 <DBW_Pwm_Set_Duty>
|
|
DBW_Start();
|
|
8004152: f7ff ff5f bl 8004014 <DBW_Start>
|
|
ac_timer = 1500;
|
|
8004156: 4b3e ldr r3, [pc, #248] @ (8004250 <DBW_TPS_AutoCal+0x1e4>)
|
|
8004158: 4a42 ldr r2, [pc, #264] @ (8004264 <DBW_TPS_AutoCal+0x1f8>)
|
|
800415a: 601a str r2, [r3, #0]
|
|
ac_mode = 4;
|
|
800415c: 4b3d ldr r3, [pc, #244] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
800415e: 2204 movs r2, #4
|
|
8004160: 601a str r2, [r3, #0]
|
|
}
|
|
8004162: e070 b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
} else if (ac_mode == 4) {
|
|
8004164: 4b3b ldr r3, [pc, #236] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004166: 681b ldr r3, [r3, #0]
|
|
8004168: 2b04 cmp r3, #4
|
|
800416a: d154 bne.n 8004216 <DBW_TPS_AutoCal+0x1aa>
|
|
uint32_t tmp = 0;
|
|
800416c: 2300 movs r3, #0
|
|
800416e: 60bb str r3, [r7, #8]
|
|
for (int i = 0; i < 16; i++)
|
|
8004170: 2300 movs r3, #0
|
|
8004172: 607b str r3, [r7, #4]
|
|
8004174: e00a b.n 800418c <DBW_TPS_AutoCal+0x120>
|
|
tmp += Adc_Read(2);
|
|
8004176: 2002 movs r0, #2
|
|
8004178: f7fe fb62 bl 8002840 <Adc_Read>
|
|
800417c: 0003 movs r3, r0
|
|
800417e: 001a movs r2, r3
|
|
8004180: 68bb ldr r3, [r7, #8]
|
|
8004182: 189b adds r3, r3, r2
|
|
8004184: 60bb str r3, [r7, #8]
|
|
for (int i = 0; i < 16; i++)
|
|
8004186: 687b ldr r3, [r7, #4]
|
|
8004188: 3301 adds r3, #1
|
|
800418a: 607b str r3, [r7, #4]
|
|
800418c: 687b ldr r3, [r7, #4]
|
|
800418e: 2b0f cmp r3, #15
|
|
8004190: ddf1 ble.n 8004176 <DBW_TPS_AutoCal+0x10a>
|
|
config->tps1_max = tmp >> 4;
|
|
8004192: 68bb ldr r3, [r7, #8]
|
|
8004194: 091a lsrs r2, r3, #4
|
|
8004196: 4b34 ldr r3, [pc, #208] @ (8004268 <DBW_TPS_AutoCal+0x1fc>)
|
|
8004198: 681b ldr r3, [r3, #0]
|
|
800419a: b292 uxth r2, r2
|
|
800419c: 821a strh r2, [r3, #16]
|
|
tmp = 0;
|
|
800419e: 2300 movs r3, #0
|
|
80041a0: 60bb str r3, [r7, #8]
|
|
for (int i = 0; i < 16; i++)
|
|
80041a2: 2300 movs r3, #0
|
|
80041a4: 603b str r3, [r7, #0]
|
|
80041a6: e00a b.n 80041be <DBW_TPS_AutoCal+0x152>
|
|
tmp += Adc_Read(3);
|
|
80041a8: 2003 movs r0, #3
|
|
80041aa: f7fe fb49 bl 8002840 <Adc_Read>
|
|
80041ae: 0003 movs r3, r0
|
|
80041b0: 001a movs r2, r3
|
|
80041b2: 68bb ldr r3, [r7, #8]
|
|
80041b4: 189b adds r3, r3, r2
|
|
80041b6: 60bb str r3, [r7, #8]
|
|
for (int i = 0; i < 16; i++)
|
|
80041b8: 683b ldr r3, [r7, #0]
|
|
80041ba: 3301 adds r3, #1
|
|
80041bc: 603b str r3, [r7, #0]
|
|
80041be: 683b ldr r3, [r7, #0]
|
|
80041c0: 2b0f cmp r3, #15
|
|
80041c2: ddf1 ble.n 80041a8 <DBW_TPS_AutoCal+0x13c>
|
|
config->tps2_max = tmp >> 4;
|
|
80041c4: 68bb ldr r3, [r7, #8]
|
|
80041c6: 091a lsrs r2, r3, #4
|
|
80041c8: 4b27 ldr r3, [pc, #156] @ (8004268 <DBW_TPS_AutoCal+0x1fc>)
|
|
80041ca: 681b ldr r3, [r3, #0]
|
|
80041cc: b292 uxth r2, r2
|
|
80041ce: 831a strh r2, [r3, #24]
|
|
DBW_Stop();
|
|
80041d0: f7ff ff36 bl 8004040 <DBW_Stop>
|
|
DBW_Pwm_Set_Duty((signed short) (0), (pwm_t*) &ttl1_pwm);
|
|
80041d4: 4b21 ldr r3, [pc, #132] @ (800425c <DBW_TPS_AutoCal+0x1f0>)
|
|
80041d6: 0019 movs r1, r3
|
|
80041d8: 2000 movs r0, #0
|
|
80041da: f7ff fda1 bl 8003d20 <DBW_Pwm_Set_Duty>
|
|
Apply_Sensor_Calibration();
|
|
80041de: f7fe ff2d bl 800303c <Apply_Sensor_Calibration>
|
|
Write_Config();
|
|
80041e2: f002 fa8b bl 80066fc <Write_Config>
|
|
ac_timer = 10000;
|
|
80041e6: 4b1a ldr r3, [pc, #104] @ (8004250 <DBW_TPS_AutoCal+0x1e4>)
|
|
80041e8: 4a21 ldr r2, [pc, #132] @ (8004270 <DBW_TPS_AutoCal+0x204>)
|
|
80041ea: 601a str r2, [r3, #0]
|
|
ac_mode = 5;
|
|
80041ec: 4b19 ldr r3, [pc, #100] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
80041ee: 2205 movs r2, #5
|
|
80041f0: 601a str r2, [r3, #0]
|
|
Comms_Reset(&RX);
|
|
80041f2: 4b20 ldr r3, [pc, #128] @ (8004274 <DBW_TPS_AutoCal+0x208>)
|
|
80041f4: 0018 movs r0, r3
|
|
80041f6: f001 ff2d bl 8006054 <Comms_Reset>
|
|
Comms_Reset(&TX);
|
|
80041fa: 4b1f ldr r3, [pc, #124] @ (8004278 <DBW_TPS_AutoCal+0x20c>)
|
|
80041fc: 0018 movs r0, r3
|
|
80041fe: f001 ff29 bl 8006054 <Comms_Reset>
|
|
USART1->ICR &= ~USART_CR1_RXNEIE;
|
|
8004202: 4b1e ldr r3, [pc, #120] @ (800427c <DBW_TPS_AutoCal+0x210>)
|
|
8004204: 6a1a ldr r2, [r3, #32]
|
|
8004206: 4b1d ldr r3, [pc, #116] @ (800427c <DBW_TPS_AutoCal+0x210>)
|
|
8004208: 2120 movs r1, #32
|
|
800420a: 438a bics r2, r1
|
|
800420c: 621a str r2, [r3, #32]
|
|
NVIC_DisableIRQ(USART1_IRQn);
|
|
800420e: 201b movs r0, #27
|
|
8004210: f7fe fef2 bl 8002ff8 <__NVIC_DisableIRQ>
|
|
}
|
|
8004214: e017 b.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
} else if (ac_mode == 5) {
|
|
8004216: 4b0f ldr r3, [pc, #60] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004218: 681b ldr r3, [r3, #0]
|
|
800421a: 2b05 cmp r3, #5
|
|
800421c: d113 bne.n 8004246 <DBW_TPS_AutoCal+0x1da>
|
|
ac_mode = 0;
|
|
800421e: 4b0d ldr r3, [pc, #52] @ (8004254 <DBW_TPS_AutoCal+0x1e8>)
|
|
8004220: 2200 movs r2, #0
|
|
8004222: 601a str r2, [r3, #0]
|
|
var.status0 &= ~DBW_STATUS0_PPSTPS_CAL_F;
|
|
8004224: 4b0c ldr r3, [pc, #48] @ (8004258 <DBW_TPS_AutoCal+0x1ec>)
|
|
8004226: 889b ldrh r3, [r3, #4]
|
|
8004228: b29b uxth r3, r3
|
|
800422a: 4a15 ldr r2, [pc, #84] @ (8004280 <DBW_TPS_AutoCal+0x214>)
|
|
800422c: 4013 ands r3, r2
|
|
800422e: b29a uxth r2, r3
|
|
8004230: 4b09 ldr r3, [pc, #36] @ (8004258 <DBW_TPS_AutoCal+0x1ec>)
|
|
8004232: 809a strh r2, [r3, #4]
|
|
USART1->ICR |= USART_CR1_RXNEIE;
|
|
8004234: 4b11 ldr r3, [pc, #68] @ (800427c <DBW_TPS_AutoCal+0x210>)
|
|
8004236: 6a1a ldr r2, [r3, #32]
|
|
8004238: 4b10 ldr r3, [pc, #64] @ (800427c <DBW_TPS_AutoCal+0x210>)
|
|
800423a: 2120 movs r1, #32
|
|
800423c: 430a orrs r2, r1
|
|
800423e: 621a str r2, [r3, #32]
|
|
NVIC_EnableIRQ(USART1_IRQn);
|
|
8004240: 201b movs r0, #27
|
|
8004242: f7fe febf bl 8002fc4 <__NVIC_EnableIRQ>
|
|
}
|
|
8004246: 46c0 nop @ (mov r8, r8)
|
|
8004248: 46bd mov sp, r7
|
|
800424a: b006 add sp, #24
|
|
800424c: bd80 pop {r7, pc}
|
|
800424e: 46c0 nop @ (mov r8, r8)
|
|
8004250: 20000000 .word 0x20000000
|
|
8004254: 200009d0 .word 0x200009d0
|
|
8004258: 20000998 .word 0x20000998
|
|
800425c: 200009d4 .word 0x200009d4
|
|
8004260: ffffe890 .word 0xffffe890
|
|
8004264: 000005dc .word 0x000005dc
|
|
8004268: 200009cc .word 0x200009cc
|
|
800426c: 00002328 .word 0x00002328
|
|
8004270: 00002710 .word 0x00002710
|
|
8004274: 20000b34 .word 0x20000b34
|
|
8004278: 20000c50 .word 0x20000c50
|
|
800427c: 40013800 .word 0x40013800
|
|
8004280: fffff7ff .word 0xfffff7ff
|
|
|
|
08004284 <DBW_Read_sensors>:
|
|
|
|
void DBW_Read_sensors(void) {
|
|
8004284: b580 push {r7, lr}
|
|
8004286: af00 add r7, sp, #0
|
|
var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc);
|
|
8004288: 2000 movs r0, #0
|
|
800428a: f7fe fad9 bl 8002840 <Adc_Read>
|
|
800428e: 0003 movs r3, r0
|
|
8004290: 0019 movs r1, r3
|
|
8004292: 4b80 ldr r3, [pc, #512] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004294: 899b ldrh r3, [r3, #12]
|
|
8004296: b29a uxth r2, r3
|
|
8004298: 23af movs r3, #175 @ 0xaf
|
|
800429a: 009b lsls r3, r3, #2
|
|
800429c: 0018 movs r0, r3
|
|
800429e: f7fe fa81 bl 80027a4 <LPF>
|
|
80042a2: 0003 movs r3, r0
|
|
80042a4: 001a movs r2, r3
|
|
80042a6: 4b7b ldr r3, [pc, #492] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80042a8: 819a strh r2, [r3, #12]
|
|
var.pps1 = var.pps1_adc * pps1_gain + pps1_offset;
|
|
80042aa: 4b7a ldr r3, [pc, #488] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80042ac: 899b ldrh r3, [r3, #12]
|
|
80042ae: b29b uxth r3, r3
|
|
80042b0: 0018 movs r0, r3
|
|
80042b2: f7fd f89f bl 80013f4 <__aeabi_i2f>
|
|
80042b6: 1c02 adds r2, r0, #0
|
|
80042b8: 4b77 ldr r3, [pc, #476] @ (8004498 <DBW_Read_sensors+0x214>)
|
|
80042ba: 681b ldr r3, [r3, #0]
|
|
80042bc: 1c19 adds r1, r3, #0
|
|
80042be: 1c10 adds r0, r2, #0
|
|
80042c0: f7fc fce4 bl 8000c8c <__aeabi_fmul>
|
|
80042c4: 1c03 adds r3, r0, #0
|
|
80042c6: 1c1a adds r2, r3, #0
|
|
80042c8: 4b74 ldr r3, [pc, #464] @ (800449c <DBW_Read_sensors+0x218>)
|
|
80042ca: 681b ldr r3, [r3, #0]
|
|
80042cc: 1c19 adds r1, r3, #0
|
|
80042ce: 1c10 adds r0, r2, #0
|
|
80042d0: f7fc f900 bl 80004d4 <__aeabi_fadd>
|
|
80042d4: 1c03 adds r3, r0, #0
|
|
80042d6: 1c18 adds r0, r3, #0
|
|
80042d8: f7fd f86c bl 80013b4 <__aeabi_f2iz>
|
|
80042dc: 0003 movs r3, r0
|
|
80042de: b21a sxth r2, r3
|
|
80042e0: 4b6c ldr r3, [pc, #432] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80042e2: 831a strh r2, [r3, #24]
|
|
|
|
var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); // 1 is orig
|
|
80042e4: 2003 movs r0, #3
|
|
80042e6: f7fe faab bl 8002840 <Adc_Read>
|
|
80042ea: 0003 movs r3, r0
|
|
80042ec: 0019 movs r1, r3
|
|
80042ee: 4b69 ldr r3, [pc, #420] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80042f0: 89db ldrh r3, [r3, #14]
|
|
80042f2: b29a uxth r2, r3
|
|
80042f4: 23af movs r3, #175 @ 0xaf
|
|
80042f6: 009b lsls r3, r3, #2
|
|
80042f8: 0018 movs r0, r3
|
|
80042fa: f7fe fa53 bl 80027a4 <LPF>
|
|
80042fe: 0003 movs r3, r0
|
|
8004300: 001a movs r2, r3
|
|
8004302: 4b64 ldr r3, [pc, #400] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004304: 81da strh r2, [r3, #14]
|
|
var.pps2 = var.pps2_adc * pps2_gain + pps2_offset;
|
|
8004306: 4b63 ldr r3, [pc, #396] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004308: 89db ldrh r3, [r3, #14]
|
|
800430a: b29b uxth r3, r3
|
|
800430c: 0018 movs r0, r3
|
|
800430e: f7fd f871 bl 80013f4 <__aeabi_i2f>
|
|
8004312: 1c02 adds r2, r0, #0
|
|
8004314: 4b62 ldr r3, [pc, #392] @ (80044a0 <DBW_Read_sensors+0x21c>)
|
|
8004316: 681b ldr r3, [r3, #0]
|
|
8004318: 1c19 adds r1, r3, #0
|
|
800431a: 1c10 adds r0, r2, #0
|
|
800431c: f7fc fcb6 bl 8000c8c <__aeabi_fmul>
|
|
8004320: 1c03 adds r3, r0, #0
|
|
8004322: 1c1a adds r2, r3, #0
|
|
8004324: 4b5f ldr r3, [pc, #380] @ (80044a4 <DBW_Read_sensors+0x220>)
|
|
8004326: 681b ldr r3, [r3, #0]
|
|
8004328: 1c19 adds r1, r3, #0
|
|
800432a: 1c10 adds r0, r2, #0
|
|
800432c: f7fc f8d2 bl 80004d4 <__aeabi_fadd>
|
|
8004330: 1c03 adds r3, r0, #0
|
|
8004332: 1c18 adds r0, r3, #0
|
|
8004334: f7fd f83e bl 80013b4 <__aeabi_f2iz>
|
|
8004338: 0003 movs r3, r0
|
|
800433a: b21a sxth r2, r3
|
|
800433c: 4b55 ldr r3, [pc, #340] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800433e: 835a strh r2, [r3, #26]
|
|
|
|
var.pps_delta = var.pps1 - var.pps2;
|
|
8004340: 4b54 ldr r3, [pc, #336] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004342: 8b1b ldrh r3, [r3, #24]
|
|
8004344: b21b sxth r3, r3
|
|
8004346: b29a uxth r2, r3
|
|
8004348: 4b52 ldr r3, [pc, #328] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800434a: 8b5b ldrh r3, [r3, #26]
|
|
800434c: b21b sxth r3, r3
|
|
800434e: b29b uxth r3, r3
|
|
8004350: 1ad3 subs r3, r2, r3
|
|
8004352: b29b uxth r3, r3
|
|
8004354: b21a sxth r2, r3
|
|
8004356: 4b4f ldr r3, [pc, #316] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004358: 855a strh r2, [r3, #42] @ 0x2a
|
|
var.pps = (var.pps1 + var.pps2) >> 1;
|
|
800435a: 4b4e ldr r3, [pc, #312] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800435c: 8b1b ldrh r3, [r3, #24]
|
|
800435e: b21b sxth r3, r3
|
|
8004360: 001a movs r2, r3
|
|
8004362: 4b4c ldr r3, [pc, #304] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004364: 8b5b ldrh r3, [r3, #26]
|
|
8004366: b21b sxth r3, r3
|
|
8004368: 18d3 adds r3, r2, r3
|
|
800436a: 105b asrs r3, r3, #1
|
|
800436c: b21a sxth r2, r3
|
|
800436e: 4b49 ldr r3, [pc, #292] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004370: 841a strh r2, [r3, #32]
|
|
|
|
//Calculate TPS sensor reading
|
|
var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc);
|
|
8004372: 2002 movs r0, #2
|
|
8004374: f7fe fa64 bl 8002840 <Adc_Read>
|
|
8004378: 0003 movs r3, r0
|
|
800437a: 0019 movs r1, r3
|
|
800437c: 4b45 ldr r3, [pc, #276] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800437e: 8a1b ldrh r3, [r3, #16]
|
|
8004380: b29a uxth r2, r3
|
|
8004382: 23af movs r3, #175 @ 0xaf
|
|
8004384: 009b lsls r3, r3, #2
|
|
8004386: 0018 movs r0, r3
|
|
8004388: f7fe fa0c bl 80027a4 <LPF>
|
|
800438c: 0003 movs r3, r0
|
|
800438e: 001a movs r2, r3
|
|
8004390: 4b40 ldr r3, [pc, #256] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004392: 821a strh r2, [r3, #16]
|
|
var.tps1 = var.tps1_adc * tps1_gain + tps1_offset;
|
|
8004394: 4b3f ldr r3, [pc, #252] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004396: 8a1b ldrh r3, [r3, #16]
|
|
8004398: b29b uxth r3, r3
|
|
800439a: 0018 movs r0, r3
|
|
800439c: f7fd f82a bl 80013f4 <__aeabi_i2f>
|
|
80043a0: 1c02 adds r2, r0, #0
|
|
80043a2: 4b41 ldr r3, [pc, #260] @ (80044a8 <DBW_Read_sensors+0x224>)
|
|
80043a4: 681b ldr r3, [r3, #0]
|
|
80043a6: 1c19 adds r1, r3, #0
|
|
80043a8: 1c10 adds r0, r2, #0
|
|
80043aa: f7fc fc6f bl 8000c8c <__aeabi_fmul>
|
|
80043ae: 1c03 adds r3, r0, #0
|
|
80043b0: 1c1a adds r2, r3, #0
|
|
80043b2: 4b3e ldr r3, [pc, #248] @ (80044ac <DBW_Read_sensors+0x228>)
|
|
80043b4: 681b ldr r3, [r3, #0]
|
|
80043b6: 1c19 adds r1, r3, #0
|
|
80043b8: 1c10 adds r0, r2, #0
|
|
80043ba: f7fc f88b bl 80004d4 <__aeabi_fadd>
|
|
80043be: 1c03 adds r3, r0, #0
|
|
80043c0: 1c18 adds r0, r3, #0
|
|
80043c2: f7fc fff7 bl 80013b4 <__aeabi_f2iz>
|
|
80043c6: 0003 movs r3, r0
|
|
80043c8: b21a sxth r2, r3
|
|
80043ca: 4b32 ldr r3, [pc, #200] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80043cc: 839a strh r2, [r3, #28]
|
|
|
|
var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //3 is orig
|
|
80043ce: 2001 movs r0, #1
|
|
80043d0: f7fe fa36 bl 8002840 <Adc_Read>
|
|
80043d4: 0003 movs r3, r0
|
|
80043d6: 0019 movs r1, r3
|
|
80043d8: 4b2e ldr r3, [pc, #184] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80043da: 8a5b ldrh r3, [r3, #18]
|
|
80043dc: b29a uxth r2, r3
|
|
80043de: 23af movs r3, #175 @ 0xaf
|
|
80043e0: 009b lsls r3, r3, #2
|
|
80043e2: 0018 movs r0, r3
|
|
80043e4: f7fe f9de bl 80027a4 <LPF>
|
|
80043e8: 0003 movs r3, r0
|
|
80043ea: 001a movs r2, r3
|
|
80043ec: 4b29 ldr r3, [pc, #164] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80043ee: 825a strh r2, [r3, #18]
|
|
var.tps2 = var.tps2_adc * tps2_gain + tps2_offset;
|
|
80043f0: 4b28 ldr r3, [pc, #160] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
80043f2: 8a5b ldrh r3, [r3, #18]
|
|
80043f4: b29b uxth r3, r3
|
|
80043f6: 0018 movs r0, r3
|
|
80043f8: f7fc fffc bl 80013f4 <__aeabi_i2f>
|
|
80043fc: 1c02 adds r2, r0, #0
|
|
80043fe: 4b2c ldr r3, [pc, #176] @ (80044b0 <DBW_Read_sensors+0x22c>)
|
|
8004400: 681b ldr r3, [r3, #0]
|
|
8004402: 1c19 adds r1, r3, #0
|
|
8004404: 1c10 adds r0, r2, #0
|
|
8004406: f7fc fc41 bl 8000c8c <__aeabi_fmul>
|
|
800440a: 1c03 adds r3, r0, #0
|
|
800440c: 1c1a adds r2, r3, #0
|
|
800440e: 4b29 ldr r3, [pc, #164] @ (80044b4 <DBW_Read_sensors+0x230>)
|
|
8004410: 681b ldr r3, [r3, #0]
|
|
8004412: 1c19 adds r1, r3, #0
|
|
8004414: 1c10 adds r0, r2, #0
|
|
8004416: f7fc f85d bl 80004d4 <__aeabi_fadd>
|
|
800441a: 1c03 adds r3, r0, #0
|
|
800441c: 1c18 adds r0, r3, #0
|
|
800441e: f7fc ffc9 bl 80013b4 <__aeabi_f2iz>
|
|
8004422: 0003 movs r3, r0
|
|
8004424: b21a sxth r2, r3
|
|
8004426: 4b1b ldr r3, [pc, #108] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004428: 83da strh r2, [r3, #30]
|
|
|
|
// calculate tps and pps delta and values
|
|
var.tps_delta = var.tps1 - var.tps2;
|
|
800442a: 4b1a ldr r3, [pc, #104] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800442c: 8b9b ldrh r3, [r3, #28]
|
|
800442e: b21b sxth r3, r3
|
|
8004430: b29a uxth r2, r3
|
|
8004432: 4b18 ldr r3, [pc, #96] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004434: 8bdb ldrh r3, [r3, #30]
|
|
8004436: b21b sxth r3, r3
|
|
8004438: b29b uxth r3, r3
|
|
800443a: 1ad3 subs r3, r2, r3
|
|
800443c: b29b uxth r3, r3
|
|
800443e: b21a sxth r2, r3
|
|
8004440: 4b14 ldr r3, [pc, #80] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004442: 859a strh r2, [r3, #44] @ 0x2c
|
|
var.tps = (var.tps1 + var.tps2) >> 1;
|
|
8004444: 4b13 ldr r3, [pc, #76] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004446: 8b9b ldrh r3, [r3, #28]
|
|
8004448: b21b sxth r3, r3
|
|
800444a: 001a movs r2, r3
|
|
800444c: 4b11 ldr r3, [pc, #68] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800444e: 8bdb ldrh r3, [r3, #30]
|
|
8004450: b21b sxth r3, r3
|
|
8004452: 18d3 adds r3, r2, r3
|
|
8004454: 105b asrs r3, r3, #1
|
|
8004456: b21a sxth r2, r3
|
|
8004458: 4b0e ldr r3, [pc, #56] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800445a: 845a strh r2, [r3, #34] @ 0x22
|
|
|
|
var.pps_delta = var.pps1 - var.pps2;
|
|
800445c: 4b0d ldr r3, [pc, #52] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800445e: 8b1b ldrh r3, [r3, #24]
|
|
8004460: b21b sxth r3, r3
|
|
8004462: b29a uxth r2, r3
|
|
8004464: 4b0b ldr r3, [pc, #44] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004466: 8b5b ldrh r3, [r3, #26]
|
|
8004468: b21b sxth r3, r3
|
|
800446a: b29b uxth r3, r3
|
|
800446c: 1ad3 subs r3, r2, r3
|
|
800446e: b29b uxth r3, r3
|
|
8004470: b21a sxth r2, r3
|
|
8004472: 4b08 ldr r3, [pc, #32] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004474: 855a strh r2, [r3, #42] @ 0x2a
|
|
var.pps = (var.pps1 + var.pps2) >> 1;
|
|
8004476: 4b07 ldr r3, [pc, #28] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004478: 8b1b ldrh r3, [r3, #24]
|
|
800447a: b21b sxth r3, r3
|
|
800447c: 001a movs r2, r3
|
|
800447e: 4b05 ldr r3, [pc, #20] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
8004480: 8b5b ldrh r3, [r3, #26]
|
|
8004482: b21b sxth r3, r3
|
|
8004484: 18d3 adds r3, r2, r3
|
|
8004486: 105b asrs r3, r3, #1
|
|
8004488: b21a sxth r2, r3
|
|
800448a: 4b02 ldr r3, [pc, #8] @ (8004494 <DBW_Read_sensors+0x210>)
|
|
800448c: 841a strh r2, [r3, #32]
|
|
}
|
|
800448e: 46c0 nop @ (mov r8, r8)
|
|
8004490: 46bd mov sp, r7
|
|
8004492: bd80 pop {r7, pc}
|
|
8004494: 20000998 .word 0x20000998
|
|
8004498: 200009fc .word 0x200009fc
|
|
800449c: 20000a00 .word 0x20000a00
|
|
80044a0: 20000a04 .word 0x20000a04
|
|
80044a4: 20000a08 .word 0x20000a08
|
|
80044a8: 20000a0c .word 0x20000a0c
|
|
80044ac: 20000a10 .word 0x20000a10
|
|
80044b0: 20000a14 .word 0x20000a14
|
|
80044b4: 20000a18 .word 0x20000a18
|
|
|
|
080044b8 <__NVIC_EnableIRQ>:
|
|
{
|
|
80044b8: b580 push {r7, lr}
|
|
80044ba: b082 sub sp, #8
|
|
80044bc: af00 add r7, sp, #0
|
|
80044be: 0002 movs r2, r0
|
|
80044c0: 1dfb adds r3, r7, #7
|
|
80044c2: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80044c4: 1dfb adds r3, r7, #7
|
|
80044c6: 781b ldrb r3, [r3, #0]
|
|
80044c8: 2b7f cmp r3, #127 @ 0x7f
|
|
80044ca: d809 bhi.n 80044e0 <__NVIC_EnableIRQ+0x28>
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80044cc: 1dfb adds r3, r7, #7
|
|
80044ce: 781b ldrb r3, [r3, #0]
|
|
80044d0: 001a movs r2, r3
|
|
80044d2: 231f movs r3, #31
|
|
80044d4: 401a ands r2, r3
|
|
80044d6: 4b04 ldr r3, [pc, #16] @ (80044e8 <__NVIC_EnableIRQ+0x30>)
|
|
80044d8: 2101 movs r1, #1
|
|
80044da: 4091 lsls r1, r2
|
|
80044dc: 000a movs r2, r1
|
|
80044de: 601a str r2, [r3, #0]
|
|
}
|
|
80044e0: 46c0 nop @ (mov r8, r8)
|
|
80044e2: 46bd mov sp, r7
|
|
80044e4: b002 add sp, #8
|
|
80044e6: bd80 pop {r7, pc}
|
|
80044e8: e000e100 .word 0xe000e100
|
|
|
|
080044ec <TIM3_Init>:
|
|
#include "main.h"
|
|
//Variables
|
|
uint32_t counter0 = 0, counter1 = 0, Counter = 0;
|
|
uint8_t gap = 0;
|
|
// idle in section
|
|
void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3
|
|
80044ec: b580 push {r7, lr}
|
|
80044ee: af00 add r7, sp, #0
|
|
// PB4 AF1 TIM3 Input1
|
|
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
|
|
80044f0: 4b2e ldr r3, [pc, #184] @ (80045ac <TIM3_Init+0xc0>)
|
|
80044f2: 695a ldr r2, [r3, #20]
|
|
80044f4: 4b2d ldr r3, [pc, #180] @ (80045ac <TIM3_Init+0xc0>)
|
|
80044f6: 2180 movs r1, #128 @ 0x80
|
|
80044f8: 02c9 lsls r1, r1, #11
|
|
80044fa: 430a orrs r2, r1
|
|
80044fc: 615a str r2, [r3, #20]
|
|
GPIOB->MODER &= ~(3 << (4 * 2));
|
|
80044fe: 4b2c ldr r3, [pc, #176] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004500: 681a ldr r2, [r3, #0]
|
|
8004502: 4b2b ldr r3, [pc, #172] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004504: 492b ldr r1, [pc, #172] @ (80045b4 <TIM3_Init+0xc8>)
|
|
8004506: 400a ands r2, r1
|
|
8004508: 601a str r2, [r3, #0]
|
|
GPIOB->MODER |= (2 << (4 * 2));
|
|
800450a: 4b29 ldr r3, [pc, #164] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800450c: 681a ldr r2, [r3, #0]
|
|
800450e: 4b28 ldr r3, [pc, #160] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004510: 2180 movs r1, #128 @ 0x80
|
|
8004512: 0089 lsls r1, r1, #2
|
|
8004514: 430a orrs r2, r1
|
|
8004516: 601a str r2, [r3, #0]
|
|
GPIOB->OTYPER &= ~(1 << 4 * 1);
|
|
8004518: 4b25 ldr r3, [pc, #148] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800451a: 685a ldr r2, [r3, #4]
|
|
800451c: 4b24 ldr r3, [pc, #144] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800451e: 2110 movs r1, #16
|
|
8004520: 438a bics r2, r1
|
|
8004522: 605a str r2, [r3, #4]
|
|
GPIOB->OSPEEDR &= ~(3 << (4 * 2));
|
|
8004524: 4b22 ldr r3, [pc, #136] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004526: 689a ldr r2, [r3, #8]
|
|
8004528: 4b21 ldr r3, [pc, #132] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800452a: 4922 ldr r1, [pc, #136] @ (80045b4 <TIM3_Init+0xc8>)
|
|
800452c: 400a ands r2, r1
|
|
800452e: 609a str r2, [r3, #8]
|
|
GPIOB->PUPDR &= ~(3 << (4 * 2));
|
|
8004530: 4b1f ldr r3, [pc, #124] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004532: 68da ldr r2, [r3, #12]
|
|
8004534: 4b1e ldr r3, [pc, #120] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004536: 491f ldr r1, [pc, #124] @ (80045b4 <TIM3_Init+0xc8>)
|
|
8004538: 400a ands r2, r1
|
|
800453a: 60da str r2, [r3, #12]
|
|
GPIOB->AFR[0] &= ~(15 << (4 * 4));
|
|
800453c: 4b1c ldr r3, [pc, #112] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800453e: 6a1a ldr r2, [r3, #32]
|
|
8004540: 4b1b ldr r3, [pc, #108] @ (80045b0 <TIM3_Init+0xc4>)
|
|
8004542: 491d ldr r1, [pc, #116] @ (80045b8 <TIM3_Init+0xcc>)
|
|
8004544: 400a ands r2, r1
|
|
8004546: 621a str r2, [r3, #32]
|
|
GPIOB->AFR[0] |= (1 << (4 * 4));
|
|
8004548: 4b19 ldr r3, [pc, #100] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800454a: 6a1a ldr r2, [r3, #32]
|
|
800454c: 4b18 ldr r3, [pc, #96] @ (80045b0 <TIM3_Init+0xc4>)
|
|
800454e: 2180 movs r1, #128 @ 0x80
|
|
8004550: 0249 lsls r1, r1, #9
|
|
8004552: 430a orrs r2, r1
|
|
8004554: 621a str r2, [r3, #32]
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
|
|
8004556: 4b15 ldr r3, [pc, #84] @ (80045ac <TIM3_Init+0xc0>)
|
|
8004558: 69da ldr r2, [r3, #28]
|
|
800455a: 4b14 ldr r3, [pc, #80] @ (80045ac <TIM3_Init+0xc0>)
|
|
800455c: 2102 movs r1, #2
|
|
800455e: 430a orrs r2, r1
|
|
8004560: 61da str r2, [r3, #28]
|
|
select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
|
|
value),
|
|
select the falling edge on CC2 (CC2P = 1). */
|
|
/* (4) Enable interrupt on Capture/Compare 1 */
|
|
/* (5) Enable counter */
|
|
TIM3->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
|
|
8004562: 4b16 ldr r3, [pc, #88] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004564: 699a ldr r2, [r3, #24]
|
|
8004566: 4b15 ldr r3, [pc, #84] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004568: 4915 ldr r1, [pc, #84] @ (80045c0 <TIM3_Init+0xd4>)
|
|
800456a: 430a orrs r2, r1
|
|
800456c: 619a str r2, [r3, #24]
|
|
TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
|
|
800456e: 4b13 ldr r3, [pc, #76] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004570: 689a ldr r2, [r3, #8]
|
|
8004572: 4b12 ldr r3, [pc, #72] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004574: 2154 movs r1, #84 @ 0x54
|
|
8004576: 430a orrs r2, r1
|
|
8004578: 609a str r2, [r3, #8]
|
|
TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
|
|
800457a: 4b10 ldr r3, [pc, #64] @ (80045bc <TIM3_Init+0xd0>)
|
|
800457c: 6a1a ldr r2, [r3, #32]
|
|
800457e: 4b0f ldr r3, [pc, #60] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004580: 2131 movs r1, #49 @ 0x31
|
|
8004582: 430a orrs r2, r1
|
|
8004584: 621a str r2, [r3, #32]
|
|
TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */
|
|
8004586: 4b0d ldr r3, [pc, #52] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004588: 68da ldr r2, [r3, #12]
|
|
800458a: 4b0c ldr r3, [pc, #48] @ (80045bc <TIM3_Init+0xd0>)
|
|
800458c: 2102 movs r1, #2
|
|
800458e: 430a orrs r2, r1
|
|
8004590: 60da str r2, [r3, #12]
|
|
TIM3->CR1 |= TIM_CR1_CEN; /* (5) */
|
|
8004592: 4b0a ldr r3, [pc, #40] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004594: 681a ldr r2, [r3, #0]
|
|
8004596: 4b09 ldr r3, [pc, #36] @ (80045bc <TIM3_Init+0xd0>)
|
|
8004598: 2101 movs r1, #1
|
|
800459a: 430a orrs r2, r1
|
|
800459c: 601a str r2, [r3, #0]
|
|
NVIC_EnableIRQ(TIM3_IRQn);
|
|
800459e: 2010 movs r0, #16
|
|
80045a0: f7ff ff8a bl 80044b8 <__NVIC_EnableIRQ>
|
|
}
|
|
80045a4: 46c0 nop @ (mov r8, r8)
|
|
80045a6: 46bd mov sp, r7
|
|
80045a8: bd80 pop {r7, pc}
|
|
80045aa: 46c0 nop @ (mov r8, r8)
|
|
80045ac: 40021000 .word 0x40021000
|
|
80045b0: 48000400 .word 0x48000400
|
|
80045b4: fffffcff .word 0xfffffcff
|
|
80045b8: fff0ffff .word 0xfff0ffff
|
|
80045bc: 40000400 .word 0x40000400
|
|
80045c0: 00000201 .word 0x00000201
|
|
|
|
080045c4 <TIM14_Init>:
|
|
void TIM14_Init(void) { //configure IN2 as rpm input PB1 TIM14
|
|
80045c4: b580 push {r7, lr}
|
|
80045c6: af00 add r7, sp, #0
|
|
// PB1 AF0 TIM14 Input1
|
|
// prescaler 1:21 ->1/4uS tick (since APBx presc !=1, timer clocks = APBx_cls x 2)
|
|
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
|
|
80045c8: 4b2c ldr r3, [pc, #176] @ (800467c <TIM14_Init+0xb8>)
|
|
80045ca: 695a ldr r2, [r3, #20]
|
|
80045cc: 4b2b ldr r3, [pc, #172] @ (800467c <TIM14_Init+0xb8>)
|
|
80045ce: 2180 movs r1, #128 @ 0x80
|
|
80045d0: 02c9 lsls r1, r1, #11
|
|
80045d2: 430a orrs r2, r1
|
|
80045d4: 615a str r2, [r3, #20]
|
|
GPIOB->MODER &= ~(3 << (1 * 2));
|
|
80045d6: 4b2a ldr r3, [pc, #168] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045d8: 681a ldr r2, [r3, #0]
|
|
80045da: 4b29 ldr r3, [pc, #164] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045dc: 210c movs r1, #12
|
|
80045de: 438a bics r2, r1
|
|
80045e0: 601a str r2, [r3, #0]
|
|
GPIOB->MODER |= (2 << (1 * 2));
|
|
80045e2: 4b27 ldr r3, [pc, #156] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045e4: 681a ldr r2, [r3, #0]
|
|
80045e6: 4b26 ldr r3, [pc, #152] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045e8: 2108 movs r1, #8
|
|
80045ea: 430a orrs r2, r1
|
|
80045ec: 601a str r2, [r3, #0]
|
|
GPIOB->OTYPER &= ~(1 << 1 * 1);
|
|
80045ee: 4b24 ldr r3, [pc, #144] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045f0: 685a ldr r2, [r3, #4]
|
|
80045f2: 4b23 ldr r3, [pc, #140] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045f4: 2102 movs r1, #2
|
|
80045f6: 438a bics r2, r1
|
|
80045f8: 605a str r2, [r3, #4]
|
|
GPIOB->OSPEEDR &= ~(3 << (1 * 2));
|
|
80045fa: 4b21 ldr r3, [pc, #132] @ (8004680 <TIM14_Init+0xbc>)
|
|
80045fc: 689a ldr r2, [r3, #8]
|
|
80045fe: 4b20 ldr r3, [pc, #128] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004600: 210c movs r1, #12
|
|
8004602: 438a bics r2, r1
|
|
8004604: 609a str r2, [r3, #8]
|
|
GPIOB->PUPDR &= ~(3 << (1 * 2));
|
|
8004606: 4b1e ldr r3, [pc, #120] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004608: 68da ldr r2, [r3, #12]
|
|
800460a: 4b1d ldr r3, [pc, #116] @ (8004680 <TIM14_Init+0xbc>)
|
|
800460c: 210c movs r1, #12
|
|
800460e: 438a bics r2, r1
|
|
8004610: 60da str r2, [r3, #12]
|
|
GPIOB->AFR[0] &= ~(15 << (1 * 4));
|
|
8004612: 4b1b ldr r3, [pc, #108] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004614: 6a1a ldr r2, [r3, #32]
|
|
8004616: 4b1a ldr r3, [pc, #104] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004618: 21f0 movs r1, #240 @ 0xf0
|
|
800461a: 438a bics r2, r1
|
|
800461c: 621a str r2, [r3, #32]
|
|
GPIOB->AFR[0] |= (0 << (1 * 4));
|
|
800461e: 4a18 ldr r2, [pc, #96] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004620: 4b17 ldr r3, [pc, #92] @ (8004680 <TIM14_Init+0xbc>)
|
|
8004622: 6a12 ldr r2, [r2, #32]
|
|
8004624: 621a str r2, [r3, #32]
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
|
|
8004626: 4b15 ldr r3, [pc, #84] @ (800467c <TIM14_Init+0xb8>)
|
|
8004628: 69da ldr r2, [r3, #28]
|
|
800462a: 4b14 ldr r3, [pc, #80] @ (800467c <TIM14_Init+0xb8>)
|
|
800462c: 2180 movs r1, #128 @ 0x80
|
|
800462e: 0049 lsls r1, r1, #1
|
|
8004630: 430a orrs r2, r1
|
|
8004632: 61da str r2, [r3, #28]
|
|
TIM14->ARR = 0xFFFF;
|
|
8004634: 4b13 ldr r3, [pc, #76] @ (8004684 <TIM14_Init+0xc0>)
|
|
8004636: 4a14 ldr r2, [pc, #80] @ (8004688 <TIM14_Init+0xc4>)
|
|
8004638: 62da str r2, [r3, #44] @ 0x2c
|
|
TIM14->PSC = 599;
|
|
800463a: 4b12 ldr r3, [pc, #72] @ (8004684 <TIM14_Init+0xc0>)
|
|
800463c: 4a13 ldr r2, [pc, #76] @ (800468c <TIM14_Init+0xc8>)
|
|
800463e: 629a str r2, [r3, #40] @ 0x28
|
|
select the rising edge on CC1 (CC1P = 0, reset value)
|
|
and prescaler at each valid transition (IC1PS = 00, reset value) */
|
|
/* (2) Enable capture by setting CC1E */
|
|
/* (3) Enable interrupt on Capture/Compare */
|
|
/* (4) Enable counter */
|
|
TIM14->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
|
|
8004640: 4b10 ldr r3, [pc, #64] @ (8004684 <TIM14_Init+0xc0>)
|
|
8004642: 699a ldr r2, [r3, #24]
|
|
8004644: 4b0f ldr r3, [pc, #60] @ (8004684 <TIM14_Init+0xc0>)
|
|
8004646: 2131 movs r1, #49 @ 0x31
|
|
8004648: 430a orrs r2, r1
|
|
800464a: 619a str r2, [r3, #24]
|
|
TIM14->CCER |= TIM_CCER_CC1E; /* (2) */
|
|
800464c: 4b0d ldr r3, [pc, #52] @ (8004684 <TIM14_Init+0xc0>)
|
|
800464e: 6a1a ldr r2, [r3, #32]
|
|
8004650: 4b0c ldr r3, [pc, #48] @ (8004684 <TIM14_Init+0xc0>)
|
|
8004652: 2101 movs r1, #1
|
|
8004654: 430a orrs r2, r1
|
|
8004656: 621a str r2, [r3, #32]
|
|
TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */
|
|
8004658: 4b0a ldr r3, [pc, #40] @ (8004684 <TIM14_Init+0xc0>)
|
|
800465a: 68da ldr r2, [r3, #12]
|
|
800465c: 4b09 ldr r3, [pc, #36] @ (8004684 <TIM14_Init+0xc0>)
|
|
800465e: 2102 movs r1, #2
|
|
8004660: 430a orrs r2, r1
|
|
8004662: 60da str r2, [r3, #12]
|
|
TIM14->CR1 |= TIM_CR1_CEN; /* (4) */
|
|
8004664: 4b07 ldr r3, [pc, #28] @ (8004684 <TIM14_Init+0xc0>)
|
|
8004666: 681a ldr r2, [r3, #0]
|
|
8004668: 4b06 ldr r3, [pc, #24] @ (8004684 <TIM14_Init+0xc0>)
|
|
800466a: 2101 movs r1, #1
|
|
800466c: 430a orrs r2, r1
|
|
800466e: 601a str r2, [r3, #0]
|
|
NVIC_EnableIRQ(TIM14_IRQn);
|
|
8004670: 2013 movs r0, #19
|
|
8004672: f7ff ff21 bl 80044b8 <__NVIC_EnableIRQ>
|
|
}
|
|
8004676: 46c0 nop @ (mov r8, r8)
|
|
8004678: 46bd mov sp, r7
|
|
800467a: bd80 pop {r7, pc}
|
|
800467c: 40021000 .word 0x40021000
|
|
8004680: 48000400 .word 0x48000400
|
|
8004684: 40002000 .word 0x40002000
|
|
8004688: 0000ffff .word 0x0000ffff
|
|
800468c: 00000257 .word 0x00000257
|
|
|
|
08004690 <TIM3_IRQHandler>:
|
|
void TIM3_IRQHandler(void) {
|
|
8004690: b580 push {r7, lr}
|
|
8004692: af00 add r7, sp, #0
|
|
if ((TIM3->SR & TIM_SR_CC1IF) != 0) {
|
|
8004694: 4b15 ldr r3, [pc, #84] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
8004696: 691b ldr r3, [r3, #16]
|
|
8004698: 2202 movs r2, #2
|
|
800469a: 4013 ands r3, r2
|
|
800469c: d023 beq.n 80046e6 <TIM3_IRQHandler+0x56>
|
|
if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
|
|
800469e: 4b13 ldr r3, [pc, #76] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046a0: 691a ldr r2, [r3, #16]
|
|
80046a2: 2380 movs r3, #128 @ 0x80
|
|
80046a4: 009b lsls r3, r3, #2
|
|
80046a6: 4013 ands r3, r2
|
|
80046a8: d006 beq.n 80046b8 <TIM3_IRQHandler+0x28>
|
|
{
|
|
/* Overflow error management */
|
|
/* Reinitialize the laps computing */
|
|
TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
|
|
80046aa: 4b10 ldr r3, [pc, #64] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046ac: 691a ldr r2, [r3, #16]
|
|
80046ae: 4b0f ldr r3, [pc, #60] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046b0: 490f ldr r1, [pc, #60] @ (80046f0 <TIM3_IRQHandler+0x60>)
|
|
80046b2: 400a ands r2, r1
|
|
80046b4: 611a str r2, [r3, #16]
|
|
return;
|
|
80046b6: e016 b.n 80046e6 <TIM3_IRQHandler+0x56>
|
|
} else {
|
|
counter0 = TIM3->CCR1;
|
|
80046b8: 4b0c ldr r3, [pc, #48] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046ba: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80046bc: 4b0d ldr r3, [pc, #52] @ (80046f4 <TIM3_IRQHandler+0x64>)
|
|
80046be: 601a str r2, [r3, #0]
|
|
var.idle_dc = (TIM3->CCR2) * 1000 / TIM3->CCR1; //Get DC
|
|
80046c0: 4b0a ldr r3, [pc, #40] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046c2: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80046c4: 0013 movs r3, r2
|
|
80046c6: 015b lsls r3, r3, #5
|
|
80046c8: 1a9b subs r3, r3, r2
|
|
80046ca: 009b lsls r3, r3, #2
|
|
80046cc: 189b adds r3, r3, r2
|
|
80046ce: 00db lsls r3, r3, #3
|
|
80046d0: 001a movs r2, r3
|
|
80046d2: 4b06 ldr r3, [pc, #24] @ (80046ec <TIM3_IRQHandler+0x5c>)
|
|
80046d4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80046d6: 0019 movs r1, r3
|
|
80046d8: 0010 movs r0, r2
|
|
80046da: f7fb fd15 bl 8000108 <__udivsi3>
|
|
80046de: 0003 movs r3, r0
|
|
80046e0: b29a uxth r2, r3
|
|
80046e2: 4b05 ldr r3, [pc, #20] @ (80046f8 <TIM3_IRQHandler+0x68>)
|
|
80046e4: 851a strh r2, [r3, #40] @ 0x28
|
|
}
|
|
} else {
|
|
/* Unexpected Interrupt */
|
|
/* Manage an error for robust application */
|
|
}
|
|
}
|
|
80046e6: 46bd mov sp, r7
|
|
80046e8: bd80 pop {r7, pc}
|
|
80046ea: 46c0 nop @ (mov r8, r8)
|
|
80046ec: 40000400 .word 0x40000400
|
|
80046f0: fffffdfd .word 0xfffffdfd
|
|
80046f4: 20000a44 .word 0x20000a44
|
|
80046f8: 20000998 .word 0x20000998
|
|
|
|
080046fc <TIM14_IRQHandler>:
|
|
void TIM14_IRQHandler(void) {
|
|
80046fc: b580 push {r7, lr}
|
|
80046fe: af00 add r7, sp, #0
|
|
if ((TIM14->SR & TIM_SR_CC1IF) != 0) {
|
|
8004700: 4b25 ldr r3, [pc, #148] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
8004702: 691b ldr r3, [r3, #16]
|
|
8004704: 2202 movs r2, #2
|
|
8004706: 4013 ands r3, r2
|
|
8004708: d043 beq.n 8004792 <TIM14_IRQHandler+0x96>
|
|
if ((TIM14->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
|
|
800470a: 4b23 ldr r3, [pc, #140] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
800470c: 691a ldr r2, [r3, #16]
|
|
800470e: 2380 movs r3, #128 @ 0x80
|
|
8004710: 009b lsls r3, r3, #2
|
|
8004712: 4013 ands r3, r2
|
|
8004714: d00c beq.n 8004730 <TIM14_IRQHandler+0x34>
|
|
{
|
|
/* Overflow error management */
|
|
/* Reinitialize the laps computing */
|
|
TIM14->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
|
|
8004716: 4b20 ldr r3, [pc, #128] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
8004718: 691a ldr r2, [r3, #16]
|
|
800471a: 4b1f ldr r3, [pc, #124] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
800471c: 491f ldr r1, [pc, #124] @ (800479c <TIM14_IRQHandler+0xa0>)
|
|
800471e: 400a ands r2, r1
|
|
8004720: 611a str r2, [r3, #16]
|
|
var.rpm = 0;
|
|
8004722: 4b1f ldr r3, [pc, #124] @ (80047a0 <TIM14_IRQHandler+0xa4>)
|
|
8004724: 2200 movs r2, #0
|
|
8004726: 865a strh r2, [r3, #50] @ 0x32
|
|
gap = 0;
|
|
8004728: 4b1e ldr r3, [pc, #120] @ (80047a4 <TIM14_IRQHandler+0xa8>)
|
|
800472a: 2200 movs r2, #0
|
|
800472c: 701a strb r2, [r3, #0]
|
|
return;
|
|
800472e: e030 b.n 8004792 <TIM14_IRQHandler+0x96>
|
|
}
|
|
if (gap == 0) /* Test if it is the first rising edge */
|
|
8004730: 4b1c ldr r3, [pc, #112] @ (80047a4 <TIM14_IRQHandler+0xa8>)
|
|
8004732: 781b ldrb r3, [r3, #0]
|
|
8004734: 2b00 cmp r3, #0
|
|
8004736: d107 bne.n 8004748 <TIM14_IRQHandler+0x4c>
|
|
{
|
|
counter0 = TIM14->CCR1; /* Read the capture counter which clears the
|
|
8004738: 4b17 ldr r3, [pc, #92] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
800473a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800473c: 4b1a ldr r3, [pc, #104] @ (80047a8 <TIM14_IRQHandler+0xac>)
|
|
800473e: 601a str r2, [r3, #0]
|
|
CC1ICF */
|
|
gap = 1; /* Indicate that the first rising edge has yet been detected */
|
|
8004740: 4b18 ldr r3, [pc, #96] @ (80047a4 <TIM14_IRQHandler+0xa8>)
|
|
8004742: 2201 movs r2, #1
|
|
8004744: 701a strb r2, [r3, #0]
|
|
8004746: e024 b.n 8004792 <TIM14_IRQHandler+0x96>
|
|
} else {
|
|
counter1 = TIM14->CCR1; /* Read the capture counter which clears the
|
|
8004748: 4b13 ldr r3, [pc, #76] @ (8004798 <TIM14_IRQHandler+0x9c>)
|
|
800474a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800474c: 4b17 ldr r3, [pc, #92] @ (80047ac <TIM14_IRQHandler+0xb0>)
|
|
800474e: 601a str r2, [r3, #0]
|
|
CC1ICF */
|
|
if (counter1 > counter0) /* Check capture counter overflow */
|
|
8004750: 4b16 ldr r3, [pc, #88] @ (80047ac <TIM14_IRQHandler+0xb0>)
|
|
8004752: 681a ldr r2, [r3, #0]
|
|
8004754: 4b14 ldr r3, [pc, #80] @ (80047a8 <TIM14_IRQHandler+0xac>)
|
|
8004756: 681b ldr r3, [r3, #0]
|
|
8004758: 429a cmp r2, r3
|
|
800475a: d907 bls.n 800476c <TIM14_IRQHandler+0x70>
|
|
{
|
|
Counter = counter1 - counter0;
|
|
800475c: 4b13 ldr r3, [pc, #76] @ (80047ac <TIM14_IRQHandler+0xb0>)
|
|
800475e: 681a ldr r2, [r3, #0]
|
|
8004760: 4b11 ldr r3, [pc, #68] @ (80047a8 <TIM14_IRQHandler+0xac>)
|
|
8004762: 681b ldr r3, [r3, #0]
|
|
8004764: 1ad2 subs r2, r2, r3
|
|
8004766: 4b12 ldr r3, [pc, #72] @ (80047b0 <TIM14_IRQHandler+0xb4>)
|
|
8004768: 601a str r2, [r3, #0]
|
|
800476a: e009 b.n 8004780 <TIM14_IRQHandler+0x84>
|
|
} else {
|
|
Counter = counter1 + 0xFFFF - counter0 + 1;
|
|
800476c: 4b0f ldr r3, [pc, #60] @ (80047ac <TIM14_IRQHandler+0xb0>)
|
|
800476e: 681a ldr r2, [r3, #0]
|
|
8004770: 4b0d ldr r3, [pc, #52] @ (80047a8 <TIM14_IRQHandler+0xac>)
|
|
8004772: 681b ldr r3, [r3, #0]
|
|
8004774: 1ad3 subs r3, r2, r3
|
|
8004776: 2280 movs r2, #128 @ 0x80
|
|
8004778: 0252 lsls r2, r2, #9
|
|
800477a: 189a adds r2, r3, r2
|
|
800477c: 4b0c ldr r3, [pc, #48] @ (80047b0 <TIM14_IRQHandler+0xb4>)
|
|
800477e: 601a str r2, [r3, #0]
|
|
}
|
|
counter0 = counter1;
|
|
8004780: 4b0a ldr r3, [pc, #40] @ (80047ac <TIM14_IRQHandler+0xb0>)
|
|
8004782: 681a ldr r2, [r3, #0]
|
|
8004784: 4b08 ldr r3, [pc, #32] @ (80047a8 <TIM14_IRQHandler+0xac>)
|
|
8004786: 601a str r2, [r3, #0]
|
|
var.rpm = Counter;
|
|
8004788: 4b09 ldr r3, [pc, #36] @ (80047b0 <TIM14_IRQHandler+0xb4>)
|
|
800478a: 681b ldr r3, [r3, #0]
|
|
800478c: b29a uxth r2, r3
|
|
800478e: 4b04 ldr r3, [pc, #16] @ (80047a0 <TIM14_IRQHandler+0xa4>)
|
|
8004790: 865a strh r2, [r3, #50] @ 0x32
|
|
}
|
|
} else {
|
|
/* Unexpected Interrupt */
|
|
/* Manage an error for robust application */
|
|
}
|
|
}
|
|
8004792: 46bd mov sp, r7
|
|
8004794: bd80 pop {r7, pc}
|
|
8004796: 46c0 nop @ (mov r8, r8)
|
|
8004798: 40002000 .word 0x40002000
|
|
800479c: fffffdfd .word 0xfffffdfd
|
|
80047a0: 20000998 .word 0x20000998
|
|
80047a4: 20000a50 .word 0x20000a50
|
|
80047a8: 20000a44 .word 0x20000a44
|
|
80047ac: 20000a48 .word 0x20000a48
|
|
80047b0: 20000a4c .word 0x20000a4c
|
|
|
|
080047b4 <__NVIC_EnableIRQ>:
|
|
{
|
|
80047b4: b580 push {r7, lr}
|
|
80047b6: b082 sub sp, #8
|
|
80047b8: af00 add r7, sp, #0
|
|
80047ba: 0002 movs r2, r0
|
|
80047bc: 1dfb adds r3, r7, #7
|
|
80047be: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80047c0: 1dfb adds r3, r7, #7
|
|
80047c2: 781b ldrb r3, [r3, #0]
|
|
80047c4: 2b7f cmp r3, #127 @ 0x7f
|
|
80047c6: d809 bhi.n 80047dc <__NVIC_EnableIRQ+0x28>
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80047c8: 1dfb adds r3, r7, #7
|
|
80047ca: 781b ldrb r3, [r3, #0]
|
|
80047cc: 001a movs r2, r3
|
|
80047ce: 231f movs r3, #31
|
|
80047d0: 401a ands r2, r3
|
|
80047d2: 4b04 ldr r3, [pc, #16] @ (80047e4 <__NVIC_EnableIRQ+0x30>)
|
|
80047d4: 2101 movs r1, #1
|
|
80047d6: 4091 lsls r1, r2
|
|
80047d8: 000a movs r2, r1
|
|
80047da: 601a str r2, [r3, #0]
|
|
}
|
|
80047dc: 46c0 nop @ (mov r8, r8)
|
|
80047de: 46bd mov sp, r7
|
|
80047e0: b002 add sp, #8
|
|
80047e2: bd80 pop {r7, pc}
|
|
80047e4: e000e100 .word 0xe000e100
|
|
|
|
080047e8 <main>:
|
|
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void) {
|
|
80047e8: b580 push {r7, lr}
|
|
80047ea: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
80047ec: f002 f824 bl 8006838 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
80047f0: f000 f90c bl 8004a0c <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
80047f4: f000 fa3c bl 8004c70 <MX_GPIO_Init>
|
|
MX_ADC_Init();
|
|
80047f8: f000 f96e bl 8004ad8 <MX_ADC_Init>
|
|
// MX_CAN_Init();
|
|
MX_USART1_UART_Init();
|
|
80047fc: f000 fa08 bl 8004c10 <MX_USART1_UART_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
//load flash copy of config to RAM
|
|
// memcpy((void*)&config_ram,(void*)(0x0800F000), sizeof(config_t));
|
|
memcpy((void*) &config_ram, (void*) &config_flash, sizeof(config_t));
|
|
8004800: 4a7a ldr r2, [pc, #488] @ (80049ec <main+0x204>)
|
|
8004802: 4b7b ldr r3, [pc, #492] @ (80049f0 <main+0x208>)
|
|
8004804: 0010 movs r0, r2
|
|
8004806: 0019 movs r1, r3
|
|
8004808: 23d6 movs r3, #214 @ 0xd6
|
|
800480a: 009b lsls r3, r3, #2
|
|
800480c: 001a movs r2, r3
|
|
800480e: f004 f8ab bl 8008968 <memcpy>
|
|
config = &config_ram;
|
|
8004812: 4b78 ldr r3, [pc, #480] @ (80049f4 <main+0x20c>)
|
|
8004814: 4a75 ldr r2, [pc, #468] @ (80049ec <main+0x204>)
|
|
8004816: 601a str r2, [r3, #0]
|
|
|
|
//calculate gain and offset for PPS and TPS calc
|
|
Apply_Sensor_Calibration();
|
|
8004818: f7fe fc10 bl 800303c <Apply_Sensor_Calibration>
|
|
config->config_bits &= ~CONFIG_TESTMODE_F;
|
|
800481c: 4b75 ldr r3, [pc, #468] @ (80049f4 <main+0x20c>)
|
|
800481e: 681b ldr r3, [r3, #0]
|
|
8004820: 4a75 ldr r2, [pc, #468] @ (80049f8 <main+0x210>)
|
|
8004822: 5a9b ldrh r3, [r3, r2]
|
|
8004824: b29a uxth r2, r3
|
|
8004826: 4b73 ldr r3, [pc, #460] @ (80049f4 <main+0x20c>)
|
|
8004828: 681b ldr r3, [r3, #0]
|
|
800482a: 2104 movs r1, #4
|
|
800482c: 438a bics r2, r1
|
|
800482e: b291 uxth r1, r2
|
|
8004830: 4a71 ldr r2, [pc, #452] @ (80049f8 <main+0x210>)
|
|
8004832: 5299 strh r1, [r3, r2]
|
|
|
|
//clear momms
|
|
memset((void*) &var, 0, sizeof(var_t));
|
|
8004834: 4b71 ldr r3, [pc, #452] @ (80049fc <main+0x214>)
|
|
8004836: 2234 movs r2, #52 @ 0x34
|
|
8004838: 2100 movs r1, #0
|
|
800483a: 0018 movs r0, r3
|
|
800483c: f004 f868 bl 8008910 <memset>
|
|
//Initialize TS Comms
|
|
Comms_Init();
|
|
8004840: f001 fb98 bl 8005f74 <Comms_Init>
|
|
NVIC_EnableIRQ(USART1_IRQn);
|
|
8004844: 201b movs r0, #27
|
|
8004846: f7ff ffb5 bl 80047b4 <__NVIC_EnableIRQ>
|
|
|
|
// check if safety features are enabled
|
|
if (config->config_bits & CONFIG_SAFETY_FEATURES_F) {
|
|
800484a: 4b6a ldr r3, [pc, #424] @ (80049f4 <main+0x20c>)
|
|
800484c: 681b ldr r3, [r3, #0]
|
|
800484e: 4a6a ldr r2, [pc, #424] @ (80049f8 <main+0x210>)
|
|
8004850: 5a9b ldrh r3, [r3, r2]
|
|
8004852: b29b uxth r3, r3
|
|
8004854: 001a movs r2, r3
|
|
8004856: 2308 movs r3, #8
|
|
8004858: 4013 ands r3, r2
|
|
800485a: d00c beq.n 8004876 <main+0x8e>
|
|
Check_Safety_Limits();
|
|
800485c: f000 fd6a bl 8005334 <Check_Safety_Limits>
|
|
Safety_TPS_Safety_Timer_Start();
|
|
8004860: f001 f9a6 bl 8005bb0 <Safety_TPS_Safety_Timer_Start>
|
|
//TODO Watch_Dog_Init();
|
|
// change status
|
|
var.status1 |= DBW_STATUS1_SAFETY_F;
|
|
8004864: 4b65 ldr r3, [pc, #404] @ (80049fc <main+0x214>)
|
|
8004866: 88db ldrh r3, [r3, #6]
|
|
8004868: b29b uxth r3, r3
|
|
800486a: 2201 movs r2, #1
|
|
800486c: 4313 orrs r3, r2
|
|
800486e: b29a uxth r2, r3
|
|
8004870: 4b62 ldr r3, [pc, #392] @ (80049fc <main+0x214>)
|
|
8004872: 80da strh r2, [r3, #6]
|
|
8004874: e007 b.n 8004886 <main+0x9e>
|
|
}
|
|
// if not change status to safy disabled
|
|
else
|
|
var.status1 &= ~DBW_STATUS1_SAFETY_F;
|
|
8004876: 4b61 ldr r3, [pc, #388] @ (80049fc <main+0x214>)
|
|
8004878: 88db ldrh r3, [r3, #6]
|
|
800487a: b29b uxth r3, r3
|
|
800487c: 2201 movs r2, #1
|
|
800487e: 4393 bics r3, r2
|
|
8004880: b29a uxth r2, r3
|
|
8004882: 4b5e ldr r3, [pc, #376] @ (80049fc <main+0x214>)
|
|
8004884: 80da strh r2, [r3, #6]
|
|
|
|
// Check if CAN has to be initialized
|
|
if ((config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN)
|
|
8004886: 4b5b ldr r3, [pc, #364] @ (80049f4 <main+0x20c>)
|
|
8004888: 681b ldr r3, [r3, #0]
|
|
800488a: 7e9b ldrb r3, [r3, #26]
|
|
800488c: b2db uxtb r3, r3
|
|
800488e: 2b01 cmp r3, #1
|
|
8004890: d009 beq.n 80048a6 <main+0xbe>
|
|
|| (config->idle_input_option == IDLE_OPTION_MS_CAN)
|
|
8004892: 4b58 ldr r3, [pc, #352] @ (80049f4 <main+0x20c>)
|
|
8004894: 681b ldr r3, [r3, #0]
|
|
8004896: 7edb ldrb r3, [r3, #27]
|
|
8004898: b2db uxtb r3, r3
|
|
800489a: 2b03 cmp r3, #3
|
|
800489c: d003 beq.n 80048a6 <main+0xbe>
|
|
|| config->can_ms29bit_options == 0x01) {
|
|
800489e: 4b55 ldr r3, [pc, #340] @ (80049f4 <main+0x20c>)
|
|
80048a0: 681b ldr r3, [r3, #0]
|
|
80048a2: 4a57 ldr r2, [pc, #348] @ (8004a00 <main+0x218>)
|
|
80048a4: 5c9b ldrb r3, [r3, r2]
|
|
// Can_Init();
|
|
|
|
}
|
|
if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) {
|
|
80048a6: 4b53 ldr r3, [pc, #332] @ (80049f4 <main+0x20c>)
|
|
80048a8: 681b ldr r3, [r3, #0]
|
|
80048aa: 7edb ldrb r3, [r3, #27]
|
|
80048ac: b2db uxtb r3, r3
|
|
80048ae: 2b01 cmp r3, #1
|
|
80048b0: d101 bne.n 80048b6 <main+0xce>
|
|
TIM3_Init();
|
|
80048b2: f7ff fe1b bl 80044ec <TIM3_Init>
|
|
}
|
|
if (1) {
|
|
TIM14_Init(); //rpm input init
|
|
80048b6: f7ff fe85 bl 80045c4 <TIM14_Init>
|
|
TIM16_Init(); // vss out init
|
|
80048ba: f000 fc79 bl 80051b0 <TIM16_Init>
|
|
TIM17_Init(); //Mazda rx8 can message init
|
|
80048be: f000 fcb1 bl 8005224 <TIM17_Init>
|
|
}
|
|
Adc_Init();
|
|
80048c2: f7fd ff17 bl 80026f4 <Adc_Init>
|
|
DBW_Init();
|
|
80048c6: f7fe fcc3 bl 8003250 <DBW_Init>
|
|
DBW_Pwm_Init();
|
|
80048ca: f7ff f82d bl 8003928 <DBW_Pwm_Init>
|
|
|
|
//check if program flash is write protected and set status
|
|
if (FLASH->WRPR & 0x00003FFF)
|
|
80048ce: 4b4d ldr r3, [pc, #308] @ (8004a04 <main+0x21c>)
|
|
80048d0: 6a1b ldr r3, [r3, #32]
|
|
80048d2: 049b lsls r3, r3, #18
|
|
80048d4: 0c9b lsrs r3, r3, #18
|
|
80048d6: d009 beq.n 80048ec <main+0x104>
|
|
var.status0 |= DBW_STATUS0_UNPROTECTED_F;
|
|
80048d8: 4b48 ldr r3, [pc, #288] @ (80049fc <main+0x214>)
|
|
80048da: 889b ldrh r3, [r3, #4]
|
|
80048dc: b29b uxth r3, r3
|
|
80048de: 2280 movs r2, #128 @ 0x80
|
|
80048e0: 0152 lsls r2, r2, #5
|
|
80048e2: 4313 orrs r3, r2
|
|
80048e4: b29a uxth r2, r3
|
|
80048e6: 4b45 ldr r3, [pc, #276] @ (80049fc <main+0x214>)
|
|
80048e8: 809a strh r2, [r3, #4]
|
|
80048ea: e007 b.n 80048fc <main+0x114>
|
|
else
|
|
var.status0 &= ~DBW_STATUS0_UNPROTECTED_F;
|
|
80048ec: 4b43 ldr r3, [pc, #268] @ (80049fc <main+0x214>)
|
|
80048ee: 889b ldrh r3, [r3, #4]
|
|
80048f0: b29b uxth r3, r3
|
|
80048f2: 4a45 ldr r2, [pc, #276] @ (8004a08 <main+0x220>)
|
|
80048f4: 4013 ands r3, r2
|
|
80048f6: b29a uxth r2, r3
|
|
80048f8: 4b40 ldr r3, [pc, #256] @ (80049fc <main+0x214>)
|
|
80048fa: 809a strh r2, [r3, #4]
|
|
|
|
//check if agreement is set if so start DBW drive
|
|
if (config->config_bits & CONFIG_AGREEMENT_F) {
|
|
80048fc: 4b3d ldr r3, [pc, #244] @ (80049f4 <main+0x20c>)
|
|
80048fe: 681b ldr r3, [r3, #0]
|
|
8004900: 4a3d ldr r2, [pc, #244] @ (80049f8 <main+0x210>)
|
|
8004902: 5a9b ldrh r3, [r3, r2]
|
|
8004904: b29b uxth r3, r3
|
|
8004906: 001a movs r2, r3
|
|
8004908: 2301 movs r3, #1
|
|
800490a: 4013 ands r3, r2
|
|
800490c: d008 beq.n 8004920 <main+0x138>
|
|
var.status0 |= DBW_STATUS0_AGREEMENT_F;
|
|
800490e: 4b3b ldr r3, [pc, #236] @ (80049fc <main+0x214>)
|
|
8004910: 889b ldrh r3, [r3, #4]
|
|
8004912: b29b uxth r3, r3
|
|
8004914: 2202 movs r2, #2
|
|
8004916: 4313 orrs r3, r2
|
|
8004918: b29a uxth r2, r3
|
|
800491a: 4b38 ldr r3, [pc, #224] @ (80049fc <main+0x214>)
|
|
800491c: 809a strh r2, [r3, #4]
|
|
800491e: e007 b.n 8004930 <main+0x148>
|
|
} else
|
|
var.status0 &= ~DBW_STATUS0_AGREEMENT_F;
|
|
8004920: 4b36 ldr r3, [pc, #216] @ (80049fc <main+0x214>)
|
|
8004922: 889b ldrh r3, [r3, #4]
|
|
8004924: b29b uxth r3, r3
|
|
8004926: 2202 movs r2, #2
|
|
8004928: 4393 bics r3, r2
|
|
800492a: b29a uxth r2, r3
|
|
800492c: 4b33 ldr r3, [pc, #204] @ (80049fc <main+0x214>)
|
|
800492e: 809a strh r2, [r3, #4]
|
|
|
|
// check if TPS and PPS are calibrated
|
|
|
|
if (config->config_bits & CONFIG_SENSORS_CALIBRATED_F) {
|
|
8004930: 4b30 ldr r3, [pc, #192] @ (80049f4 <main+0x20c>)
|
|
8004932: 681b ldr r3, [r3, #0]
|
|
8004934: 4a30 ldr r2, [pc, #192] @ (80049f8 <main+0x210>)
|
|
8004936: 5a9b ldrh r3, [r3, r2]
|
|
8004938: b29b uxth r3, r3
|
|
800493a: 001a movs r2, r3
|
|
800493c: 2302 movs r3, #2
|
|
800493e: 4013 ands r3, r2
|
|
8004940: d008 beq.n 8004954 <main+0x16c>
|
|
var.status0 |= DBW_STATUS0_SENSOR_CAL_F;
|
|
8004942: 4b2e ldr r3, [pc, #184] @ (80049fc <main+0x214>)
|
|
8004944: 889b ldrh r3, [r3, #4]
|
|
8004946: b29b uxth r3, r3
|
|
8004948: 2204 movs r2, #4
|
|
800494a: 4313 orrs r3, r2
|
|
800494c: b29a uxth r2, r3
|
|
800494e: 4b2b ldr r3, [pc, #172] @ (80049fc <main+0x214>)
|
|
8004950: 809a strh r2, [r3, #4]
|
|
8004952: e007 b.n 8004964 <main+0x17c>
|
|
}
|
|
|
|
else {
|
|
var.status0 &= ~DBW_STATUS0_SENSOR_CAL_F;
|
|
8004954: 4b29 ldr r3, [pc, #164] @ (80049fc <main+0x214>)
|
|
8004956: 889b ldrh r3, [r3, #4]
|
|
8004958: b29b uxth r3, r3
|
|
800495a: 2204 movs r2, #4
|
|
800495c: 4393 bics r3, r2
|
|
800495e: b29a uxth r2, r3
|
|
8004960: 4b26 ldr r3, [pc, #152] @ (80049fc <main+0x214>)
|
|
8004962: 809a strh r2, [r3, #4]
|
|
}
|
|
|
|
// start DBW if sensors are calibrated and agreement is accepted
|
|
if ((var.status0 & DBW_STATUS0_AGREEMENT_F)
|
|
8004964: 4b25 ldr r3, [pc, #148] @ (80049fc <main+0x214>)
|
|
8004966: 889b ldrh r3, [r3, #4]
|
|
8004968: b29b uxth r3, r3
|
|
800496a: 001a movs r2, r3
|
|
800496c: 2302 movs r3, #2
|
|
800496e: 4013 ands r3, r2
|
|
8004970: d009 beq.n 8004986 <main+0x19e>
|
|
&& (var.status0 & DBW_STATUS0_SENSOR_CAL_F)) {
|
|
8004972: 4b22 ldr r3, [pc, #136] @ (80049fc <main+0x214>)
|
|
8004974: 889b ldrh r3, [r3, #4]
|
|
8004976: b29b uxth r3, r3
|
|
8004978: 001a movs r2, r3
|
|
800497a: 2304 movs r3, #4
|
|
800497c: 4013 ands r3, r2
|
|
800497e: d002 beq.n 8004986 <main+0x19e>
|
|
DBW_Start();
|
|
8004980: f7ff fb48 bl 8004014 <DBW_Start>
|
|
8004984: e001 b.n 800498a <main+0x1a2>
|
|
} else
|
|
DBW_Stop();
|
|
8004986: f7ff fb5b bl 8004040 <DBW_Stop>
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1) {
|
|
/* USER CODE END WHILE */
|
|
|
|
// is something to be transmitted on serial
|
|
Poll_Tx();
|
|
800498a: f001 fd85 bl 8006498 <Poll_Tx>
|
|
|
|
// Update WDT and check ADC range if safety features are enabled
|
|
if ((var.status1 & DBW_STATUS1_SAFETY_F) && var.clock > 1000) {
|
|
800498e: 4b1b ldr r3, [pc, #108] @ (80049fc <main+0x214>)
|
|
8004990: 88db ldrh r3, [r3, #6]
|
|
8004992: b29b uxth r3, r3
|
|
8004994: 001a movs r2, r3
|
|
8004996: 2301 movs r3, #1
|
|
8004998: 4013 ands r3, r2
|
|
800499a: d009 beq.n 80049b0 <main+0x1c8>
|
|
800499c: 4b17 ldr r3, [pc, #92] @ (80049fc <main+0x214>)
|
|
800499e: 681a ldr r2, [r3, #0]
|
|
80049a0: 23fa movs r3, #250 @ 0xfa
|
|
80049a2: 009b lsls r3, r3, #2
|
|
80049a4: 429a cmp r2, r3
|
|
80049a6: d903 bls.n 80049b0 <main+0x1c8>
|
|
//TODO Watch_Dog_Update();
|
|
Check_Adc_Range();
|
|
80049a8: f000 fe5e bl 8005668 <Check_Adc_Range>
|
|
Check_TPS_Target();
|
|
80049ac: f001 f922 bl 8005bf4 <Check_TPS_Target>
|
|
}
|
|
|
|
//check if tesmode is turned on
|
|
if (config->config_bits & CONFIG_TESTMODE_F) {
|
|
80049b0: 4b10 ldr r3, [pc, #64] @ (80049f4 <main+0x20c>)
|
|
80049b2: 681b ldr r3, [r3, #0]
|
|
80049b4: 4a10 ldr r2, [pc, #64] @ (80049f8 <main+0x210>)
|
|
80049b6: 5a9b ldrh r3, [r3, r2]
|
|
80049b8: b29b uxth r3, r3
|
|
80049ba: 001a movs r2, r3
|
|
80049bc: 2304 movs r3, #4
|
|
80049be: 4013 ands r3, r2
|
|
80049c0: d00c beq.n 80049dc <main+0x1f4>
|
|
var.status0 &= ~DBW_STATUS0_READY_F;
|
|
80049c2: 4b0e ldr r3, [pc, #56] @ (80049fc <main+0x214>)
|
|
80049c4: 889b ldrh r3, [r3, #4]
|
|
80049c6: b29b uxth r3, r3
|
|
80049c8: 2201 movs r2, #1
|
|
80049ca: 4393 bics r3, r2
|
|
80049cc: b29a uxth r2, r3
|
|
80049ce: 4b0b ldr r3, [pc, #44] @ (80049fc <main+0x214>)
|
|
80049d0: 809a strh r2, [r3, #4]
|
|
DBW_TPS_AutoCal();
|
|
80049d2: f7ff fb4b bl 800406c <DBW_TPS_AutoCal>
|
|
DBW_Read_sensors();
|
|
80049d6: f7ff fc55 bl 8004284 <DBW_Read_sensors>
|
|
80049da: e001 b.n 80049e0 <main+0x1f8>
|
|
} else {
|
|
DBW_Process();
|
|
80049dc: f7fe fc82 bl 80032e4 <DBW_Process>
|
|
}
|
|
|
|
CAN_Send_TX_Buffer();
|
|
80049e0: f7fe f830 bl 8002a44 <CAN_Send_TX_Buffer>
|
|
if (1) {
|
|
MAZDA_CAN_Read();
|
|
80049e4: f000 fb54 bl 8005090 <MAZDA_CAN_Read>
|
|
Poll_Tx();
|
|
80049e8: e7cf b.n 800498a <main+0x1a2>
|
|
80049ea: 46c0 nop @ (mov r8, r8)
|
|
80049ec: 20000640 .word 0x20000640
|
|
80049f0: 0800f000 .word 0x0800f000
|
|
80049f4: 200009cc .word 0x200009cc
|
|
80049f8: 0000033a .word 0x0000033a
|
|
80049fc: 20000998 .word 0x20000998
|
|
8004a00: 00000353 .word 0x00000353
|
|
8004a04: 40022000 .word 0x40022000
|
|
8004a08: ffffefff .word 0xffffefff
|
|
|
|
08004a0c <SystemClock_Config>:
|
|
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void) {
|
|
8004a0c: b590 push {r4, r7, lr}
|
|
8004a0e: b099 sub sp, #100 @ 0x64
|
|
8004a10: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
|
|
8004a12: 242c movs r4, #44 @ 0x2c
|
|
8004a14: 193b adds r3, r7, r4
|
|
8004a16: 0018 movs r0, r3
|
|
8004a18: 2334 movs r3, #52 @ 0x34
|
|
8004a1a: 001a movs r2, r3
|
|
8004a1c: 2100 movs r1, #0
|
|
8004a1e: f003 ff77 bl 8008910 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
|
|
8004a22: 231c movs r3, #28
|
|
8004a24: 18fb adds r3, r7, r3
|
|
8004a26: 0018 movs r0, r3
|
|
8004a28: 2310 movs r3, #16
|
|
8004a2a: 001a movs r2, r3
|
|
8004a2c: 2100 movs r1, #0
|
|
8004a2e: f003 ff6f bl 8008910 <memset>
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
|
|
8004a32: 003b movs r3, r7
|
|
8004a34: 0018 movs r0, r3
|
|
8004a36: 231c movs r3, #28
|
|
8004a38: 001a movs r2, r3
|
|
8004a3a: 2100 movs r1, #0
|
|
8004a3c: f003 ff68 bl 8008910 <memset>
|
|
|
|
/** Initializes the CPU, AHB and APB busses clocks
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI14
|
|
8004a40: 0021 movs r1, r4
|
|
8004a42: 187b adds r3, r7, r1
|
|
8004a44: 2211 movs r2, #17
|
|
8004a46: 601a str r2, [r3, #0]
|
|
| RCC_OSCILLATORTYPE_HSE;
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8004a48: 187b adds r3, r7, r1
|
|
8004a4a: 2201 movs r2, #1
|
|
8004a4c: 605a str r2, [r3, #4]
|
|
RCC_OscInitStruct.HSI14State = RCC_HSI14_ON;
|
|
8004a4e: 187b adds r3, r7, r1
|
|
8004a50: 2201 movs r2, #1
|
|
8004a52: 615a str r2, [r3, #20]
|
|
RCC_OscInitStruct.HSI14CalibrationValue = 16;
|
|
8004a54: 187b adds r3, r7, r1
|
|
8004a56: 2210 movs r2, #16
|
|
8004a58: 619a str r2, [r3, #24]
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8004a5a: 187b adds r3, r7, r1
|
|
8004a5c: 2202 movs r2, #2
|
|
8004a5e: 625a str r2, [r3, #36] @ 0x24
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
8004a60: 187b adds r3, r7, r1
|
|
8004a62: 2280 movs r2, #128 @ 0x80
|
|
8004a64: 0252 lsls r2, r2, #9
|
|
8004a66: 629a str r2, [r3, #40] @ 0x28
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
|
8004a68: 187b adds r3, r7, r1
|
|
8004a6a: 22a0 movs r2, #160 @ 0xa0
|
|
8004a6c: 0392 lsls r2, r2, #14
|
|
8004a6e: 62da str r2, [r3, #44] @ 0x2c
|
|
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
|
|
8004a70: 187b adds r3, r7, r1
|
|
8004a72: 2201 movs r2, #1
|
|
8004a74: 631a str r2, [r3, #48] @ 0x30
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
|
8004a76: 187b adds r3, r7, r1
|
|
8004a78: 0018 movs r0, r3
|
|
8004a7a: f002 fdf5 bl 8007668 <HAL_RCC_OscConfig>
|
|
8004a7e: 1e03 subs r3, r0, #0
|
|
8004a80: d001 beq.n 8004a86 <SystemClock_Config+0x7a>
|
|
Error_Handler();
|
|
8004a82: f000 f94d bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Initializes the CPU, AHB and APB busses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
|
8004a86: 211c movs r1, #28
|
|
8004a88: 187b adds r3, r7, r1
|
|
8004a8a: 2207 movs r2, #7
|
|
8004a8c: 601a str r2, [r3, #0]
|
|
| RCC_CLOCKTYPE_PCLK1;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8004a8e: 187b adds r3, r7, r1
|
|
8004a90: 2202 movs r2, #2
|
|
8004a92: 605a str r2, [r3, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8004a94: 187b adds r3, r7, r1
|
|
8004a96: 2200 movs r2, #0
|
|
8004a98: 609a str r2, [r3, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8004a9a: 187b adds r3, r7, r1
|
|
8004a9c: 2200 movs r2, #0
|
|
8004a9e: 60da str r2, [r3, #12]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
|
|
8004aa0: 187b adds r3, r7, r1
|
|
8004aa2: 2101 movs r1, #1
|
|
8004aa4: 0018 movs r0, r3
|
|
8004aa6: f003 f965 bl 8007d74 <HAL_RCC_ClockConfig>
|
|
8004aaa: 1e03 subs r3, r0, #0
|
|
8004aac: d001 beq.n 8004ab2 <SystemClock_Config+0xa6>
|
|
Error_Handler();
|
|
8004aae: f000 f937 bl 8004d20 <Error_Handler>
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
8004ab2: 003b movs r3, r7
|
|
8004ab4: 2201 movs r2, #1
|
|
8004ab6: 601a str r2, [r3, #0]
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
|
|
8004ab8: 003b movs r3, r7
|
|
8004aba: 2200 movs r2, #0
|
|
8004abc: 609a str r2, [r3, #8]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
|
|
8004abe: 003b movs r3, r7
|
|
8004ac0: 0018 movs r0, r3
|
|
8004ac2: f003 fad1 bl 8008068 <HAL_RCCEx_PeriphCLKConfig>
|
|
8004ac6: 1e03 subs r3, r0, #0
|
|
8004ac8: d001 beq.n 8004ace <SystemClock_Config+0xc2>
|
|
Error_Handler();
|
|
8004aca: f000 f929 bl 8004d20 <Error_Handler>
|
|
}
|
|
}
|
|
8004ace: 46c0 nop @ (mov r8, r8)
|
|
8004ad0: 46bd mov sp, r7
|
|
8004ad2: b019 add sp, #100 @ 0x64
|
|
8004ad4: bd90 pop {r4, r7, pc}
|
|
...
|
|
|
|
08004ad8 <MX_ADC_Init>:
|
|
/**
|
|
* @brief ADC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC_Init(void) {
|
|
8004ad8: b580 push {r7, lr}
|
|
8004ada: b084 sub sp, #16
|
|
8004adc: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC_Init 0 */
|
|
|
|
/* USER CODE END ADC_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = { 0 };
|
|
8004ade: 1d3b adds r3, r7, #4
|
|
8004ae0: 0018 movs r0, r3
|
|
8004ae2: 230c movs r3, #12
|
|
8004ae4: 001a movs r2, r3
|
|
8004ae6: 2100 movs r1, #0
|
|
8004ae8: f003 ff12 bl 8008910 <memset>
|
|
/* USER CODE BEGIN ADC_Init 1 */
|
|
|
|
/* USER CODE END ADC_Init 1 */
|
|
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
|
|
*/
|
|
hadc.Instance = ADC1;
|
|
8004aec: 4b46 ldr r3, [pc, #280] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004aee: 4a47 ldr r2, [pc, #284] @ (8004c0c <MX_ADC_Init+0x134>)
|
|
8004af0: 601a str r2, [r3, #0]
|
|
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
|
|
8004af2: 4b45 ldr r3, [pc, #276] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004af4: 2200 movs r2, #0
|
|
8004af6: 605a str r2, [r3, #4]
|
|
hadc.Init.Resolution = ADC_RESOLUTION_12B;
|
|
8004af8: 4b43 ldr r3, [pc, #268] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004afa: 2200 movs r2, #0
|
|
8004afc: 609a str r2, [r3, #8]
|
|
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8004afe: 4b42 ldr r3, [pc, #264] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b00: 2200 movs r2, #0
|
|
8004b02: 60da str r2, [r3, #12]
|
|
hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
|
|
8004b04: 4b40 ldr r3, [pc, #256] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b06: 2201 movs r2, #1
|
|
8004b08: 611a str r2, [r3, #16]
|
|
hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
8004b0a: 4b3f ldr r3, [pc, #252] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b0c: 2204 movs r2, #4
|
|
8004b0e: 615a str r2, [r3, #20]
|
|
hadc.Init.LowPowerAutoWait = DISABLE;
|
|
8004b10: 4b3d ldr r3, [pc, #244] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b12: 2200 movs r2, #0
|
|
8004b14: 761a strb r2, [r3, #24]
|
|
hadc.Init.LowPowerAutoPowerOff = DISABLE;
|
|
8004b16: 4b3c ldr r3, [pc, #240] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b18: 2200 movs r2, #0
|
|
8004b1a: 765a strb r2, [r3, #25]
|
|
hadc.Init.ContinuousConvMode = DISABLE;
|
|
8004b1c: 4b3a ldr r3, [pc, #232] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b1e: 2200 movs r2, #0
|
|
8004b20: 769a strb r2, [r3, #26]
|
|
hadc.Init.DiscontinuousConvMode = DISABLE;
|
|
8004b22: 4b39 ldr r3, [pc, #228] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b24: 2200 movs r2, #0
|
|
8004b26: 76da strb r2, [r3, #27]
|
|
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8004b28: 4b37 ldr r3, [pc, #220] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b2a: 22c2 movs r2, #194 @ 0xc2
|
|
8004b2c: 32ff adds r2, #255 @ 0xff
|
|
8004b2e: 61da str r2, [r3, #28]
|
|
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
8004b30: 4b35 ldr r3, [pc, #212] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b32: 2200 movs r2, #0
|
|
8004b34: 621a str r2, [r3, #32]
|
|
hadc.Init.DMAContinuousRequests = DISABLE;
|
|
8004b36: 4b34 ldr r3, [pc, #208] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b38: 2224 movs r2, #36 @ 0x24
|
|
8004b3a: 2100 movs r1, #0
|
|
8004b3c: 5499 strb r1, [r3, r2]
|
|
hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED;
|
|
8004b3e: 4b32 ldr r3, [pc, #200] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b40: 2201 movs r2, #1
|
|
8004b42: 629a str r2, [r3, #40] @ 0x28
|
|
if (HAL_ADC_Init(&hadc) != HAL_OK) {
|
|
8004b44: 4b30 ldr r3, [pc, #192] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b46: 0018 movs r0, r3
|
|
8004b48: f001 feda bl 8006900 <HAL_ADC_Init>
|
|
8004b4c: 1e03 subs r3, r0, #0
|
|
8004b4e: d001 beq.n 8004b54 <MX_ADC_Init+0x7c>
|
|
Error_Handler();
|
|
8004b50: f000 f8e6 bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_0;
|
|
8004b54: 1d3b adds r3, r7, #4
|
|
8004b56: 2200 movs r2, #0
|
|
8004b58: 601a str r2, [r3, #0]
|
|
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
|
|
8004b5a: 1d3b adds r3, r7, #4
|
|
8004b5c: 2280 movs r2, #128 @ 0x80
|
|
8004b5e: 0152 lsls r2, r2, #5
|
|
8004b60: 605a str r2, [r3, #4]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
|
8004b62: 1d3b adds r3, r7, #4
|
|
8004b64: 2280 movs r2, #128 @ 0x80
|
|
8004b66: 0552 lsls r2, r2, #21
|
|
8004b68: 609a str r2, [r3, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004b6a: 1d3a adds r2, r7, #4
|
|
8004b6c: 4b26 ldr r3, [pc, #152] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b6e: 0011 movs r1, r2
|
|
8004b70: 0018 movs r0, r3
|
|
8004b72: f002 f805 bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004b76: 1e03 subs r3, r0, #0
|
|
8004b78: d001 beq.n 8004b7e <MX_ADC_Init+0xa6>
|
|
Error_Handler();
|
|
8004b7a: f000 f8d1 bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_1;
|
|
8004b7e: 1d3b adds r3, r7, #4
|
|
8004b80: 2201 movs r2, #1
|
|
8004b82: 601a str r2, [r3, #0]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004b84: 1d3a adds r2, r7, #4
|
|
8004b86: 4b20 ldr r3, [pc, #128] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004b88: 0011 movs r1, r2
|
|
8004b8a: 0018 movs r0, r3
|
|
8004b8c: f001 fff8 bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004b90: 1e03 subs r3, r0, #0
|
|
8004b92: d001 beq.n 8004b98 <MX_ADC_Init+0xc0>
|
|
Error_Handler();
|
|
8004b94: f000 f8c4 bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_2;
|
|
8004b98: 1d3b adds r3, r7, #4
|
|
8004b9a: 2202 movs r2, #2
|
|
8004b9c: 601a str r2, [r3, #0]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004b9e: 1d3a adds r2, r7, #4
|
|
8004ba0: 4b19 ldr r3, [pc, #100] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004ba2: 0011 movs r1, r2
|
|
8004ba4: 0018 movs r0, r3
|
|
8004ba6: f001 ffeb bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004baa: 1e03 subs r3, r0, #0
|
|
8004bac: d001 beq.n 8004bb2 <MX_ADC_Init+0xda>
|
|
Error_Handler();
|
|
8004bae: f000 f8b7 bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_3;
|
|
8004bb2: 1d3b adds r3, r7, #4
|
|
8004bb4: 2203 movs r2, #3
|
|
8004bb6: 601a str r2, [r3, #0]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004bb8: 1d3a adds r2, r7, #4
|
|
8004bba: 4b13 ldr r3, [pc, #76] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004bbc: 0011 movs r1, r2
|
|
8004bbe: 0018 movs r0, r3
|
|
8004bc0: f001 ffde bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004bc4: 1e03 subs r3, r0, #0
|
|
8004bc6: d001 beq.n 8004bcc <MX_ADC_Init+0xf4>
|
|
Error_Handler();
|
|
8004bc8: f000 f8aa bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_4;
|
|
8004bcc: 1d3b adds r3, r7, #4
|
|
8004bce: 2204 movs r2, #4
|
|
8004bd0: 601a str r2, [r3, #0]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004bd2: 1d3a adds r2, r7, #4
|
|
8004bd4: 4b0c ldr r3, [pc, #48] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004bd6: 0011 movs r1, r2
|
|
8004bd8: 0018 movs r0, r3
|
|
8004bda: f001 ffd1 bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004bde: 1e03 subs r3, r0, #0
|
|
8004be0: d001 beq.n 8004be6 <MX_ADC_Init+0x10e>
|
|
Error_Handler();
|
|
8004be2: f000 f89d bl 8004d20 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel to be converted.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_5;
|
|
8004be6: 1d3b adds r3, r7, #4
|
|
8004be8: 2205 movs r2, #5
|
|
8004bea: 601a str r2, [r3, #0]
|
|
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) {
|
|
8004bec: 1d3a adds r2, r7, #4
|
|
8004bee: 4b06 ldr r3, [pc, #24] @ (8004c08 <MX_ADC_Init+0x130>)
|
|
8004bf0: 0011 movs r1, r2
|
|
8004bf2: 0018 movs r0, r3
|
|
8004bf4: f001 ffc4 bl 8006b80 <HAL_ADC_ConfigChannel>
|
|
8004bf8: 1e03 subs r3, r0, #0
|
|
8004bfa: d001 beq.n 8004c00 <MX_ADC_Init+0x128>
|
|
Error_Handler();
|
|
8004bfc: f000 f890 bl 8004d20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC_Init 2 */
|
|
|
|
/* USER CODE END ADC_Init 2 */
|
|
|
|
}
|
|
8004c00: 46c0 nop @ (mov r8, r8)
|
|
8004c02: 46bd mov sp, r7
|
|
8004c04: b004 add sp, #16
|
|
8004c06: bd80 pop {r7, pc}
|
|
8004c08: 20000a54 .word 0x20000a54
|
|
8004c0c: 40012400 .word 0x40012400
|
|
|
|
08004c10 <MX_USART1_UART_Init>:
|
|
/**
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void) {
|
|
8004c10: b580 push {r7, lr}
|
|
8004c12: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8004c14: 4b14 ldr r3, [pc, #80] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c16: 4a15 ldr r2, [pc, #84] @ (8004c6c <MX_USART1_UART_Init+0x5c>)
|
|
8004c18: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8004c1a: 4b13 ldr r3, [pc, #76] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c1c: 22e1 movs r2, #225 @ 0xe1
|
|
8004c1e: 0252 lsls r2, r2, #9
|
|
8004c20: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8004c22: 4b11 ldr r3, [pc, #68] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c24: 2200 movs r2, #0
|
|
8004c26: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8004c28: 4b0f ldr r3, [pc, #60] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c2a: 2200 movs r2, #0
|
|
8004c2c: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8004c2e: 4b0e ldr r3, [pc, #56] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c30: 2200 movs r2, #0
|
|
8004c32: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8004c34: 4b0c ldr r3, [pc, #48] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c36: 220c movs r2, #12
|
|
8004c38: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8004c3a: 4b0b ldr r3, [pc, #44] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c3c: 2200 movs r2, #0
|
|
8004c3e: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8004c40: 4b09 ldr r3, [pc, #36] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c42: 2200 movs r2, #0
|
|
8004c44: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8004c46: 4b08 ldr r3, [pc, #32] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c48: 2200 movs r2, #0
|
|
8004c4a: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8004c4c: 4b06 ldr r3, [pc, #24] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c4e: 2200 movs r2, #0
|
|
8004c50: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK) {
|
|
8004c52: 4b05 ldr r3, [pc, #20] @ (8004c68 <MX_USART1_UART_Init+0x58>)
|
|
8004c54: 0018 movs r0, r3
|
|
8004c56: f003 fb05 bl 8008264 <HAL_UART_Init>
|
|
8004c5a: 1e03 subs r3, r0, #0
|
|
8004c5c: d001 beq.n 8004c62 <MX_USART1_UART_Init+0x52>
|
|
Error_Handler();
|
|
8004c5e: f000 f85f bl 8004d20 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8004c62: 46c0 nop @ (mov r8, r8)
|
|
8004c64: 46bd mov sp, r7
|
|
8004c66: bd80 pop {r7, pc}
|
|
8004c68: 20000a94 .word 0x20000a94
|
|
8004c6c: 40013800 .word 0x40013800
|
|
|
|
08004c70 <MX_GPIO_Init>:
|
|
/**
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void) {
|
|
8004c70: b590 push {r4, r7, lr}
|
|
8004c72: b089 sub sp, #36 @ 0x24
|
|
8004c74: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
|
|
8004c76: 240c movs r4, #12
|
|
8004c78: 193b adds r3, r7, r4
|
|
8004c7a: 0018 movs r0, r3
|
|
8004c7c: 2314 movs r3, #20
|
|
8004c7e: 001a movs r2, r3
|
|
8004c80: 2100 movs r1, #0
|
|
8004c82: f003 fe45 bl 8008910 <memset>
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8004c86: 4b23 ldr r3, [pc, #140] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004c88: 695a ldr r2, [r3, #20]
|
|
8004c8a: 4b22 ldr r3, [pc, #136] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004c8c: 2180 movs r1, #128 @ 0x80
|
|
8004c8e: 03c9 lsls r1, r1, #15
|
|
8004c90: 430a orrs r2, r1
|
|
8004c92: 615a str r2, [r3, #20]
|
|
8004c94: 4b1f ldr r3, [pc, #124] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004c96: 695a ldr r2, [r3, #20]
|
|
8004c98: 2380 movs r3, #128 @ 0x80
|
|
8004c9a: 03db lsls r3, r3, #15
|
|
8004c9c: 4013 ands r3, r2
|
|
8004c9e: 60bb str r3, [r7, #8]
|
|
8004ca0: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8004ca2: 4b1c ldr r3, [pc, #112] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004ca4: 695a ldr r2, [r3, #20]
|
|
8004ca6: 4b1b ldr r3, [pc, #108] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004ca8: 2180 movs r1, #128 @ 0x80
|
|
8004caa: 0289 lsls r1, r1, #10
|
|
8004cac: 430a orrs r2, r1
|
|
8004cae: 615a str r2, [r3, #20]
|
|
8004cb0: 4b18 ldr r3, [pc, #96] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004cb2: 695a ldr r2, [r3, #20]
|
|
8004cb4: 2380 movs r3, #128 @ 0x80
|
|
8004cb6: 029b lsls r3, r3, #10
|
|
8004cb8: 4013 ands r3, r2
|
|
8004cba: 607b str r3, [r7, #4]
|
|
8004cbc: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8004cbe: 4b15 ldr r3, [pc, #84] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004cc0: 695a ldr r2, [r3, #20]
|
|
8004cc2: 4b14 ldr r3, [pc, #80] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004cc4: 2180 movs r1, #128 @ 0x80
|
|
8004cc6: 02c9 lsls r1, r1, #11
|
|
8004cc8: 430a orrs r2, r1
|
|
8004cca: 615a str r2, [r3, #20]
|
|
8004ccc: 4b11 ldr r3, [pc, #68] @ (8004d14 <MX_GPIO_Init+0xa4>)
|
|
8004cce: 695a ldr r2, [r3, #20]
|
|
8004cd0: 2380 movs r3, #128 @ 0x80
|
|
8004cd2: 02db lsls r3, r3, #11
|
|
8004cd4: 4013 ands r3, r2
|
|
8004cd6: 603b str r3, [r7, #0]
|
|
8004cd8: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB,
|
|
8004cda: 490f ldr r1, [pc, #60] @ (8004d18 <MX_GPIO_Init+0xa8>)
|
|
8004cdc: 4b0f ldr r3, [pc, #60] @ (8004d1c <MX_GPIO_Init+0xac>)
|
|
8004cde: 2200 movs r2, #0
|
|
8004ce0: 0018 movs r0, r3
|
|
8004ce2: f002 fc89 bl 80075f8 <HAL_GPIO_WritePin>
|
|
// GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
// GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
/*Configure GPIO pins : PWM1_Pin PWM2_Pin FAULT_Pin D2_Pin
|
|
D1_Pin GPO1_Pin GPO2_1_Pin GPO2_2_Pin */
|
|
GPIO_InitStruct.Pin = PWM1_Pin | PWM2_Pin | FAULT_Pin | D2_Pin | D1_Pin
|
|
8004ce6: 0021 movs r1, r4
|
|
8004ce8: 187b adds r3, r7, r1
|
|
8004cea: 4a0b ldr r2, [pc, #44] @ (8004d18 <MX_GPIO_Init+0xa8>)
|
|
8004cec: 601a str r2, [r3, #0]
|
|
| GPO1_Pin | GPO2_1_Pin | GPO2_2_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8004cee: 187b adds r3, r7, r1
|
|
8004cf0: 2201 movs r2, #1
|
|
8004cf2: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004cf4: 187b adds r3, r7, r1
|
|
8004cf6: 2200 movs r2, #0
|
|
8004cf8: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004cfa: 187b adds r3, r7, r1
|
|
8004cfc: 2200 movs r2, #0
|
|
8004cfe: 60da str r2, [r3, #12]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8004d00: 187b adds r3, r7, r1
|
|
8004d02: 4a06 ldr r2, [pc, #24] @ (8004d1c <MX_GPIO_Init+0xac>)
|
|
8004d04: 0019 movs r1, r3
|
|
8004d06: 0010 movs r0, r2
|
|
8004d08: f002 fafe bl 8007308 <HAL_GPIO_Init>
|
|
|
|
}
|
|
8004d0c: 46c0 nop @ (mov r8, r8)
|
|
8004d0e: 46bd mov sp, r7
|
|
8004d10: b009 add sp, #36 @ 0x24
|
|
8004d12: bd90 pop {r4, r7, pc}
|
|
8004d14: 40021000 .word 0x40021000
|
|
8004d18: 00007ce0 .word 0x00007ce0
|
|
8004d1c: 48000400 .word 0x48000400
|
|
|
|
08004d20 <Error_Handler>:
|
|
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void) {
|
|
8004d20: b580 push {r7, lr}
|
|
8004d22: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
|
|
/* USER CODE END Error_Handler_Debug */
|
|
}
|
|
8004d24: 46c0 nop @ (mov r8, r8)
|
|
8004d26: 46bd mov sp, r7
|
|
8004d28: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004d2c <MAZDA_Send_Data>:
|
|
*/
|
|
#include "main.h"
|
|
uint32_t var_time = 0, rpm_time = 0, can_tim = 0;
|
|
can_msg_typedef tmpCanMsg;
|
|
//https://www.chamberofunderstanding.co.uk/2021/06/11/rx8-project-part-21-canbus-6-working-code/
|
|
void MAZDA_Send_Data(void) {
|
|
8004d2c: b580 push {r7, lr}
|
|
8004d2e: af00 add r7, sp, #0
|
|
can_tim++;
|
|
8004d30: 4bcd ldr r3, [pc, #820] @ (8005068 <MAZDA_Send_Data+0x33c>)
|
|
8004d32: 681b ldr r3, [r3, #0]
|
|
8004d34: 1c5a adds r2, r3, #1
|
|
8004d36: 4bcc ldr r3, [pc, #816] @ (8005068 <MAZDA_Send_Data+0x33c>)
|
|
8004d38: 601a str r2, [r3, #0]
|
|
tmpCanMsg.id = 0x201; // Send RPM = Actual RPM * 3.85 Throttle Pedal 0x00 - 0xC8 in 0.5% increments Send KPH = (Actual KPH * 100) + 10000
|
|
8004d3a: 4bcc ldr r3, [pc, #816] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004d3c: 4acc ldr r2, [pc, #816] @ (8005070 <MAZDA_Send_Data+0x344>)
|
|
8004d3e: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004d40: 4bca ldr r3, [pc, #808] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004d42: 2200 movs r2, #0
|
|
8004d44: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004d46: 4bc9 ldr r3, [pc, #804] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004d48: 2200 movs r2, #0
|
|
8004d4a: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 7;
|
|
8004d4c: 4bc7 ldr r3, [pc, #796] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004d4e: 2207 movs r2, #7
|
|
8004d50: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = (((uint16_t) (var.rpm * 3.85)) >> 8); // RPM high
|
|
8004d52: 4bc8 ldr r3, [pc, #800] @ (8005074 <MAZDA_Send_Data+0x348>)
|
|
8004d54: 8e5b ldrh r3, [r3, #50] @ 0x32
|
|
8004d56: b29b uxth r3, r3
|
|
8004d58: 0018 movs r0, r3
|
|
8004d5a: f7fd fb1d bl 8002398 <__aeabi_i2d>
|
|
8004d5e: 4ac6 ldr r2, [pc, #792] @ (8005078 <MAZDA_Send_Data+0x34c>)
|
|
8004d60: 4bc6 ldr r3, [pc, #792] @ (800507c <MAZDA_Send_Data+0x350>)
|
|
8004d62: f7fc fbdd bl 8001520 <__aeabi_dmul>
|
|
8004d66: 0002 movs r2, r0
|
|
8004d68: 000b movs r3, r1
|
|
8004d6a: 0010 movs r0, r2
|
|
8004d6c: 0019 movs r1, r3
|
|
8004d6e: f7fb fb93 bl 8000498 <__aeabi_d2uiz>
|
|
8004d72: 0003 movs r3, r0
|
|
8004d74: b29b uxth r3, r3
|
|
8004d76: 0a1b lsrs r3, r3, #8
|
|
8004d78: b29b uxth r3, r3
|
|
8004d7a: b2da uxtb r2, r3
|
|
8004d7c: 4bbb ldr r3, [pc, #748] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004d7e: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = (uint8_t) ((var.rpm) * 3.85); // RPM low
|
|
8004d80: 4bbc ldr r3, [pc, #752] @ (8005074 <MAZDA_Send_Data+0x348>)
|
|
8004d82: 8e5b ldrh r3, [r3, #50] @ 0x32
|
|
8004d84: b29b uxth r3, r3
|
|
8004d86: 0018 movs r0, r3
|
|
8004d88: f7fd fb06 bl 8002398 <__aeabi_i2d>
|
|
8004d8c: 4aba ldr r2, [pc, #744] @ (8005078 <MAZDA_Send_Data+0x34c>)
|
|
8004d8e: 4bbb ldr r3, [pc, #748] @ (800507c <MAZDA_Send_Data+0x350>)
|
|
8004d90: f7fc fbc6 bl 8001520 <__aeabi_dmul>
|
|
8004d94: 0002 movs r2, r0
|
|
8004d96: 000b movs r3, r1
|
|
8004d98: 0010 movs r0, r2
|
|
8004d9a: 0019 movs r1, r3
|
|
8004d9c: f7fb fb7c bl 8000498 <__aeabi_d2uiz>
|
|
8004da0: 0003 movs r3, r0
|
|
8004da2: b2da uxtb r2, r3
|
|
8004da4: 4bb1 ldr r3, [pc, #708] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004da6: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0xFF;
|
|
8004da8: 4bb0 ldr r3, [pc, #704] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004daa: 22ff movs r2, #255 @ 0xff
|
|
8004dac: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0xFF;
|
|
8004dae: 4baf ldr r3, [pc, #700] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004db0: 22ff movs r2, #255 @ 0xff
|
|
8004db2: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = (var.vss * 100 + 10000) >> 8; // VSS KPH high
|
|
8004db4: 4baf ldr r3, [pc, #700] @ (8005074 <MAZDA_Send_Data+0x348>)
|
|
8004db6: 8e1b ldrh r3, [r3, #48] @ 0x30
|
|
8004db8: b29b uxth r3, r3
|
|
8004dba: 001a movs r2, r3
|
|
8004dbc: 2364 movs r3, #100 @ 0x64
|
|
8004dbe: 4353 muls r3, r2
|
|
8004dc0: 4aaf ldr r2, [pc, #700] @ (8005080 <MAZDA_Send_Data+0x354>)
|
|
8004dc2: 4694 mov ip, r2
|
|
8004dc4: 4463 add r3, ip
|
|
8004dc6: 121b asrs r3, r3, #8
|
|
8004dc8: b2da uxtb r2, r3
|
|
8004dca: 4ba8 ldr r3, [pc, #672] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004dcc: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = (var.vss * 100 + 10000); // VSS KPH low
|
|
8004dce: 4ba9 ldr r3, [pc, #676] @ (8005074 <MAZDA_Send_Data+0x348>)
|
|
8004dd0: 8e1b ldrh r3, [r3, #48] @ 0x30
|
|
8004dd2: b29b uxth r3, r3
|
|
8004dd4: b2db uxtb r3, r3
|
|
8004dd6: 2264 movs r2, #100 @ 0x64
|
|
8004dd8: 4353 muls r3, r2
|
|
8004dda: b2db uxtb r3, r3
|
|
8004ddc: 3310 adds r3, #16
|
|
8004dde: b2da uxtb r2, r3
|
|
8004de0: 4ba2 ldr r3, [pc, #648] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004de2: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = var.pps / 5; // TPS
|
|
8004de4: 4ba3 ldr r3, [pc, #652] @ (8005074 <MAZDA_Send_Data+0x348>)
|
|
8004de6: 8c1b ldrh r3, [r3, #32]
|
|
8004de8: b21b sxth r3, r3
|
|
8004dea: 2105 movs r1, #5
|
|
8004dec: 0018 movs r0, r3
|
|
8004dee: f7fb fa15 bl 800021c <__divsi3>
|
|
8004df2: 0003 movs r3, r0
|
|
8004df4: b21b sxth r3, r3
|
|
8004df6: b2da uxtb r2, r3
|
|
8004df8: 4b9c ldr r3, [pc, #624] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004dfa: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0xFF;
|
|
8004dfc: 4b9b ldr r3, [pc, #620] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004dfe: 22ff movs r2, #255 @ 0xff
|
|
8004e00: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004e02: 4b9a ldr r3, [pc, #616] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e04: 0018 movs r0, r3
|
|
8004e06: f7fd fe55 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
|
|
tmpCanMsg.id = 0x250;
|
|
8004e0a: 4b98 ldr r3, [pc, #608] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e0c: 2294 movs r2, #148 @ 0x94
|
|
8004e0e: 0092 lsls r2, r2, #2
|
|
8004e10: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004e12: 4b96 ldr r3, [pc, #600] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e14: 2200 movs r2, #0
|
|
8004e16: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004e18: 4b94 ldr r3, [pc, #592] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e1a: 2200 movs r2, #0
|
|
8004e1c: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 8;
|
|
8004e1e: 4b93 ldr r3, [pc, #588] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e20: 2208 movs r2, #8
|
|
8004e22: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x00;
|
|
8004e24: 4b91 ldr r3, [pc, #580] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e26: 2200 movs r2, #0
|
|
8004e28: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0x00;
|
|
8004e2a: 4b90 ldr r3, [pc, #576] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e2c: 2200 movs r2, #0
|
|
8004e2e: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0xCF;
|
|
8004e30: 4b8e ldr r3, [pc, #568] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e32: 22cf movs r2, #207 @ 0xcf
|
|
8004e34: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x87;
|
|
8004e36: 4b8d ldr r3, [pc, #564] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e38: 2287 movs r2, #135 @ 0x87
|
|
8004e3a: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x7F;
|
|
8004e3c: 4b8b ldr r3, [pc, #556] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e3e: 227f movs r2, #127 @ 0x7f
|
|
8004e40: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 0x83;
|
|
8004e42: 4b8a ldr r3, [pc, #552] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e44: 2283 movs r2, #131 @ 0x83
|
|
8004e46: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x00;
|
|
8004e48: 4b88 ldr r3, [pc, #544] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e4a: 2200 movs r2, #0
|
|
8004e4c: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0x00;
|
|
8004e4e: 4b87 ldr r3, [pc, #540] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e50: 2200 movs r2, #0
|
|
8004e52: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004e54: 4b85 ldr r3, [pc, #532] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e56: 0018 movs r0, r3
|
|
8004e58: f7fd fe2c bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
|
|
tmpCanMsg.id = 0x620; // Type of ABS
|
|
8004e5c: 4b83 ldr r3, [pc, #524] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e5e: 22c4 movs r2, #196 @ 0xc4
|
|
8004e60: 00d2 lsls r2, r2, #3
|
|
8004e62: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004e64: 4b81 ldr r3, [pc, #516] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e66: 2200 movs r2, #0
|
|
8004e68: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004e6a: 4b80 ldr r3, [pc, #512] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e6c: 2200 movs r2, #0
|
|
8004e6e: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 1;
|
|
8004e70: 4b7e ldr r3, [pc, #504] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e72: 2201 movs r2, #1
|
|
8004e74: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x00;
|
|
8004e76: 4b7d ldr r3, [pc, #500] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e78: 2200 movs r2, #0
|
|
8004e7a: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0x00;
|
|
8004e7c: 4b7b ldr r3, [pc, #492] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e7e: 2200 movs r2, #0
|
|
8004e80: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0x00;
|
|
8004e82: 4b7a ldr r3, [pc, #488] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e84: 2200 movs r2, #0
|
|
8004e86: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x00;
|
|
8004e88: 4b78 ldr r3, [pc, #480] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e8a: 2200 movs r2, #0
|
|
8004e8c: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x00;
|
|
8004e8e: 4b77 ldr r3, [pc, #476] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e90: 2200 movs r2, #0
|
|
8004e92: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 0x00;
|
|
8004e94: 4b75 ldr r3, [pc, #468] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e96: 2200 movs r2, #0
|
|
8004e98: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x02; // ABS type 2,3 or 4
|
|
8004e9a: 4b74 ldr r3, [pc, #464] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004e9c: 2202 movs r2, #2
|
|
8004e9e: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0x00;
|
|
8004ea0: 4b72 ldr r3, [pc, #456] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ea2: 2200 movs r2, #0
|
|
8004ea4: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004ea6: 4b71 ldr r3, [pc, #452] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ea8: 0018 movs r0, r3
|
|
8004eaa: f7fd fe03 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
tmpCanMsg.id = 0x630; // Type of Transmission and Wheel Size
|
|
8004eae: 4b6f ldr r3, [pc, #444] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004eb0: 22c6 movs r2, #198 @ 0xc6
|
|
8004eb2: 00d2 lsls r2, r2, #3
|
|
8004eb4: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004eb6: 4b6d ldr r3, [pc, #436] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004eb8: 2200 movs r2, #0
|
|
8004eba: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004ebc: 4b6b ldr r3, [pc, #428] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ebe: 2200 movs r2, #0
|
|
8004ec0: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 1;
|
|
8004ec2: 4b6a ldr r3, [pc, #424] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ec4: 2201 movs r2, #1
|
|
8004ec6: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x08; //8 = MT, 2 = AT
|
|
8004ec8: 4b68 ldr r3, [pc, #416] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004eca: 2208 movs r2, #8
|
|
8004ecc: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0x00;
|
|
8004ece: 4b67 ldr r3, [pc, #412] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ed0: 2200 movs r2, #0
|
|
8004ed2: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0x00;
|
|
8004ed4: 4b65 ldr r3, [pc, #404] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ed6: 2200 movs r2, #0
|
|
8004ed8: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x00;
|
|
8004eda: 4b64 ldr r3, [pc, #400] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004edc: 2200 movs r2, #0
|
|
8004ede: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x00;
|
|
8004ee0: 4b62 ldr r3, [pc, #392] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ee2: 2200 movs r2, #0
|
|
8004ee4: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 0x00;
|
|
8004ee6: 4b61 ldr r3, [pc, #388] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ee8: 2200 movs r2, #0
|
|
8004eea: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x6A; // Wheel Size
|
|
8004eec: 4b5f ldr r3, [pc, #380] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004eee: 226a movs r2, #106 @ 0x6a
|
|
8004ef0: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0x6A; // Wheel Size
|
|
8004ef2: 4b5e ldr r3, [pc, #376] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ef4: 226a movs r2, #106 @ 0x6a
|
|
8004ef6: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004ef8: 4b5c ldr r3, [pc, #368] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004efa: 0018 movs r0, r3
|
|
8004efc: f7fd fdda bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
tmpCanMsg.id = 0x650; // CRUISE CONTROL
|
|
8004f00: 4b5a ldr r3, [pc, #360] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f02: 22ca movs r2, #202 @ 0xca
|
|
8004f04: 00d2 lsls r2, r2, #3
|
|
8004f06: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004f08: 4b58 ldr r3, [pc, #352] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f0a: 2200 movs r2, #0
|
|
8004f0c: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004f0e: 4b57 ldr r3, [pc, #348] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f10: 2200 movs r2, #0
|
|
8004f12: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 1;
|
|
8004f14: 4b55 ldr r3, [pc, #340] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f16: 2201 movs r2, #1
|
|
8004f18: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x00; // 0x40 Green 0x80 Yellow 0xC0 Both
|
|
8004f1a: 4b54 ldr r3, [pc, #336] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f1c: 2200 movs r2, #0
|
|
8004f1e: 711a strb r2, [r3, #4]
|
|
//tmpCanMsg.data[3] = 0x87;
|
|
//tmpCanMsg.data[4] = 0x7f;
|
|
//tmpCanMsg.data[5] = 0x83;
|
|
//tmpCanMsg.data[6] = 0;
|
|
//tmpCanMsg.data[7] = 0;
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004f20: 4b52 ldr r3, [pc, #328] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f22: 0018 movs r0, r3
|
|
8004f24: f7fd fdc6 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
if (can_tim>4){
|
|
8004f28: 4b4f ldr r3, [pc, #316] @ (8005068 <MAZDA_Send_Data+0x33c>)
|
|
8004f2a: 681b ldr r3, [r3, #0]
|
|
8004f2c: 2b04 cmp r3, #4
|
|
8004f2e: d800 bhi.n 8004f32 <MAZDA_Send_Data+0x206>
|
|
8004f30: e097 b.n 8005062 <MAZDA_Send_Data+0x336>
|
|
can_tim = 0;
|
|
8004f32: 4b4d ldr r3, [pc, #308] @ (8005068 <MAZDA_Send_Data+0x33c>)
|
|
8004f34: 2200 movs r2, #0
|
|
8004f36: 601a str r2, [r3, #0]
|
|
tmpCanMsg.id = 0x203; //This needs sending witin 0.5 seconds of ignition otherwise traction light will come on
|
|
8004f38: 4b4c ldr r3, [pc, #304] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f3a: 4a52 ldr r2, [pc, #328] @ (8005084 <MAZDA_Send_Data+0x358>)
|
|
8004f3c: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004f3e: 4b4b ldr r3, [pc, #300] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f40: 2200 movs r2, #0
|
|
8004f42: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004f44: 4b49 ldr r3, [pc, #292] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f46: 2200 movs r2, #0
|
|
8004f48: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 7;
|
|
8004f4a: 4b48 ldr r3, [pc, #288] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f4c: 2207 movs r2, #7
|
|
8004f4e: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x16;
|
|
8004f50: 4b46 ldr r3, [pc, #280] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f52: 2216 movs r2, #22
|
|
8004f54: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0x16;
|
|
8004f56: 4b45 ldr r3, [pc, #276] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f58: 2216 movs r2, #22
|
|
8004f5a: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0x16;
|
|
8004f5c: 4b43 ldr r3, [pc, #268] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f5e: 2216 movs r2, #22
|
|
8004f60: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x16;
|
|
8004f62: 4b42 ldr r3, [pc, #264] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f64: 2216 movs r2, #22
|
|
8004f66: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0xAF;
|
|
8004f68: 4b40 ldr r3, [pc, #256] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f6a: 22af movs r2, #175 @ 0xaf
|
|
8004f6c: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 3;
|
|
8004f6e: 4b3f ldr r3, [pc, #252] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f70: 2203 movs r2, #3
|
|
8004f72: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x16;
|
|
8004f74: 4b3d ldr r3, [pc, #244] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f76: 2216 movs r2, #22
|
|
8004f78: 729a strb r2, [r3, #10]
|
|
//tmpCanMsg.data[7] = ;
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004f7a: 4b3c ldr r3, [pc, #240] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f7c: 0018 movs r0, r3
|
|
8004f7e: f7fd fd99 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
tmpCanMsg.id = 0x215; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on
|
|
8004f82: 4b3a ldr r3, [pc, #232] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f84: 4a40 ldr r2, [pc, #256] @ (8005088 <MAZDA_Send_Data+0x35c>)
|
|
8004f86: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004f88: 4b38 ldr r3, [pc, #224] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f8a: 2200 movs r2, #0
|
|
8004f8c: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004f8e: 4b37 ldr r3, [pc, #220] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f90: 2200 movs r2, #0
|
|
8004f92: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 8;
|
|
8004f94: 4b35 ldr r3, [pc, #212] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f96: 2208 movs r2, #8
|
|
8004f98: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x02;
|
|
8004f9a: 4b34 ldr r3, [pc, #208] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004f9c: 2202 movs r2, #2
|
|
8004f9e: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0x2D;
|
|
8004fa0: 4b32 ldr r3, [pc, #200] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fa2: 222d movs r2, #45 @ 0x2d
|
|
8004fa4: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0x02;
|
|
8004fa6: 4b31 ldr r3, [pc, #196] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fa8: 2202 movs r2, #2
|
|
8004faa: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x2D;
|
|
8004fac: 4b2f ldr r3, [pc, #188] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fae: 222d movs r2, #45 @ 0x2d
|
|
8004fb0: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x02;
|
|
8004fb2: 4b2e ldr r3, [pc, #184] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fb4: 2202 movs r2, #2
|
|
8004fb6: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 0x2A;
|
|
8004fb8: 4b2c ldr r3, [pc, #176] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fba: 222a movs r2, #42 @ 0x2a
|
|
8004fbc: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x06;
|
|
8004fbe: 4b2b ldr r3, [pc, #172] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fc0: 2206 movs r2, #6
|
|
8004fc2: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0x81;
|
|
8004fc4: 4b29 ldr r3, [pc, #164] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fc6: 2281 movs r2, #129 @ 0x81
|
|
8004fc8: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8004fca: 4b28 ldr r3, [pc, #160] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fcc: 0018 movs r0, r3
|
|
8004fce: f7fd fd71 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
tmpCanMsg.id = 0x231; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on
|
|
8004fd2: 4b26 ldr r3, [pc, #152] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fd4: 4a2d ldr r2, [pc, #180] @ (800508c <MAZDA_Send_Data+0x360>)
|
|
8004fd6: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8004fd8: 4b24 ldr r3, [pc, #144] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fda: 2200 movs r2, #0
|
|
8004fdc: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
8004fde: 4b23 ldr r3, [pc, #140] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fe0: 2200 movs r2, #0
|
|
8004fe2: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 5;
|
|
8004fe4: 4b21 ldr r3, [pc, #132] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fe6: 2205 movs r2, #5
|
|
8004fe8: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 15;
|
|
8004fea: 4b20 ldr r3, [pc, #128] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004fec: 220f movs r2, #15
|
|
8004fee: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0;
|
|
8004ff0: 4b1e ldr r3, [pc, #120] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ff2: 2200 movs r2, #0
|
|
8004ff4: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0xff;
|
|
8004ff6: 4b1d ldr r3, [pc, #116] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ff8: 22ff movs r2, #255 @ 0xff
|
|
8004ffa: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0xff;
|
|
8004ffc: 4b1b ldr r3, [pc, #108] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8004ffe: 22ff movs r2, #255 @ 0xff
|
|
8005000: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x00;
|
|
8005002: 4b1a ldr r3, [pc, #104] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005004: 2200 movs r2, #0
|
|
8005006: 721a strb r2, [r3, #8]
|
|
//tmpCanMsg.data[5] = 0x37;
|
|
//tmpCanMsg.data[6] = 0x06;
|
|
//tmpCanMsg.data[7] = 0x81;
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8005008: 4b18 ldr r3, [pc, #96] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800500a: 0018 movs r0, r3
|
|
800500c: f7fd fd52 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
tmpCanMsg.id = 0x240; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on
|
|
8005010: 4b16 ldr r3, [pc, #88] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005012: 2290 movs r2, #144 @ 0x90
|
|
8005014: 0092 lsls r2, r2, #2
|
|
8005016: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
8005018: 4b14 ldr r3, [pc, #80] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800501a: 2200 movs r2, #0
|
|
800501c: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
800501e: 4b13 ldr r3, [pc, #76] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005020: 2200 movs r2, #0
|
|
8005022: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 8;
|
|
8005024: 4b11 ldr r3, [pc, #68] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005026: 2208 movs r2, #8
|
|
8005028: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x04;
|
|
800502a: 4b10 ldr r3, [pc, #64] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800502c: 2204 movs r2, #4
|
|
800502e: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = 0;
|
|
8005030: 4b0e ldr r3, [pc, #56] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005032: 2200 movs r2, #0
|
|
8005034: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 40;
|
|
8005036: 4b0d ldr r3, [pc, #52] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005038: 2228 movs r2, #40 @ 0x28
|
|
800503a: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x00;
|
|
800503c: 4b0b ldr r3, [pc, #44] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800503e: 2200 movs r2, #0
|
|
8005040: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x02;
|
|
8005042: 4b0a ldr r3, [pc, #40] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005044: 2202 movs r2, #2
|
|
8005046: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 55;
|
|
8005048: 4b08 ldr r3, [pc, #32] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800504a: 2237 movs r2, #55 @ 0x37
|
|
800504c: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0x06;
|
|
800504e: 4b07 ldr r3, [pc, #28] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005050: 2206 movs r2, #6
|
|
8005052: 729a strb r2, [r3, #10]
|
|
tmpCanMsg.data[7] = 0x81;
|
|
8005054: 4b05 ldr r3, [pc, #20] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
8005056: 2281 movs r2, #129 @ 0x81
|
|
8005058: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
800505a: 4b04 ldr r3, [pc, #16] @ (800506c <MAZDA_Send_Data+0x340>)
|
|
800505c: 0018 movs r0, r3
|
|
800505e: f7fd fd29 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
}
|
|
}
|
|
8005062: 46c0 nop @ (mov r8, r8)
|
|
8005064: 46bd mov sp, r7
|
|
8005066: bd80 pop {r7, pc}
|
|
8005068: 20000b18 .word 0x20000b18
|
|
800506c: 20000b1c .word 0x20000b1c
|
|
8005070: 00000201 .word 0x00000201
|
|
8005074: 20000998 .word 0x20000998
|
|
8005078: cccccccd .word 0xcccccccd
|
|
800507c: 400ecccc .word 0x400ecccc
|
|
8005080: 00002710 .word 0x00002710
|
|
8005084: 00000203 .word 0x00000203
|
|
8005088: 00000215 .word 0x00000215
|
|
800508c: 00000231 .word 0x00000231
|
|
|
|
08005090 <MAZDA_CAN_Read>:
|
|
void MAZDA_CAN_Read(void) {
|
|
8005090: b580 push {r7, lr}
|
|
8005092: af00 add r7, sp, #0
|
|
CAN_Read_RX_Buffer(&tmpCanMsg);
|
|
8005094: 4b36 ldr r3, [pc, #216] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005096: 0018 movs r0, r3
|
|
8005098: f7fd fee4 bl 8002e64 <CAN_Read_RX_Buffer>
|
|
if (tmpCanMsg.id == 0x4c0) {
|
|
800509c: 4b34 ldr r3, [pc, #208] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800509e: 681a ldr r2, [r3, #0]
|
|
80050a0: 2398 movs r3, #152 @ 0x98
|
|
80050a2: 00db lsls r3, r3, #3
|
|
80050a4: 429a cmp r2, r3
|
|
80050a6: d140 bne.n 800512a <MAZDA_CAN_Read+0x9a>
|
|
tmpCanMsg.id = 0x420; // Engine Temp Odometer from 4c0 Oil Pressure Check Engine Low Water Bat Charge Oil Pressure
|
|
80050a8: 4b31 ldr r3, [pc, #196] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050aa: 2284 movs r2, #132 @ 0x84
|
|
80050ac: 00d2 lsls r2, r2, #3
|
|
80050ae: 601a str r2, [r3, #0]
|
|
tmpCanMsg.format = STD_FORMAT;
|
|
80050b0: 4b2f ldr r3, [pc, #188] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050b2: 2200 movs r2, #0
|
|
80050b4: 735a strb r2, [r3, #13]
|
|
tmpCanMsg.frame = DATA_FRAME;
|
|
80050b6: 4b2e ldr r3, [pc, #184] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050b8: 2200 movs r2, #0
|
|
80050ba: 739a strb r2, [r3, #14]
|
|
tmpCanMsg.lenght = 8;
|
|
80050bc: 4b2c ldr r3, [pc, #176] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050be: 2208 movs r2, #8
|
|
80050c0: 731a strb r2, [r3, #12]
|
|
tmpCanMsg.data[0] = 0x00; // clt
|
|
80050c2: 4b2b ldr r3, [pc, #172] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050c4: 2200 movs r2, #0
|
|
80050c6: 711a strb r2, [r3, #4]
|
|
tmpCanMsg.data[1] = tmpCanMsg.data[1]; // Odometer from 4c0 (pwm)
|
|
80050c8: 4b29 ldr r3, [pc, #164] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050ca: 795a ldrb r2, [r3, #5]
|
|
80050cc: 4b28 ldr r3, [pc, #160] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050ce: 715a strb r2, [r3, #5]
|
|
tmpCanMsg.data[2] = 0x00;
|
|
80050d0: 4b27 ldr r3, [pc, #156] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050d2: 2200 movs r2, #0
|
|
80050d4: 719a strb r2, [r3, #6]
|
|
tmpCanMsg.data[3] = 0x00;
|
|
80050d6: 4b26 ldr r3, [pc, #152] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050d8: 2200 movs r2, #0
|
|
80050da: 71da strb r2, [r3, #7]
|
|
tmpCanMsg.data[4] = 0x00; //Oil Pressure 0x00 - 0x01 (pwm)
|
|
80050dc: 4b24 ldr r3, [pc, #144] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050de: 2200 movs r2, #0
|
|
80050e0: 721a strb r2, [r3, #8]
|
|
tmpCanMsg.data[5] = 0x00; // Check Engine Bit 7 MIL Check Engine Bit 8 BL
|
|
80050e2: 4b23 ldr r3, [pc, #140] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050e4: 2200 movs r2, #0
|
|
80050e6: 725a strb r2, [r3, #9]
|
|
tmpCanMsg.data[6] = 0;
|
|
80050e8: 4b21 ldr r3, [pc, #132] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050ea: 2200 movs r2, #0
|
|
80050ec: 729a strb r2, [r3, #10]
|
|
if (var.vbat_adc < 1200) {
|
|
80050ee: 4b21 ldr r3, [pc, #132] @ (8005174 <MAZDA_CAN_Read+0xe4>)
|
|
80050f0: 8adb ldrh r3, [r3, #22]
|
|
80050f2: b29a uxth r2, r3
|
|
80050f4: 2396 movs r3, #150 @ 0x96
|
|
80050f6: 00db lsls r3, r3, #3
|
|
80050f8: 429a cmp r2, r3
|
|
80050fa: d207 bcs.n 800510c <MAZDA_CAN_Read+0x7c>
|
|
tmpCanMsg.data[6] |= 1 << 2;
|
|
80050fc: 4b1c ldr r3, [pc, #112] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
80050fe: 7a9b ldrb r3, [r3, #10]
|
|
8005100: 2204 movs r2, #4
|
|
8005102: 4313 orrs r3, r2
|
|
8005104: b2da uxtb r2, r3
|
|
8005106: 4b1a ldr r3, [pc, #104] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005108: 729a strb r2, [r3, #10]
|
|
800510a: e006 b.n 800511a <MAZDA_CAN_Read+0x8a>
|
|
} else {
|
|
tmpCanMsg.data[6] &= ~(1 << 2);
|
|
800510c: 4b18 ldr r3, [pc, #96] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800510e: 7a9b ldrb r3, [r3, #10]
|
|
8005110: 2204 movs r2, #4
|
|
8005112: 4393 bics r3, r2
|
|
8005114: b2da uxtb r2, r3
|
|
8005116: 4b16 ldr r3, [pc, #88] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005118: 729a strb r2, [r3, #10]
|
|
}
|
|
//tmpCanMsg.data[6] = var.ic_status2; //Low Water Bit 2 MIL Bat Charge Bit 7 MIL Oil Pressure Bit 8 MIL
|
|
tmpCanMsg.data[7] = 0x00;
|
|
800511a: 4b15 ldr r3, [pc, #84] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800511c: 2200 movs r2, #0
|
|
800511e: 72da strb r2, [r3, #11]
|
|
CAN_Add_TX_Buffer(&tmpCanMsg);
|
|
8005120: 4b13 ldr r3, [pc, #76] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005122: 0018 movs r0, r3
|
|
8005124: f7fd fcc6 bl 8002ab4 <CAN_Add_TX_Buffer>
|
|
} else if (tmpCanMsg.id == 0x4B1) {
|
|
var.vss = ((tmpCanMsg.data[4] << 8) + tmpCanMsg.data[5] + (tmpCanMsg.data[6] << 8) + tmpCanMsg.data[7]) / 4;
|
|
//todo // add option to make vss output on/off
|
|
VSS_Set((uint8_t)var.vss);
|
|
}
|
|
}
|
|
8005128: e01f b.n 800516a <MAZDA_CAN_Read+0xda>
|
|
} else if (tmpCanMsg.id == 0x4B1) {
|
|
800512a: 4b11 ldr r3, [pc, #68] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800512c: 681b ldr r3, [r3, #0]
|
|
800512e: 4a12 ldr r2, [pc, #72] @ (8005178 <MAZDA_CAN_Read+0xe8>)
|
|
8005130: 4293 cmp r3, r2
|
|
8005132: d11a bne.n 800516a <MAZDA_CAN_Read+0xda>
|
|
var.vss = ((tmpCanMsg.data[4] << 8) + tmpCanMsg.data[5] + (tmpCanMsg.data[6] << 8) + tmpCanMsg.data[7]) / 4;
|
|
8005134: 4b0e ldr r3, [pc, #56] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005136: 7a1b ldrb r3, [r3, #8]
|
|
8005138: 021b lsls r3, r3, #8
|
|
800513a: 4a0d ldr r2, [pc, #52] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800513c: 7a52 ldrb r2, [r2, #9]
|
|
800513e: 189a adds r2, r3, r2
|
|
8005140: 4b0b ldr r3, [pc, #44] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
8005142: 7a9b ldrb r3, [r3, #10]
|
|
8005144: 021b lsls r3, r3, #8
|
|
8005146: 18d3 adds r3, r2, r3
|
|
8005148: 4a09 ldr r2, [pc, #36] @ (8005170 <MAZDA_CAN_Read+0xe0>)
|
|
800514a: 7ad2 ldrb r2, [r2, #11]
|
|
800514c: 189b adds r3, r3, r2
|
|
800514e: 2b00 cmp r3, #0
|
|
8005150: da00 bge.n 8005154 <MAZDA_CAN_Read+0xc4>
|
|
8005152: 3303 adds r3, #3
|
|
8005154: 109b asrs r3, r3, #2
|
|
8005156: b29a uxth r2, r3
|
|
8005158: 4b06 ldr r3, [pc, #24] @ (8005174 <MAZDA_CAN_Read+0xe4>)
|
|
800515a: 861a strh r2, [r3, #48] @ 0x30
|
|
VSS_Set((uint8_t)var.vss);
|
|
800515c: 4b05 ldr r3, [pc, #20] @ (8005174 <MAZDA_CAN_Read+0xe4>)
|
|
800515e: 8e1b ldrh r3, [r3, #48] @ 0x30
|
|
8005160: b29b uxth r3, r3
|
|
8005162: b2db uxtb r3, r3
|
|
8005164: 0018 movs r0, r3
|
|
8005166: f000 f897 bl 8005298 <VSS_Set>
|
|
}
|
|
800516a: 46c0 nop @ (mov r8, r8)
|
|
800516c: 46bd mov sp, r7
|
|
800516e: bd80 pop {r7, pc}
|
|
8005170: 20000b1c .word 0x20000b1c
|
|
8005174: 20000998 .word 0x20000998
|
|
8005178: 000004b1 .word 0x000004b1
|
|
|
|
0800517c <__NVIC_EnableIRQ>:
|
|
{
|
|
800517c: b580 push {r7, lr}
|
|
800517e: b082 sub sp, #8
|
|
8005180: af00 add r7, sp, #0
|
|
8005182: 0002 movs r2, r0
|
|
8005184: 1dfb adds r3, r7, #7
|
|
8005186: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8005188: 1dfb adds r3, r7, #7
|
|
800518a: 781b ldrb r3, [r3, #0]
|
|
800518c: 2b7f cmp r3, #127 @ 0x7f
|
|
800518e: d809 bhi.n 80051a4 <__NVIC_EnableIRQ+0x28>
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8005190: 1dfb adds r3, r7, #7
|
|
8005192: 781b ldrb r3, [r3, #0]
|
|
8005194: 001a movs r2, r3
|
|
8005196: 231f movs r3, #31
|
|
8005198: 401a ands r2, r3
|
|
800519a: 4b04 ldr r3, [pc, #16] @ (80051ac <__NVIC_EnableIRQ+0x30>)
|
|
800519c: 2101 movs r1, #1
|
|
800519e: 4091 lsls r1, r2
|
|
80051a0: 000a movs r2, r1
|
|
80051a2: 601a str r2, [r3, #0]
|
|
}
|
|
80051a4: 46c0 nop @ (mov r8, r8)
|
|
80051a6: 46bd mov sp, r7
|
|
80051a8: b002 add sp, #8
|
|
80051aa: bd80 pop {r7, pc}
|
|
80051ac: e000e100 .word 0xe000e100
|
|
|
|
080051b0 <TIM16_Init>:
|
|
* Author: v0stap
|
|
*/
|
|
|
|
#include "main.h"
|
|
|
|
void TIM16_Init(void) {
|
|
80051b0: b580 push {r7, lr}
|
|
80051b2: af00 add r7, sp, #0
|
|
RCC->APB2ENR |= RCC_APB2ENR_TIM16EN;
|
|
80051b4: 4b17 ldr r3, [pc, #92] @ (8005214 <TIM16_Init+0x64>)
|
|
80051b6: 699a ldr r2, [r3, #24]
|
|
80051b8: 4b16 ldr r3, [pc, #88] @ (8005214 <TIM16_Init+0x64>)
|
|
80051ba: 2180 movs r1, #128 @ 0x80
|
|
80051bc: 0289 lsls r1, r1, #10
|
|
80051be: 430a orrs r2, r1
|
|
80051c0: 619a str r2, [r3, #24]
|
|
TIM16->PSC = 480;
|
|
80051c2: 4b15 ldr r3, [pc, #84] @ (8005218 <TIM16_Init+0x68>)
|
|
80051c4: 22f0 movs r2, #240 @ 0xf0
|
|
80051c6: 0052 lsls r2, r2, #1
|
|
80051c8: 629a str r2, [r3, #40] @ 0x28
|
|
TIM16->ARR = 70287;
|
|
80051ca: 4b13 ldr r3, [pc, #76] @ (8005218 <TIM16_Init+0x68>)
|
|
80051cc: 4a13 ldr r2, [pc, #76] @ (800521c <TIM16_Init+0x6c>)
|
|
80051ce: 62da str r2, [r3, #44] @ 0x2c
|
|
TIM16->CR1 |= 1 << 0 | 1 << 7;
|
|
80051d0: 4b11 ldr r3, [pc, #68] @ (8005218 <TIM16_Init+0x68>)
|
|
80051d2: 681a ldr r2, [r3, #0]
|
|
80051d4: 4b10 ldr r3, [pc, #64] @ (8005218 <TIM16_Init+0x68>)
|
|
80051d6: 2181 movs r1, #129 @ 0x81
|
|
80051d8: 430a orrs r2, r1
|
|
80051da: 601a str r2, [r3, #0]
|
|
TIM16->CR2 = 0;
|
|
80051dc: 4b0e ldr r3, [pc, #56] @ (8005218 <TIM16_Init+0x68>)
|
|
80051de: 2200 movs r2, #0
|
|
80051e0: 605a str r2, [r3, #4]
|
|
TIM16->SMCR = 0;
|
|
80051e2: 4b0d ldr r3, [pc, #52] @ (8005218 <TIM16_Init+0x68>)
|
|
80051e4: 2200 movs r2, #0
|
|
80051e6: 609a str r2, [r3, #8]
|
|
TIM16->DIER = 1 << 0;
|
|
80051e8: 4b0b ldr r3, [pc, #44] @ (8005218 <TIM16_Init+0x68>)
|
|
80051ea: 2201 movs r2, #1
|
|
80051ec: 60da str r2, [r3, #12]
|
|
TIM16->CCMR1 = 0;
|
|
80051ee: 4b0a ldr r3, [pc, #40] @ (8005218 <TIM16_Init+0x68>)
|
|
80051f0: 2200 movs r2, #0
|
|
80051f2: 619a str r2, [r3, #24]
|
|
TIM16->CCMR2 = 0;
|
|
80051f4: 4b08 ldr r3, [pc, #32] @ (8005218 <TIM16_Init+0x68>)
|
|
80051f6: 2200 movs r2, #0
|
|
80051f8: 61da str r2, [r3, #28]
|
|
TIM16->CCER = 0x1111;
|
|
80051fa: 4b07 ldr r3, [pc, #28] @ (8005218 <TIM16_Init+0x68>)
|
|
80051fc: 4a08 ldr r2, [pc, #32] @ (8005220 <TIM16_Init+0x70>)
|
|
80051fe: 621a str r2, [r3, #32]
|
|
TIM16->SR = 0;
|
|
8005200: 4b05 ldr r3, [pc, #20] @ (8005218 <TIM16_Init+0x68>)
|
|
8005202: 2200 movs r2, #0
|
|
8005204: 611a str r2, [r3, #16]
|
|
NVIC_EnableIRQ(TIM16_IRQn);
|
|
8005206: 2015 movs r0, #21
|
|
8005208: f7ff ffb8 bl 800517c <__NVIC_EnableIRQ>
|
|
}
|
|
800520c: 46c0 nop @ (mov r8, r8)
|
|
800520e: 46bd mov sp, r7
|
|
8005210: bd80 pop {r7, pc}
|
|
8005212: 46c0 nop @ (mov r8, r8)
|
|
8005214: 40021000 .word 0x40021000
|
|
8005218: 40014400 .word 0x40014400
|
|
800521c: 0001128f .word 0x0001128f
|
|
8005220: 00001111 .word 0x00001111
|
|
|
|
08005224 <TIM17_Init>:
|
|
|
|
void TIM17_Init(void) {
|
|
8005224: b580 push {r7, lr}
|
|
8005226: af00 add r7, sp, #0
|
|
RCC->APB2ENR |= RCC_APB2ENR_TIM17EN;
|
|
8005228: 4b17 ldr r3, [pc, #92] @ (8005288 <TIM17_Init+0x64>)
|
|
800522a: 699a ldr r2, [r3, #24]
|
|
800522c: 4b16 ldr r3, [pc, #88] @ (8005288 <TIM17_Init+0x64>)
|
|
800522e: 2180 movs r1, #128 @ 0x80
|
|
8005230: 02c9 lsls r1, r1, #11
|
|
8005232: 430a orrs r2, r1
|
|
8005234: 619a str r2, [r3, #24]
|
|
TIM17->PSC = 479;
|
|
8005236: 4b15 ldr r3, [pc, #84] @ (800528c <TIM17_Init+0x68>)
|
|
8005238: 22e0 movs r2, #224 @ 0xe0
|
|
800523a: 32ff adds r2, #255 @ 0xff
|
|
800523c: 629a str r2, [r3, #40] @ 0x28
|
|
TIM17->ARR = 10000;
|
|
800523e: 4b13 ldr r3, [pc, #76] @ (800528c <TIM17_Init+0x68>)
|
|
8005240: 4a13 ldr r2, [pc, #76] @ (8005290 <TIM17_Init+0x6c>)
|
|
8005242: 62da str r2, [r3, #44] @ 0x2c
|
|
TIM17->CR1 |= 1 << 0 | 1 << 7;
|
|
8005244: 4b11 ldr r3, [pc, #68] @ (800528c <TIM17_Init+0x68>)
|
|
8005246: 681a ldr r2, [r3, #0]
|
|
8005248: 4b10 ldr r3, [pc, #64] @ (800528c <TIM17_Init+0x68>)
|
|
800524a: 2181 movs r1, #129 @ 0x81
|
|
800524c: 430a orrs r2, r1
|
|
800524e: 601a str r2, [r3, #0]
|
|
TIM17->CR2 = 0;
|
|
8005250: 4b0e ldr r3, [pc, #56] @ (800528c <TIM17_Init+0x68>)
|
|
8005252: 2200 movs r2, #0
|
|
8005254: 605a str r2, [r3, #4]
|
|
TIM17->SMCR = 0;
|
|
8005256: 4b0d ldr r3, [pc, #52] @ (800528c <TIM17_Init+0x68>)
|
|
8005258: 2200 movs r2, #0
|
|
800525a: 609a str r2, [r3, #8]
|
|
TIM17->DIER = 1 << 0;
|
|
800525c: 4b0b ldr r3, [pc, #44] @ (800528c <TIM17_Init+0x68>)
|
|
800525e: 2201 movs r2, #1
|
|
8005260: 60da str r2, [r3, #12]
|
|
TIM17->CCMR1 = 0;
|
|
8005262: 4b0a ldr r3, [pc, #40] @ (800528c <TIM17_Init+0x68>)
|
|
8005264: 2200 movs r2, #0
|
|
8005266: 619a str r2, [r3, #24]
|
|
TIM17->CCMR2 = 0;
|
|
8005268: 4b08 ldr r3, [pc, #32] @ (800528c <TIM17_Init+0x68>)
|
|
800526a: 2200 movs r2, #0
|
|
800526c: 61da str r2, [r3, #28]
|
|
TIM17->CCER = 0x1111;
|
|
800526e: 4b07 ldr r3, [pc, #28] @ (800528c <TIM17_Init+0x68>)
|
|
8005270: 4a08 ldr r2, [pc, #32] @ (8005294 <TIM17_Init+0x70>)
|
|
8005272: 621a str r2, [r3, #32]
|
|
TIM17->SR = 0;
|
|
8005274: 4b05 ldr r3, [pc, #20] @ (800528c <TIM17_Init+0x68>)
|
|
8005276: 2200 movs r2, #0
|
|
8005278: 611a str r2, [r3, #16]
|
|
NVIC_EnableIRQ(TIM17_IRQn);
|
|
800527a: 2016 movs r0, #22
|
|
800527c: f7ff ff7e bl 800517c <__NVIC_EnableIRQ>
|
|
}
|
|
8005280: 46c0 nop @ (mov r8, r8)
|
|
8005282: 46bd mov sp, r7
|
|
8005284: bd80 pop {r7, pc}
|
|
8005286: 46c0 nop @ (mov r8, r8)
|
|
8005288: 40021000 .word 0x40021000
|
|
800528c: 40014800 .word 0x40014800
|
|
8005290: 00002710 .word 0x00002710
|
|
8005294: 00001111 .word 0x00001111
|
|
|
|
08005298 <VSS_Set>:
|
|
|
|
void VSS_Set(uint8_t vss) {
|
|
8005298: b580 push {r7, lr}
|
|
800529a: b082 sub sp, #8
|
|
800529c: af00 add r7, sp, #0
|
|
800529e: 0002 movs r2, r0
|
|
80052a0: 1dfb adds r3, r7, #7
|
|
80052a2: 701a strb r2, [r3, #0]
|
|
if (vss < 3) {
|
|
80052a4: 1dfb adds r3, r7, #7
|
|
80052a6: 781b ldrb r3, [r3, #0]
|
|
80052a8: 2b02 cmp r3, #2
|
|
80052aa: d806 bhi.n 80052ba <VSS_Set+0x22>
|
|
TIM16->CR1 &= ~(1 << 0);
|
|
80052ac: 4b0d ldr r3, [pc, #52] @ (80052e4 <VSS_Set+0x4c>)
|
|
80052ae: 681a ldr r2, [r3, #0]
|
|
80052b0: 4b0c ldr r3, [pc, #48] @ (80052e4 <VSS_Set+0x4c>)
|
|
80052b2: 2101 movs r1, #1
|
|
80052b4: 438a bics r2, r1
|
|
80052b6: 601a str r2, [r3, #0]
|
|
} else {
|
|
TIM16->CR1 |= 1 << 0;
|
|
TIM16->ARR = 70287 / vss;
|
|
}
|
|
}
|
|
80052b8: e00f b.n 80052da <VSS_Set+0x42>
|
|
TIM16->CR1 |= 1 << 0;
|
|
80052ba: 4b0a ldr r3, [pc, #40] @ (80052e4 <VSS_Set+0x4c>)
|
|
80052bc: 681a ldr r2, [r3, #0]
|
|
80052be: 4b09 ldr r3, [pc, #36] @ (80052e4 <VSS_Set+0x4c>)
|
|
80052c0: 2101 movs r1, #1
|
|
80052c2: 430a orrs r2, r1
|
|
80052c4: 601a str r2, [r3, #0]
|
|
TIM16->ARR = 70287 / vss;
|
|
80052c6: 1dfb adds r3, r7, #7
|
|
80052c8: 781b ldrb r3, [r3, #0]
|
|
80052ca: 0019 movs r1, r3
|
|
80052cc: 4806 ldr r0, [pc, #24] @ (80052e8 <VSS_Set+0x50>)
|
|
80052ce: f7fa ffa5 bl 800021c <__divsi3>
|
|
80052d2: 0003 movs r3, r0
|
|
80052d4: 001a movs r2, r3
|
|
80052d6: 4b03 ldr r3, [pc, #12] @ (80052e4 <VSS_Set+0x4c>)
|
|
80052d8: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
80052da: 46c0 nop @ (mov r8, r8)
|
|
80052dc: 46bd mov sp, r7
|
|
80052de: b002 add sp, #8
|
|
80052e0: bd80 pop {r7, pc}
|
|
80052e2: 46c0 nop @ (mov r8, r8)
|
|
80052e4: 40014400 .word 0x40014400
|
|
80052e8: 0001128f .word 0x0001128f
|
|
|
|
080052ec <TIM16_IRQHandler>:
|
|
|
|
|
|
void TIM16_IRQHandler(void) {
|
|
80052ec: b580 push {r7, lr}
|
|
80052ee: af00 add r7, sp, #0
|
|
TIM16->SR &= ~(1 << 0);
|
|
80052f0: 4b06 ldr r3, [pc, #24] @ (800530c <TIM16_IRQHandler+0x20>)
|
|
80052f2: 691a ldr r2, [r3, #16]
|
|
80052f4: 4b05 ldr r3, [pc, #20] @ (800530c <TIM16_IRQHandler+0x20>)
|
|
80052f6: 2101 movs r1, #1
|
|
80052f8: 438a bics r2, r1
|
|
80052fa: 611a str r2, [r3, #16]
|
|
//TIM2->CNT = 600;
|
|
HAL_GPIO_TogglePin(GPIOB, GPO1_Pin);
|
|
80052fc: 4b04 ldr r3, [pc, #16] @ (8005310 <TIM16_IRQHandler+0x24>)
|
|
80052fe: 2120 movs r1, #32
|
|
8005300: 0018 movs r0, r3
|
|
8005302: f002 f996 bl 8007632 <HAL_GPIO_TogglePin>
|
|
}
|
|
8005306: 46c0 nop @ (mov r8, r8)
|
|
8005308: 46bd mov sp, r7
|
|
800530a: bd80 pop {r7, pc}
|
|
800530c: 40014400 .word 0x40014400
|
|
8005310: 48000400 .word 0x48000400
|
|
|
|
08005314 <TIM17_IRQHandler>:
|
|
void TIM17_IRQHandler(void) {
|
|
8005314: b580 push {r7, lr}
|
|
8005316: af00 add r7, sp, #0
|
|
TIM17->SR &= ~(1 << 0);
|
|
8005318: 4b05 ldr r3, [pc, #20] @ (8005330 <TIM17_IRQHandler+0x1c>)
|
|
800531a: 691a ldr r2, [r3, #16]
|
|
800531c: 4b04 ldr r3, [pc, #16] @ (8005330 <TIM17_IRQHandler+0x1c>)
|
|
800531e: 2101 movs r1, #1
|
|
8005320: 438a bics r2, r1
|
|
8005322: 611a str r2, [r3, #16]
|
|
//TIM2->CNT = 600;
|
|
MAZDA_Send_Data();
|
|
8005324: f7ff fd02 bl 8004d2c <MAZDA_Send_Data>
|
|
}
|
|
8005328: 46c0 nop @ (mov r8, r8)
|
|
800532a: 46bd mov sp, r7
|
|
800532c: bd80 pop {r7, pc}
|
|
800532e: 46c0 nop @ (mov r8, r8)
|
|
8005330: 40014800 .word 0x40014800
|
|
|
|
08005334 <Check_Safety_Limits>:
|
|
while (IWDG->SR)
|
|
;
|
|
|
|
}
|
|
|
|
void Check_Safety_Limits(void) {
|
|
8005334: b580 push {r7, lr}
|
|
8005336: af00 add r7, sp, #0
|
|
|
|
//PPS1
|
|
|
|
if (config->pps1_min < config->pps1_max) {
|
|
8005338: 4bc3 ldr r3, [pc, #780] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800533a: 681b ldr r3, [r3, #0]
|
|
800533c: 885b ldrh r3, [r3, #2]
|
|
800533e: b29a uxth r2, r3
|
|
8005340: 4bc1 ldr r3, [pc, #772] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005342: 681b ldr r3, [r3, #0]
|
|
8005344: 889b ldrh r3, [r3, #4]
|
|
8005346: b29b uxth r3, r3
|
|
8005348: 429a cmp r2, r3
|
|
800534a: d22c bcs.n 80053a6 <Check_Safety_Limits+0x72>
|
|
if ((config->pps1_margin > config->pps1_min)
|
|
800534c: 4bbe ldr r3, [pc, #760] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800534e: 681a ldr r2, [r3, #0]
|
|
8005350: 23cf movs r3, #207 @ 0xcf
|
|
8005352: 009b lsls r3, r3, #2
|
|
8005354: 5ad3 ldrh r3, [r2, r3]
|
|
8005356: b29a uxth r2, r3
|
|
8005358: 4bbb ldr r3, [pc, #748] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800535a: 681b ldr r3, [r3, #0]
|
|
800535c: 885b ldrh r3, [r3, #2]
|
|
800535e: b29b uxth r3, r3
|
|
8005360: 429a cmp r2, r3
|
|
8005362: d80f bhi.n 8005384 <Check_Safety_Limits+0x50>
|
|
|| ((config->pps1_max + config->pps1_margin) > 4095)) {
|
|
8005364: 4bb8 ldr r3, [pc, #736] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005366: 681b ldr r3, [r3, #0]
|
|
8005368: 889b ldrh r3, [r3, #4]
|
|
800536a: b29b uxth r3, r3
|
|
800536c: 0019 movs r1, r3
|
|
800536e: 4bb6 ldr r3, [pc, #728] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005370: 681a ldr r2, [r3, #0]
|
|
8005372: 23cf movs r3, #207 @ 0xcf
|
|
8005374: 009b lsls r3, r3, #2
|
|
8005376: 5ad3 ldrh r3, [r2, r3]
|
|
8005378: b29b uxth r3, r3
|
|
800537a: 18ca adds r2, r1, r3
|
|
800537c: 2380 movs r3, #128 @ 0x80
|
|
800537e: 015b lsls r3, r3, #5
|
|
8005380: 429a cmp r2, r3
|
|
8005382: db3c blt.n 80053fe <Check_Safety_Limits+0xca>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
8005384: 4bb1 ldr r3, [pc, #708] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005386: 889b ldrh r3, [r3, #4]
|
|
8005388: b29b uxth r3, r3
|
|
800538a: 2280 movs r2, #128 @ 0x80
|
|
800538c: 0192 lsls r2, r2, #6
|
|
800538e: 4313 orrs r3, r2
|
|
8005390: b29a uxth r2, r3
|
|
8005392: 4bae ldr r3, [pc, #696] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005394: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005396: f7fe fe53 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg1, 42);
|
|
800539a: 4bad ldr r3, [pc, #692] @ (8005650 <Check_Safety_Limits+0x31c>)
|
|
800539c: 212a movs r1, #42 @ 0x2a
|
|
800539e: 0018 movs r0, r3
|
|
80053a0: f001 f842 bl 8006428 <TX_Schedule>
|
|
80053a4: e02b b.n 80053fe <Check_Safety_Limits+0xca>
|
|
}
|
|
} else {
|
|
//config->pps1_min > config->pps1_max
|
|
if ((config->pps1_margin > config->pps1_max)
|
|
80053a6: 4ba8 ldr r3, [pc, #672] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80053a8: 681a ldr r2, [r3, #0]
|
|
80053aa: 23cf movs r3, #207 @ 0xcf
|
|
80053ac: 009b lsls r3, r3, #2
|
|
80053ae: 5ad3 ldrh r3, [r2, r3]
|
|
80053b0: b29a uxth r2, r3
|
|
80053b2: 4ba5 ldr r3, [pc, #660] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80053b4: 681b ldr r3, [r3, #0]
|
|
80053b6: 889b ldrh r3, [r3, #4]
|
|
80053b8: b29b uxth r3, r3
|
|
80053ba: 429a cmp r2, r3
|
|
80053bc: d80f bhi.n 80053de <Check_Safety_Limits+0xaa>
|
|
|| ((config->pps1_min + config->pps1_margin) > 4095)) {
|
|
80053be: 4ba2 ldr r3, [pc, #648] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80053c0: 681b ldr r3, [r3, #0]
|
|
80053c2: 885b ldrh r3, [r3, #2]
|
|
80053c4: b29b uxth r3, r3
|
|
80053c6: 0019 movs r1, r3
|
|
80053c8: 4b9f ldr r3, [pc, #636] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80053ca: 681a ldr r2, [r3, #0]
|
|
80053cc: 23cf movs r3, #207 @ 0xcf
|
|
80053ce: 009b lsls r3, r3, #2
|
|
80053d0: 5ad3 ldrh r3, [r2, r3]
|
|
80053d2: b29b uxth r3, r3
|
|
80053d4: 18ca adds r2, r1, r3
|
|
80053d6: 2380 movs r3, #128 @ 0x80
|
|
80053d8: 015b lsls r3, r3, #5
|
|
80053da: 429a cmp r2, r3
|
|
80053dc: db0f blt.n 80053fe <Check_Safety_Limits+0xca>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
80053de: 4b9b ldr r3, [pc, #620] @ (800564c <Check_Safety_Limits+0x318>)
|
|
80053e0: 889b ldrh r3, [r3, #4]
|
|
80053e2: b29b uxth r3, r3
|
|
80053e4: 2280 movs r2, #128 @ 0x80
|
|
80053e6: 0192 lsls r2, r2, #6
|
|
80053e8: 4313 orrs r3, r2
|
|
80053ea: b29a uxth r2, r3
|
|
80053ec: 4b97 ldr r3, [pc, #604] @ (800564c <Check_Safety_Limits+0x318>)
|
|
80053ee: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80053f0: f7fe fe26 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg1, 42);
|
|
80053f4: 4b96 ldr r3, [pc, #600] @ (8005650 <Check_Safety_Limits+0x31c>)
|
|
80053f6: 212a movs r1, #42 @ 0x2a
|
|
80053f8: 0018 movs r0, r3
|
|
80053fa: f001 f815 bl 8006428 <TX_Schedule>
|
|
}
|
|
}
|
|
//PPS2
|
|
|
|
if (config->pps2_min < config->pps2_max) {
|
|
80053fe: 4b92 ldr r3, [pc, #584] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005400: 681b ldr r3, [r3, #0]
|
|
8005402: 88db ldrh r3, [r3, #6]
|
|
8005404: b29a uxth r2, r3
|
|
8005406: 4b90 ldr r3, [pc, #576] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005408: 681b ldr r3, [r3, #0]
|
|
800540a: 899b ldrh r3, [r3, #12]
|
|
800540c: b29b uxth r3, r3
|
|
800540e: 429a cmp r2, r3
|
|
8005410: d22a bcs.n 8005468 <Check_Safety_Limits+0x134>
|
|
if ((config->pps2_margin > config->pps2_min)
|
|
8005412: 4b8d ldr r3, [pc, #564] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005414: 681b ldr r3, [r3, #0]
|
|
8005416: 4a8f ldr r2, [pc, #572] @ (8005654 <Check_Safety_Limits+0x320>)
|
|
8005418: 5a9b ldrh r3, [r3, r2]
|
|
800541a: b29a uxth r2, r3
|
|
800541c: 4b8a ldr r3, [pc, #552] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800541e: 681b ldr r3, [r3, #0]
|
|
8005420: 88db ldrh r3, [r3, #6]
|
|
8005422: b29b uxth r3, r3
|
|
8005424: 429a cmp r2, r3
|
|
8005426: d80e bhi.n 8005446 <Check_Safety_Limits+0x112>
|
|
|| ((config->pps2_max + config->pps2_margin) > 4095)) {
|
|
8005428: 4b87 ldr r3, [pc, #540] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800542a: 681b ldr r3, [r3, #0]
|
|
800542c: 899b ldrh r3, [r3, #12]
|
|
800542e: b29b uxth r3, r3
|
|
8005430: 0019 movs r1, r3
|
|
8005432: 4b85 ldr r3, [pc, #532] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005434: 681b ldr r3, [r3, #0]
|
|
8005436: 4a87 ldr r2, [pc, #540] @ (8005654 <Check_Safety_Limits+0x320>)
|
|
8005438: 5a9b ldrh r3, [r3, r2]
|
|
800543a: b29b uxth r3, r3
|
|
800543c: 18ca adds r2, r1, r3
|
|
800543e: 2380 movs r3, #128 @ 0x80
|
|
8005440: 015b lsls r3, r3, #5
|
|
8005442: 429a cmp r2, r3
|
|
8005444: db3a blt.n 80054bc <Check_Safety_Limits+0x188>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
8005446: 4b81 ldr r3, [pc, #516] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005448: 889b ldrh r3, [r3, #4]
|
|
800544a: b29b uxth r3, r3
|
|
800544c: 2280 movs r2, #128 @ 0x80
|
|
800544e: 0192 lsls r2, r2, #6
|
|
8005450: 4313 orrs r3, r2
|
|
8005452: b29a uxth r2, r3
|
|
8005454: 4b7d ldr r3, [pc, #500] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005456: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005458: f7fe fdf2 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg2, 42);
|
|
800545c: 4b7e ldr r3, [pc, #504] @ (8005658 <Check_Safety_Limits+0x324>)
|
|
800545e: 212a movs r1, #42 @ 0x2a
|
|
8005460: 0018 movs r0, r3
|
|
8005462: f000 ffe1 bl 8006428 <TX_Schedule>
|
|
8005466: e029 b.n 80054bc <Check_Safety_Limits+0x188>
|
|
}
|
|
} else {
|
|
//config->pps2_min > config->pps1_max
|
|
if ((config->pps2_margin > config->pps2_max)
|
|
8005468: 4b77 ldr r3, [pc, #476] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800546a: 681b ldr r3, [r3, #0]
|
|
800546c: 4a79 ldr r2, [pc, #484] @ (8005654 <Check_Safety_Limits+0x320>)
|
|
800546e: 5a9b ldrh r3, [r3, r2]
|
|
8005470: b29a uxth r2, r3
|
|
8005472: 4b75 ldr r3, [pc, #468] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005474: 681b ldr r3, [r3, #0]
|
|
8005476: 899b ldrh r3, [r3, #12]
|
|
8005478: b29b uxth r3, r3
|
|
800547a: 429a cmp r2, r3
|
|
800547c: d80e bhi.n 800549c <Check_Safety_Limits+0x168>
|
|
|| ((config->pps2_min + config->pps2_margin) > 4095)) {
|
|
800547e: 4b72 ldr r3, [pc, #456] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005480: 681b ldr r3, [r3, #0]
|
|
8005482: 88db ldrh r3, [r3, #6]
|
|
8005484: b29b uxth r3, r3
|
|
8005486: 0019 movs r1, r3
|
|
8005488: 4b6f ldr r3, [pc, #444] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800548a: 681b ldr r3, [r3, #0]
|
|
800548c: 4a71 ldr r2, [pc, #452] @ (8005654 <Check_Safety_Limits+0x320>)
|
|
800548e: 5a9b ldrh r3, [r3, r2]
|
|
8005490: b29b uxth r3, r3
|
|
8005492: 18ca adds r2, r1, r3
|
|
8005494: 2380 movs r3, #128 @ 0x80
|
|
8005496: 015b lsls r3, r3, #5
|
|
8005498: 429a cmp r2, r3
|
|
800549a: db0f blt.n 80054bc <Check_Safety_Limits+0x188>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
800549c: 4b6b ldr r3, [pc, #428] @ (800564c <Check_Safety_Limits+0x318>)
|
|
800549e: 889b ldrh r3, [r3, #4]
|
|
80054a0: b29b uxth r3, r3
|
|
80054a2: 2280 movs r2, #128 @ 0x80
|
|
80054a4: 0192 lsls r2, r2, #6
|
|
80054a6: 4313 orrs r3, r2
|
|
80054a8: b29a uxth r2, r3
|
|
80054aa: 4b68 ldr r3, [pc, #416] @ (800564c <Check_Safety_Limits+0x318>)
|
|
80054ac: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80054ae: f7fe fdc7 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg2, 42);
|
|
80054b2: 4b69 ldr r3, [pc, #420] @ (8005658 <Check_Safety_Limits+0x324>)
|
|
80054b4: 212a movs r1, #42 @ 0x2a
|
|
80054b6: 0018 movs r0, r3
|
|
80054b8: f000 ffb6 bl 8006428 <TX_Schedule>
|
|
}
|
|
}
|
|
|
|
//TPS1
|
|
|
|
if (config->tps1_min < config->tps1_max) {
|
|
80054bc: 4b62 ldr r3, [pc, #392] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054be: 681b ldr r3, [r3, #0]
|
|
80054c0: 89db ldrh r3, [r3, #14]
|
|
80054c2: b29a uxth r2, r3
|
|
80054c4: 4b60 ldr r3, [pc, #384] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054c6: 681b ldr r3, [r3, #0]
|
|
80054c8: 8a1b ldrh r3, [r3, #16]
|
|
80054ca: b29b uxth r3, r3
|
|
80054cc: 429a cmp r2, r3
|
|
80054ce: d22a bcs.n 8005526 <Check_Safety_Limits+0x1f2>
|
|
if ((config->tps1_margin > config->tps1_min)
|
|
80054d0: 4b5d ldr r3, [pc, #372] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054d2: 681b ldr r3, [r3, #0]
|
|
80054d4: 4a61 ldr r2, [pc, #388] @ (800565c <Check_Safety_Limits+0x328>)
|
|
80054d6: 5a9b ldrh r3, [r3, r2]
|
|
80054d8: b29a uxth r2, r3
|
|
80054da: 4b5b ldr r3, [pc, #364] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054dc: 681b ldr r3, [r3, #0]
|
|
80054de: 89db ldrh r3, [r3, #14]
|
|
80054e0: b29b uxth r3, r3
|
|
80054e2: 429a cmp r2, r3
|
|
80054e4: d80e bhi.n 8005504 <Check_Safety_Limits+0x1d0>
|
|
|| ((config->tps1_max + config->tps1_margin) > 4095)) {
|
|
80054e6: 4b58 ldr r3, [pc, #352] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054e8: 681b ldr r3, [r3, #0]
|
|
80054ea: 8a1b ldrh r3, [r3, #16]
|
|
80054ec: b29b uxth r3, r3
|
|
80054ee: 0019 movs r1, r3
|
|
80054f0: 4b55 ldr r3, [pc, #340] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80054f2: 681b ldr r3, [r3, #0]
|
|
80054f4: 4a59 ldr r2, [pc, #356] @ (800565c <Check_Safety_Limits+0x328>)
|
|
80054f6: 5a9b ldrh r3, [r3, r2]
|
|
80054f8: b29b uxth r3, r3
|
|
80054fa: 18ca adds r2, r1, r3
|
|
80054fc: 2380 movs r3, #128 @ 0x80
|
|
80054fe: 015b lsls r3, r3, #5
|
|
8005500: 429a cmp r2, r3
|
|
8005502: db3a blt.n 800557a <Check_Safety_Limits+0x246>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
8005504: 4b51 ldr r3, [pc, #324] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005506: 889b ldrh r3, [r3, #4]
|
|
8005508: b29b uxth r3, r3
|
|
800550a: 2280 movs r2, #128 @ 0x80
|
|
800550c: 0192 lsls r2, r2, #6
|
|
800550e: 4313 orrs r3, r2
|
|
8005510: b29a uxth r2, r3
|
|
8005512: 4b4e ldr r3, [pc, #312] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005514: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005516: f7fe fd93 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg3, 42);
|
|
800551a: 4b51 ldr r3, [pc, #324] @ (8005660 <Check_Safety_Limits+0x32c>)
|
|
800551c: 212a movs r1, #42 @ 0x2a
|
|
800551e: 0018 movs r0, r3
|
|
8005520: f000 ff82 bl 8006428 <TX_Schedule>
|
|
8005524: e029 b.n 800557a <Check_Safety_Limits+0x246>
|
|
}
|
|
} else {
|
|
//config->tps1_min > config->tps1_max
|
|
if ((config->tps1_margin > config->tps1_max)
|
|
8005526: 4b48 ldr r3, [pc, #288] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005528: 681b ldr r3, [r3, #0]
|
|
800552a: 4a4c ldr r2, [pc, #304] @ (800565c <Check_Safety_Limits+0x328>)
|
|
800552c: 5a9b ldrh r3, [r3, r2]
|
|
800552e: b29a uxth r2, r3
|
|
8005530: 4b45 ldr r3, [pc, #276] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005532: 681b ldr r3, [r3, #0]
|
|
8005534: 8a1b ldrh r3, [r3, #16]
|
|
8005536: b29b uxth r3, r3
|
|
8005538: 429a cmp r2, r3
|
|
800553a: d80e bhi.n 800555a <Check_Safety_Limits+0x226>
|
|
|| ((config->tps1_min + config->tps1_margin) > 4095)) {
|
|
800553c: 4b42 ldr r3, [pc, #264] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800553e: 681b ldr r3, [r3, #0]
|
|
8005540: 89db ldrh r3, [r3, #14]
|
|
8005542: b29b uxth r3, r3
|
|
8005544: 0019 movs r1, r3
|
|
8005546: 4b40 ldr r3, [pc, #256] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005548: 681b ldr r3, [r3, #0]
|
|
800554a: 4a44 ldr r2, [pc, #272] @ (800565c <Check_Safety_Limits+0x328>)
|
|
800554c: 5a9b ldrh r3, [r3, r2]
|
|
800554e: b29b uxth r3, r3
|
|
8005550: 18ca adds r2, r1, r3
|
|
8005552: 2380 movs r3, #128 @ 0x80
|
|
8005554: 015b lsls r3, r3, #5
|
|
8005556: 429a cmp r2, r3
|
|
8005558: db0f blt.n 800557a <Check_Safety_Limits+0x246>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
800555a: 4b3c ldr r3, [pc, #240] @ (800564c <Check_Safety_Limits+0x318>)
|
|
800555c: 889b ldrh r3, [r3, #4]
|
|
800555e: b29b uxth r3, r3
|
|
8005560: 2280 movs r2, #128 @ 0x80
|
|
8005562: 0192 lsls r2, r2, #6
|
|
8005564: 4313 orrs r3, r2
|
|
8005566: b29a uxth r2, r3
|
|
8005568: 4b38 ldr r3, [pc, #224] @ (800564c <Check_Safety_Limits+0x318>)
|
|
800556a: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
800556c: f7fe fd68 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg3, 42);
|
|
8005570: 4b3b ldr r3, [pc, #236] @ (8005660 <Check_Safety_Limits+0x32c>)
|
|
8005572: 212a movs r1, #42 @ 0x2a
|
|
8005574: 0018 movs r0, r3
|
|
8005576: f000 ff57 bl 8006428 <TX_Schedule>
|
|
}
|
|
}
|
|
//TPS2
|
|
|
|
if (config->tps2_min < config->tps2_max) {
|
|
800557a: 4b33 ldr r3, [pc, #204] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800557c: 681b ldr r3, [r3, #0]
|
|
800557e: 8a5b ldrh r3, [r3, #18]
|
|
8005580: b29a uxth r2, r3
|
|
8005582: 4b31 ldr r3, [pc, #196] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005584: 681b ldr r3, [r3, #0]
|
|
8005586: 8b1b ldrh r3, [r3, #24]
|
|
8005588: b29b uxth r3, r3
|
|
800558a: 429a cmp r2, r3
|
|
800558c: d22c bcs.n 80055e8 <Check_Safety_Limits+0x2b4>
|
|
if ((config->tps2_margin > config->tps2_min)
|
|
800558e: 4b2e ldr r3, [pc, #184] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005590: 681a ldr r2, [r3, #0]
|
|
8005592: 23d1 movs r3, #209 @ 0xd1
|
|
8005594: 009b lsls r3, r3, #2
|
|
8005596: 5ad3 ldrh r3, [r2, r3]
|
|
8005598: b29a uxth r2, r3
|
|
800559a: 4b2b ldr r3, [pc, #172] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800559c: 681b ldr r3, [r3, #0]
|
|
800559e: 8a5b ldrh r3, [r3, #18]
|
|
80055a0: b29b uxth r3, r3
|
|
80055a2: 429a cmp r2, r3
|
|
80055a4: d80f bhi.n 80055c6 <Check_Safety_Limits+0x292>
|
|
|| ((config->tps2_max + config->tps2_margin) > 4095)) {
|
|
80055a6: 4b28 ldr r3, [pc, #160] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80055a8: 681b ldr r3, [r3, #0]
|
|
80055aa: 8b1b ldrh r3, [r3, #24]
|
|
80055ac: b29b uxth r3, r3
|
|
80055ae: 0019 movs r1, r3
|
|
80055b0: 4b25 ldr r3, [pc, #148] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80055b2: 681a ldr r2, [r3, #0]
|
|
80055b4: 23d1 movs r3, #209 @ 0xd1
|
|
80055b6: 009b lsls r3, r3, #2
|
|
80055b8: 5ad3 ldrh r3, [r2, r3]
|
|
80055ba: b29b uxth r3, r3
|
|
80055bc: 18ca adds r2, r1, r3
|
|
80055be: 2380 movs r3, #128 @ 0x80
|
|
80055c0: 015b lsls r3, r3, #5
|
|
80055c2: 429a cmp r2, r3
|
|
80055c4: db3c blt.n 8005640 <Check_Safety_Limits+0x30c>
|
|
//config errror
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
80055c6: 4b21 ldr r3, [pc, #132] @ (800564c <Check_Safety_Limits+0x318>)
|
|
80055c8: 889b ldrh r3, [r3, #4]
|
|
80055ca: b29b uxth r3, r3
|
|
80055cc: 2280 movs r2, #128 @ 0x80
|
|
80055ce: 0192 lsls r2, r2, #6
|
|
80055d0: 4313 orrs r3, r2
|
|
80055d2: b29a uxth r2, r3
|
|
80055d4: 4b1d ldr r3, [pc, #116] @ (800564c <Check_Safety_Limits+0x318>)
|
|
80055d6: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80055d8: f7fe fd32 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg4, 42);
|
|
80055dc: 4b21 ldr r3, [pc, #132] @ (8005664 <Check_Safety_Limits+0x330>)
|
|
80055de: 212a movs r1, #42 @ 0x2a
|
|
80055e0: 0018 movs r0, r3
|
|
80055e2: f000 ff21 bl 8006428 <TX_Schedule>
|
|
DBW_Stop();
|
|
TX_Schedule((unsigned char*) msg4, 42);
|
|
}
|
|
}
|
|
|
|
}
|
|
80055e6: e02b b.n 8005640 <Check_Safety_Limits+0x30c>
|
|
if ((config->tps2_margin > config->tps2_max)
|
|
80055e8: 4b17 ldr r3, [pc, #92] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80055ea: 681a ldr r2, [r3, #0]
|
|
80055ec: 23d1 movs r3, #209 @ 0xd1
|
|
80055ee: 009b lsls r3, r3, #2
|
|
80055f0: 5ad3 ldrh r3, [r2, r3]
|
|
80055f2: b29a uxth r2, r3
|
|
80055f4: 4b14 ldr r3, [pc, #80] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
80055f6: 681b ldr r3, [r3, #0]
|
|
80055f8: 8b1b ldrh r3, [r3, #24]
|
|
80055fa: b29b uxth r3, r3
|
|
80055fc: 429a cmp r2, r3
|
|
80055fe: d80f bhi.n 8005620 <Check_Safety_Limits+0x2ec>
|
|
|| ((config->tps2_min + config->tps2_margin) > 4095)) {
|
|
8005600: 4b11 ldr r3, [pc, #68] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
8005602: 681b ldr r3, [r3, #0]
|
|
8005604: 8a5b ldrh r3, [r3, #18]
|
|
8005606: b29b uxth r3, r3
|
|
8005608: 0019 movs r1, r3
|
|
800560a: 4b0f ldr r3, [pc, #60] @ (8005648 <Check_Safety_Limits+0x314>)
|
|
800560c: 681a ldr r2, [r3, #0]
|
|
800560e: 23d1 movs r3, #209 @ 0xd1
|
|
8005610: 009b lsls r3, r3, #2
|
|
8005612: 5ad3 ldrh r3, [r2, r3]
|
|
8005614: b29b uxth r3, r3
|
|
8005616: 18ca adds r2, r1, r3
|
|
8005618: 2380 movs r3, #128 @ 0x80
|
|
800561a: 015b lsls r3, r3, #5
|
|
800561c: 429a cmp r2, r3
|
|
800561e: db0f blt.n 8005640 <Check_Safety_Limits+0x30c>
|
|
var.status0 |= DBW_STATUS0_CONF_ERROR_F;
|
|
8005620: 4b0a ldr r3, [pc, #40] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005622: 889b ldrh r3, [r3, #4]
|
|
8005624: b29b uxth r3, r3
|
|
8005626: 2280 movs r2, #128 @ 0x80
|
|
8005628: 0192 lsls r2, r2, #6
|
|
800562a: 4313 orrs r3, r2
|
|
800562c: b29a uxth r2, r3
|
|
800562e: 4b07 ldr r3, [pc, #28] @ (800564c <Check_Safety_Limits+0x318>)
|
|
8005630: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005632: f7fe fd05 bl 8004040 <DBW_Stop>
|
|
TX_Schedule((unsigned char*) msg4, 42);
|
|
8005636: 4b0b ldr r3, [pc, #44] @ (8005664 <Check_Safety_Limits+0x330>)
|
|
8005638: 212a movs r1, #42 @ 0x2a
|
|
800563a: 0018 movs r0, r3
|
|
800563c: f000 fef4 bl 8006428 <TX_Schedule>
|
|
}
|
|
8005640: 46c0 nop @ (mov r8, r8)
|
|
8005642: 46bd mov sp, r7
|
|
8005644: bd80 pop {r7, pc}
|
|
8005646: 46c0 nop @ (mov r8, r8)
|
|
8005648: 200009cc .word 0x200009cc
|
|
800564c: 20000998 .word 0x20000998
|
|
8005650: 08008a30 .word 0x08008a30
|
|
8005654: 0000033e .word 0x0000033e
|
|
8005658: 08008a5c .word 0x08008a5c
|
|
800565c: 00000342 .word 0x00000342
|
|
8005660: 08008a88 .word 0x08008a88
|
|
8005664: 08008ab4 .word 0x08008ab4
|
|
|
|
08005668 <Check_Adc_Range>:
|
|
|
|
void Check_Adc_Range(void) {
|
|
8005668: b580 push {r7, lr}
|
|
800566a: af00 add r7, sp, #0
|
|
|
|
//PPS1
|
|
if (config->pps1_min < config->pps1_max) {
|
|
800566c: 4bc1 ldr r3, [pc, #772] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800566e: 681b ldr r3, [r3, #0]
|
|
8005670: 885b ldrh r3, [r3, #2]
|
|
8005672: b29a uxth r2, r3
|
|
8005674: 4bbf ldr r3, [pc, #764] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005676: 681b ldr r3, [r3, #0]
|
|
8005678: 889b ldrh r3, [r3, #4]
|
|
800567a: b29b uxth r3, r3
|
|
800567c: 429a cmp r2, r3
|
|
800567e: d240 bcs.n 8005702 <Check_Adc_Range+0x9a>
|
|
|
|
if (var.pps1_adc < (config->pps1_min - config->pps1_margin)) {
|
|
8005680: 4bbd ldr r3, [pc, #756] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005682: 899b ldrh r3, [r3, #12]
|
|
8005684: b29b uxth r3, r3
|
|
8005686: 0019 movs r1, r3
|
|
8005688: 4bba ldr r3, [pc, #744] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800568a: 681b ldr r3, [r3, #0]
|
|
800568c: 885b ldrh r3, [r3, #2]
|
|
800568e: b29b uxth r3, r3
|
|
8005690: 0018 movs r0, r3
|
|
8005692: 4bb8 ldr r3, [pc, #736] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005694: 681a ldr r2, [r3, #0]
|
|
8005696: 23cf movs r3, #207 @ 0xcf
|
|
8005698: 009b lsls r3, r3, #2
|
|
800569a: 5ad3 ldrh r3, [r2, r3]
|
|
800569c: b29b uxth r3, r3
|
|
800569e: 1ac3 subs r3, r0, r3
|
|
80056a0: 4299 cmp r1, r3
|
|
80056a2: da0d bge.n 80056c0 <Check_Adc_Range+0x58>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80056a4: 4bb4 ldr r3, [pc, #720] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056a6: 889b ldrh r3, [r3, #4]
|
|
80056a8: b29b uxth r3, r3
|
|
80056aa: 2280 movs r2, #128 @ 0x80
|
|
80056ac: 01d2 lsls r2, r2, #7
|
|
80056ae: 4313 orrs r3, r2
|
|
80056b0: b29a uxth r2, r3
|
|
80056b2: 4bb1 ldr r3, [pc, #708] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056b4: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80056b6: f7fe fcc3 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_GND;
|
|
80056ba: 4baf ldr r3, [pc, #700] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056bc: 2201 movs r2, #1
|
|
80056be: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.pps1_adc > (config->pps1_max + config->pps1_margin)) {
|
|
80056c0: 4bad ldr r3, [pc, #692] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056c2: 899b ldrh r3, [r3, #12]
|
|
80056c4: b29b uxth r3, r3
|
|
80056c6: 0019 movs r1, r3
|
|
80056c8: 4baa ldr r3, [pc, #680] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80056ca: 681b ldr r3, [r3, #0]
|
|
80056cc: 889b ldrh r3, [r3, #4]
|
|
80056ce: b29b uxth r3, r3
|
|
80056d0: 0018 movs r0, r3
|
|
80056d2: 4ba8 ldr r3, [pc, #672] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80056d4: 681a ldr r2, [r3, #0]
|
|
80056d6: 23cf movs r3, #207 @ 0xcf
|
|
80056d8: 009b lsls r3, r3, #2
|
|
80056da: 5ad3 ldrh r3, [r2, r3]
|
|
80056dc: b29b uxth r3, r3
|
|
80056de: 18c3 adds r3, r0, r3
|
|
80056e0: 4299 cmp r1, r3
|
|
80056e2: dd4e ble.n 8005782 <Check_Adc_Range+0x11a>
|
|
//Fault condition PPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80056e4: 4ba4 ldr r3, [pc, #656] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056e6: 889b ldrh r3, [r3, #4]
|
|
80056e8: b29b uxth r3, r3
|
|
80056ea: 2280 movs r2, #128 @ 0x80
|
|
80056ec: 01d2 lsls r2, r2, #7
|
|
80056ee: 4313 orrs r3, r2
|
|
80056f0: b29a uxth r2, r3
|
|
80056f2: 4ba1 ldr r3, [pc, #644] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056f4: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80056f6: f7fe fca3 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_VREF;
|
|
80056fa: 4b9f ldr r3, [pc, #636] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80056fc: 2202 movs r2, #2
|
|
80056fe: 815a strh r2, [r3, #10]
|
|
8005700: e03f b.n 8005782 <Check_Adc_Range+0x11a>
|
|
}
|
|
} else {
|
|
//config->pps1_min < config->pps1_max
|
|
if (var.pps1_adc < (config->pps1_max - config->pps1_margin)) {
|
|
8005702: 4b9d ldr r3, [pc, #628] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005704: 899b ldrh r3, [r3, #12]
|
|
8005706: b29b uxth r3, r3
|
|
8005708: 0019 movs r1, r3
|
|
800570a: 4b9a ldr r3, [pc, #616] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800570c: 681b ldr r3, [r3, #0]
|
|
800570e: 889b ldrh r3, [r3, #4]
|
|
8005710: b29b uxth r3, r3
|
|
8005712: 0018 movs r0, r3
|
|
8005714: 4b97 ldr r3, [pc, #604] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005716: 681a ldr r2, [r3, #0]
|
|
8005718: 23cf movs r3, #207 @ 0xcf
|
|
800571a: 009b lsls r3, r3, #2
|
|
800571c: 5ad3 ldrh r3, [r2, r3]
|
|
800571e: b29b uxth r3, r3
|
|
8005720: 1ac3 subs r3, r0, r3
|
|
8005722: 4299 cmp r1, r3
|
|
8005724: da0d bge.n 8005742 <Check_Adc_Range+0xda>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005726: 4b94 ldr r3, [pc, #592] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005728: 889b ldrh r3, [r3, #4]
|
|
800572a: b29b uxth r3, r3
|
|
800572c: 2280 movs r2, #128 @ 0x80
|
|
800572e: 01d2 lsls r2, r2, #7
|
|
8005730: 4313 orrs r3, r2
|
|
8005732: b29a uxth r2, r3
|
|
8005734: 4b90 ldr r3, [pc, #576] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005736: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005738: f7fe fc82 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_GND;
|
|
800573c: 4b8e ldr r3, [pc, #568] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800573e: 2201 movs r2, #1
|
|
8005740: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.pps1_adc > (config->pps1_min + config->pps1_margin)) {
|
|
8005742: 4b8d ldr r3, [pc, #564] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005744: 899b ldrh r3, [r3, #12]
|
|
8005746: b29b uxth r3, r3
|
|
8005748: 0019 movs r1, r3
|
|
800574a: 4b8a ldr r3, [pc, #552] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800574c: 681b ldr r3, [r3, #0]
|
|
800574e: 885b ldrh r3, [r3, #2]
|
|
8005750: b29b uxth r3, r3
|
|
8005752: 0018 movs r0, r3
|
|
8005754: 4b87 ldr r3, [pc, #540] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005756: 681a ldr r2, [r3, #0]
|
|
8005758: 23cf movs r3, #207 @ 0xcf
|
|
800575a: 009b lsls r3, r3, #2
|
|
800575c: 5ad3 ldrh r3, [r2, r3]
|
|
800575e: b29b uxth r3, r3
|
|
8005760: 18c3 adds r3, r0, r3
|
|
8005762: 4299 cmp r1, r3
|
|
8005764: dd0d ble.n 8005782 <Check_Adc_Range+0x11a>
|
|
//Fault condition PPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005766: 4b84 ldr r3, [pc, #528] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005768: 889b ldrh r3, [r3, #4]
|
|
800576a: b29b uxth r3, r3
|
|
800576c: 2280 movs r2, #128 @ 0x80
|
|
800576e: 01d2 lsls r2, r2, #7
|
|
8005770: 4313 orrs r3, r2
|
|
8005772: b29a uxth r2, r3
|
|
8005774: 4b80 ldr r3, [pc, #512] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005776: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005778: f7fe fc62 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_VREF;
|
|
800577c: 4b7e ldr r3, [pc, #504] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800577e: 2202 movs r2, #2
|
|
8005780: 815a strh r2, [r3, #10]
|
|
}
|
|
}
|
|
|
|
//PPS2
|
|
if (config->pps2_min < config->pps2_max) {
|
|
8005782: 4b7c ldr r3, [pc, #496] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005784: 681b ldr r3, [r3, #0]
|
|
8005786: 88db ldrh r3, [r3, #6]
|
|
8005788: b29a uxth r2, r3
|
|
800578a: 4b7a ldr r3, [pc, #488] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800578c: 681b ldr r3, [r3, #0]
|
|
800578e: 899b ldrh r3, [r3, #12]
|
|
8005790: b29b uxth r3, r3
|
|
8005792: 429a cmp r2, r3
|
|
8005794: d23e bcs.n 8005814 <Check_Adc_Range+0x1ac>
|
|
if (var.pps2_adc < (config->pps2_min - config->pps2_margin)) {
|
|
8005796: 4b78 ldr r3, [pc, #480] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005798: 89db ldrh r3, [r3, #14]
|
|
800579a: b29b uxth r3, r3
|
|
800579c: 0019 movs r1, r3
|
|
800579e: 4b75 ldr r3, [pc, #468] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80057a0: 681b ldr r3, [r3, #0]
|
|
80057a2: 88db ldrh r3, [r3, #6]
|
|
80057a4: b29b uxth r3, r3
|
|
80057a6: 0018 movs r0, r3
|
|
80057a8: 4b72 ldr r3, [pc, #456] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80057aa: 681b ldr r3, [r3, #0]
|
|
80057ac: 4a73 ldr r2, [pc, #460] @ (800597c <Check_Adc_Range+0x314>)
|
|
80057ae: 5a9b ldrh r3, [r3, r2]
|
|
80057b0: b29b uxth r3, r3
|
|
80057b2: 1ac3 subs r3, r0, r3
|
|
80057b4: 4299 cmp r1, r3
|
|
80057b6: da0d bge.n 80057d4 <Check_Adc_Range+0x16c>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80057b8: 4b6f ldr r3, [pc, #444] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80057ba: 889b ldrh r3, [r3, #4]
|
|
80057bc: b29b uxth r3, r3
|
|
80057be: 2280 movs r2, #128 @ 0x80
|
|
80057c0: 01d2 lsls r2, r2, #7
|
|
80057c2: 4313 orrs r3, r2
|
|
80057c4: b29a uxth r2, r3
|
|
80057c6: 4b6c ldr r3, [pc, #432] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80057c8: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80057ca: f7fe fc39 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS2_SS_GND;
|
|
80057ce: 4b6a ldr r3, [pc, #424] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80057d0: 2203 movs r2, #3
|
|
80057d2: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.pps2_adc > (config->pps2_max + config->pps2_margin)) {
|
|
80057d4: 4b68 ldr r3, [pc, #416] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80057d6: 89db ldrh r3, [r3, #14]
|
|
80057d8: b29b uxth r3, r3
|
|
80057da: 0019 movs r1, r3
|
|
80057dc: 4b65 ldr r3, [pc, #404] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80057de: 681b ldr r3, [r3, #0]
|
|
80057e0: 899b ldrh r3, [r3, #12]
|
|
80057e2: b29b uxth r3, r3
|
|
80057e4: 0018 movs r0, r3
|
|
80057e6: 4b63 ldr r3, [pc, #396] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80057e8: 681b ldr r3, [r3, #0]
|
|
80057ea: 4a64 ldr r2, [pc, #400] @ (800597c <Check_Adc_Range+0x314>)
|
|
80057ec: 5a9b ldrh r3, [r3, r2]
|
|
80057ee: b29b uxth r3, r3
|
|
80057f0: 18c3 adds r3, r0, r3
|
|
80057f2: 4299 cmp r1, r3
|
|
80057f4: dd4c ble.n 8005890 <Check_Adc_Range+0x228>
|
|
//Fault condition PPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80057f6: 4b60 ldr r3, [pc, #384] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80057f8: 889b ldrh r3, [r3, #4]
|
|
80057fa: b29b uxth r3, r3
|
|
80057fc: 2280 movs r2, #128 @ 0x80
|
|
80057fe: 01d2 lsls r2, r2, #7
|
|
8005800: 4313 orrs r3, r2
|
|
8005802: b29a uxth r2, r3
|
|
8005804: 4b5c ldr r3, [pc, #368] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005806: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005808: f7fe fc1a bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_VREF;
|
|
800580c: 4b5a ldr r3, [pc, #360] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800580e: 2202 movs r2, #2
|
|
8005810: 815a strh r2, [r3, #10]
|
|
8005812: e03d b.n 8005890 <Check_Adc_Range+0x228>
|
|
}
|
|
} else {
|
|
|
|
if (var.pps2_adc < (config->pps2_max - config->pps2_margin)) {
|
|
8005814: 4b58 ldr r3, [pc, #352] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005816: 89db ldrh r3, [r3, #14]
|
|
8005818: b29b uxth r3, r3
|
|
800581a: 0019 movs r1, r3
|
|
800581c: 4b55 ldr r3, [pc, #340] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800581e: 681b ldr r3, [r3, #0]
|
|
8005820: 899b ldrh r3, [r3, #12]
|
|
8005822: b29b uxth r3, r3
|
|
8005824: 0018 movs r0, r3
|
|
8005826: 4b53 ldr r3, [pc, #332] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005828: 681b ldr r3, [r3, #0]
|
|
800582a: 4a54 ldr r2, [pc, #336] @ (800597c <Check_Adc_Range+0x314>)
|
|
800582c: 5a9b ldrh r3, [r3, r2]
|
|
800582e: b29b uxth r3, r3
|
|
8005830: 1ac3 subs r3, r0, r3
|
|
8005832: 4299 cmp r1, r3
|
|
8005834: da0d bge.n 8005852 <Check_Adc_Range+0x1ea>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005836: 4b50 ldr r3, [pc, #320] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005838: 889b ldrh r3, [r3, #4]
|
|
800583a: b29b uxth r3, r3
|
|
800583c: 2280 movs r2, #128 @ 0x80
|
|
800583e: 01d2 lsls r2, r2, #7
|
|
8005840: 4313 orrs r3, r2
|
|
8005842: b29a uxth r2, r3
|
|
8005844: 4b4c ldr r3, [pc, #304] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005846: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005848: f7fe fbfa bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS2_SS_GND;
|
|
800584c: 4b4a ldr r3, [pc, #296] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800584e: 2203 movs r2, #3
|
|
8005850: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.pps2_adc > (config->pps2_min + config->pps2_margin)) {
|
|
8005852: 4b49 ldr r3, [pc, #292] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005854: 89db ldrh r3, [r3, #14]
|
|
8005856: b29b uxth r3, r3
|
|
8005858: 0019 movs r1, r3
|
|
800585a: 4b46 ldr r3, [pc, #280] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800585c: 681b ldr r3, [r3, #0]
|
|
800585e: 88db ldrh r3, [r3, #6]
|
|
8005860: b29b uxth r3, r3
|
|
8005862: 0018 movs r0, r3
|
|
8005864: 4b43 ldr r3, [pc, #268] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005866: 681b ldr r3, [r3, #0]
|
|
8005868: 4a44 ldr r2, [pc, #272] @ (800597c <Check_Adc_Range+0x314>)
|
|
800586a: 5a9b ldrh r3, [r3, r2]
|
|
800586c: b29b uxth r3, r3
|
|
800586e: 18c3 adds r3, r0, r3
|
|
8005870: 4299 cmp r1, r3
|
|
8005872: dd0d ble.n 8005890 <Check_Adc_Range+0x228>
|
|
//Fault condition PPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005874: 4b40 ldr r3, [pc, #256] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005876: 889b ldrh r3, [r3, #4]
|
|
8005878: b29b uxth r3, r3
|
|
800587a: 2280 movs r2, #128 @ 0x80
|
|
800587c: 01d2 lsls r2, r2, #7
|
|
800587e: 4313 orrs r3, r2
|
|
8005880: b29a uxth r2, r3
|
|
8005882: 4b3d ldr r3, [pc, #244] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005884: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005886: f7fe fbdb bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS1_SS_VREF;
|
|
800588a: 4b3b ldr r3, [pc, #236] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800588c: 2202 movs r2, #2
|
|
800588e: 815a strh r2, [r3, #10]
|
|
}
|
|
}
|
|
|
|
//PPS Delta
|
|
if ((var.pps_delta > config->pps_delta_margin)
|
|
8005890: 4b39 ldr r3, [pc, #228] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005892: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8005894: b21a sxth r2, r3
|
|
8005896: 4b37 ldr r3, [pc, #220] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005898: 6819 ldr r1, [r3, #0]
|
|
800589a: 23d0 movs r3, #208 @ 0xd0
|
|
800589c: 009b lsls r3, r3, #2
|
|
800589e: 5acb ldrh r3, [r1, r3]
|
|
80058a0: b21b sxth r3, r3
|
|
80058a2: 429a cmp r2, r3
|
|
80058a4: dc0e bgt.n 80058c4 <Check_Adc_Range+0x25c>
|
|
|| (var.pps_delta < ((int16_t) -config->pps_delta_margin))) {
|
|
80058a6: 4b34 ldr r3, [pc, #208] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80058a8: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
80058aa: b21a sxth r2, r3
|
|
80058ac: 4b31 ldr r3, [pc, #196] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80058ae: 6819 ldr r1, [r3, #0]
|
|
80058b0: 23d0 movs r3, #208 @ 0xd0
|
|
80058b2: 009b lsls r3, r3, #2
|
|
80058b4: 5acb ldrh r3, [r1, r3]
|
|
80058b6: b21b sxth r3, r3
|
|
80058b8: b29b uxth r3, r3
|
|
80058ba: 425b negs r3, r3
|
|
80058bc: b29b uxth r3, r3
|
|
80058be: b21b sxth r3, r3
|
|
80058c0: 429a cmp r2, r3
|
|
80058c2: da0d bge.n 80058e0 <Check_Adc_Range+0x278>
|
|
//Fault condition PPS DELTA
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80058c4: 4b2c ldr r3, [pc, #176] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80058c6: 889b ldrh r3, [r3, #4]
|
|
80058c8: b29b uxth r3, r3
|
|
80058ca: 2280 movs r2, #128 @ 0x80
|
|
80058cc: 01d2 lsls r2, r2, #7
|
|
80058ce: 4313 orrs r3, r2
|
|
80058d0: b29a uxth r2, r3
|
|
80058d2: 4b29 ldr r3, [pc, #164] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80058d4: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80058d6: f7fe fbb3 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_PPS_DELTA;
|
|
80058da: 4b27 ldr r3, [pc, #156] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80058dc: 2205 movs r2, #5
|
|
80058de: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
//##########################################
|
|
//TPS1
|
|
if (config->tps1_min < config->tps1_max) {
|
|
80058e0: 4b24 ldr r3, [pc, #144] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80058e2: 681b ldr r3, [r3, #0]
|
|
80058e4: 89db ldrh r3, [r3, #14]
|
|
80058e6: b29a uxth r2, r3
|
|
80058e8: 4b22 ldr r3, [pc, #136] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80058ea: 681b ldr r3, [r3, #0]
|
|
80058ec: 8a1b ldrh r3, [r3, #16]
|
|
80058ee: b29b uxth r3, r3
|
|
80058f0: 429a cmp r2, r3
|
|
80058f2: d247 bcs.n 8005984 <Check_Adc_Range+0x31c>
|
|
if (var.tps1_adc < (config->tps1_min - config->tps1_margin)) {
|
|
80058f4: 4b20 ldr r3, [pc, #128] @ (8005978 <Check_Adc_Range+0x310>)
|
|
80058f6: 8a1b ldrh r3, [r3, #16]
|
|
80058f8: b29b uxth r3, r3
|
|
80058fa: 0019 movs r1, r3
|
|
80058fc: 4b1d ldr r3, [pc, #116] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
80058fe: 681b ldr r3, [r3, #0]
|
|
8005900: 89db ldrh r3, [r3, #14]
|
|
8005902: b29b uxth r3, r3
|
|
8005904: 0018 movs r0, r3
|
|
8005906: 4b1b ldr r3, [pc, #108] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005908: 681b ldr r3, [r3, #0]
|
|
800590a: 4a1d ldr r2, [pc, #116] @ (8005980 <Check_Adc_Range+0x318>)
|
|
800590c: 5a9b ldrh r3, [r3, r2]
|
|
800590e: b29b uxth r3, r3
|
|
8005910: 1ac3 subs r3, r0, r3
|
|
8005912: 4299 cmp r1, r3
|
|
8005914: da0d bge.n 8005932 <Check_Adc_Range+0x2ca>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005916: 4b18 ldr r3, [pc, #96] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005918: 889b ldrh r3, [r3, #4]
|
|
800591a: b29b uxth r3, r3
|
|
800591c: 2280 movs r2, #128 @ 0x80
|
|
800591e: 01d2 lsls r2, r2, #7
|
|
8005920: 4313 orrs r3, r2
|
|
8005922: b29a uxth r2, r3
|
|
8005924: 4b14 ldr r3, [pc, #80] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005926: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005928: f7fe fb8a bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS1_SS_GND;
|
|
800592c: 4b12 ldr r3, [pc, #72] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800592e: 2206 movs r2, #6
|
|
8005930: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.tps1_adc > (config->tps1_max + config->tps1_margin)) {
|
|
8005932: 4b11 ldr r3, [pc, #68] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005934: 8a1b ldrh r3, [r3, #16]
|
|
8005936: b29b uxth r3, r3
|
|
8005938: 0019 movs r1, r3
|
|
800593a: 4b0e ldr r3, [pc, #56] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
800593c: 681b ldr r3, [r3, #0]
|
|
800593e: 8a1b ldrh r3, [r3, #16]
|
|
8005940: b29b uxth r3, r3
|
|
8005942: 0018 movs r0, r3
|
|
8005944: 4b0b ldr r3, [pc, #44] @ (8005974 <Check_Adc_Range+0x30c>)
|
|
8005946: 681b ldr r3, [r3, #0]
|
|
8005948: 4a0d ldr r2, [pc, #52] @ (8005980 <Check_Adc_Range+0x318>)
|
|
800594a: 5a9b ldrh r3, [r3, r2]
|
|
800594c: b29b uxth r3, r3
|
|
800594e: 18c3 adds r3, r0, r3
|
|
8005950: 4299 cmp r1, r3
|
|
8005952: dd55 ble.n 8005a00 <Check_Adc_Range+0x398>
|
|
//Fault condition TPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005954: 4b08 ldr r3, [pc, #32] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005956: 889b ldrh r3, [r3, #4]
|
|
8005958: b29b uxth r3, r3
|
|
800595a: 2280 movs r2, #128 @ 0x80
|
|
800595c: 01d2 lsls r2, r2, #7
|
|
800595e: 4313 orrs r3, r2
|
|
8005960: b29a uxth r2, r3
|
|
8005962: 4b05 ldr r3, [pc, #20] @ (8005978 <Check_Adc_Range+0x310>)
|
|
8005964: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005966: f7fe fb6b bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS1_SS_VREF;
|
|
800596a: 4b03 ldr r3, [pc, #12] @ (8005978 <Check_Adc_Range+0x310>)
|
|
800596c: 2207 movs r2, #7
|
|
800596e: 815a strh r2, [r3, #10]
|
|
8005970: e046 b.n 8005a00 <Check_Adc_Range+0x398>
|
|
8005972: 46c0 nop @ (mov r8, r8)
|
|
8005974: 200009cc .word 0x200009cc
|
|
8005978: 20000998 .word 0x20000998
|
|
800597c: 0000033e .word 0x0000033e
|
|
8005980: 00000342 .word 0x00000342
|
|
}
|
|
} else {
|
|
|
|
if (var.tps1_adc < (config->tps1_max - config->tps1_margin)) {
|
|
8005984: 4b78 ldr r3, [pc, #480] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005986: 8a1b ldrh r3, [r3, #16]
|
|
8005988: b29b uxth r3, r3
|
|
800598a: 0019 movs r1, r3
|
|
800598c: 4b77 ldr r3, [pc, #476] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
800598e: 681b ldr r3, [r3, #0]
|
|
8005990: 8a1b ldrh r3, [r3, #16]
|
|
8005992: b29b uxth r3, r3
|
|
8005994: 0018 movs r0, r3
|
|
8005996: 4b75 ldr r3, [pc, #468] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005998: 681b ldr r3, [r3, #0]
|
|
800599a: 4a75 ldr r2, [pc, #468] @ (8005b70 <Check_Adc_Range+0x508>)
|
|
800599c: 5a9b ldrh r3, [r3, r2]
|
|
800599e: b29b uxth r3, r3
|
|
80059a0: 1ac3 subs r3, r0, r3
|
|
80059a2: 4299 cmp r1, r3
|
|
80059a4: da0d bge.n 80059c2 <Check_Adc_Range+0x35a>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80059a6: 4b70 ldr r3, [pc, #448] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059a8: 889b ldrh r3, [r3, #4]
|
|
80059aa: b29b uxth r3, r3
|
|
80059ac: 2280 movs r2, #128 @ 0x80
|
|
80059ae: 01d2 lsls r2, r2, #7
|
|
80059b0: 4313 orrs r3, r2
|
|
80059b2: b29a uxth r2, r3
|
|
80059b4: 4b6c ldr r3, [pc, #432] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059b6: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80059b8: f7fe fb42 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS1_SS_GND;
|
|
80059bc: 4b6a ldr r3, [pc, #424] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059be: 2206 movs r2, #6
|
|
80059c0: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.tps1_adc > (config->tps1_min + config->tps1_margin)) {
|
|
80059c2: 4b69 ldr r3, [pc, #420] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059c4: 8a1b ldrh r3, [r3, #16]
|
|
80059c6: b29b uxth r3, r3
|
|
80059c8: 0019 movs r1, r3
|
|
80059ca: 4b68 ldr r3, [pc, #416] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
80059cc: 681b ldr r3, [r3, #0]
|
|
80059ce: 89db ldrh r3, [r3, #14]
|
|
80059d0: b29b uxth r3, r3
|
|
80059d2: 0018 movs r0, r3
|
|
80059d4: 4b65 ldr r3, [pc, #404] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
80059d6: 681b ldr r3, [r3, #0]
|
|
80059d8: 4a65 ldr r2, [pc, #404] @ (8005b70 <Check_Adc_Range+0x508>)
|
|
80059da: 5a9b ldrh r3, [r3, r2]
|
|
80059dc: b29b uxth r3, r3
|
|
80059de: 18c3 adds r3, r0, r3
|
|
80059e0: 4299 cmp r1, r3
|
|
80059e2: dd0d ble.n 8005a00 <Check_Adc_Range+0x398>
|
|
//Fault condition TPS1 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
80059e4: 4b60 ldr r3, [pc, #384] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059e6: 889b ldrh r3, [r3, #4]
|
|
80059e8: b29b uxth r3, r3
|
|
80059ea: 2280 movs r2, #128 @ 0x80
|
|
80059ec: 01d2 lsls r2, r2, #7
|
|
80059ee: 4313 orrs r3, r2
|
|
80059f0: b29a uxth r2, r3
|
|
80059f2: 4b5d ldr r3, [pc, #372] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059f4: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
80059f6: f7fe fb23 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS1_SS_VREF;
|
|
80059fa: 4b5b ldr r3, [pc, #364] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
80059fc: 2207 movs r2, #7
|
|
80059fe: 815a strh r2, [r3, #10]
|
|
}
|
|
}
|
|
|
|
//TPS2
|
|
if (config->tps2_min < config->tps2_max) {
|
|
8005a00: 4b5a ldr r3, [pc, #360] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a02: 681b ldr r3, [r3, #0]
|
|
8005a04: 8a5b ldrh r3, [r3, #18]
|
|
8005a06: b29a uxth r2, r3
|
|
8005a08: 4b58 ldr r3, [pc, #352] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a0a: 681b ldr r3, [r3, #0]
|
|
8005a0c: 8b1b ldrh r3, [r3, #24]
|
|
8005a0e: b29b uxth r3, r3
|
|
8005a10: 429a cmp r2, r3
|
|
8005a12: d240 bcs.n 8005a96 <Check_Adc_Range+0x42e>
|
|
if (var.tps2_adc < (config->tps2_min - config->tps2_margin)) {
|
|
8005a14: 4b54 ldr r3, [pc, #336] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a16: 8a5b ldrh r3, [r3, #18]
|
|
8005a18: b29b uxth r3, r3
|
|
8005a1a: 0019 movs r1, r3
|
|
8005a1c: 4b53 ldr r3, [pc, #332] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a1e: 681b ldr r3, [r3, #0]
|
|
8005a20: 8a5b ldrh r3, [r3, #18]
|
|
8005a22: b29b uxth r3, r3
|
|
8005a24: 0018 movs r0, r3
|
|
8005a26: 4b51 ldr r3, [pc, #324] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a28: 681a ldr r2, [r3, #0]
|
|
8005a2a: 23d1 movs r3, #209 @ 0xd1
|
|
8005a2c: 009b lsls r3, r3, #2
|
|
8005a2e: 5ad3 ldrh r3, [r2, r3]
|
|
8005a30: b29b uxth r3, r3
|
|
8005a32: 1ac3 subs r3, r0, r3
|
|
8005a34: 4299 cmp r1, r3
|
|
8005a36: da0d bge.n 8005a54 <Check_Adc_Range+0x3ec>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005a38: 4b4b ldr r3, [pc, #300] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a3a: 889b ldrh r3, [r3, #4]
|
|
8005a3c: b29b uxth r3, r3
|
|
8005a3e: 2280 movs r2, #128 @ 0x80
|
|
8005a40: 01d2 lsls r2, r2, #7
|
|
8005a42: 4313 orrs r3, r2
|
|
8005a44: b29a uxth r2, r3
|
|
8005a46: 4b48 ldr r3, [pc, #288] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a48: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005a4a: f7fe faf9 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS2_SS_GND;
|
|
8005a4e: 4b46 ldr r3, [pc, #280] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a50: 2208 movs r2, #8
|
|
8005a52: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.tps2_adc > (config->tps2_max + config->tps2_margin)) {
|
|
8005a54: 4b44 ldr r3, [pc, #272] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a56: 8a5b ldrh r3, [r3, #18]
|
|
8005a58: b29b uxth r3, r3
|
|
8005a5a: 0019 movs r1, r3
|
|
8005a5c: 4b43 ldr r3, [pc, #268] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a5e: 681b ldr r3, [r3, #0]
|
|
8005a60: 8b1b ldrh r3, [r3, #24]
|
|
8005a62: b29b uxth r3, r3
|
|
8005a64: 0018 movs r0, r3
|
|
8005a66: 4b41 ldr r3, [pc, #260] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005a68: 681a ldr r2, [r3, #0]
|
|
8005a6a: 23d1 movs r3, #209 @ 0xd1
|
|
8005a6c: 009b lsls r3, r3, #2
|
|
8005a6e: 5ad3 ldrh r3, [r2, r3]
|
|
8005a70: b29b uxth r3, r3
|
|
8005a72: 18c3 adds r3, r0, r3
|
|
8005a74: 4299 cmp r1, r3
|
|
8005a76: dd4e ble.n 8005b16 <Check_Adc_Range+0x4ae>
|
|
//Fault condition TPS2 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005a78: 4b3b ldr r3, [pc, #236] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a7a: 889b ldrh r3, [r3, #4]
|
|
8005a7c: b29b uxth r3, r3
|
|
8005a7e: 2280 movs r2, #128 @ 0x80
|
|
8005a80: 01d2 lsls r2, r2, #7
|
|
8005a82: 4313 orrs r3, r2
|
|
8005a84: b29a uxth r2, r3
|
|
8005a86: 4b38 ldr r3, [pc, #224] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a88: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005a8a: f7fe fad9 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS2_SS_VREF;
|
|
8005a8e: 4b36 ldr r3, [pc, #216] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a90: 2209 movs r2, #9
|
|
8005a92: 815a strh r2, [r3, #10]
|
|
8005a94: e03f b.n 8005b16 <Check_Adc_Range+0x4ae>
|
|
}
|
|
} else {
|
|
if (var.tps2_adc < (config->tps2_max - config->tps2_margin)) {
|
|
8005a96: 4b34 ldr r3, [pc, #208] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005a98: 8a5b ldrh r3, [r3, #18]
|
|
8005a9a: b29b uxth r3, r3
|
|
8005a9c: 0019 movs r1, r3
|
|
8005a9e: 4b33 ldr r3, [pc, #204] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005aa0: 681b ldr r3, [r3, #0]
|
|
8005aa2: 8b1b ldrh r3, [r3, #24]
|
|
8005aa4: b29b uxth r3, r3
|
|
8005aa6: 0018 movs r0, r3
|
|
8005aa8: 4b30 ldr r3, [pc, #192] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005aaa: 681a ldr r2, [r3, #0]
|
|
8005aac: 23d1 movs r3, #209 @ 0xd1
|
|
8005aae: 009b lsls r3, r3, #2
|
|
8005ab0: 5ad3 ldrh r3, [r2, r3]
|
|
8005ab2: b29b uxth r3, r3
|
|
8005ab4: 1ac3 subs r3, r0, r3
|
|
8005ab6: 4299 cmp r1, r3
|
|
8005ab8: da0d bge.n 8005ad6 <Check_Adc_Range+0x46e>
|
|
//Fault condition PPS1 min
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005aba: 4b2b ldr r3, [pc, #172] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005abc: 889b ldrh r3, [r3, #4]
|
|
8005abe: b29b uxth r3, r3
|
|
8005ac0: 2280 movs r2, #128 @ 0x80
|
|
8005ac2: 01d2 lsls r2, r2, #7
|
|
8005ac4: 4313 orrs r3, r2
|
|
8005ac6: b29a uxth r2, r3
|
|
8005ac8: 4b27 ldr r3, [pc, #156] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005aca: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005acc: f7fe fab8 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS2_SS_GND;
|
|
8005ad0: 4b25 ldr r3, [pc, #148] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005ad2: 2208 movs r2, #8
|
|
8005ad4: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (var.tps2_adc > (config->tps2_min + config->tps2_margin)) {
|
|
8005ad6: 4b24 ldr r3, [pc, #144] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005ad8: 8a5b ldrh r3, [r3, #18]
|
|
8005ada: b29b uxth r3, r3
|
|
8005adc: 0019 movs r1, r3
|
|
8005ade: 4b23 ldr r3, [pc, #140] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005ae0: 681b ldr r3, [r3, #0]
|
|
8005ae2: 8a5b ldrh r3, [r3, #18]
|
|
8005ae4: b29b uxth r3, r3
|
|
8005ae6: 0018 movs r0, r3
|
|
8005ae8: 4b20 ldr r3, [pc, #128] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005aea: 681a ldr r2, [r3, #0]
|
|
8005aec: 23d1 movs r3, #209 @ 0xd1
|
|
8005aee: 009b lsls r3, r3, #2
|
|
8005af0: 5ad3 ldrh r3, [r2, r3]
|
|
8005af2: b29b uxth r3, r3
|
|
8005af4: 18c3 adds r3, r0, r3
|
|
8005af6: 4299 cmp r1, r3
|
|
8005af8: dd0d ble.n 8005b16 <Check_Adc_Range+0x4ae>
|
|
//Fault condition TPS2 MAX
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005afa: 4b1b ldr r3, [pc, #108] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005afc: 889b ldrh r3, [r3, #4]
|
|
8005afe: b29b uxth r3, r3
|
|
8005b00: 2280 movs r2, #128 @ 0x80
|
|
8005b02: 01d2 lsls r2, r2, #7
|
|
8005b04: 4313 orrs r3, r2
|
|
8005b06: b29a uxth r2, r3
|
|
8005b08: 4b17 ldr r3, [pc, #92] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b0a: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005b0c: f7fe fa98 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS2_SS_VREF;
|
|
8005b10: 4b15 ldr r3, [pc, #84] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b12: 2209 movs r2, #9
|
|
8005b14: 815a strh r2, [r3, #10]
|
|
}
|
|
}
|
|
|
|
//TPS Delta
|
|
if ((var.tps_delta > config->tps_delta_margin)
|
|
8005b16: 4b14 ldr r3, [pc, #80] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b18: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005b1a: b21b sxth r3, r3
|
|
8005b1c: 0019 movs r1, r3
|
|
8005b1e: 4b13 ldr r3, [pc, #76] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005b20: 681b ldr r3, [r3, #0]
|
|
8005b22: 4a14 ldr r2, [pc, #80] @ (8005b74 <Check_Adc_Range+0x50c>)
|
|
8005b24: 5a9b ldrh r3, [r3, r2]
|
|
8005b26: b29b uxth r3, r3
|
|
8005b28: 4299 cmp r1, r3
|
|
8005b2a: dc0c bgt.n 8005b46 <Check_Adc_Range+0x4de>
|
|
|| (var.tps_delta < ((int16_t) -config->tps_delta_margin))) {
|
|
8005b2c: 4b0e ldr r3, [pc, #56] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b2e: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8005b30: b21a sxth r2, r3
|
|
8005b32: 4b0e ldr r3, [pc, #56] @ (8005b6c <Check_Adc_Range+0x504>)
|
|
8005b34: 681b ldr r3, [r3, #0]
|
|
8005b36: 490f ldr r1, [pc, #60] @ (8005b74 <Check_Adc_Range+0x50c>)
|
|
8005b38: 5a5b ldrh r3, [r3, r1]
|
|
8005b3a: b29b uxth r3, r3
|
|
8005b3c: 425b negs r3, r3
|
|
8005b3e: b29b uxth r3, r3
|
|
8005b40: b21b sxth r3, r3
|
|
8005b42: 429a cmp r2, r3
|
|
8005b44: da0d bge.n 8005b62 <Check_Adc_Range+0x4fa>
|
|
//Fault condition PPS DELTA
|
|
var.status0 |= DBW_STATUS0_SENSOR_FAULT_F;
|
|
8005b46: 4b08 ldr r3, [pc, #32] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b48: 889b ldrh r3, [r3, #4]
|
|
8005b4a: b29b uxth r3, r3
|
|
8005b4c: 2280 movs r2, #128 @ 0x80
|
|
8005b4e: 01d2 lsls r2, r2, #7
|
|
8005b50: 4313 orrs r3, r2
|
|
8005b52: b29a uxth r2, r3
|
|
8005b54: 4b04 ldr r3, [pc, #16] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b56: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005b58: f7fe fa72 bl 8004040 <DBW_Stop>
|
|
var.status3 = STATUS3_TPS_DELTA;
|
|
8005b5c: 4b02 ldr r3, [pc, #8] @ (8005b68 <Check_Adc_Range+0x500>)
|
|
8005b5e: 220a movs r2, #10
|
|
8005b60: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
}
|
|
8005b62: 46c0 nop @ (mov r8, r8)
|
|
8005b64: 46bd mov sp, r7
|
|
8005b66: bd80 pop {r7, pc}
|
|
8005b68: 20000998 .word 0x20000998
|
|
8005b6c: 200009cc .word 0x200009cc
|
|
8005b70: 00000342 .word 0x00000342
|
|
8005b74: 00000346 .word 0x00000346
|
|
|
|
08005b78 <Safety_TPS_Safety_Timer>:
|
|
|
|
volatile int dbw_target_tmr1, dbw_target_tmr2;
|
|
|
|
void Safety_TPS_Safety_Timer(void) {
|
|
8005b78: b580 push {r7, lr}
|
|
8005b7a: af00 add r7, sp, #0
|
|
if (dbw_target_tmr1 > 0)
|
|
8005b7c: 4b0a ldr r3, [pc, #40] @ (8005ba8 <Safety_TPS_Safety_Timer+0x30>)
|
|
8005b7e: 681b ldr r3, [r3, #0]
|
|
8005b80: 2b00 cmp r3, #0
|
|
8005b82: dd04 ble.n 8005b8e <Safety_TPS_Safety_Timer+0x16>
|
|
dbw_target_tmr1--;
|
|
8005b84: 4b08 ldr r3, [pc, #32] @ (8005ba8 <Safety_TPS_Safety_Timer+0x30>)
|
|
8005b86: 681b ldr r3, [r3, #0]
|
|
8005b88: 1e5a subs r2, r3, #1
|
|
8005b8a: 4b07 ldr r3, [pc, #28] @ (8005ba8 <Safety_TPS_Safety_Timer+0x30>)
|
|
8005b8c: 601a str r2, [r3, #0]
|
|
if (dbw_target_tmr2 > 0)
|
|
8005b8e: 4b07 ldr r3, [pc, #28] @ (8005bac <Safety_TPS_Safety_Timer+0x34>)
|
|
8005b90: 681b ldr r3, [r3, #0]
|
|
8005b92: 2b00 cmp r3, #0
|
|
8005b94: dd04 ble.n 8005ba0 <Safety_TPS_Safety_Timer+0x28>
|
|
dbw_target_tmr2--;
|
|
8005b96: 4b05 ldr r3, [pc, #20] @ (8005bac <Safety_TPS_Safety_Timer+0x34>)
|
|
8005b98: 681b ldr r3, [r3, #0]
|
|
8005b9a: 1e5a subs r2, r3, #1
|
|
8005b9c: 4b03 ldr r3, [pc, #12] @ (8005bac <Safety_TPS_Safety_Timer+0x34>)
|
|
8005b9e: 601a str r2, [r3, #0]
|
|
}
|
|
8005ba0: 46c0 nop @ (mov r8, r8)
|
|
8005ba2: 46bd mov sp, r7
|
|
8005ba4: bd80 pop {r7, pc}
|
|
8005ba6: 46c0 nop @ (mov r8, r8)
|
|
8005ba8: 20000b2c .word 0x20000b2c
|
|
8005bac: 20000b30 .word 0x20000b30
|
|
|
|
08005bb0 <Safety_TPS_Safety_Timer_Start>:
|
|
|
|
void Safety_TPS_Safety_Timer_Start(void) {
|
|
8005bb0: b580 push {r7, lr}
|
|
8005bb2: af00 add r7, sp, #0
|
|
//enable timers. add 1S time to start, because safety system starts in 1S after startup
|
|
dbw_target_tmr1 = config->tps_error_time1 + 1000;
|
|
8005bb4: 4b0a ldr r3, [pc, #40] @ (8005be0 <Safety_TPS_Safety_Timer_Start+0x30>)
|
|
8005bb6: 681b ldr r3, [r3, #0]
|
|
8005bb8: 4a0a ldr r2, [pc, #40] @ (8005be4 <Safety_TPS_Safety_Timer_Start+0x34>)
|
|
8005bba: 5a9b ldrh r3, [r3, r2]
|
|
8005bbc: b29b uxth r3, r3
|
|
8005bbe: 21fa movs r1, #250 @ 0xfa
|
|
8005bc0: 0089 lsls r1, r1, #2
|
|
8005bc2: 185a adds r2, r3, r1
|
|
8005bc4: 4b08 ldr r3, [pc, #32] @ (8005be8 <Safety_TPS_Safety_Timer_Start+0x38>)
|
|
8005bc6: 601a str r2, [r3, #0]
|
|
dbw_target_tmr2 = config->tps_error_time2 + 1000;
|
|
8005bc8: 4b05 ldr r3, [pc, #20] @ (8005be0 <Safety_TPS_Safety_Timer_Start+0x30>)
|
|
8005bca: 681b ldr r3, [r3, #0]
|
|
8005bcc: 4a07 ldr r2, [pc, #28] @ (8005bec <Safety_TPS_Safety_Timer_Start+0x3c>)
|
|
8005bce: 5a9b ldrh r3, [r3, r2]
|
|
8005bd0: b29b uxth r3, r3
|
|
8005bd2: 185a adds r2, r3, r1
|
|
8005bd4: 4b06 ldr r3, [pc, #24] @ (8005bf0 <Safety_TPS_Safety_Timer_Start+0x40>)
|
|
8005bd6: 601a str r2, [r3, #0]
|
|
}
|
|
8005bd8: 46c0 nop @ (mov r8, r8)
|
|
8005bda: 46bd mov sp, r7
|
|
8005bdc: bd80 pop {r7, pc}
|
|
8005bde: 46c0 nop @ (mov r8, r8)
|
|
8005be0: 200009cc .word 0x200009cc
|
|
8005be4: 0000034a .word 0x0000034a
|
|
8005be8: 20000b2c .word 0x20000b2c
|
|
8005bec: 0000034e .word 0x0000034e
|
|
8005bf0: 20000b30 .word 0x20000b30
|
|
|
|
08005bf4 <Check_TPS_Target>:
|
|
|
|
void Check_TPS_Target() {
|
|
8005bf4: b580 push {r7, lr}
|
|
8005bf6: af00 add r7, sp, #0
|
|
if (var.tps_error > 0) {
|
|
8005bf8: 4b50 ldr r3, [pc, #320] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005bfa: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005bfc: b21b sxth r3, r3
|
|
8005bfe: 2b00 cmp r3, #0
|
|
8005c00: dd4a ble.n 8005c98 <Check_TPS_Target+0xa4>
|
|
//check if tps is within specified target
|
|
if (var.tps_error < config->tps_error_margin1)
|
|
8005c02: 4b4e ldr r3, [pc, #312] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c04: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005c06: b21a sxth r2, r3
|
|
8005c08: 4b4d ldr r3, [pc, #308] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005c0a: 6819 ldr r1, [r3, #0]
|
|
8005c0c: 23d2 movs r3, #210 @ 0xd2
|
|
8005c0e: 009b lsls r3, r3, #2
|
|
8005c10: 5acb ldrh r3, [r1, r3]
|
|
8005c12: b21b sxth r3, r3
|
|
8005c14: 429a cmp r2, r3
|
|
8005c16: da08 bge.n 8005c2a <Check_TPS_Target+0x36>
|
|
dbw_target_tmr1 = config->tps_error_time1;
|
|
8005c18: 4b49 ldr r3, [pc, #292] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005c1a: 681b ldr r3, [r3, #0]
|
|
8005c1c: 4a49 ldr r2, [pc, #292] @ (8005d44 <Check_TPS_Target+0x150>)
|
|
8005c1e: 5a9b ldrh r3, [r3, r2]
|
|
8005c20: b29b uxth r3, r3
|
|
8005c22: 001a movs r2, r3
|
|
8005c24: 4b48 ldr r3, [pc, #288] @ (8005d48 <Check_TPS_Target+0x154>)
|
|
8005c26: 601a str r2, [r3, #0]
|
|
8005c28: e010 b.n 8005c4c <Check_TPS_Target+0x58>
|
|
else {
|
|
// if not in range in specified time
|
|
if (dbw_target_tmr1 == 0) {
|
|
8005c2a: 4b47 ldr r3, [pc, #284] @ (8005d48 <Check_TPS_Target+0x154>)
|
|
8005c2c: 681b ldr r3, [r3, #0]
|
|
8005c2e: 2b00 cmp r3, #0
|
|
8005c30: d10c bne.n 8005c4c <Check_TPS_Target+0x58>
|
|
//fault
|
|
var.status0 |= DBW_STATUS0_FAULT_F;
|
|
8005c32: 4b42 ldr r3, [pc, #264] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c34: 889b ldrh r3, [r3, #4]
|
|
8005c36: b29b uxth r3, r3
|
|
8005c38: 2208 movs r2, #8
|
|
8005c3a: 4313 orrs r3, r2
|
|
8005c3c: b29a uxth r2, r3
|
|
8005c3e: 4b3f ldr r3, [pc, #252] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c40: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005c42: f7fe f9fd bl 8004040 <DBW_Stop>
|
|
var.status2 = STATUS3_TARGET1_FAULT;
|
|
8005c46: 4b3d ldr r3, [pc, #244] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c48: 220b movs r2, #11
|
|
8005c4a: 811a strh r2, [r3, #8]
|
|
}
|
|
}
|
|
|
|
if (var.tps_error < config->tps_error_margin2)
|
|
8005c4c: 4b3b ldr r3, [pc, #236] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c4e: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005c50: b21a sxth r2, r3
|
|
8005c52: 4b3b ldr r3, [pc, #236] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005c54: 6819 ldr r1, [r3, #0]
|
|
8005c56: 23d3 movs r3, #211 @ 0xd3
|
|
8005c58: 009b lsls r3, r3, #2
|
|
8005c5a: 5acb ldrh r3, [r1, r3]
|
|
8005c5c: b21b sxth r3, r3
|
|
8005c5e: 429a cmp r2, r3
|
|
8005c60: da08 bge.n 8005c74 <Check_TPS_Target+0x80>
|
|
dbw_target_tmr2 = config->tps_error_time2;
|
|
8005c62: 4b37 ldr r3, [pc, #220] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005c64: 681b ldr r3, [r3, #0]
|
|
8005c66: 4a39 ldr r2, [pc, #228] @ (8005d4c <Check_TPS_Target+0x158>)
|
|
8005c68: 5a9b ldrh r3, [r3, r2]
|
|
8005c6a: b29b uxth r3, r3
|
|
8005c6c: 001a movs r2, r3
|
|
8005c6e: 4b38 ldr r3, [pc, #224] @ (8005d50 <Check_TPS_Target+0x15c>)
|
|
8005c70: 601a str r2, [r3, #0]
|
|
var.status2 = STATUS3_TARGET2_FAULT;
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
8005c72: e05f b.n 8005d34 <Check_TPS_Target+0x140>
|
|
if (dbw_target_tmr2 == 0) {
|
|
8005c74: 4b36 ldr r3, [pc, #216] @ (8005d50 <Check_TPS_Target+0x15c>)
|
|
8005c76: 681b ldr r3, [r3, #0]
|
|
8005c78: 2b00 cmp r3, #0
|
|
8005c7a: d15b bne.n 8005d34 <Check_TPS_Target+0x140>
|
|
var.status0 |= DBW_STATUS0_FAULT_F;
|
|
8005c7c: 4b2f ldr r3, [pc, #188] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c7e: 889b ldrh r3, [r3, #4]
|
|
8005c80: b29b uxth r3, r3
|
|
8005c82: 2208 movs r2, #8
|
|
8005c84: 4313 orrs r3, r2
|
|
8005c86: b29a uxth r2, r3
|
|
8005c88: 4b2c ldr r3, [pc, #176] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c8a: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005c8c: f7fe f9d8 bl 8004040 <DBW_Stop>
|
|
var.status2 = STATUS3_TARGET2_FAULT;
|
|
8005c90: 4b2a ldr r3, [pc, #168] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c92: 220c movs r2, #12
|
|
8005c94: 811a strh r2, [r3, #8]
|
|
}
|
|
8005c96: e04d b.n 8005d34 <Check_TPS_Target+0x140>
|
|
if (var.tps_error > (-config->tps_error_margin1))
|
|
8005c98: 4b28 ldr r3, [pc, #160] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005c9a: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005c9c: b21b sxth r3, r3
|
|
8005c9e: 0019 movs r1, r3
|
|
8005ca0: 4b27 ldr r3, [pc, #156] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005ca2: 681a ldr r2, [r3, #0]
|
|
8005ca4: 23d2 movs r3, #210 @ 0xd2
|
|
8005ca6: 009b lsls r3, r3, #2
|
|
8005ca8: 5ad3 ldrh r3, [r2, r3]
|
|
8005caa: b21b sxth r3, r3
|
|
8005cac: 425b negs r3, r3
|
|
8005cae: 4299 cmp r1, r3
|
|
8005cb0: dd08 ble.n 8005cc4 <Check_TPS_Target+0xd0>
|
|
dbw_target_tmr1 = config->tps_error_time1;
|
|
8005cb2: 4b23 ldr r3, [pc, #140] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005cb4: 681b ldr r3, [r3, #0]
|
|
8005cb6: 4a23 ldr r2, [pc, #140] @ (8005d44 <Check_TPS_Target+0x150>)
|
|
8005cb8: 5a9b ldrh r3, [r3, r2]
|
|
8005cba: b29b uxth r3, r3
|
|
8005cbc: 001a movs r2, r3
|
|
8005cbe: 4b22 ldr r3, [pc, #136] @ (8005d48 <Check_TPS_Target+0x154>)
|
|
8005cc0: 601a str r2, [r3, #0]
|
|
8005cc2: e010 b.n 8005ce6 <Check_TPS_Target+0xf2>
|
|
if (dbw_target_tmr1 == 0) {
|
|
8005cc4: 4b20 ldr r3, [pc, #128] @ (8005d48 <Check_TPS_Target+0x154>)
|
|
8005cc6: 681b ldr r3, [r3, #0]
|
|
8005cc8: 2b00 cmp r3, #0
|
|
8005cca: d10c bne.n 8005ce6 <Check_TPS_Target+0xf2>
|
|
var.status0 |= DBW_STATUS0_FAULT_F;
|
|
8005ccc: 4b1b ldr r3, [pc, #108] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005cce: 889b ldrh r3, [r3, #4]
|
|
8005cd0: b29b uxth r3, r3
|
|
8005cd2: 2208 movs r2, #8
|
|
8005cd4: 4313 orrs r3, r2
|
|
8005cd6: b29a uxth r2, r3
|
|
8005cd8: 4b18 ldr r3, [pc, #96] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005cda: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005cdc: f7fe f9b0 bl 8004040 <DBW_Stop>
|
|
var.status2 = STATUS3_TARGET1_FAULT;
|
|
8005ce0: 4b16 ldr r3, [pc, #88] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005ce2: 220b movs r2, #11
|
|
8005ce4: 811a strh r2, [r3, #8]
|
|
if (var.tps_error > (-config->tps_error_margin2))
|
|
8005ce6: 4b15 ldr r3, [pc, #84] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005ce8: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005cea: b21b sxth r3, r3
|
|
8005cec: 0019 movs r1, r3
|
|
8005cee: 4b14 ldr r3, [pc, #80] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005cf0: 681a ldr r2, [r3, #0]
|
|
8005cf2: 23d3 movs r3, #211 @ 0xd3
|
|
8005cf4: 009b lsls r3, r3, #2
|
|
8005cf6: 5ad3 ldrh r3, [r2, r3]
|
|
8005cf8: b21b sxth r3, r3
|
|
8005cfa: 425b negs r3, r3
|
|
8005cfc: 4299 cmp r1, r3
|
|
8005cfe: dd08 ble.n 8005d12 <Check_TPS_Target+0x11e>
|
|
dbw_target_tmr2 = config->tps_error_time2;
|
|
8005d00: 4b0f ldr r3, [pc, #60] @ (8005d40 <Check_TPS_Target+0x14c>)
|
|
8005d02: 681b ldr r3, [r3, #0]
|
|
8005d04: 4a11 ldr r2, [pc, #68] @ (8005d4c <Check_TPS_Target+0x158>)
|
|
8005d06: 5a9b ldrh r3, [r3, r2]
|
|
8005d08: b29b uxth r3, r3
|
|
8005d0a: 001a movs r2, r3
|
|
8005d0c: 4b10 ldr r3, [pc, #64] @ (8005d50 <Check_TPS_Target+0x15c>)
|
|
8005d0e: 601a str r2, [r3, #0]
|
|
}
|
|
8005d10: e010 b.n 8005d34 <Check_TPS_Target+0x140>
|
|
if (dbw_target_tmr2 == 0) {
|
|
8005d12: 4b0f ldr r3, [pc, #60] @ (8005d50 <Check_TPS_Target+0x15c>)
|
|
8005d14: 681b ldr r3, [r3, #0]
|
|
8005d16: 2b00 cmp r3, #0
|
|
8005d18: d10c bne.n 8005d34 <Check_TPS_Target+0x140>
|
|
var.status0 |= DBW_STATUS0_FAULT_F;
|
|
8005d1a: 4b08 ldr r3, [pc, #32] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005d1c: 889b ldrh r3, [r3, #4]
|
|
8005d1e: b29b uxth r3, r3
|
|
8005d20: 2208 movs r2, #8
|
|
8005d22: 4313 orrs r3, r2
|
|
8005d24: b29a uxth r2, r3
|
|
8005d26: 4b05 ldr r3, [pc, #20] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005d28: 809a strh r2, [r3, #4]
|
|
DBW_Stop();
|
|
8005d2a: f7fe f989 bl 8004040 <DBW_Stop>
|
|
var.status2 = STATUS3_TARGET2_FAULT;
|
|
8005d2e: 4b03 ldr r3, [pc, #12] @ (8005d3c <Check_TPS_Target+0x148>)
|
|
8005d30: 220c movs r2, #12
|
|
8005d32: 811a strh r2, [r3, #8]
|
|
}
|
|
8005d34: 46c0 nop @ (mov r8, r8)
|
|
8005d36: 46bd mov sp, r7
|
|
8005d38: bd80 pop {r7, pc}
|
|
8005d3a: 46c0 nop @ (mov r8, r8)
|
|
8005d3c: 20000998 .word 0x20000998
|
|
8005d40: 200009cc .word 0x200009cc
|
|
8005d44: 0000034a .word 0x0000034a
|
|
8005d48: 20000b2c .word 0x20000b2c
|
|
8005d4c: 0000034e .word 0x0000034e
|
|
8005d50: 20000b30 .word 0x20000b30
|
|
|
|
08005d54 <HAL_MspInit>:
|
|
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void) {
|
|
8005d54: b580 push {r7, lr}
|
|
8005d56: b082 sub sp, #8
|
|
8005d58: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8005d5a: 4b0f ldr r3, [pc, #60] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d5c: 699a ldr r2, [r3, #24]
|
|
8005d5e: 4b0e ldr r3, [pc, #56] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d60: 2101 movs r1, #1
|
|
8005d62: 430a orrs r2, r1
|
|
8005d64: 619a str r2, [r3, #24]
|
|
8005d66: 4b0c ldr r3, [pc, #48] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d68: 699b ldr r3, [r3, #24]
|
|
8005d6a: 2201 movs r2, #1
|
|
8005d6c: 4013 ands r3, r2
|
|
8005d6e: 607b str r3, [r7, #4]
|
|
8005d70: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005d72: 4b09 ldr r3, [pc, #36] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d74: 69da ldr r2, [r3, #28]
|
|
8005d76: 4b08 ldr r3, [pc, #32] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d78: 2180 movs r1, #128 @ 0x80
|
|
8005d7a: 0549 lsls r1, r1, #21
|
|
8005d7c: 430a orrs r2, r1
|
|
8005d7e: 61da str r2, [r3, #28]
|
|
8005d80: 4b05 ldr r3, [pc, #20] @ (8005d98 <HAL_MspInit+0x44>)
|
|
8005d82: 69da ldr r2, [r3, #28]
|
|
8005d84: 2380 movs r3, #128 @ 0x80
|
|
8005d86: 055b lsls r3, r3, #21
|
|
8005d88: 4013 ands r3, r2
|
|
8005d8a: 603b str r3, [r7, #0]
|
|
8005d8c: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8005d8e: 46c0 nop @ (mov r8, r8)
|
|
8005d90: 46bd mov sp, r7
|
|
8005d92: b002 add sp, #8
|
|
8005d94: bd80 pop {r7, pc}
|
|
8005d96: 46c0 nop @ (mov r8, r8)
|
|
8005d98: 40021000 .word 0x40021000
|
|
|
|
08005d9c <HAL_ADC_MspInit>:
|
|
* @brief ADC MSP Initialization
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) {
|
|
8005d9c: b590 push {r4, r7, lr}
|
|
8005d9e: b08b sub sp, #44 @ 0x2c
|
|
8005da0: af00 add r7, sp, #0
|
|
8005da2: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
|
|
8005da4: 2414 movs r4, #20
|
|
8005da6: 193b adds r3, r7, r4
|
|
8005da8: 0018 movs r0, r3
|
|
8005daa: 2314 movs r3, #20
|
|
8005dac: 001a movs r2, r3
|
|
8005dae: 2100 movs r1, #0
|
|
8005db0: f002 fdae bl 8008910 <memset>
|
|
if (hadc->Instance == ADC1) {
|
|
8005db4: 687b ldr r3, [r7, #4]
|
|
8005db6: 681b ldr r3, [r3, #0]
|
|
8005db8: 4a19 ldr r2, [pc, #100] @ (8005e20 <HAL_ADC_MspInit+0x84>)
|
|
8005dba: 4293 cmp r3, r2
|
|
8005dbc: d12b bne.n 8005e16 <HAL_ADC_MspInit+0x7a>
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_ADC1_CLK_ENABLE();
|
|
8005dbe: 4b19 ldr r3, [pc, #100] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005dc0: 699a ldr r2, [r3, #24]
|
|
8005dc2: 4b18 ldr r3, [pc, #96] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005dc4: 2180 movs r1, #128 @ 0x80
|
|
8005dc6: 0089 lsls r1, r1, #2
|
|
8005dc8: 430a orrs r2, r1
|
|
8005dca: 619a str r2, [r3, #24]
|
|
8005dcc: 4b15 ldr r3, [pc, #84] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005dce: 699a ldr r2, [r3, #24]
|
|
8005dd0: 2380 movs r3, #128 @ 0x80
|
|
8005dd2: 009b lsls r3, r3, #2
|
|
8005dd4: 4013 ands r3, r2
|
|
8005dd6: 613b str r3, [r7, #16]
|
|
8005dd8: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8005dda: 4b12 ldr r3, [pc, #72] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005ddc: 695a ldr r2, [r3, #20]
|
|
8005dde: 4b11 ldr r3, [pc, #68] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005de0: 2180 movs r1, #128 @ 0x80
|
|
8005de2: 0289 lsls r1, r1, #10
|
|
8005de4: 430a orrs r2, r1
|
|
8005de6: 615a str r2, [r3, #20]
|
|
8005de8: 4b0e ldr r3, [pc, #56] @ (8005e24 <HAL_ADC_MspInit+0x88>)
|
|
8005dea: 695a ldr r2, [r3, #20]
|
|
8005dec: 2380 movs r3, #128 @ 0x80
|
|
8005dee: 029b lsls r3, r3, #10
|
|
8005df0: 4013 ands r3, r2
|
|
8005df2: 60fb str r3, [r7, #12]
|
|
8005df4: 68fb ldr r3, [r7, #12]
|
|
PA2 ------> ADC_IN2
|
|
PA3 ------> ADC_IN3
|
|
PA4 ------> ADC_IN4
|
|
PA5 ------> ADC_IN5
|
|
*/
|
|
GPIO_InitStruct.Pin = PPS1_Pin | PPS2_Pin | TPS1_Pin | TPS2_Pin
|
|
8005df6: 193b adds r3, r7, r4
|
|
8005df8: 223f movs r2, #63 @ 0x3f
|
|
8005dfa: 601a str r2, [r3, #0]
|
|
| TTL_FB_Pin | VBAT_SENSE_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8005dfc: 193b adds r3, r7, r4
|
|
8005dfe: 2203 movs r2, #3
|
|
8005e00: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8005e02: 193b adds r3, r7, r4
|
|
8005e04: 2200 movs r2, #0
|
|
8005e06: 609a str r2, [r3, #8]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8005e08: 193a adds r2, r7, r4
|
|
8005e0a: 2390 movs r3, #144 @ 0x90
|
|
8005e0c: 05db lsls r3, r3, #23
|
|
8005e0e: 0011 movs r1, r2
|
|
8005e10: 0018 movs r0, r3
|
|
8005e12: f001 fa79 bl 8007308 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN ADC1_MspInit 1 */
|
|
|
|
/* USER CODE END ADC1_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8005e16: 46c0 nop @ (mov r8, r8)
|
|
8005e18: 46bd mov sp, r7
|
|
8005e1a: b00b add sp, #44 @ 0x2c
|
|
8005e1c: bd90 pop {r4, r7, pc}
|
|
8005e1e: 46c0 nop @ (mov r8, r8)
|
|
8005e20: 40012400 .word 0x40012400
|
|
8005e24: 40021000 .word 0x40021000
|
|
|
|
08005e28 <HAL_UART_MspInit>:
|
|
* @brief UART MSP Initialization
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef *huart) {
|
|
8005e28: b590 push {r4, r7, lr}
|
|
8005e2a: b08b sub sp, #44 @ 0x2c
|
|
8005e2c: af00 add r7, sp, #0
|
|
8005e2e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
|
|
8005e30: 2414 movs r4, #20
|
|
8005e32: 193b adds r3, r7, r4
|
|
8005e34: 0018 movs r0, r3
|
|
8005e36: 2314 movs r3, #20
|
|
8005e38: 001a movs r2, r3
|
|
8005e3a: 2100 movs r1, #0
|
|
8005e3c: f002 fd68 bl 8008910 <memset>
|
|
if (huart->Instance == USART1) {
|
|
8005e40: 687b ldr r3, [r7, #4]
|
|
8005e42: 681b ldr r3, [r3, #0]
|
|
8005e44: 4a1d ldr r2, [pc, #116] @ (8005ebc <HAL_UART_MspInit+0x94>)
|
|
8005e46: 4293 cmp r3, r2
|
|
8005e48: d133 bne.n 8005eb2 <HAL_UART_MspInit+0x8a>
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8005e4a: 4b1d ldr r3, [pc, #116] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e4c: 699a ldr r2, [r3, #24]
|
|
8005e4e: 4b1c ldr r3, [pc, #112] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e50: 2180 movs r1, #128 @ 0x80
|
|
8005e52: 01c9 lsls r1, r1, #7
|
|
8005e54: 430a orrs r2, r1
|
|
8005e56: 619a str r2, [r3, #24]
|
|
8005e58: 4b19 ldr r3, [pc, #100] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e5a: 699a ldr r2, [r3, #24]
|
|
8005e5c: 2380 movs r3, #128 @ 0x80
|
|
8005e5e: 01db lsls r3, r3, #7
|
|
8005e60: 4013 ands r3, r2
|
|
8005e62: 613b str r3, [r7, #16]
|
|
8005e64: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8005e66: 4b16 ldr r3, [pc, #88] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e68: 695a ldr r2, [r3, #20]
|
|
8005e6a: 4b15 ldr r3, [pc, #84] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e6c: 2180 movs r1, #128 @ 0x80
|
|
8005e6e: 0289 lsls r1, r1, #10
|
|
8005e70: 430a orrs r2, r1
|
|
8005e72: 615a str r2, [r3, #20]
|
|
8005e74: 4b12 ldr r3, [pc, #72] @ (8005ec0 <HAL_UART_MspInit+0x98>)
|
|
8005e76: 695a ldr r2, [r3, #20]
|
|
8005e78: 2380 movs r3, #128 @ 0x80
|
|
8005e7a: 029b lsls r3, r3, #10
|
|
8005e7c: 4013 ands r3, r2
|
|
8005e7e: 60fb str r3, [r7, #12]
|
|
8005e80: 68fb ldr r3, [r7, #12]
|
|
/**USART1 GPIO Configuration
|
|
PA9 ------> USART1_TX
|
|
PA10 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
|
|
8005e82: 193b adds r3, r7, r4
|
|
8005e84: 22c0 movs r2, #192 @ 0xc0
|
|
8005e86: 00d2 lsls r2, r2, #3
|
|
8005e88: 601a str r2, [r3, #0]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8005e8a: 0021 movs r1, r4
|
|
8005e8c: 187b adds r3, r7, r1
|
|
8005e8e: 2202 movs r2, #2
|
|
8005e90: 605a str r2, [r3, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8005e92: 187b adds r3, r7, r1
|
|
8005e94: 2200 movs r2, #0
|
|
8005e96: 609a str r2, [r3, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
8005e98: 187b adds r3, r7, r1
|
|
8005e9a: 2203 movs r2, #3
|
|
8005e9c: 60da str r2, [r3, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_USART1;
|
|
8005e9e: 187b adds r3, r7, r1
|
|
8005ea0: 2201 movs r2, #1
|
|
8005ea2: 611a str r2, [r3, #16]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8005ea4: 187a adds r2, r7, r1
|
|
8005ea6: 2390 movs r3, #144 @ 0x90
|
|
8005ea8: 05db lsls r3, r3, #23
|
|
8005eaa: 0011 movs r1, r2
|
|
8005eac: 0018 movs r0, r3
|
|
8005eae: f001 fa2b bl 8007308 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART1_MspInit 1 */
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8005eb2: 46c0 nop @ (mov r8, r8)
|
|
8005eb4: 46bd mov sp, r7
|
|
8005eb6: b00b add sp, #44 @ 0x2c
|
|
8005eb8: bd90 pop {r4, r7, pc}
|
|
8005eba: 46c0 nop @ (mov r8, r8)
|
|
8005ebc: 40013800 .word 0x40013800
|
|
8005ec0: 40021000 .word 0x40021000
|
|
|
|
08005ec4 <NMI_Handler>:
|
|
/* Cortex-M0 Processor Interruption and Exception Handlers */
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void) {
|
|
8005ec4: b580 push {r7, lr}
|
|
8005ec6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 1 */
|
|
}
|
|
8005ec8: 46c0 nop @ (mov r8, r8)
|
|
8005eca: 46bd mov sp, r7
|
|
8005ecc: bd80 pop {r7, pc}
|
|
|
|
08005ece <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void) {
|
|
8005ece: b580 push {r7, lr}
|
|
8005ed0: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1) {
|
|
8005ed2: 46c0 nop @ (mov r8, r8)
|
|
8005ed4: e7fd b.n 8005ed2 <HardFault_Handler+0x4>
|
|
|
|
08005ed6 <SVC_Handler>:
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void) {
|
|
8005ed6: b580 push {r7, lr}
|
|
8005ed8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVC_IRQn 0 */
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
|
|
|
/* USER CODE END SVC_IRQn 1 */
|
|
}
|
|
8005eda: 46c0 nop @ (mov r8, r8)
|
|
8005edc: 46bd mov sp, r7
|
|
8005ede: bd80 pop {r7, pc}
|
|
|
|
08005ee0 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void) {
|
|
8005ee0: b580 push {r7, lr}
|
|
8005ee2: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8005ee4: 46c0 nop @ (mov r8, r8)
|
|
8005ee6: 46bd mov sp, r7
|
|
8005ee8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005eec <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void) {
|
|
8005eec: b580 push {r7, lr}
|
|
8005eee: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8005ef0: f000 fcea bl 80068c8 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
var.clock++;
|
|
8005ef4: 4b16 ldr r3, [pc, #88] @ (8005f50 <SysTick_Handler+0x64>)
|
|
8005ef6: 681b ldr r3, [r3, #0]
|
|
8005ef8: 1c5a adds r2, r3, #1
|
|
8005efa: 4b15 ldr r3, [pc, #84] @ (8005f50 <SysTick_Handler+0x64>)
|
|
8005efc: 601a str r2, [r3, #0]
|
|
TS_Comms_RX_Timeout();
|
|
8005efe: f000 fc53 bl 80067a8 <TS_Comms_RX_Timeout>
|
|
|
|
if (dbw_fast_process_timer)
|
|
8005f02: 4b14 ldr r3, [pc, #80] @ (8005f54 <SysTick_Handler+0x68>)
|
|
8005f04: 881b ldrh r3, [r3, #0]
|
|
8005f06: b29b uxth r3, r3
|
|
8005f08: 2b00 cmp r3, #0
|
|
8005f0a: d006 beq.n 8005f1a <SysTick_Handler+0x2e>
|
|
dbw_fast_process_timer--;
|
|
8005f0c: 4b11 ldr r3, [pc, #68] @ (8005f54 <SysTick_Handler+0x68>)
|
|
8005f0e: 881b ldrh r3, [r3, #0]
|
|
8005f10: b29b uxth r3, r3
|
|
8005f12: 3b01 subs r3, #1
|
|
8005f14: b29a uxth r2, r3
|
|
8005f16: 4b0f ldr r3, [pc, #60] @ (8005f54 <SysTick_Handler+0x68>)
|
|
8005f18: 801a strh r2, [r3, #0]
|
|
|
|
//Can_Timeouts();
|
|
|
|
if ((ac_mode != 0) && (config->config_bits & CONFIG_TESTMODE_F)) {
|
|
8005f1a: 4b0f ldr r3, [pc, #60] @ (8005f58 <SysTick_Handler+0x6c>)
|
|
8005f1c: 681b ldr r3, [r3, #0]
|
|
8005f1e: 2b00 cmp r3, #0
|
|
8005f20: d011 beq.n 8005f46 <SysTick_Handler+0x5a>
|
|
8005f22: 4b0e ldr r3, [pc, #56] @ (8005f5c <SysTick_Handler+0x70>)
|
|
8005f24: 681b ldr r3, [r3, #0]
|
|
8005f26: 4a0e ldr r2, [pc, #56] @ (8005f60 <SysTick_Handler+0x74>)
|
|
8005f28: 5a9b ldrh r3, [r3, r2]
|
|
8005f2a: b29b uxth r3, r3
|
|
8005f2c: 001a movs r2, r3
|
|
8005f2e: 2304 movs r3, #4
|
|
8005f30: 4013 ands r3, r2
|
|
8005f32: d008 beq.n 8005f46 <SysTick_Handler+0x5a>
|
|
if (ac_timer)
|
|
8005f34: 4b0b ldr r3, [pc, #44] @ (8005f64 <SysTick_Handler+0x78>)
|
|
8005f36: 681b ldr r3, [r3, #0]
|
|
8005f38: 2b00 cmp r3, #0
|
|
8005f3a: d004 beq.n 8005f46 <SysTick_Handler+0x5a>
|
|
ac_timer--;
|
|
8005f3c: 4b09 ldr r3, [pc, #36] @ (8005f64 <SysTick_Handler+0x78>)
|
|
8005f3e: 681b ldr r3, [r3, #0]
|
|
8005f40: 1e5a subs r2, r3, #1
|
|
8005f42: 4b08 ldr r3, [pc, #32] @ (8005f64 <SysTick_Handler+0x78>)
|
|
8005f44: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
Safety_TPS_Safety_Timer();
|
|
8005f46: f7ff fe17 bl 8005b78 <Safety_TPS_Safety_Timer>
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8005f4a: 46c0 nop @ (mov r8, r8)
|
|
8005f4c: 46bd mov sp, r7
|
|
8005f4e: bd80 pop {r7, pc}
|
|
8005f50: 20000998 .word 0x20000998
|
|
8005f54: 20000a1c .word 0x20000a1c
|
|
8005f58: 200009d0 .word 0x200009d0
|
|
8005f5c: 200009cc .word 0x200009cc
|
|
8005f60: 0000033a .word 0x0000033a
|
|
8005f64: 20000000 .word 0x20000000
|
|
|
|
08005f68 <SystemInit>:
|
|
/**
|
|
* @brief Setup the microcontroller system
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void) {
|
|
8005f68: b580 push {r7, lr}
|
|
8005f6a: af00 add r7, sp, #0
|
|
before branch to main program. This call is made inside
|
|
the "startup_stm32f0xx.s" file.
|
|
User can setups the default system clock (System clock source, PLL Multiplier
|
|
and Divider factors, AHB/APBx prescalers and Flash settings).
|
|
*/
|
|
}
|
|
8005f6c: 46c0 nop @ (mov r8, r8)
|
|
8005f6e: 46bd mov sp, r7
|
|
8005f70: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005f74 <Comms_Init>:
|
|
const char Signature[20] = { "speeduino DBW 2.0.0" };
|
|
const char Revision[20] = { "speeduino DBW 2.0.0" };
|
|
|
|
volatile var_t tx_bufer;
|
|
|
|
void Comms_Init(void) {
|
|
8005f74: b580 push {r7, lr}
|
|
8005f76: af00 add r7, sp, #0
|
|
Comms_Reset(&TX);
|
|
8005f78: 4b0b ldr r3, [pc, #44] @ (8005fa8 <Comms_Init+0x34>)
|
|
8005f7a: 0018 movs r0, r3
|
|
8005f7c: f000 f86a bl 8006054 <Comms_Reset>
|
|
Comms_Reset(&RX);
|
|
8005f80: 4b0a ldr r3, [pc, #40] @ (8005fac <Comms_Init+0x38>)
|
|
8005f82: 0018 movs r0, r3
|
|
8005f84: f000 f866 bl 8006054 <Comms_Reset>
|
|
|
|
USART1->ISR &= ~USART_ISR_RXNE;
|
|
8005f88: 4b09 ldr r3, [pc, #36] @ (8005fb0 <Comms_Init+0x3c>)
|
|
8005f8a: 69da ldr r2, [r3, #28]
|
|
8005f8c: 4b08 ldr r3, [pc, #32] @ (8005fb0 <Comms_Init+0x3c>)
|
|
8005f8e: 2120 movs r1, #32
|
|
8005f90: 438a bics r2, r1
|
|
8005f92: 61da str r2, [r3, #28]
|
|
USART1->CR1 |= USART_CR1_RXNEIE;
|
|
8005f94: 4b06 ldr r3, [pc, #24] @ (8005fb0 <Comms_Init+0x3c>)
|
|
8005f96: 681a ldr r2, [r3, #0]
|
|
8005f98: 4b05 ldr r3, [pc, #20] @ (8005fb0 <Comms_Init+0x3c>)
|
|
8005f9a: 2120 movs r1, #32
|
|
8005f9c: 430a orrs r2, r1
|
|
8005f9e: 601a str r2, [r3, #0]
|
|
|
|
}
|
|
8005fa0: 46c0 nop @ (mov r8, r8)
|
|
8005fa2: 46bd mov sp, r7
|
|
8005fa4: bd80 pop {r7, pc}
|
|
8005fa6: 46c0 nop @ (mov r8, r8)
|
|
8005fa8: 20000c50 .word 0x20000c50
|
|
8005fac: 20000b34 .word 0x20000b34
|
|
8005fb0: 40013800 .word 0x40013800
|
|
|
|
08005fb4 <USART1_IRQHandler>:
|
|
|
|
void USART1_IRQHandler(void) {
|
|
8005fb4: b580 push {r7, lr}
|
|
8005fb6: b082 sub sp, #8
|
|
8005fb8: af00 add r7, sp, #0
|
|
uint8_t tmp;
|
|
if (USART1->ISR & USART_ISR_RXNE) {
|
|
8005fba: 4b23 ldr r3, [pc, #140] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fbc: 69db ldr r3, [r3, #28]
|
|
8005fbe: 2220 movs r2, #32
|
|
8005fc0: 4013 ands r3, r2
|
|
8005fc2: d01f beq.n 8006004 <USART1_IRQHandler+0x50>
|
|
tmp = USART1->RDR;
|
|
8005fc4: 4b20 ldr r3, [pc, #128] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fc6: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8005fc8: b29a uxth r2, r3
|
|
8005fca: 1dfb adds r3, r7, #7
|
|
8005fcc: 701a strb r2, [r3, #0]
|
|
USART1->ISR &= ~USART_ISR_RXNE;
|
|
8005fce: 4b1e ldr r3, [pc, #120] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fd0: 69da ldr r2, [r3, #28]
|
|
8005fd2: 4b1d ldr r3, [pc, #116] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fd4: 2120 movs r1, #32
|
|
8005fd6: 438a bics r2, r1
|
|
8005fd8: 61da str r2, [r3, #28]
|
|
//if there are any RX errors reset comms else process data
|
|
if (USART1->ISR & 0x000F) {
|
|
8005fda: 4b1b ldr r3, [pc, #108] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fdc: 69db ldr r3, [r3, #28]
|
|
8005fde: 220f movs r2, #15
|
|
8005fe0: 4013 ands r3, r2
|
|
8005fe2: d00a beq.n 8005ffa <USART1_IRQHandler+0x46>
|
|
Comms_Reset(&RX);
|
|
8005fe4: 4b19 ldr r3, [pc, #100] @ (800604c <USART1_IRQHandler+0x98>)
|
|
8005fe6: 0018 movs r0, r3
|
|
8005fe8: f000 f834 bl 8006054 <Comms_Reset>
|
|
USART1->ISR &= ~0x000F;
|
|
8005fec: 4b16 ldr r3, [pc, #88] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005fee: 69da ldr r2, [r3, #28]
|
|
8005ff0: 4b15 ldr r3, [pc, #84] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8005ff2: 210f movs r1, #15
|
|
8005ff4: 438a bics r2, r1
|
|
8005ff6: 61da str r2, [r3, #28]
|
|
8005ff8: e004 b.n 8006004 <USART1_IRQHandler+0x50>
|
|
} else {
|
|
Rx_Char(tmp);
|
|
8005ffa: 1dfb adds r3, r7, #7
|
|
8005ffc: 781b ldrb r3, [r3, #0]
|
|
8005ffe: 0018 movs r0, r3
|
|
8006000: f000 f846 bl 8006090 <Rx_Char>
|
|
}
|
|
}
|
|
//transmit interrupt
|
|
if (USART1->ISR & USART_ISR_TC) {
|
|
8006004: 4b10 ldr r3, [pc, #64] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8006006: 69db ldr r3, [r3, #28]
|
|
8006008: 2240 movs r2, #64 @ 0x40
|
|
800600a: 4013 ands r3, r2
|
|
800600c: d018 beq.n 8006040 <USART1_IRQHandler+0x8c>
|
|
if (TX.bytes_done < TX.cnt) {
|
|
800600e: 4b10 ldr r3, [pc, #64] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
8006010: 895a ldrh r2, [r3, #10]
|
|
8006012: 4b0f ldr r3, [pc, #60] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
8006014: 891b ldrh r3, [r3, #8]
|
|
8006016: 429a cmp r2, r3
|
|
8006018: d210 bcs.n 800603c <USART1_IRQHandler+0x88>
|
|
USART1->TDR = *TX.address;
|
|
800601a: 4b0d ldr r3, [pc, #52] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
800601c: 68db ldr r3, [r3, #12]
|
|
800601e: 781a ldrb r2, [r3, #0]
|
|
8006020: 4b09 ldr r3, [pc, #36] @ (8006048 <USART1_IRQHandler+0x94>)
|
|
8006022: 851a strh r2, [r3, #40] @ 0x28
|
|
TX.address++;
|
|
8006024: 4b0a ldr r3, [pc, #40] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
8006026: 68db ldr r3, [r3, #12]
|
|
8006028: 1c5a adds r2, r3, #1
|
|
800602a: 4b09 ldr r3, [pc, #36] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
800602c: 60da str r2, [r3, #12]
|
|
TX.bytes_done++;
|
|
800602e: 4b08 ldr r3, [pc, #32] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
8006030: 895b ldrh r3, [r3, #10]
|
|
8006032: 3301 adds r3, #1
|
|
8006034: b29a uxth r2, r3
|
|
8006036: 4b06 ldr r3, [pc, #24] @ (8006050 <USART1_IRQHandler+0x9c>)
|
|
8006038: 815a strh r2, [r3, #10]
|
|
} else
|
|
TX_Done();
|
|
|
|
}
|
|
}
|
|
800603a: e001 b.n 8006040 <USART1_IRQHandler+0x8c>
|
|
TX_Done();
|
|
800603c: f000 fa66 bl 800650c <TX_Done>
|
|
}
|
|
8006040: 46c0 nop @ (mov r8, r8)
|
|
8006042: 46bd mov sp, r7
|
|
8006044: b002 add sp, #8
|
|
8006046: bd80 pop {r7, pc}
|
|
8006048: 40013800 .word 0x40013800
|
|
800604c: 20000b34 .word 0x20000b34
|
|
8006050: 20000c50 .word 0x20000c50
|
|
|
|
08006054 <Comms_Reset>:
|
|
|
|
void Comms_Reset(comms_status *CS) {
|
|
8006054: b580 push {r7, lr}
|
|
8006056: b082 sub sp, #8
|
|
8006058: af00 add r7, sp, #0
|
|
800605a: 6078 str r0, [r7, #4]
|
|
|
|
CS->mode = IDLE; //Mode Idle
|
|
800605c: 687b ldr r3, [r7, #4]
|
|
800605e: 2200 movs r2, #0
|
|
8006060: 701a strb r2, [r3, #0]
|
|
CS->cnt = 0; //Nothing to receive
|
|
8006062: 687b ldr r3, [r7, #4]
|
|
8006064: 2200 movs r2, #0
|
|
8006066: 811a strh r2, [r3, #8]
|
|
CS->bytes_done = 0; //Nothing received
|
|
8006068: 687b ldr r3, [r7, #4]
|
|
800606a: 2200 movs r2, #0
|
|
800606c: 815a strh r2, [r3, #10]
|
|
CS->crc32 = 0; //Reset crc32
|
|
800606e: 687b ldr r3, [r7, #4]
|
|
8006070: 2200 movs r2, #0
|
|
8006072: 619a str r2, [r3, #24]
|
|
CS->pause_flag = 0;
|
|
8006074: 687b ldr r3, [r7, #4]
|
|
8006076: 2200 movs r2, #0
|
|
8006078: 759a strb r2, [r3, #22]
|
|
CS->address = &CS->cmd; //Point incoming characters to cmd_bufer
|
|
800607a: 687b ldr r3, [r7, #4]
|
|
800607c: 1c5a adds r2, r3, #1
|
|
800607e: 687b ldr r3, [r7, #4]
|
|
8006080: 60da str r2, [r3, #12]
|
|
CS->timeout = 0;
|
|
8006082: 687b ldr r3, [r7, #4]
|
|
8006084: 2200 movs r2, #0
|
|
8006086: 829a strh r2, [r3, #20]
|
|
}
|
|
8006088: 46c0 nop @ (mov r8, r8)
|
|
800608a: 46bd mov sp, r7
|
|
800608c: b002 add sp, #8
|
|
800608e: bd80 pop {r7, pc}
|
|
|
|
08006090 <Rx_Char>:
|
|
|
|
void Rx_Char(unsigned char data) {
|
|
8006090: b580 push {r7, lr}
|
|
8006092: b082 sub sp, #8
|
|
8006094: af00 add r7, sp, #0
|
|
8006096: 0002 movs r2, r0
|
|
8006098: 1dfb adds r3, r7, #7
|
|
800609a: 701a strb r2, [r3, #0]
|
|
|
|
RX.bytes_done++;
|
|
800609c: 4bc5 ldr r3, [pc, #788] @ (80063b4 <Rx_Char+0x324>)
|
|
800609e: 895b ldrh r3, [r3, #10]
|
|
80060a0: 3301 adds r3, #1
|
|
80060a2: b29a uxth r2, r3
|
|
80060a4: 4bc3 ldr r3, [pc, #780] @ (80063b4 <Rx_Char+0x324>)
|
|
80060a6: 815a strh r2, [r3, #10]
|
|
|
|
if (RX.bytes_done == 1) {
|
|
80060a8: 4bc2 ldr r3, [pc, #776] @ (80063b4 <Rx_Char+0x324>)
|
|
80060aa: 895b ldrh r3, [r3, #10]
|
|
80060ac: 2b01 cmp r3, #1
|
|
80060ae: d159 bne.n 8006164 <Rx_Char+0xd4>
|
|
if (data == 'A') {
|
|
80060b0: 1dfb adds r3, r7, #7
|
|
80060b2: 781b ldrb r3, [r3, #0]
|
|
80060b4: 2b41 cmp r3, #65 @ 0x41
|
|
80060b6: d10b bne.n 80060d0 <Rx_Char+0x40>
|
|
SCI_flags |= SCI_FLAGS_TX_VARIABLES;
|
|
80060b8: 4bbf ldr r3, [pc, #764] @ (80063b8 <Rx_Char+0x328>)
|
|
80060ba: 781b ldrb r3, [r3, #0]
|
|
80060bc: 2202 movs r2, #2
|
|
80060be: 4313 orrs r3, r2
|
|
80060c0: b2da uxtb r2, r3
|
|
80060c2: 4bbd ldr r3, [pc, #756] @ (80063b8 <Rx_Char+0x328>)
|
|
80060c4: 701a strb r2, [r3, #0]
|
|
Comms_Reset(&RX);
|
|
80060c6: 4bbb ldr r3, [pc, #748] @ (80063b4 <Rx_Char+0x324>)
|
|
80060c8: 0018 movs r0, r3
|
|
80060ca: f7ff ffc3 bl 8006054 <Comms_Reset>
|
|
80060ce: e1a6 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (data == 'Q') {
|
|
80060d0: 1dfb adds r3, r7, #7
|
|
80060d2: 781b ldrb r3, [r3, #0]
|
|
80060d4: 2b51 cmp r3, #81 @ 0x51
|
|
80060d6: d109 bne.n 80060ec <Rx_Char+0x5c>
|
|
TX_Schedule((unsigned char*) Revision, 20);
|
|
80060d8: 4bb8 ldr r3, [pc, #736] @ (80063bc <Rx_Char+0x32c>)
|
|
80060da: 2114 movs r1, #20
|
|
80060dc: 0018 movs r0, r3
|
|
80060de: f000 f9a3 bl 8006428 <TX_Schedule>
|
|
Comms_Reset(&RX);
|
|
80060e2: 4bb4 ldr r3, [pc, #720] @ (80063b4 <Rx_Char+0x324>)
|
|
80060e4: 0018 movs r0, r3
|
|
80060e6: f7ff ffb5 bl 8006054 <Comms_Reset>
|
|
80060ea: e198 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (data == 'S') {
|
|
80060ec: 1dfb adds r3, r7, #7
|
|
80060ee: 781b ldrb r3, [r3, #0]
|
|
80060f0: 2b53 cmp r3, #83 @ 0x53
|
|
80060f2: d109 bne.n 8006108 <Rx_Char+0x78>
|
|
TX_Schedule((unsigned char*) Signature, 20);
|
|
80060f4: 4bb2 ldr r3, [pc, #712] @ (80063c0 <Rx_Char+0x330>)
|
|
80060f6: 2114 movs r1, #20
|
|
80060f8: 0018 movs r0, r3
|
|
80060fa: f000 f995 bl 8006428 <TX_Schedule>
|
|
Comms_Reset(&RX);
|
|
80060fe: 4bad ldr r3, [pc, #692] @ (80063b4 <Rx_Char+0x324>)
|
|
8006100: 0018 movs r0, r3
|
|
8006102: f7ff ffa7 bl 8006054 <Comms_Reset>
|
|
8006106: e18a b.n 800641e <Rx_Char+0x38e>
|
|
} else if (data == 'B') {
|
|
8006108: 1dfb adds r3, r7, #7
|
|
800610a: 781b ldrb r3, [r3, #0]
|
|
800610c: 2b42 cmp r3, #66 @ 0x42
|
|
800610e: d107 bne.n 8006120 <Rx_Char+0x90>
|
|
Store_config();
|
|
8006110: 4bac ldr r3, [pc, #688] @ (80063c4 <Rx_Char+0x334>)
|
|
8006112: 681b ldr r3, [r3, #0]
|
|
8006114: 4798 blx r3
|
|
Comms_Reset(&RX);
|
|
8006116: 4ba7 ldr r3, [pc, #668] @ (80063b4 <Rx_Char+0x324>)
|
|
8006118: 0018 movs r0, r3
|
|
800611a: f7ff ff9b bl 8006054 <Comms_Reset>
|
|
800611e: e17e b.n 800641e <Rx_Char+0x38e>
|
|
} else if ((data == 'r') || (data == 'w') || (data == 'k')
|
|
8006120: 1dfb adds r3, r7, #7
|
|
8006122: 781b ldrb r3, [r3, #0]
|
|
8006124: 2b72 cmp r3, #114 @ 0x72
|
|
8006126: d00f beq.n 8006148 <Rx_Char+0xb8>
|
|
8006128: 1dfb adds r3, r7, #7
|
|
800612a: 781b ldrb r3, [r3, #0]
|
|
800612c: 2b77 cmp r3, #119 @ 0x77
|
|
800612e: d00b beq.n 8006148 <Rx_Char+0xb8>
|
|
8006130: 1dfb adds r3, r7, #7
|
|
8006132: 781b ldrb r3, [r3, #0]
|
|
8006134: 2b6b cmp r3, #107 @ 0x6b
|
|
8006136: d007 beq.n 8006148 <Rx_Char+0xb8>
|
|
|| (data == 'b') || (data == 'z')) {
|
|
8006138: 1dfb adds r3, r7, #7
|
|
800613a: 781b ldrb r3, [r3, #0]
|
|
800613c: 2b62 cmp r3, #98 @ 0x62
|
|
800613e: d003 beq.n 8006148 <Rx_Char+0xb8>
|
|
8006140: 1dfb adds r3, r7, #7
|
|
8006142: 781b ldrb r3, [r3, #0]
|
|
8006144: 2b7a cmp r3, #122 @ 0x7a
|
|
8006146: d108 bne.n 800615a <Rx_Char+0xca>
|
|
RX.timeout = 500;
|
|
8006148: 4b9a ldr r3, [pc, #616] @ (80063b4 <Rx_Char+0x324>)
|
|
800614a: 22fa movs r2, #250 @ 0xfa
|
|
800614c: 0052 lsls r2, r2, #1
|
|
800614e: 829a strh r2, [r3, #20]
|
|
RX.cmd = data;
|
|
8006150: 4b98 ldr r3, [pc, #608] @ (80063b4 <Rx_Char+0x324>)
|
|
8006152: 1dfa adds r2, r7, #7
|
|
8006154: 7812 ldrb r2, [r2, #0]
|
|
8006156: 705a strb r2, [r3, #1]
|
|
8006158: e161 b.n 800641e <Rx_Char+0x38e>
|
|
} else {
|
|
Comms_Reset(&RX);
|
|
800615a: 4b96 ldr r3, [pc, #600] @ (80063b4 <Rx_Char+0x324>)
|
|
800615c: 0018 movs r0, r3
|
|
800615e: f7ff ff79 bl 8006054 <Comms_Reset>
|
|
return;
|
|
8006162: e15c b.n 800641e <Rx_Char+0x38e>
|
|
}
|
|
|
|
} else if (RX.bytes_done == 2) {
|
|
8006164: 4b93 ldr r3, [pc, #588] @ (80063b4 <Rx_Char+0x324>)
|
|
8006166: 895b ldrh r3, [r3, #10]
|
|
8006168: 2b02 cmp r3, #2
|
|
800616a: d104 bne.n 8006176 <Rx_Char+0xe6>
|
|
RX.CANid = data;
|
|
800616c: 4b91 ldr r3, [pc, #580] @ (80063b4 <Rx_Char+0x324>)
|
|
800616e: 1dfa adds r2, r7, #7
|
|
8006170: 7812 ldrb r2, [r2, #0]
|
|
8006172: 709a strb r2, [r3, #2]
|
|
8006174: e153 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.bytes_done == 3) {
|
|
8006176: 4b8f ldr r3, [pc, #572] @ (80063b4 <Rx_Char+0x324>)
|
|
8006178: 895b ldrh r3, [r3, #10]
|
|
800617a: 2b03 cmp r3, #3
|
|
800617c: d110 bne.n 80061a0 <Rx_Char+0x110>
|
|
RX.table_index = data;
|
|
800617e: 4b8d ldr r3, [pc, #564] @ (80063b4 <Rx_Char+0x324>)
|
|
8006180: 1dfa adds r2, r7, #7
|
|
8006182: 7812 ldrb r2, [r2, #0]
|
|
8006184: 70da strb r2, [r3, #3]
|
|
if (RX.cmd == 'b') {
|
|
8006186: 4b8b ldr r3, [pc, #556] @ (80063b4 <Rx_Char+0x324>)
|
|
8006188: 785b ldrb r3, [r3, #1]
|
|
800618a: 2b62 cmp r3, #98 @ 0x62
|
|
800618c: d000 beq.n 8006190 <Rx_Char+0x100>
|
|
800618e: e146 b.n 800641e <Rx_Char+0x38e>
|
|
Store_config();
|
|
8006190: 4b8c ldr r3, [pc, #560] @ (80063c4 <Rx_Char+0x334>)
|
|
8006192: 681b ldr r3, [r3, #0]
|
|
8006194: 4798 blx r3
|
|
Comms_Reset(&RX);
|
|
8006196: 4b87 ldr r3, [pc, #540] @ (80063b4 <Rx_Char+0x324>)
|
|
8006198: 0018 movs r0, r3
|
|
800619a: f7ff ff5b bl 8006054 <Comms_Reset>
|
|
return;
|
|
800619e: e13e b.n 800641e <Rx_Char+0x38e>
|
|
}
|
|
} else if (RX.bytes_done == 4) {
|
|
80061a0: 4b84 ldr r3, [pc, #528] @ (80063b4 <Rx_Char+0x324>)
|
|
80061a2: 895b ldrh r3, [r3, #10]
|
|
80061a4: 2b04 cmp r3, #4
|
|
80061a6: d108 bne.n 80061ba <Rx_Char+0x12a>
|
|
RX.offset = 0x00;
|
|
80061a8: 4b82 ldr r3, [pc, #520] @ (80063b4 <Rx_Char+0x324>)
|
|
80061aa: 2200 movs r2, #0
|
|
80061ac: 809a strh r2, [r3, #4]
|
|
RX.offset = (unsigned short) data;
|
|
80061ae: 1dfb adds r3, r7, #7
|
|
80061b0: 781b ldrb r3, [r3, #0]
|
|
80061b2: b29a uxth r2, r3
|
|
80061b4: 4b7f ldr r3, [pc, #508] @ (80063b4 <Rx_Char+0x324>)
|
|
80061b6: 809a strh r2, [r3, #4]
|
|
80061b8: e131 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.bytes_done == 5) {
|
|
80061ba: 4b7e ldr r3, [pc, #504] @ (80063b4 <Rx_Char+0x324>)
|
|
80061bc: 895b ldrh r3, [r3, #10]
|
|
80061be: 2b05 cmp r3, #5
|
|
80061c0: d10d bne.n 80061de <Rx_Char+0x14e>
|
|
RX.offset |= ((unsigned short) data) << 8;
|
|
80061c2: 4b7c ldr r3, [pc, #496] @ (80063b4 <Rx_Char+0x324>)
|
|
80061c4: 889b ldrh r3, [r3, #4]
|
|
80061c6: b21a sxth r2, r3
|
|
80061c8: 1dfb adds r3, r7, #7
|
|
80061ca: 781b ldrb r3, [r3, #0]
|
|
80061cc: b21b sxth r3, r3
|
|
80061ce: 021b lsls r3, r3, #8
|
|
80061d0: b21b sxth r3, r3
|
|
80061d2: 4313 orrs r3, r2
|
|
80061d4: b21b sxth r3, r3
|
|
80061d6: b29a uxth r2, r3
|
|
80061d8: 4b76 ldr r3, [pc, #472] @ (80063b4 <Rx_Char+0x324>)
|
|
80061da: 809a strh r2, [r3, #4]
|
|
80061dc: e11f b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.bytes_done == 6) {
|
|
80061de: 4b75 ldr r3, [pc, #468] @ (80063b4 <Rx_Char+0x324>)
|
|
80061e0: 895b ldrh r3, [r3, #10]
|
|
80061e2: 2b06 cmp r3, #6
|
|
80061e4: d108 bne.n 80061f8 <Rx_Char+0x168>
|
|
RX.data_size = 0x00;
|
|
80061e6: 4b73 ldr r3, [pc, #460] @ (80063b4 <Rx_Char+0x324>)
|
|
80061e8: 2200 movs r2, #0
|
|
80061ea: 80da strh r2, [r3, #6]
|
|
RX.data_size = (unsigned short) data;
|
|
80061ec: 1dfb adds r3, r7, #7
|
|
80061ee: 781b ldrb r3, [r3, #0]
|
|
80061f0: b29a uxth r2, r3
|
|
80061f2: 4b70 ldr r3, [pc, #448] @ (80063b4 <Rx_Char+0x324>)
|
|
80061f4: 80da strh r2, [r3, #6]
|
|
80061f6: e112 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.bytes_done == 7) {
|
|
80061f8: 4b6e ldr r3, [pc, #440] @ (80063b4 <Rx_Char+0x324>)
|
|
80061fa: 895b ldrh r3, [r3, #10]
|
|
80061fc: 2b07 cmp r3, #7
|
|
80061fe: d000 beq.n 8006202 <Rx_Char+0x172>
|
|
8006200: e0ee b.n 80063e0 <Rx_Char+0x350>
|
|
RX.data_size += ((unsigned short) data) << 8;
|
|
8006202: 4b6c ldr r3, [pc, #432] @ (80063b4 <Rx_Char+0x324>)
|
|
8006204: 88da ldrh r2, [r3, #6]
|
|
8006206: 1dfb adds r3, r7, #7
|
|
8006208: 781b ldrb r3, [r3, #0]
|
|
800620a: b29b uxth r3, r3
|
|
800620c: 021b lsls r3, r3, #8
|
|
800620e: b29b uxth r3, r3
|
|
8006210: 18d3 adds r3, r2, r3
|
|
8006212: b29a uxth r2, r3
|
|
8006214: 4b67 ldr r3, [pc, #412] @ (80063b4 <Rx_Char+0x324>)
|
|
8006216: 80da strh r2, [r3, #6]
|
|
|
|
if (RX.CANid == TS_CAN_ID) {
|
|
8006218: 4b66 ldr r3, [pc, #408] @ (80063b4 <Rx_Char+0x324>)
|
|
800621a: 789b ldrb r3, [r3, #2]
|
|
800621c: 2b00 cmp r3, #0
|
|
800621e: d000 beq.n 8006222 <Rx_Char+0x192>
|
|
8006220: e0b5 b.n 800638e <Rx_Char+0x2fe>
|
|
|
|
if (RX.cmd == 'k') {
|
|
8006222: 4b64 ldr r3, [pc, #400] @ (80063b4 <Rx_Char+0x324>)
|
|
8006224: 785b ldrb r3, [r3, #1]
|
|
8006226: 2b6b cmp r3, #107 @ 0x6b
|
|
8006228: d10b bne.n 8006242 <Rx_Char+0x1b2>
|
|
SCI_flags |= SCI_FLAGS_CRC32;
|
|
800622a: 4b63 ldr r3, [pc, #396] @ (80063b8 <Rx_Char+0x328>)
|
|
800622c: 781b ldrb r3, [r3, #0]
|
|
800622e: 2201 movs r2, #1
|
|
8006230: 4313 orrs r3, r2
|
|
8006232: b2da uxtb r2, r3
|
|
8006234: 4b60 ldr r3, [pc, #384] @ (80063b8 <Rx_Char+0x328>)
|
|
8006236: 701a strb r2, [r3, #0]
|
|
Comms_Reset(&RX);
|
|
8006238: 4b5e ldr r3, [pc, #376] @ (80063b4 <Rx_Char+0x324>)
|
|
800623a: 0018 movs r0, r3
|
|
800623c: f7ff ff0a bl 8006054 <Comms_Reset>
|
|
return;
|
|
8006240: e0ed b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.cmd == 'z') {
|
|
8006242: 4b5c ldr r3, [pc, #368] @ (80063b4 <Rx_Char+0x324>)
|
|
8006244: 785b ldrb r3, [r3, #1]
|
|
8006246: 2b7a cmp r3, #122 @ 0x7a
|
|
8006248: d141 bne.n 80062ce <Rx_Char+0x23e>
|
|
// process command buttons
|
|
if (RX.data_size == 0x0100) {
|
|
800624a: 4b5a ldr r3, [pc, #360] @ (80063b4 <Rx_Char+0x324>)
|
|
800624c: 88da ldrh r2, [r3, #6]
|
|
800624e: 2380 movs r3, #128 @ 0x80
|
|
8006250: 005b lsls r3, r3, #1
|
|
8006252: 429a cmp r2, r3
|
|
8006254: d102 bne.n 800625c <Rx_Char+0x1cc>
|
|
Apply_Sensor_Calibration();
|
|
8006256: f7fc fef1 bl 800303c <Apply_Sensor_Calibration>
|
|
800625a: e033 b.n 80062c4 <Rx_Char+0x234>
|
|
} else if (RX.data_size == 0x0200) {
|
|
800625c: 4b55 ldr r3, [pc, #340] @ (80063b4 <Rx_Char+0x324>)
|
|
800625e: 88da ldrh r2, [r3, #6]
|
|
8006260: 2380 movs r3, #128 @ 0x80
|
|
8006262: 009b lsls r3, r3, #2
|
|
8006264: 429a cmp r2, r3
|
|
8006266: d10e bne.n 8006286 <Rx_Char+0x1f6>
|
|
DBW_Stop();
|
|
8006268: f7fd feea bl 8004040 <DBW_Stop>
|
|
config->config_bits |= CONFIG_TESTMODE_F;
|
|
800626c: 4b56 ldr r3, [pc, #344] @ (80063c8 <Rx_Char+0x338>)
|
|
800626e: 681b ldr r3, [r3, #0]
|
|
8006270: 4a56 ldr r2, [pc, #344] @ (80063cc <Rx_Char+0x33c>)
|
|
8006272: 5a9b ldrh r3, [r3, r2]
|
|
8006274: b29a uxth r2, r3
|
|
8006276: 4b54 ldr r3, [pc, #336] @ (80063c8 <Rx_Char+0x338>)
|
|
8006278: 681b ldr r3, [r3, #0]
|
|
800627a: 2104 movs r1, #4
|
|
800627c: 430a orrs r2, r1
|
|
800627e: b291 uxth r1, r2
|
|
8006280: 4a52 ldr r2, [pc, #328] @ (80063cc <Rx_Char+0x33c>)
|
|
8006282: 5299 strh r1, [r3, r2]
|
|
8006284: e01e b.n 80062c4 <Rx_Char+0x234>
|
|
} else if (RX.data_size == 0x0300) {
|
|
8006286: 4b4b ldr r3, [pc, #300] @ (80063b4 <Rx_Char+0x324>)
|
|
8006288: 88da ldrh r2, [r3, #6]
|
|
800628a: 23c0 movs r3, #192 @ 0xc0
|
|
800628c: 009b lsls r3, r3, #2
|
|
800628e: 429a cmp r2, r3
|
|
8006290: d10c bne.n 80062ac <Rx_Char+0x21c>
|
|
config->config_bits &= ~CONFIG_TESTMODE_F;
|
|
8006292: 4b4d ldr r3, [pc, #308] @ (80063c8 <Rx_Char+0x338>)
|
|
8006294: 681b ldr r3, [r3, #0]
|
|
8006296: 4a4d ldr r2, [pc, #308] @ (80063cc <Rx_Char+0x33c>)
|
|
8006298: 5a9b ldrh r3, [r3, r2]
|
|
800629a: b29a uxth r2, r3
|
|
800629c: 4b4a ldr r3, [pc, #296] @ (80063c8 <Rx_Char+0x338>)
|
|
800629e: 681b ldr r3, [r3, #0]
|
|
80062a0: 2104 movs r1, #4
|
|
80062a2: 438a bics r2, r1
|
|
80062a4: b291 uxth r1, r2
|
|
80062a6: 4a49 ldr r2, [pc, #292] @ (80063cc <Rx_Char+0x33c>)
|
|
80062a8: 5299 strh r1, [r3, r2]
|
|
80062aa: e00b b.n 80062c4 <Rx_Char+0x234>
|
|
} else if (RX.data_size == 0x0400) {
|
|
80062ac: 4b41 ldr r3, [pc, #260] @ (80063b4 <Rx_Char+0x324>)
|
|
80062ae: 88da ldrh r2, [r3, #6]
|
|
80062b0: 2380 movs r3, #128 @ 0x80
|
|
80062b2: 00db lsls r3, r3, #3
|
|
80062b4: 429a cmp r2, r3
|
|
80062b6: d105 bne.n 80062c4 <Rx_Char+0x234>
|
|
//Start TPS AUTOCAL
|
|
ac_timer = 200;
|
|
80062b8: 4b45 ldr r3, [pc, #276] @ (80063d0 <Rx_Char+0x340>)
|
|
80062ba: 22c8 movs r2, #200 @ 0xc8
|
|
80062bc: 601a str r2, [r3, #0]
|
|
ac_mode = 1;
|
|
80062be: 4b45 ldr r3, [pc, #276] @ (80063d4 <Rx_Char+0x344>)
|
|
80062c0: 2201 movs r2, #1
|
|
80062c2: 601a str r2, [r3, #0]
|
|
}
|
|
Comms_Reset(&RX);
|
|
80062c4: 4b3b ldr r3, [pc, #236] @ (80063b4 <Rx_Char+0x324>)
|
|
80062c6: 0018 movs r0, r3
|
|
80062c8: f7ff fec4 bl 8006054 <Comms_Reset>
|
|
80062cc: e0a7 b.n 800641e <Rx_Char+0x38e>
|
|
} else if (RX.cmd == 'r') {
|
|
80062ce: 4b39 ldr r3, [pc, #228] @ (80063b4 <Rx_Char+0x324>)
|
|
80062d0: 785b ldrb r3, [r3, #1]
|
|
80062d2: 2b72 cmp r3, #114 @ 0x72
|
|
80062d4: d139 bne.n 800634a <Rx_Char+0x2ba>
|
|
// Read different tables
|
|
if (RX.table_index == 0x01) {
|
|
80062d6: 4b37 ldr r3, [pc, #220] @ (80063b4 <Rx_Char+0x324>)
|
|
80062d8: 78db ldrb r3, [r3, #3]
|
|
80062da: 2b01 cmp r3, #1
|
|
80062dc: d10b bne.n 80062f6 <Rx_Char+0x266>
|
|
TX_Schedule((unsigned char*) config + RX.offset,
|
|
80062de: 4b3a ldr r3, [pc, #232] @ (80063c8 <Rx_Char+0x338>)
|
|
80062e0: 681b ldr r3, [r3, #0]
|
|
80062e2: 4a34 ldr r2, [pc, #208] @ (80063b4 <Rx_Char+0x324>)
|
|
80062e4: 8892 ldrh r2, [r2, #4]
|
|
80062e6: 189a adds r2, r3, r2
|
|
80062e8: 4b32 ldr r3, [pc, #200] @ (80063b4 <Rx_Char+0x324>)
|
|
80062ea: 88db ldrh r3, [r3, #6]
|
|
80062ec: 0019 movs r1, r3
|
|
80062ee: 0010 movs r0, r2
|
|
80062f0: f000 f89a bl 8006428 <TX_Schedule>
|
|
80062f4: e024 b.n 8006340 <Rx_Char+0x2b0>
|
|
RX.data_size);
|
|
} else if (RX.table_index == 0x07) {
|
|
80062f6: 4b2f ldr r3, [pc, #188] @ (80063b4 <Rx_Char+0x324>)
|
|
80062f8: 78db ldrb r3, [r3, #3]
|
|
80062fa: 2b07 cmp r3, #7
|
|
80062fc: d10d bne.n 800631a <Rx_Char+0x28a>
|
|
Copy_Tx_Vars();
|
|
80062fe: f000 f947 bl 8006590 <Copy_Tx_Vars>
|
|
TX_Schedule((unsigned char*) &tx_bufer + RX.offset,
|
|
8006302: 4b2c ldr r3, [pc, #176] @ (80063b4 <Rx_Char+0x324>)
|
|
8006304: 889b ldrh r3, [r3, #4]
|
|
8006306: 001a movs r2, r3
|
|
8006308: 4b33 ldr r3, [pc, #204] @ (80063d8 <Rx_Char+0x348>)
|
|
800630a: 18d2 adds r2, r2, r3
|
|
800630c: 4b29 ldr r3, [pc, #164] @ (80063b4 <Rx_Char+0x324>)
|
|
800630e: 88db ldrh r3, [r3, #6]
|
|
8006310: 0019 movs r1, r3
|
|
8006312: 0010 movs r0, r2
|
|
8006314: f000 f888 bl 8006428 <TX_Schedule>
|
|
8006318: e012 b.n 8006340 <Rx_Char+0x2b0>
|
|
RX.data_size);
|
|
} else if (RX.table_index == 0x0e) {
|
|
800631a: 4b26 ldr r3, [pc, #152] @ (80063b4 <Rx_Char+0x324>)
|
|
800631c: 78db ldrb r3, [r3, #3]
|
|
800631e: 2b0e cmp r3, #14
|
|
8006320: d105 bne.n 800632e <Rx_Char+0x29e>
|
|
TX_Schedule((unsigned char*) Signature, 20);
|
|
8006322: 4b27 ldr r3, [pc, #156] @ (80063c0 <Rx_Char+0x330>)
|
|
8006324: 2114 movs r1, #20
|
|
8006326: 0018 movs r0, r3
|
|
8006328: f000 f87e bl 8006428 <TX_Schedule>
|
|
800632c: e008 b.n 8006340 <Rx_Char+0x2b0>
|
|
} else if (RX.table_index == 0x0f) {
|
|
800632e: 4b21 ldr r3, [pc, #132] @ (80063b4 <Rx_Char+0x324>)
|
|
8006330: 78db ldrb r3, [r3, #3]
|
|
8006332: 2b0f cmp r3, #15
|
|
8006334: d104 bne.n 8006340 <Rx_Char+0x2b0>
|
|
TX_Schedule((unsigned char*) Revision, 20);
|
|
8006336: 4b21 ldr r3, [pc, #132] @ (80063bc <Rx_Char+0x32c>)
|
|
8006338: 2114 movs r1, #20
|
|
800633a: 0018 movs r0, r3
|
|
800633c: f000 f874 bl 8006428 <TX_Schedule>
|
|
}
|
|
Comms_Reset(&RX);
|
|
8006340: 4b1c ldr r3, [pc, #112] @ (80063b4 <Rx_Char+0x324>)
|
|
8006342: 0018 movs r0, r3
|
|
8006344: f7ff fe86 bl 8006054 <Comms_Reset>
|
|
return;
|
|
8006348: e069 b.n 800641e <Rx_Char+0x38e>
|
|
} else {
|
|
//Comms are not reset for 'w' command
|
|
// setup write pointer
|
|
RX.cnt = RX.bytes_done + RX.data_size;
|
|
800634a: 4b1a ldr r3, [pc, #104] @ (80063b4 <Rx_Char+0x324>)
|
|
800634c: 895a ldrh r2, [r3, #10]
|
|
800634e: 4b19 ldr r3, [pc, #100] @ (80063b4 <Rx_Char+0x324>)
|
|
8006350: 88db ldrh r3, [r3, #6]
|
|
8006352: 18d3 adds r3, r2, r3
|
|
8006354: b29a uxth r2, r3
|
|
8006356: 4b17 ldr r3, [pc, #92] @ (80063b4 <Rx_Char+0x324>)
|
|
8006358: 811a strh r2, [r3, #8]
|
|
if (RX.table_index == 0x01) {
|
|
800635a: 4b16 ldr r3, [pc, #88] @ (80063b4 <Rx_Char+0x324>)
|
|
800635c: 78db ldrb r3, [r3, #3]
|
|
800635e: 2b01 cmp r3, #1
|
|
8006360: d107 bne.n 8006372 <Rx_Char+0x2e2>
|
|
RX.address = (unsigned char*) config + RX.offset;
|
|
8006362: 4b19 ldr r3, [pc, #100] @ (80063c8 <Rx_Char+0x338>)
|
|
8006364: 681b ldr r3, [r3, #0]
|
|
8006366: 4a13 ldr r2, [pc, #76] @ (80063b4 <Rx_Char+0x324>)
|
|
8006368: 8892 ldrh r2, [r2, #4]
|
|
800636a: 189a adds r2, r3, r2
|
|
800636c: 4b11 ldr r3, [pc, #68] @ (80063b4 <Rx_Char+0x324>)
|
|
800636e: 60da str r2, [r3, #12]
|
|
// Do not allow more then 256 bytes to be written to CAN buffer
|
|
if (RX.data_size > 256)
|
|
Comms_Reset(&RX);
|
|
}
|
|
|
|
return;
|
|
8006370: e054 b.n 800641c <Rx_Char+0x38c>
|
|
RX.address = (unsigned char*) RX.can_bufer;
|
|
8006372: 4b10 ldr r3, [pc, #64] @ (80063b4 <Rx_Char+0x324>)
|
|
8006374: 4a19 ldr r2, [pc, #100] @ (80063dc <Rx_Char+0x34c>)
|
|
8006376: 60da str r2, [r3, #12]
|
|
if (RX.data_size > 256)
|
|
8006378: 4b0e ldr r3, [pc, #56] @ (80063b4 <Rx_Char+0x324>)
|
|
800637a: 88da ldrh r2, [r3, #6]
|
|
800637c: 2380 movs r3, #128 @ 0x80
|
|
800637e: 005b lsls r3, r3, #1
|
|
8006380: 429a cmp r2, r3
|
|
8006382: d94b bls.n 800641c <Rx_Char+0x38c>
|
|
Comms_Reset(&RX);
|
|
8006384: 4b0b ldr r3, [pc, #44] @ (80063b4 <Rx_Char+0x324>)
|
|
8006386: 0018 movs r0, r3
|
|
8006388: f7ff fe64 bl 8006054 <Comms_Reset>
|
|
return;
|
|
800638c: e046 b.n 800641c <Rx_Char+0x38c>
|
|
}
|
|
|
|
} else {
|
|
// if received CANID != TS_CANID
|
|
if ((RX.cmd == 'k') || (RX.cmd == 'r')) {
|
|
800638e: 4b09 ldr r3, [pc, #36] @ (80063b4 <Rx_Char+0x324>)
|
|
8006390: 785b ldrb r3, [r3, #1]
|
|
8006392: 2b6b cmp r3, #107 @ 0x6b
|
|
8006394: d003 beq.n 800639e <Rx_Char+0x30e>
|
|
8006396: 4b07 ldr r3, [pc, #28] @ (80063b4 <Rx_Char+0x324>)
|
|
8006398: 785b ldrb r3, [r3, #1]
|
|
800639a: 2b72 cmp r3, #114 @ 0x72
|
|
800639c: d104 bne.n 80063a8 <Rx_Char+0x318>
|
|
//TODO pass data to CAN device
|
|
Comms_Reset(&RX);
|
|
800639e: 4b05 ldr r3, [pc, #20] @ (80063b4 <Rx_Char+0x324>)
|
|
80063a0: 0018 movs r0, r3
|
|
80063a2: f7ff fe57 bl 8006054 <Comms_Reset>
|
|
return;
|
|
80063a6: e03a b.n 800641e <Rx_Char+0x38e>
|
|
}
|
|
Comms_Reset(&RX);
|
|
80063a8: 4b02 ldr r3, [pc, #8] @ (80063b4 <Rx_Char+0x324>)
|
|
80063aa: 0018 movs r0, r3
|
|
80063ac: f7ff fe52 bl 8006054 <Comms_Reset>
|
|
return;
|
|
80063b0: e035 b.n 800641e <Rx_Char+0x38e>
|
|
80063b2: 46c0 nop @ (mov r8, r8)
|
|
80063b4: 20000b34 .word 0x20000b34
|
|
80063b8: 20000d6c .word 0x20000d6c
|
|
80063bc: 08008b0c .word 0x08008b0c
|
|
80063c0: 08008af8 .word 0x08008af8
|
|
80063c4: 20000008 .word 0x20000008
|
|
80063c8: 200009cc .word 0x200009cc
|
|
80063cc: 0000033a .word 0x0000033a
|
|
80063d0: 20000000 .word 0x20000000
|
|
80063d4: 200009d0 .word 0x200009d0
|
|
80063d8: 20000d78 .word 0x20000d78
|
|
80063dc: 20000b50 .word 0x20000b50
|
|
}
|
|
} else {
|
|
//receive data TX.bytes_done >7
|
|
*(RX.address) = data;
|
|
80063e0: 4b10 ldr r3, [pc, #64] @ (8006424 <Rx_Char+0x394>)
|
|
80063e2: 68db ldr r3, [r3, #12]
|
|
80063e4: 1dfa adds r2, r7, #7
|
|
80063e6: 7812 ldrb r2, [r2, #0]
|
|
80063e8: 701a strb r2, [r3, #0]
|
|
RX.address++;
|
|
80063ea: 4b0e ldr r3, [pc, #56] @ (8006424 <Rx_Char+0x394>)
|
|
80063ec: 68db ldr r3, [r3, #12]
|
|
80063ee: 1c5a adds r2, r3, #1
|
|
80063f0: 4b0c ldr r3, [pc, #48] @ (8006424 <Rx_Char+0x394>)
|
|
80063f2: 60da str r2, [r3, #12]
|
|
|
|
if (RX.bytes_done >= RX.cnt) {
|
|
80063f4: 4b0b ldr r3, [pc, #44] @ (8006424 <Rx_Char+0x394>)
|
|
80063f6: 895a ldrh r2, [r3, #10]
|
|
80063f8: 4b0a ldr r3, [pc, #40] @ (8006424 <Rx_Char+0x394>)
|
|
80063fa: 891b ldrh r3, [r3, #8]
|
|
80063fc: 429a cmp r2, r3
|
|
80063fe: d30e bcc.n 800641e <Rx_Char+0x38e>
|
|
if (RX.table_index == 0x0d) {
|
|
8006400: 4b08 ldr r3, [pc, #32] @ (8006424 <Rx_Char+0x394>)
|
|
8006402: 78db ldrb r3, [r3, #3]
|
|
8006404: 2b0d cmp r3, #13
|
|
8006406: d104 bne.n 8006412 <Rx_Char+0x382>
|
|
//TODO Call command by index
|
|
Comms_Reset(&RX);
|
|
8006408: 4b06 ldr r3, [pc, #24] @ (8006424 <Rx_Char+0x394>)
|
|
800640a: 0018 movs r0, r3
|
|
800640c: f7ff fe22 bl 8006054 <Comms_Reset>
|
|
8006410: e005 b.n 800641e <Rx_Char+0x38e>
|
|
} else {
|
|
// Expecting here ends data write chain
|
|
Comms_Reset(&RX);
|
|
8006412: 4b04 ldr r3, [pc, #16] @ (8006424 <Rx_Char+0x394>)
|
|
8006414: 0018 movs r0, r3
|
|
8006416: f7ff fe1d bl 8006054 <Comms_Reset>
|
|
800641a: e000 b.n 800641e <Rx_Char+0x38e>
|
|
return;
|
|
800641c: 46c0 nop @ (mov r8, r8)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} // RX Char
|
|
800641e: 46bd mov sp, r7
|
|
8006420: b002 add sp, #8
|
|
8006422: bd80 pop {r7, pc}
|
|
8006424: 20000b34 .word 0x20000b34
|
|
|
|
08006428 <TX_Schedule>:
|
|
|
|
void TX_Schedule(unsigned char *data, unsigned short count) {
|
|
8006428: b580 push {r7, lr}
|
|
800642a: b082 sub sp, #8
|
|
800642c: af00 add r7, sp, #0
|
|
800642e: 6078 str r0, [r7, #4]
|
|
8006430: 000a movs r2, r1
|
|
8006432: 1cbb adds r3, r7, #2
|
|
8006434: 801a strh r2, [r3, #0]
|
|
//Schedule transmission
|
|
TX.mode = TRANSMISSION_IN_PROGRESS; // Set TX mode to transmit
|
|
8006436: 4b16 ldr r3, [pc, #88] @ (8006490 <TX_Schedule+0x68>)
|
|
8006438: 2201 movs r2, #1
|
|
800643a: 701a strb r2, [r3, #0]
|
|
|
|
TX.cnt = count; // Set number of byte to be transmited
|
|
800643c: 4b14 ldr r3, [pc, #80] @ (8006490 <TX_Schedule+0x68>)
|
|
800643e: 1cba adds r2, r7, #2
|
|
8006440: 8812 ldrh r2, [r2, #0]
|
|
8006442: 811a strh r2, [r3, #8]
|
|
TX.bytes_done = 0; // Set number of bytes transmitted
|
|
8006444: 4b12 ldr r3, [pc, #72] @ (8006490 <TX_Schedule+0x68>)
|
|
8006446: 2200 movs r2, #0
|
|
8006448: 815a strh r2, [r3, #10]
|
|
TX.address = data; // Store updated address
|
|
800644a: 4b11 ldr r3, [pc, #68] @ (8006490 <TX_Schedule+0x68>)
|
|
800644c: 687a ldr r2, [r7, #4]
|
|
800644e: 60da str r2, [r3, #12]
|
|
|
|
//transmit first data byte
|
|
USART1->ICR |= USART_ICR_TCCF;
|
|
8006450: 4b10 ldr r3, [pc, #64] @ (8006494 <TX_Schedule+0x6c>)
|
|
8006452: 6a1a ldr r2, [r3, #32]
|
|
8006454: 4b0f ldr r3, [pc, #60] @ (8006494 <TX_Schedule+0x6c>)
|
|
8006456: 2140 movs r1, #64 @ 0x40
|
|
8006458: 430a orrs r2, r1
|
|
800645a: 621a str r2, [r3, #32]
|
|
USART1->TDR = *data;
|
|
800645c: 687b ldr r3, [r7, #4]
|
|
800645e: 781a ldrb r2, [r3, #0]
|
|
8006460: 4b0c ldr r3, [pc, #48] @ (8006494 <TX_Schedule+0x6c>)
|
|
8006462: 851a strh r2, [r3, #40] @ 0x28
|
|
USART1->CR1 |= USART_CR1_TCIE;
|
|
8006464: 4b0b ldr r3, [pc, #44] @ (8006494 <TX_Schedule+0x6c>)
|
|
8006466: 681a ldr r2, [r3, #0]
|
|
8006468: 4b0a ldr r3, [pc, #40] @ (8006494 <TX_Schedule+0x6c>)
|
|
800646a: 2140 movs r1, #64 @ 0x40
|
|
800646c: 430a orrs r2, r1
|
|
800646e: 601a str r2, [r3, #0]
|
|
|
|
TX.bytes_done++;
|
|
8006470: 4b07 ldr r3, [pc, #28] @ (8006490 <TX_Schedule+0x68>)
|
|
8006472: 895b ldrh r3, [r3, #10]
|
|
8006474: 3301 adds r3, #1
|
|
8006476: b29a uxth r2, r3
|
|
8006478: 4b05 ldr r3, [pc, #20] @ (8006490 <TX_Schedule+0x68>)
|
|
800647a: 815a strh r2, [r3, #10]
|
|
TX.address++;
|
|
800647c: 4b04 ldr r3, [pc, #16] @ (8006490 <TX_Schedule+0x68>)
|
|
800647e: 68db ldr r3, [r3, #12]
|
|
8006480: 1c5a adds r2, r3, #1
|
|
8006482: 4b03 ldr r3, [pc, #12] @ (8006490 <TX_Schedule+0x68>)
|
|
8006484: 60da str r2, [r3, #12]
|
|
// else{
|
|
//
|
|
//
|
|
// }
|
|
|
|
return;
|
|
8006486: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
8006488: 46bd mov sp, r7
|
|
800648a: b002 add sp, #8
|
|
800648c: bd80 pop {r7, pc}
|
|
800648e: 46c0 nop @ (mov r8, r8)
|
|
8006490: 20000c50 .word 0x20000c50
|
|
8006494: 40013800 .word 0x40013800
|
|
|
|
08006498 <Poll_Tx>:
|
|
|
|
void Poll_Tx(void) {
|
|
8006498: b580 push {r7, lr}
|
|
800649a: af00 add r7, sp, #0
|
|
|
|
if (TX.mode == TRANSMISSION_IN_PROGRESS) {
|
|
800649c: 4b17 ldr r3, [pc, #92] @ (80064fc <Poll_Tx+0x64>)
|
|
800649e: 781b ldrb r3, [r3, #0]
|
|
80064a0: 2b01 cmp r3, #1
|
|
80064a2: d029 beq.n 80064f8 <Poll_Tx+0x60>
|
|
// do nothing because transmitter is busy;
|
|
}
|
|
// Check if variables should be transmitted
|
|
else if (SCI_flags & SCI_FLAGS_TX_VARIABLES) {
|
|
80064a4: 4b16 ldr r3, [pc, #88] @ (8006500 <Poll_Tx+0x68>)
|
|
80064a6: 781b ldrb r3, [r3, #0]
|
|
80064a8: 001a movs r2, r3
|
|
80064aa: 2302 movs r3, #2
|
|
80064ac: 4013 ands r3, r2
|
|
80064ae: d00e beq.n 80064ce <Poll_Tx+0x36>
|
|
//Copy variables to tx_bufer
|
|
Copy_Tx_Vars();
|
|
80064b0: f000 f86e bl 8006590 <Copy_Tx_Vars>
|
|
TX_Schedule((unsigned char*) &tx_bufer, sizeof(var_t));
|
|
80064b4: 4b13 ldr r3, [pc, #76] @ (8006504 <Poll_Tx+0x6c>)
|
|
80064b6: 2134 movs r1, #52 @ 0x34
|
|
80064b8: 0018 movs r0, r3
|
|
80064ba: f7ff ffb5 bl 8006428 <TX_Schedule>
|
|
SCI_flags &= ~SCI_FLAGS_TX_VARIABLES;
|
|
80064be: 4b10 ldr r3, [pc, #64] @ (8006500 <Poll_Tx+0x68>)
|
|
80064c0: 781b ldrb r3, [r3, #0]
|
|
80064c2: 2202 movs r2, #2
|
|
80064c4: 4393 bics r3, r2
|
|
80064c6: b2da uxtb r2, r3
|
|
80064c8: 4b0d ldr r3, [pc, #52] @ (8006500 <Poll_Tx+0x68>)
|
|
80064ca: 701a strb r2, [r3, #0]
|
|
return;
|
|
80064cc: e014 b.n 80064f8 <Poll_Tx+0x60>
|
|
|
|
} else if (SCI_flags & SCI_FLAGS_CRC32) {
|
|
80064ce: 4b0c ldr r3, [pc, #48] @ (8006500 <Poll_Tx+0x68>)
|
|
80064d0: 781b ldrb r3, [r3, #0]
|
|
80064d2: 001a movs r2, r3
|
|
80064d4: 2301 movs r3, #1
|
|
80064d6: 4013 ands r3, r2
|
|
80064d8: d00e beq.n 80064f8 <Poll_Tx+0x60>
|
|
SCI_flags &= ~SCI_FLAGS_CRC32;
|
|
80064da: 4b09 ldr r3, [pc, #36] @ (8006500 <Poll_Tx+0x68>)
|
|
80064dc: 781b ldrb r3, [r3, #0]
|
|
80064de: 2201 movs r2, #1
|
|
80064e0: 4393 bics r3, r2
|
|
80064e2: b2da uxtb r2, r3
|
|
80064e4: 4b06 ldr r3, [pc, #24] @ (8006500 <Poll_Tx+0x68>)
|
|
80064e6: 701a strb r2, [r3, #0]
|
|
CRC32();
|
|
80064e8: f000 f82a bl 8006540 <CRC32>
|
|
TX_Schedule((unsigned char*) &crc32_bufer[0], 4);
|
|
80064ec: 4b06 ldr r3, [pc, #24] @ (8006508 <Poll_Tx+0x70>)
|
|
80064ee: 2104 movs r1, #4
|
|
80064f0: 0018 movs r0, r3
|
|
80064f2: f7ff ff99 bl 8006428 <TX_Schedule>
|
|
return;
|
|
80064f6: 46c0 nop @ (mov r8, r8)
|
|
|
|
}
|
|
|
|
}
|
|
80064f8: 46bd mov sp, r7
|
|
80064fa: bd80 pop {r7, pc}
|
|
80064fc: 20000c50 .word 0x20000c50
|
|
8006500: 20000d6c .word 0x20000d6c
|
|
8006504: 20000d78 .word 0x20000d78
|
|
8006508: 20000d70 .word 0x20000d70
|
|
|
|
0800650c <TX_Done>:
|
|
|
|
void TX_Done(void) {
|
|
800650c: b580 push {r7, lr}
|
|
800650e: af00 add r7, sp, #0
|
|
Comms_Reset(&TX);
|
|
8006510: 4b09 ldr r3, [pc, #36] @ (8006538 <TX_Done+0x2c>)
|
|
8006512: 0018 movs r0, r3
|
|
8006514: f7ff fd9e bl 8006054 <Comms_Reset>
|
|
//disable TX interrupt
|
|
USART1->CR1 &= ~USART_CR1_TCIE;
|
|
8006518: 4b08 ldr r3, [pc, #32] @ (800653c <TX_Done+0x30>)
|
|
800651a: 681a ldr r2, [r3, #0]
|
|
800651c: 4b07 ldr r3, [pc, #28] @ (800653c <TX_Done+0x30>)
|
|
800651e: 2140 movs r1, #64 @ 0x40
|
|
8006520: 438a bics r2, r1
|
|
8006522: 601a str r2, [r3, #0]
|
|
USART1->ICR |= USART_ICR_TCCF;
|
|
8006524: 4b05 ldr r3, [pc, #20] @ (800653c <TX_Done+0x30>)
|
|
8006526: 6a1a ldr r2, [r3, #32]
|
|
8006528: 4b04 ldr r3, [pc, #16] @ (800653c <TX_Done+0x30>)
|
|
800652a: 2140 movs r1, #64 @ 0x40
|
|
800652c: 430a orrs r2, r1
|
|
800652e: 621a str r2, [r3, #32]
|
|
|
|
}
|
|
8006530: 46c0 nop @ (mov r8, r8)
|
|
8006532: 46bd mov sp, r7
|
|
8006534: bd80 pop {r7, pc}
|
|
8006536: 46c0 nop @ (mov r8, r8)
|
|
8006538: 20000c50 .word 0x20000c50
|
|
800653c: 40013800 .word 0x40013800
|
|
|
|
08006540 <CRC32>:
|
|
|
|
void CRC32(void) {
|
|
8006540: b580 push {r7, lr}
|
|
8006542: b082 sub sp, #8
|
|
8006544: af00 add r7, sp, #0
|
|
unsigned int tmp;
|
|
|
|
tmp = (unsigned int) crc32((void*) config, sizeof(config_t));
|
|
8006546: 4b10 ldr r3, [pc, #64] @ (8006588 <CRC32+0x48>)
|
|
8006548: 681b ldr r3, [r3, #0]
|
|
800654a: 22d6 movs r2, #214 @ 0xd6
|
|
800654c: 0092 lsls r2, r2, #2
|
|
800654e: 0011 movs r1, r2
|
|
8006550: 0018 movs r0, r3
|
|
8006552: f000 f899 bl 8006688 <crc32>
|
|
8006556: 0003 movs r3, r0
|
|
8006558: 607b str r3, [r7, #4]
|
|
crc32_bufer[0] = (unsigned char) ((tmp >> 24) & 0x000000ff);
|
|
800655a: 687b ldr r3, [r7, #4]
|
|
800655c: 0e1b lsrs r3, r3, #24
|
|
800655e: b2da uxtb r2, r3
|
|
8006560: 4b0a ldr r3, [pc, #40] @ (800658c <CRC32+0x4c>)
|
|
8006562: 701a strb r2, [r3, #0]
|
|
crc32_bufer[1] = (unsigned char) ((tmp >> 16) & 0x000000ff);
|
|
8006564: 687b ldr r3, [r7, #4]
|
|
8006566: 0c1b lsrs r3, r3, #16
|
|
8006568: b2da uxtb r2, r3
|
|
800656a: 4b08 ldr r3, [pc, #32] @ (800658c <CRC32+0x4c>)
|
|
800656c: 705a strb r2, [r3, #1]
|
|
crc32_bufer[2] = (unsigned char) ((tmp >> 8) & 0x000000ff);
|
|
800656e: 687b ldr r3, [r7, #4]
|
|
8006570: 0a1b lsrs r3, r3, #8
|
|
8006572: b2da uxtb r2, r3
|
|
8006574: 4b05 ldr r3, [pc, #20] @ (800658c <CRC32+0x4c>)
|
|
8006576: 709a strb r2, [r3, #2]
|
|
crc32_bufer[3] = (unsigned char) ((tmp) & 0x000000ff);
|
|
8006578: 687b ldr r3, [r7, #4]
|
|
800657a: b2da uxtb r2, r3
|
|
800657c: 4b03 ldr r3, [pc, #12] @ (800658c <CRC32+0x4c>)
|
|
800657e: 70da strb r2, [r3, #3]
|
|
}
|
|
8006580: 46c0 nop @ (mov r8, r8)
|
|
8006582: 46bd mov sp, r7
|
|
8006584: b002 add sp, #8
|
|
8006586: bd80 pop {r7, pc}
|
|
8006588: 200009cc .word 0x200009cc
|
|
800658c: 20000d70 .word 0x20000d70
|
|
|
|
08006590 <Copy_Tx_Vars>:
|
|
|
|
void Copy_Tx_Vars(void) {
|
|
8006590: b580 push {r7, lr}
|
|
8006592: af00 add r7, sp, #0
|
|
|
|
//TODO copy all variables from *var to tx_bufer to make sure
|
|
// nothing is changed while transmission is in progress
|
|
//tx_bufer.a = var->a;
|
|
|
|
tx_bufer.clock = var.clock;
|
|
8006594: 4b3a ldr r3, [pc, #232] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006596: 681a ldr r2, [r3, #0]
|
|
8006598: 4b3a ldr r3, [pc, #232] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
800659a: 601a str r2, [r3, #0]
|
|
tx_bufer.status0 = var.rpm;
|
|
800659c: 4b38 ldr r3, [pc, #224] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
800659e: 8e5b ldrh r3, [r3, #50] @ 0x32
|
|
80065a0: b29a uxth r2, r3
|
|
80065a2: 4b38 ldr r3, [pc, #224] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065a4: 809a strh r2, [r3, #4]
|
|
tx_bufer.status1 = var.status1;
|
|
80065a6: 4b36 ldr r3, [pc, #216] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065a8: 88db ldrh r3, [r3, #6]
|
|
80065aa: b29a uxth r2, r3
|
|
80065ac: 4b35 ldr r3, [pc, #212] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065ae: 80da strh r2, [r3, #6]
|
|
tx_bufer.status2 = var.status2;
|
|
80065b0: 4b33 ldr r3, [pc, #204] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065b2: 891b ldrh r3, [r3, #8]
|
|
80065b4: b29a uxth r2, r3
|
|
80065b6: 4b33 ldr r3, [pc, #204] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065b8: 811a strh r2, [r3, #8]
|
|
tx_bufer.status3 = var.status3;
|
|
80065ba: 4b31 ldr r3, [pc, #196] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065bc: 895b ldrh r3, [r3, #10]
|
|
80065be: b29a uxth r2, r3
|
|
80065c0: 4b30 ldr r3, [pc, #192] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065c2: 815a strh r2, [r3, #10]
|
|
|
|
tx_bufer.pps1_adc = var.pps1_adc;
|
|
80065c4: 4b2e ldr r3, [pc, #184] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065c6: 899b ldrh r3, [r3, #12]
|
|
80065c8: b29a uxth r2, r3
|
|
80065ca: 4b2e ldr r3, [pc, #184] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065cc: 819a strh r2, [r3, #12]
|
|
tx_bufer.pps2_adc = var.pps2_adc;
|
|
80065ce: 4b2c ldr r3, [pc, #176] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065d0: 89db ldrh r3, [r3, #14]
|
|
80065d2: b29a uxth r2, r3
|
|
80065d4: 4b2b ldr r3, [pc, #172] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065d6: 81da strh r2, [r3, #14]
|
|
tx_bufer.tps1_adc = var.tps1_adc;
|
|
80065d8: 4b29 ldr r3, [pc, #164] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065da: 8a1b ldrh r3, [r3, #16]
|
|
80065dc: b29a uxth r2, r3
|
|
80065de: 4b29 ldr r3, [pc, #164] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065e0: 821a strh r2, [r3, #16]
|
|
tx_bufer.tps2_adc = var.tps2_adc;
|
|
80065e2: 4b27 ldr r3, [pc, #156] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065e4: 8a5b ldrh r3, [r3, #18]
|
|
80065e6: b29a uxth r2, r3
|
|
80065e8: 4b26 ldr r3, [pc, #152] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065ea: 825a strh r2, [r3, #18]
|
|
tx_bufer.motor_current_adc = var.motor_current_adc;
|
|
80065ec: 4b24 ldr r3, [pc, #144] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065ee: 8a9b ldrh r3, [r3, #20]
|
|
80065f0: b29a uxth r2, r3
|
|
80065f2: 4b24 ldr r3, [pc, #144] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065f4: 829a strh r2, [r3, #20]
|
|
tx_bufer.vbat_adc = var.vbat_adc;
|
|
80065f6: 4b22 ldr r3, [pc, #136] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
80065f8: 8adb ldrh r3, [r3, #22]
|
|
80065fa: b29a uxth r2, r3
|
|
80065fc: 4b21 ldr r3, [pc, #132] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
80065fe: 82da strh r2, [r3, #22]
|
|
|
|
tx_bufer.pps1 = var.pps1;
|
|
8006600: 4b1f ldr r3, [pc, #124] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006602: 8b1b ldrh r3, [r3, #24]
|
|
8006604: b21a sxth r2, r3
|
|
8006606: 4b1f ldr r3, [pc, #124] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006608: 831a strh r2, [r3, #24]
|
|
tx_bufer.pps2 = var.pps2;
|
|
800660a: 4b1d ldr r3, [pc, #116] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
800660c: 8b5b ldrh r3, [r3, #26]
|
|
800660e: b21a sxth r2, r3
|
|
8006610: 4b1c ldr r3, [pc, #112] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006612: 835a strh r2, [r3, #26]
|
|
tx_bufer.tps1 = var.tps1;
|
|
8006614: 4b1a ldr r3, [pc, #104] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006616: 8b9b ldrh r3, [r3, #28]
|
|
8006618: b21a sxth r2, r3
|
|
800661a: 4b1a ldr r3, [pc, #104] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
800661c: 839a strh r2, [r3, #28]
|
|
tx_bufer.tps2 = var.tps2;
|
|
800661e: 4b18 ldr r3, [pc, #96] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006620: 8bdb ldrh r3, [r3, #30]
|
|
8006622: b21a sxth r2, r3
|
|
8006624: 4b17 ldr r3, [pc, #92] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006626: 83da strh r2, [r3, #30]
|
|
tx_bufer.pps = var.pps;
|
|
8006628: 4b15 ldr r3, [pc, #84] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
800662a: 8c1b ldrh r3, [r3, #32]
|
|
800662c: b21a sxth r2, r3
|
|
800662e: 4b15 ldr r3, [pc, #84] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006630: 841a strh r2, [r3, #32]
|
|
tx_bufer.tps = var.tps;
|
|
8006632: 4b13 ldr r3, [pc, #76] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006634: 8c5b ldrh r3, [r3, #34] @ 0x22
|
|
8006636: b21a sxth r2, r3
|
|
8006638: 4b12 ldr r3, [pc, #72] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
800663a: 845a strh r2, [r3, #34] @ 0x22
|
|
tx_bufer.tps_error = var.tps_error;
|
|
800663c: 4b10 ldr r3, [pc, #64] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
800663e: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8006640: b21a sxth r2, r3
|
|
8006642: 4b10 ldr r3, [pc, #64] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006644: 849a strh r2, [r3, #36] @ 0x24
|
|
tx_bufer.motor_pwm = var.motor_pwm;
|
|
8006646: 4b0e ldr r3, [pc, #56] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006648: 8cdb ldrh r3, [r3, #38] @ 0x26
|
|
800664a: b21a sxth r2, r3
|
|
800664c: 4b0d ldr r3, [pc, #52] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
800664e: 84da strh r2, [r3, #38] @ 0x26
|
|
tx_bufer.idle_dc = var.idle_dc;
|
|
8006650: 4b0b ldr r3, [pc, #44] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006652: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8006654: b29a uxth r2, r3
|
|
8006656: 4b0b ldr r3, [pc, #44] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006658: 851a strh r2, [r3, #40] @ 0x28
|
|
tx_bufer.pps_delta = var.pps_delta;
|
|
800665a: 4b09 ldr r3, [pc, #36] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
800665c: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800665e: b21a sxth r2, r3
|
|
8006660: 4b08 ldr r3, [pc, #32] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006662: 855a strh r2, [r3, #42] @ 0x2a
|
|
tx_bufer.tps_delta = var.tps_delta;
|
|
8006664: 4b06 ldr r3, [pc, #24] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006666: 8d9b ldrh r3, [r3, #44] @ 0x2c
|
|
8006668: b21a sxth r2, r3
|
|
800666a: 4b06 ldr r3, [pc, #24] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
800666c: 859a strh r2, [r3, #44] @ 0x2c
|
|
tx_bufer.tps_target = var.tps_target;
|
|
800666e: 4b04 ldr r3, [pc, #16] @ (8006680 <Copy_Tx_Vars+0xf0>)
|
|
8006670: 8ddb ldrh r3, [r3, #46] @ 0x2e
|
|
8006672: b21a sxth r2, r3
|
|
8006674: 4b03 ldr r3, [pc, #12] @ (8006684 <Copy_Tx_Vars+0xf4>)
|
|
8006676: 85da strh r2, [r3, #46] @ 0x2e
|
|
}
|
|
8006678: 46c0 nop @ (mov r8, r8)
|
|
800667a: 46bd mov sp, r7
|
|
800667c: bd80 pop {r7, pc}
|
|
800667e: 46c0 nop @ (mov r8, r8)
|
|
8006680: 20000998 .word 0x20000998
|
|
8006684: 20000d78 .word 0x20000d78
|
|
|
|
08006688 <crc32>:
|
|
|
|
/**
|
|
* Online CRC calculator:
|
|
* http://www.zorc.breitbandkatze.de/crc.html
|
|
*/
|
|
uint32_t crc32(void *buf, uint32_t size) {
|
|
8006688: b580 push {r7, lr}
|
|
800668a: b082 sub sp, #8
|
|
800668c: af00 add r7, sp, #0
|
|
800668e: 6078 str r0, [r7, #4]
|
|
8006690: 6039 str r1, [r7, #0]
|
|
return crc32inc(buf, 0, size);
|
|
8006692: 683a ldr r2, [r7, #0]
|
|
8006694: 687b ldr r3, [r7, #4]
|
|
8006696: 2100 movs r1, #0
|
|
8006698: 0018 movs r0, r3
|
|
800669a: f000 f805 bl 80066a8 <crc32inc>
|
|
800669e: 0003 movs r3, r0
|
|
}
|
|
80066a0: 0018 movs r0, r3
|
|
80066a2: 46bd mov sp, r7
|
|
80066a4: b002 add sp, #8
|
|
80066a6: bd80 pop {r7, pc}
|
|
|
|
080066a8 <crc32inc>:
|
|
|
|
uint32_t crc32inc(void *buf, uint32_t crc, uint32_t size) {
|
|
80066a8: b580 push {r7, lr}
|
|
80066aa: b086 sub sp, #24
|
|
80066ac: af00 add r7, sp, #0
|
|
80066ae: 60f8 str r0, [r7, #12]
|
|
80066b0: 60b9 str r1, [r7, #8]
|
|
80066b2: 607a str r2, [r7, #4]
|
|
uint8_t *p;
|
|
|
|
p = (uint8_t*) buf;
|
|
80066b4: 68fb ldr r3, [r7, #12]
|
|
80066b6: 617b str r3, [r7, #20]
|
|
crc = crc ^ 0xFFFFFFFF;
|
|
80066b8: 68bb ldr r3, [r7, #8]
|
|
80066ba: 43db mvns r3, r3
|
|
80066bc: 60bb str r3, [r7, #8]
|
|
|
|
while (size--) {
|
|
80066be: e00f b.n 80066e0 <crc32inc+0x38>
|
|
crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
|
|
80066c0: 697b ldr r3, [r7, #20]
|
|
80066c2: 1c5a adds r2, r3, #1
|
|
80066c4: 617a str r2, [r7, #20]
|
|
80066c6: 781b ldrb r3, [r3, #0]
|
|
80066c8: 001a movs r2, r3
|
|
80066ca: 68bb ldr r3, [r7, #8]
|
|
80066cc: 4053 eors r3, r2
|
|
80066ce: 22ff movs r2, #255 @ 0xff
|
|
80066d0: 401a ands r2, r3
|
|
80066d2: 4b09 ldr r3, [pc, #36] @ (80066f8 <crc32inc+0x50>)
|
|
80066d4: 0092 lsls r2, r2, #2
|
|
80066d6: 58d2 ldr r2, [r2, r3]
|
|
80066d8: 68bb ldr r3, [r7, #8]
|
|
80066da: 0a1b lsrs r3, r3, #8
|
|
80066dc: 4053 eors r3, r2
|
|
80066de: 60bb str r3, [r7, #8]
|
|
while (size--) {
|
|
80066e0: 687b ldr r3, [r7, #4]
|
|
80066e2: 1e5a subs r2, r3, #1
|
|
80066e4: 607a str r2, [r7, #4]
|
|
80066e6: 2b00 cmp r3, #0
|
|
80066e8: d1ea bne.n 80066c0 <crc32inc+0x18>
|
|
}
|
|
|
|
return crc ^ 0xFFFFFFFF;
|
|
80066ea: 68bb ldr r3, [r7, #8]
|
|
80066ec: 43db mvns r3, r3
|
|
}
|
|
80066ee: 0018 movs r0, r3
|
|
80066f0: 46bd mov sp, r7
|
|
80066f2: b006 add sp, #24
|
|
80066f4: bd80 pop {r7, pc}
|
|
80066f6: 46c0 nop @ (mov r8, r8)
|
|
80066f8: 2000000c .word 0x2000000c
|
|
|
|
080066fc <Write_Config>:
|
|
|
|
void Write_Config(void) {
|
|
80066fc: b5b0 push {r4, r5, r7, lr}
|
|
80066fe: b088 sub sp, #32
|
|
8006700: af00 add r7, sp, #0
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8006702: b672 cpsid i
|
|
}
|
|
8006704: 46c0 nop @ (mov r8, r8)
|
|
__disable_irq();
|
|
uint32_t error;
|
|
FLASH_EraseInitTypeDef erase_pages;
|
|
erase_pages.NbPages = 2;
|
|
8006706: 003b movs r3, r7
|
|
8006708: 2202 movs r2, #2
|
|
800670a: 609a str r2, [r3, #8]
|
|
erase_pages.TypeErase = TYPEERASE_PAGES;
|
|
800670c: 003b movs r3, r7
|
|
800670e: 2200 movs r2, #0
|
|
8006710: 601a str r2, [r3, #0]
|
|
erase_pages.PageAddress = (uint32_t) &config_flash;
|
|
8006712: 4a23 ldr r2, [pc, #140] @ (80067a0 <Write_Config+0xa4>)
|
|
8006714: 003b movs r3, r7
|
|
8006716: 605a str r2, [r3, #4]
|
|
HAL_FLASH_Unlock();
|
|
8006718: f000 fc8a bl 8007030 <HAL_FLASH_Unlock>
|
|
HAL_FLASHEx_Erase(&erase_pages, &error);
|
|
800671c: 230c movs r3, #12
|
|
800671e: 18fa adds r2, r7, r3
|
|
8006720: 003b movs r3, r7
|
|
8006722: 0011 movs r1, r2
|
|
8006724: 0018 movs r0, r3
|
|
8006726: f000 fd43 bl 80071b0 <HAL_FLASHEx_Erase>
|
|
HAL_FLASH_Lock();
|
|
800672a: f000 fca7 bl 800707c <HAL_FLASH_Lock>
|
|
|
|
uint16_t num_wrt;
|
|
if (sizeof(config_t) & 0x0001)
|
|
num_wrt = (sizeof(config_t) << 1) + 1;
|
|
else
|
|
num_wrt = sizeof(config_t) << 1;
|
|
800672e: 2112 movs r1, #18
|
|
8006730: 187b adds r3, r7, r1
|
|
8006732: 22d6 movs r2, #214 @ 0xd6
|
|
8006734: 00d2 lsls r2, r2, #3
|
|
8006736: 801a strh r2, [r3, #0]
|
|
if (num_wrt > 2048)
|
|
8006738: 187b adds r3, r7, r1
|
|
800673a: 881a ldrh r2, [r3, #0]
|
|
800673c: 2380 movs r3, #128 @ 0x80
|
|
800673e: 011b lsls r3, r3, #4
|
|
8006740: 429a cmp r2, r3
|
|
8006742: d901 bls.n 8006748 <Write_Config+0x4c>
|
|
Error_Handler();
|
|
8006744: f7fe faec bl 8004d20 <Error_Handler>
|
|
|
|
HAL_FLASH_Unlock();
|
|
8006748: f000 fc72 bl 8007030 <HAL_FLASH_Unlock>
|
|
uint16_t *data, *flash_address;
|
|
data = (uint16_t*) &config_ram;
|
|
800674c: 4b15 ldr r3, [pc, #84] @ (80067a4 <Write_Config+0xa8>)
|
|
800674e: 61fb str r3, [r7, #28]
|
|
flash_address = (uint16_t*) &config_flash;
|
|
8006750: 4b13 ldr r3, [pc, #76] @ (80067a0 <Write_Config+0xa4>)
|
|
8006752: 61bb str r3, [r7, #24]
|
|
for (int i = 0; i < num_wrt; i++) {
|
|
8006754: 2300 movs r3, #0
|
|
8006756: 617b str r3, [r7, #20]
|
|
8006758: e013 b.n 8006782 <Write_Config+0x86>
|
|
HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, (uint32_t) flash_address,
|
|
800675a: 69b9 ldr r1, [r7, #24]
|
|
*data);
|
|
800675c: 69fb ldr r3, [r7, #28]
|
|
800675e: 881b ldrh r3, [r3, #0]
|
|
HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, (uint32_t) flash_address,
|
|
8006760: 001c movs r4, r3
|
|
8006762: 2300 movs r3, #0
|
|
8006764: 001d movs r5, r3
|
|
8006766: 0022 movs r2, r4
|
|
8006768: 002b movs r3, r5
|
|
800676a: 2001 movs r0, #1
|
|
800676c: f000 fbca bl 8006f04 <HAL_FLASH_Program>
|
|
data++;
|
|
8006770: 69fb ldr r3, [r7, #28]
|
|
8006772: 3302 adds r3, #2
|
|
8006774: 61fb str r3, [r7, #28]
|
|
flash_address++;
|
|
8006776: 69bb ldr r3, [r7, #24]
|
|
8006778: 3302 adds r3, #2
|
|
800677a: 61bb str r3, [r7, #24]
|
|
for (int i = 0; i < num_wrt; i++) {
|
|
800677c: 697b ldr r3, [r7, #20]
|
|
800677e: 3301 adds r3, #1
|
|
8006780: 617b str r3, [r7, #20]
|
|
8006782: 2312 movs r3, #18
|
|
8006784: 18fb adds r3, r7, r3
|
|
8006786: 881b ldrh r3, [r3, #0]
|
|
8006788: 697a ldr r2, [r7, #20]
|
|
800678a: 429a cmp r2, r3
|
|
800678c: dbe5 blt.n 800675a <Write_Config+0x5e>
|
|
}
|
|
HAL_FLASH_Lock();
|
|
800678e: f000 fc75 bl 800707c <HAL_FLASH_Lock>
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8006792: b662 cpsie i
|
|
}
|
|
8006794: 46c0 nop @ (mov r8, r8)
|
|
__enable_irq();
|
|
}
|
|
8006796: 46c0 nop @ (mov r8, r8)
|
|
8006798: 46bd mov sp, r7
|
|
800679a: b008 add sp, #32
|
|
800679c: bdb0 pop {r4, r5, r7, pc}
|
|
800679e: 46c0 nop @ (mov r8, r8)
|
|
80067a0: 0800f000 .word 0x0800f000
|
|
80067a4: 20000640 .word 0x20000640
|
|
|
|
080067a8 <TS_Comms_RX_Timeout>:
|
|
|
|
void TS_Comms_RX_Timeout(void) {
|
|
80067a8: b580 push {r7, lr}
|
|
80067aa: af00 add r7, sp, #0
|
|
if (RX.mode != IDLE) {
|
|
80067ac: 4b0c ldr r3, [pc, #48] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067ae: 781b ldrb r3, [r3, #0]
|
|
80067b0: 2b00 cmp r3, #0
|
|
80067b2: d011 beq.n 80067d8 <TS_Comms_RX_Timeout+0x30>
|
|
if (RX.timeout) {
|
|
80067b4: 4b0a ldr r3, [pc, #40] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067b6: 8a9b ldrh r3, [r3, #20]
|
|
80067b8: 2b00 cmp r3, #0
|
|
80067ba: d00d beq.n 80067d8 <TS_Comms_RX_Timeout+0x30>
|
|
RX.timeout--;
|
|
80067bc: 4b08 ldr r3, [pc, #32] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067be: 8a9b ldrh r3, [r3, #20]
|
|
80067c0: 3b01 subs r3, #1
|
|
80067c2: b29a uxth r2, r3
|
|
80067c4: 4b06 ldr r3, [pc, #24] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067c6: 829a strh r2, [r3, #20]
|
|
if (RX.timeout == 0) {
|
|
80067c8: 4b05 ldr r3, [pc, #20] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067ca: 8a9b ldrh r3, [r3, #20]
|
|
80067cc: 2b00 cmp r3, #0
|
|
80067ce: d103 bne.n 80067d8 <TS_Comms_RX_Timeout+0x30>
|
|
Comms_Reset(&RX);
|
|
80067d0: 4b03 ldr r3, [pc, #12] @ (80067e0 <TS_Comms_RX_Timeout+0x38>)
|
|
80067d2: 0018 movs r0, r3
|
|
80067d4: f7ff fc3e bl 8006054 <Comms_Reset>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
80067d8: 46c0 nop @ (mov r8, r8)
|
|
80067da: 46bd mov sp, r7
|
|
80067dc: bd80 pop {r7, pc}
|
|
80067de: 46c0 nop @ (mov r8, r8)
|
|
80067e0: 20000b34 .word 0x20000b34
|
|
|
|
080067e4 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
80067e4: 480d ldr r0, [pc, #52] @ (800681c <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
80067e6: 4685 mov sp, r0
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80067e8: 480d ldr r0, [pc, #52] @ (8006820 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
80067ea: 490e ldr r1, [pc, #56] @ (8006824 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
80067ec: 4a0e ldr r2, [pc, #56] @ (8006828 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
80067ee: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
80067f0: e002 b.n 80067f8 <LoopCopyDataInit>
|
|
|
|
080067f2 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
80067f2: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80067f4: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80067f6: 3304 adds r3, #4
|
|
|
|
080067f8 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80067f8: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80067fa: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80067fc: d3f9 bcc.n 80067f2 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80067fe: 4a0b ldr r2, [pc, #44] @ (800682c <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
8006800: 4c0b ldr r4, [pc, #44] @ (8006830 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
8006802: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8006804: e001 b.n 800680a <LoopFillZerobss>
|
|
|
|
08006806 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8006806: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8006808: 3204 adds r2, #4
|
|
|
|
0800680a <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
800680a: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
800680c: d3fb bcc.n 8006806 <FillZerobss>
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
bl SystemInit
|
|
800680e: f7ff fbab bl 8005f68 <SystemInit>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8006812: f002 f885 bl 8008920 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8006816: f7fd ffe7 bl 80047e8 <main>
|
|
|
|
0800681a <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
800681a: e7fe b.n 800681a <LoopForever>
|
|
ldr r0, =_estack
|
|
800681c: 20004000 .word 0x20004000
|
|
ldr r0, =_sdata
|
|
8006820: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8006824: 20000414 .word 0x20000414
|
|
ldr r2, =_sidata
|
|
8006828: 08008b28 .word 0x08008b28
|
|
ldr r2, =_sbss
|
|
800682c: 20000418 .word 0x20000418
|
|
ldr r4, =_ebss
|
|
8006830: 20000dd0 .word 0x20000dd0
|
|
|
|
08006834 <ADC1_COMP_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8006834: e7fe b.n 8006834 <ADC1_COMP_IRQHandler>
|
|
...
|
|
|
|
08006838 <HAL_Init>:
|
|
* In the default implementation,Systick is used as source of time base.
|
|
* The tick variable is incremented each 1ms in its ISR.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8006838: b580 push {r7, lr}
|
|
800683a: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch */
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
800683c: 4b07 ldr r3, [pc, #28] @ (800685c <HAL_Init+0x24>)
|
|
800683e: 681a ldr r2, [r3, #0]
|
|
8006840: 4b06 ldr r3, [pc, #24] @ (800685c <HAL_Init+0x24>)
|
|
8006842: 2110 movs r1, #16
|
|
8006844: 430a orrs r2, r1
|
|
8006846: 601a str r2, [r3, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8006848: 2000 movs r0, #0
|
|
800684a: f000 f809 bl 8006860 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
800684e: f7ff fa81 bl 8005d54 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006852: 2300 movs r3, #0
|
|
}
|
|
8006854: 0018 movs r0, r3
|
|
8006856: 46bd mov sp, r7
|
|
8006858: bd80 pop {r7, pc}
|
|
800685a: 46c0 nop @ (mov r8, r8)
|
|
800685c: 40022000 .word 0x40022000
|
|
|
|
08006860 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8006860: b590 push {r4, r7, lr}
|
|
8006862: b083 sub sp, #12
|
|
8006864: af00 add r7, sp, #0
|
|
8006866: 6078 str r0, [r7, #4]
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8006868: 4b14 ldr r3, [pc, #80] @ (80068bc <HAL_InitTick+0x5c>)
|
|
800686a: 681c ldr r4, [r3, #0]
|
|
800686c: 4b14 ldr r3, [pc, #80] @ (80068c0 <HAL_InitTick+0x60>)
|
|
800686e: 781b ldrb r3, [r3, #0]
|
|
8006870: 0019 movs r1, r3
|
|
8006872: 23fa movs r3, #250 @ 0xfa
|
|
8006874: 0098 lsls r0, r3, #2
|
|
8006876: f7f9 fc47 bl 8000108 <__udivsi3>
|
|
800687a: 0003 movs r3, r0
|
|
800687c: 0019 movs r1, r3
|
|
800687e: 0020 movs r0, r4
|
|
8006880: f7f9 fc42 bl 8000108 <__udivsi3>
|
|
8006884: 0003 movs r3, r0
|
|
8006886: 0018 movs r0, r3
|
|
8006888: f000 fb2f bl 8006eea <HAL_SYSTICK_Config>
|
|
800688c: 1e03 subs r3, r0, #0
|
|
800688e: d001 beq.n 8006894 <HAL_InitTick+0x34>
|
|
{
|
|
return HAL_ERROR;
|
|
8006890: 2301 movs r3, #1
|
|
8006892: e00f b.n 80068b4 <HAL_InitTick+0x54>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8006894: 687b ldr r3, [r7, #4]
|
|
8006896: 2b03 cmp r3, #3
|
|
8006898: d80b bhi.n 80068b2 <HAL_InitTick+0x52>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
800689a: 6879 ldr r1, [r7, #4]
|
|
800689c: 2301 movs r3, #1
|
|
800689e: 425b negs r3, r3
|
|
80068a0: 2200 movs r2, #0
|
|
80068a2: 0018 movs r0, r3
|
|
80068a4: f000 fb0c bl 8006ec0 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80068a8: 4b06 ldr r3, [pc, #24] @ (80068c4 <HAL_InitTick+0x64>)
|
|
80068aa: 687a ldr r2, [r7, #4]
|
|
80068ac: 601a str r2, [r3, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80068ae: 2300 movs r3, #0
|
|
80068b0: e000 b.n 80068b4 <HAL_InitTick+0x54>
|
|
return HAL_ERROR;
|
|
80068b2: 2301 movs r3, #1
|
|
}
|
|
80068b4: 0018 movs r0, r3
|
|
80068b6: 46bd mov sp, r7
|
|
80068b8: b003 add sp, #12
|
|
80068ba: bd90 pop {r4, r7, pc}
|
|
80068bc: 20000004 .word 0x20000004
|
|
80068c0: 20000410 .word 0x20000410
|
|
80068c4: 2000040c .word 0x2000040c
|
|
|
|
080068c8 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80068c8: b580 push {r7, lr}
|
|
80068ca: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80068cc: 4b05 ldr r3, [pc, #20] @ (80068e4 <HAL_IncTick+0x1c>)
|
|
80068ce: 781b ldrb r3, [r3, #0]
|
|
80068d0: 001a movs r2, r3
|
|
80068d2: 4b05 ldr r3, [pc, #20] @ (80068e8 <HAL_IncTick+0x20>)
|
|
80068d4: 681b ldr r3, [r3, #0]
|
|
80068d6: 18d2 adds r2, r2, r3
|
|
80068d8: 4b03 ldr r3, [pc, #12] @ (80068e8 <HAL_IncTick+0x20>)
|
|
80068da: 601a str r2, [r3, #0]
|
|
}
|
|
80068dc: 46c0 nop @ (mov r8, r8)
|
|
80068de: 46bd mov sp, r7
|
|
80068e0: bd80 pop {r7, pc}
|
|
80068e2: 46c0 nop @ (mov r8, r8)
|
|
80068e4: 20000410 .word 0x20000410
|
|
80068e8: 20000dac .word 0x20000dac
|
|
|
|
080068ec <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80068ec: b580 push {r7, lr}
|
|
80068ee: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80068f0: 4b02 ldr r3, [pc, #8] @ (80068fc <HAL_GetTick+0x10>)
|
|
80068f2: 681b ldr r3, [r3, #0]
|
|
}
|
|
80068f4: 0018 movs r0, r3
|
|
80068f6: 46bd mov sp, r7
|
|
80068f8: bd80 pop {r7, pc}
|
|
80068fa: 46c0 nop @ (mov r8, r8)
|
|
80068fc: 20000dac .word 0x20000dac
|
|
|
|
08006900 <HAL_ADC_Init>:
|
|
* of structure "ADC_InitTypeDef".
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8006900: b580 push {r7, lr}
|
|
8006902: b084 sub sp, #16
|
|
8006904: af00 add r7, sp, #0
|
|
8006906: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8006908: 230f movs r3, #15
|
|
800690a: 18fb adds r3, r7, r3
|
|
800690c: 2200 movs r2, #0
|
|
800690e: 701a strb r2, [r3, #0]
|
|
uint32_t tmpCFGR1 = 0U;
|
|
8006910: 2300 movs r3, #0
|
|
8006912: 60bb str r3, [r7, #8]
|
|
|
|
/* Check ADC handle */
|
|
if(hadc == NULL)
|
|
8006914: 687b ldr r3, [r7, #4]
|
|
8006916: 2b00 cmp r3, #0
|
|
8006918: d101 bne.n 800691e <HAL_ADC_Init+0x1e>
|
|
{
|
|
return HAL_ERROR;
|
|
800691a: 2301 movs r3, #1
|
|
800691c: e125 b.n 8006b6a <HAL_ADC_Init+0x26a>
|
|
/* Refer to header of this file for more details on clock enabling procedure*/
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
/* - ADC voltage regulator enable */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
800691e: 687b ldr r3, [r7, #4]
|
|
8006920: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006922: 2b00 cmp r3, #0
|
|
8006924: d10a bne.n 800693c <HAL_ADC_Init+0x3c>
|
|
{
|
|
/* Initialize ADC error code */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8006926: 687b ldr r3, [r7, #4]
|
|
8006928: 2200 movs r2, #0
|
|
800692a: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
800692c: 687b ldr r3, [r7, #4]
|
|
800692e: 2234 movs r2, #52 @ 0x34
|
|
8006930: 2100 movs r1, #0
|
|
8006932: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
8006934: 687b ldr r3, [r7, #4]
|
|
8006936: 0018 movs r0, r3
|
|
8006938: f7ff fa30 bl 8005d9c <HAL_ADC_MspInit>
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed. */
|
|
/* and if there is no conversion on going on regular group (ADC can be */
|
|
/* enabled anyway, in case of call of this function to update a parameter */
|
|
/* on the fly). */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
|
|
800693c: 687b ldr r3, [r7, #4]
|
|
800693e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006940: 2210 movs r2, #16
|
|
8006942: 4013 ands r3, r2
|
|
8006944: d000 beq.n 8006948 <HAL_ADC_Init+0x48>
|
|
8006946: e103 b.n 8006b50 <HAL_ADC_Init+0x250>
|
|
8006948: 230f movs r3, #15
|
|
800694a: 18fb adds r3, r7, r3
|
|
800694c: 781b ldrb r3, [r3, #0]
|
|
800694e: 2b00 cmp r3, #0
|
|
8006950: d000 beq.n 8006954 <HAL_ADC_Init+0x54>
|
|
8006952: e0fd b.n 8006b50 <HAL_ADC_Init+0x250>
|
|
(tmp_hal_status == HAL_OK) &&
|
|
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
|
|
8006954: 687b ldr r3, [r7, #4]
|
|
8006956: 681b ldr r3, [r3, #0]
|
|
8006958: 689b ldr r3, [r3, #8]
|
|
800695a: 2204 movs r2, #4
|
|
800695c: 4013 ands r3, r2
|
|
(tmp_hal_status == HAL_OK) &&
|
|
800695e: d000 beq.n 8006962 <HAL_ADC_Init+0x62>
|
|
8006960: e0f6 b.n 8006b50 <HAL_ADC_Init+0x250>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8006962: 687b ldr r3, [r7, #4]
|
|
8006964: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006966: 4a83 ldr r2, [pc, #524] @ (8006b74 <HAL_ADC_Init+0x274>)
|
|
8006968: 4013 ands r3, r2
|
|
800696a: 2202 movs r2, #2
|
|
800696c: 431a orrs r2, r3
|
|
800696e: 687b ldr r3, [r7, #4]
|
|
8006970: 639a str r2, [r3, #56] @ 0x38
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - ADC clock mode */
|
|
/* - ADC clock prescaler */
|
|
/* - ADC resolution */
|
|
if (ADC_IS_ENABLE(hadc) == RESET)
|
|
8006972: 687b ldr r3, [r7, #4]
|
|
8006974: 681b ldr r3, [r3, #0]
|
|
8006976: 689b ldr r3, [r3, #8]
|
|
8006978: 2203 movs r2, #3
|
|
800697a: 4013 ands r3, r2
|
|
800697c: 2b01 cmp r3, #1
|
|
800697e: d112 bne.n 80069a6 <HAL_ADC_Init+0xa6>
|
|
8006980: 687b ldr r3, [r7, #4]
|
|
8006982: 681b ldr r3, [r3, #0]
|
|
8006984: 681b ldr r3, [r3, #0]
|
|
8006986: 2201 movs r2, #1
|
|
8006988: 4013 ands r3, r2
|
|
800698a: 2b01 cmp r3, #1
|
|
800698c: d009 beq.n 80069a2 <HAL_ADC_Init+0xa2>
|
|
800698e: 687b ldr r3, [r7, #4]
|
|
8006990: 681b ldr r3, [r3, #0]
|
|
8006992: 68da ldr r2, [r3, #12]
|
|
8006994: 2380 movs r3, #128 @ 0x80
|
|
8006996: 021b lsls r3, r3, #8
|
|
8006998: 401a ands r2, r3
|
|
800699a: 2380 movs r3, #128 @ 0x80
|
|
800699c: 021b lsls r3, r3, #8
|
|
800699e: 429a cmp r2, r3
|
|
80069a0: d101 bne.n 80069a6 <HAL_ADC_Init+0xa6>
|
|
80069a2: 2301 movs r3, #1
|
|
80069a4: e000 b.n 80069a8 <HAL_ADC_Init+0xa8>
|
|
80069a6: 2300 movs r3, #0
|
|
80069a8: 2b00 cmp r3, #0
|
|
80069aa: d116 bne.n 80069da <HAL_ADC_Init+0xda>
|
|
/* parameters): */
|
|
/* - internal measurement paths: Vbat, temperature sensor, Vref */
|
|
/* (set into HAL_ADC_ConfigChannel() ) */
|
|
|
|
/* Configuration of ADC resolution */
|
|
MODIFY_REG(hadc->Instance->CFGR1,
|
|
80069ac: 687b ldr r3, [r7, #4]
|
|
80069ae: 681b ldr r3, [r3, #0]
|
|
80069b0: 68db ldr r3, [r3, #12]
|
|
80069b2: 2218 movs r2, #24
|
|
80069b4: 4393 bics r3, r2
|
|
80069b6: 0019 movs r1, r3
|
|
80069b8: 687b ldr r3, [r7, #4]
|
|
80069ba: 689a ldr r2, [r3, #8]
|
|
80069bc: 687b ldr r3, [r7, #4]
|
|
80069be: 681b ldr r3, [r3, #0]
|
|
80069c0: 430a orrs r2, r1
|
|
80069c2: 60da str r2, [r3, #12]
|
|
ADC_CFGR1_RES ,
|
|
hadc->Init.Resolution );
|
|
|
|
/* Configuration of ADC clock mode: clock source AHB or HSI with */
|
|
/* selectable prescaler */
|
|
MODIFY_REG(hadc->Instance->CFGR2 ,
|
|
80069c4: 687b ldr r3, [r7, #4]
|
|
80069c6: 681b ldr r3, [r3, #0]
|
|
80069c8: 691b ldr r3, [r3, #16]
|
|
80069ca: 009b lsls r3, r3, #2
|
|
80069cc: 0899 lsrs r1, r3, #2
|
|
80069ce: 687b ldr r3, [r7, #4]
|
|
80069d0: 685a ldr r2, [r3, #4]
|
|
80069d2: 687b ldr r3, [r7, #4]
|
|
80069d4: 681b ldr r3, [r3, #0]
|
|
80069d6: 430a orrs r2, r1
|
|
80069d8: 611a str r2, [r3, #16]
|
|
/* - external trigger polarity */
|
|
/* - data alignment */
|
|
/* - resolution */
|
|
/* - scan direction */
|
|
/* - DMA continuous request */
|
|
hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN |
|
|
80069da: 687b ldr r3, [r7, #4]
|
|
80069dc: 681b ldr r3, [r3, #0]
|
|
80069de: 68da ldr r2, [r3, #12]
|
|
80069e0: 687b ldr r3, [r7, #4]
|
|
80069e2: 681b ldr r3, [r3, #0]
|
|
80069e4: 4964 ldr r1, [pc, #400] @ (8006b78 <HAL_ADC_Init+0x278>)
|
|
80069e6: 400a ands r2, r1
|
|
80069e8: 60da str r2, [r3, #12]
|
|
ADC_CFGR1_EXTEN |
|
|
ADC_CFGR1_ALIGN |
|
|
ADC_CFGR1_SCANDIR |
|
|
ADC_CFGR1_DMACFG );
|
|
|
|
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
80069ea: 687b ldr r3, [r7, #4]
|
|
80069ec: 7e1b ldrb r3, [r3, #24]
|
|
80069ee: 039a lsls r2, r3, #14
|
|
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
|
|
80069f0: 687b ldr r3, [r7, #4]
|
|
80069f2: 7e5b ldrb r3, [r3, #25]
|
|
80069f4: 03db lsls r3, r3, #15
|
|
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
80069f6: 431a orrs r2, r3
|
|
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
80069f8: 687b ldr r3, [r7, #4]
|
|
80069fa: 7e9b ldrb r3, [r3, #26]
|
|
80069fc: 035b lsls r3, r3, #13
|
|
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
|
|
80069fe: 431a orrs r2, r3
|
|
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
|
|
8006a00: 687b ldr r3, [r7, #4]
|
|
8006a02: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006a04: 2b01 cmp r3, #1
|
|
8006a06: d002 beq.n 8006a0e <HAL_ADC_Init+0x10e>
|
|
8006a08: 2380 movs r3, #128 @ 0x80
|
|
8006a0a: 015b lsls r3, r3, #5
|
|
8006a0c: e000 b.n 8006a10 <HAL_ADC_Init+0x110>
|
|
8006a0e: 2300 movs r3, #0
|
|
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8006a10: 431a orrs r2, r3
|
|
hadc->Init.DataAlign |
|
|
8006a12: 687b ldr r3, [r7, #4]
|
|
8006a14: 68db ldr r3, [r3, #12]
|
|
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
|
|
8006a16: 431a orrs r2, r3
|
|
ADC_SCANDIR(hadc->Init.ScanConvMode) |
|
|
8006a18: 687b ldr r3, [r7, #4]
|
|
8006a1a: 691b ldr r3, [r3, #16]
|
|
8006a1c: 2b02 cmp r3, #2
|
|
8006a1e: d101 bne.n 8006a24 <HAL_ADC_Init+0x124>
|
|
8006a20: 2304 movs r3, #4
|
|
8006a22: e000 b.n 8006a26 <HAL_ADC_Init+0x126>
|
|
8006a24: 2300 movs r3, #0
|
|
hadc->Init.DataAlign |
|
|
8006a26: 431a orrs r2, r3
|
|
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
|
|
8006a28: 687b ldr r3, [r7, #4]
|
|
8006a2a: 2124 movs r1, #36 @ 0x24
|
|
8006a2c: 5c5b ldrb r3, [r3, r1]
|
|
8006a2e: 005b lsls r3, r3, #1
|
|
ADC_SCANDIR(hadc->Init.ScanConvMode) |
|
|
8006a30: 4313 orrs r3, r2
|
|
tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
8006a32: 68ba ldr r2, [r7, #8]
|
|
8006a34: 4313 orrs r3, r2
|
|
8006a36: 60bb str r3, [r7, #8]
|
|
|
|
/* Enable discontinuous mode only if continuous mode is disabled */
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
8006a38: 687b ldr r3, [r7, #4]
|
|
8006a3a: 7edb ldrb r3, [r3, #27]
|
|
8006a3c: 2b01 cmp r3, #1
|
|
8006a3e: d115 bne.n 8006a6c <HAL_ADC_Init+0x16c>
|
|
{
|
|
if (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8006a40: 687b ldr r3, [r7, #4]
|
|
8006a42: 7e9b ldrb r3, [r3, #26]
|
|
8006a44: 2b00 cmp r3, #0
|
|
8006a46: d105 bne.n 8006a54 <HAL_ADC_Init+0x154>
|
|
{
|
|
/* Enable the selected ADC group regular discontinuous mode */
|
|
tmpCFGR1 |= ADC_CFGR1_DISCEN;
|
|
8006a48: 68bb ldr r3, [r7, #8]
|
|
8006a4a: 2280 movs r2, #128 @ 0x80
|
|
8006a4c: 0252 lsls r2, r2, #9
|
|
8006a4e: 4313 orrs r3, r2
|
|
8006a50: 60bb str r3, [r7, #8]
|
|
8006a52: e00b b.n 8006a6c <HAL_ADC_Init+0x16c>
|
|
/* ADC regular group discontinuous was intended to be enabled, */
|
|
/* but ADC regular group modes continuous and sequencer discontinuous */
|
|
/* cannot be enabled simultaneously. */
|
|
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8006a54: 687b ldr r3, [r7, #4]
|
|
8006a56: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006a58: 2220 movs r2, #32
|
|
8006a5a: 431a orrs r2, r3
|
|
8006a5c: 687b ldr r3, [r7, #4]
|
|
8006a5e: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8006a60: 687b ldr r3, [r7, #4]
|
|
8006a62: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006a64: 2201 movs r2, #1
|
|
8006a66: 431a orrs r2, r3
|
|
8006a68: 687b ldr r3, [r7, #4]
|
|
8006a6a: 63da str r2, [r3, #60] @ 0x3c
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
8006a6c: 687b ldr r3, [r7, #4]
|
|
8006a6e: 69da ldr r2, [r3, #28]
|
|
8006a70: 23c2 movs r3, #194 @ 0xc2
|
|
8006a72: 33ff adds r3, #255 @ 0xff
|
|
8006a74: 429a cmp r2, r3
|
|
8006a76: d007 beq.n 8006a88 <HAL_ADC_Init+0x188>
|
|
{
|
|
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
|
|
8006a78: 687b ldr r3, [r7, #4]
|
|
8006a7a: 69da ldr r2, [r3, #28]
|
|
hadc->Init.ExternalTrigConvEdge );
|
|
8006a7c: 687b ldr r3, [r7, #4]
|
|
8006a7e: 6a1b ldr r3, [r3, #32]
|
|
tmpCFGR1 |= ( hadc->Init.ExternalTrigConv |
|
|
8006a80: 4313 orrs r3, r2
|
|
8006a82: 68ba ldr r2, [r7, #8]
|
|
8006a84: 4313 orrs r3, r2
|
|
8006a86: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
/* Update ADC configuration register with previous settings */
|
|
hadc->Instance->CFGR1 |= tmpCFGR1;
|
|
8006a88: 687b ldr r3, [r7, #4]
|
|
8006a8a: 681b ldr r3, [r3, #0]
|
|
8006a8c: 68d9 ldr r1, [r3, #12]
|
|
8006a8e: 687b ldr r3, [r7, #4]
|
|
8006a90: 681b ldr r3, [r3, #0]
|
|
8006a92: 68ba ldr r2, [r7, #8]
|
|
8006a94: 430a orrs r2, r1
|
|
8006a96: 60da str r2, [r3, #12]
|
|
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
|
|
/* (obsolete): sampling time set in this function if parameter */
|
|
/* "SamplingTimeCommon" has been set to a valid sampling time. */
|
|
/* Otherwise, sampling time is set into ADC channel initialization */
|
|
/* structure with parameter "SamplingTime" (obsolete). */
|
|
if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
|
|
8006a98: 687b ldr r3, [r7, #4]
|
|
8006a9a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006a9c: 2380 movs r3, #128 @ 0x80
|
|
8006a9e: 055b lsls r3, r3, #21
|
|
8006aa0: 429a cmp r2, r3
|
|
8006aa2: d01b beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006aa4: 687b ldr r3, [r7, #4]
|
|
8006aa6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006aa8: 2b01 cmp r3, #1
|
|
8006aaa: d017 beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006aac: 687b ldr r3, [r7, #4]
|
|
8006aae: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ab0: 2b02 cmp r3, #2
|
|
8006ab2: d013 beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006ab4: 687b ldr r3, [r7, #4]
|
|
8006ab6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ab8: 2b03 cmp r3, #3
|
|
8006aba: d00f beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006abc: 687b ldr r3, [r7, #4]
|
|
8006abe: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ac0: 2b04 cmp r3, #4
|
|
8006ac2: d00b beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006ac4: 687b ldr r3, [r7, #4]
|
|
8006ac6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ac8: 2b05 cmp r3, #5
|
|
8006aca: d007 beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006acc: 687b ldr r3, [r7, #4]
|
|
8006ace: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ad0: 2b06 cmp r3, #6
|
|
8006ad2: d003 beq.n 8006adc <HAL_ADC_Init+0x1dc>
|
|
8006ad4: 687b ldr r3, [r7, #4]
|
|
8006ad6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ad8: 2b07 cmp r3, #7
|
|
8006ada: d112 bne.n 8006b02 <HAL_ADC_Init+0x202>
|
|
{
|
|
/* Channel sampling time configuration */
|
|
/* Clear the old sample time */
|
|
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
|
|
8006adc: 687b ldr r3, [r7, #4]
|
|
8006ade: 681b ldr r3, [r3, #0]
|
|
8006ae0: 695a ldr r2, [r3, #20]
|
|
8006ae2: 687b ldr r3, [r7, #4]
|
|
8006ae4: 681b ldr r3, [r3, #0]
|
|
8006ae6: 2107 movs r1, #7
|
|
8006ae8: 438a bics r2, r1
|
|
8006aea: 615a str r2, [r3, #20]
|
|
|
|
/* Set the new sample time */
|
|
hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
|
|
8006aec: 687b ldr r3, [r7, #4]
|
|
8006aee: 681b ldr r3, [r3, #0]
|
|
8006af0: 6959 ldr r1, [r3, #20]
|
|
8006af2: 687b ldr r3, [r7, #4]
|
|
8006af4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006af6: 2207 movs r2, #7
|
|
8006af8: 401a ands r2, r3
|
|
8006afa: 687b ldr r3, [r7, #4]
|
|
8006afc: 681b ldr r3, [r3, #0]
|
|
8006afe: 430a orrs r2, r1
|
|
8006b00: 615a str r2, [r3, #20]
|
|
/* Check back that ADC registers have effectively been configured to */
|
|
/* ensure of no potential problem of ADC core IP clocking. */
|
|
/* Check through register CFGR1 (excluding analog watchdog configuration: */
|
|
/* set into separate dedicated function, and bits of ADC resolution set */
|
|
/* out of temporary variable 'tmpCFGR1'). */
|
|
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
|
|
8006b02: 687b ldr r3, [r7, #4]
|
|
8006b04: 681b ldr r3, [r3, #0]
|
|
8006b06: 68db ldr r3, [r3, #12]
|
|
8006b08: 4a1c ldr r2, [pc, #112] @ (8006b7c <HAL_ADC_Init+0x27c>)
|
|
8006b0a: 4013 ands r3, r2
|
|
8006b0c: 68ba ldr r2, [r7, #8]
|
|
8006b0e: 429a cmp r2, r3
|
|
8006b10: d10b bne.n 8006b2a <HAL_ADC_Init+0x22a>
|
|
== tmpCFGR1)
|
|
{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8006b12: 687b ldr r3, [r7, #4]
|
|
8006b14: 2200 movs r2, #0
|
|
8006b16: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8006b18: 687b ldr r3, [r7, #4]
|
|
8006b1a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006b1c: 2203 movs r2, #3
|
|
8006b1e: 4393 bics r3, r2
|
|
8006b20: 2201 movs r2, #1
|
|
8006b22: 431a orrs r2, r3
|
|
8006b24: 687b ldr r3, [r7, #4]
|
|
8006b26: 639a str r2, [r3, #56] @ 0x38
|
|
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
|
|
8006b28: e01c b.n 8006b64 <HAL_ADC_Init+0x264>
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8006b2a: 687b ldr r3, [r7, #4]
|
|
8006b2c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006b2e: 2212 movs r2, #18
|
|
8006b30: 4393 bics r3, r2
|
|
8006b32: 2210 movs r2, #16
|
|
8006b34: 431a orrs r2, r3
|
|
8006b36: 687b ldr r3, [r7, #4]
|
|
8006b38: 639a str r2, [r3, #56] @ 0x38
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8006b3a: 687b ldr r3, [r7, #4]
|
|
8006b3c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006b3e: 2201 movs r2, #1
|
|
8006b40: 431a orrs r2, r3
|
|
8006b42: 687b ldr r3, [r7, #4]
|
|
8006b44: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8006b46: 230f movs r3, #15
|
|
8006b48: 18fb adds r3, r7, r3
|
|
8006b4a: 2201 movs r2, #1
|
|
8006b4c: 701a strb r2, [r3, #0]
|
|
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
|
|
8006b4e: e009 b.n 8006b64 <HAL_ADC_Init+0x264>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8006b50: 687b ldr r3, [r7, #4]
|
|
8006b52: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006b54: 2210 movs r2, #16
|
|
8006b56: 431a orrs r2, r3
|
|
8006b58: 687b ldr r3, [r7, #4]
|
|
8006b5a: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8006b5c: 230f movs r3, #15
|
|
8006b5e: 18fb adds r3, r7, r3
|
|
8006b60: 2201 movs r2, #1
|
|
8006b62: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8006b64: 230f movs r3, #15
|
|
8006b66: 18fb adds r3, r7, r3
|
|
8006b68: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8006b6a: 0018 movs r0, r3
|
|
8006b6c: 46bd mov sp, r7
|
|
8006b6e: b004 add sp, #16
|
|
8006b70: bd80 pop {r7, pc}
|
|
8006b72: 46c0 nop @ (mov r8, r8)
|
|
8006b74: fffffefd .word 0xfffffefd
|
|
8006b78: fffe0219 .word 0xfffe0219
|
|
8006b7c: 833fffe7 .word 0x833fffe7
|
|
|
|
08006b80 <HAL_ADC_ConfigChannel>:
|
|
* @param hadc ADC handle
|
|
* @param sConfig Structure of ADC channel for regular group.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
|
{
|
|
8006b80: b580 push {r7, lr}
|
|
8006b82: b084 sub sp, #16
|
|
8006b84: af00 add r7, sp, #0
|
|
8006b86: 6078 str r0, [r7, #4]
|
|
8006b88: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8006b8a: 230f movs r3, #15
|
|
8006b8c: 18fb adds r3, r7, r3
|
|
8006b8e: 2200 movs r2, #0
|
|
8006b90: 701a strb r2, [r3, #0]
|
|
__IO uint32_t wait_loop_index = 0U;
|
|
8006b92: 2300 movs r3, #0
|
|
8006b94: 60bb str r3, [r7, #8]
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
|
|
assert_param(IS_ADC_RANK(sConfig->Rank));
|
|
|
|
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
|
|
8006b96: 687b ldr r3, [r7, #4]
|
|
8006b98: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006b9a: 2380 movs r3, #128 @ 0x80
|
|
8006b9c: 055b lsls r3, r3, #21
|
|
8006b9e: 429a cmp r2, r3
|
|
8006ba0: d011 beq.n 8006bc6 <HAL_ADC_ConfigChannel+0x46>
|
|
8006ba2: 687b ldr r3, [r7, #4]
|
|
8006ba4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006ba6: 2b01 cmp r3, #1
|
|
8006ba8: d00d beq.n 8006bc6 <HAL_ADC_ConfigChannel+0x46>
|
|
8006baa: 687b ldr r3, [r7, #4]
|
|
8006bac: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006bae: 2b02 cmp r3, #2
|
|
8006bb0: d009 beq.n 8006bc6 <HAL_ADC_ConfigChannel+0x46>
|
|
8006bb2: 687b ldr r3, [r7, #4]
|
|
8006bb4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006bb6: 2b03 cmp r3, #3
|
|
8006bb8: d005 beq.n 8006bc6 <HAL_ADC_ConfigChannel+0x46>
|
|
8006bba: 687b ldr r3, [r7, #4]
|
|
8006bbc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006bbe: 2b04 cmp r3, #4
|
|
8006bc0: d001 beq.n 8006bc6 <HAL_ADC_ConfigChannel+0x46>
|
|
8006bc2: 687b ldr r3, [r7, #4]
|
|
8006bc4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
{
|
|
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8006bc6: 687b ldr r3, [r7, #4]
|
|
8006bc8: 2234 movs r2, #52 @ 0x34
|
|
8006bca: 5c9b ldrb r3, [r3, r2]
|
|
8006bcc: 2b01 cmp r3, #1
|
|
8006bce: d101 bne.n 8006bd4 <HAL_ADC_ConfigChannel+0x54>
|
|
8006bd0: 2302 movs r3, #2
|
|
8006bd2: e0d0 b.n 8006d76 <HAL_ADC_ConfigChannel+0x1f6>
|
|
8006bd4: 687b ldr r3, [r7, #4]
|
|
8006bd6: 2234 movs r2, #52 @ 0x34
|
|
8006bd8: 2101 movs r1, #1
|
|
8006bda: 5499 strb r1, [r3, r2]
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel number */
|
|
/* - Channel sampling time */
|
|
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
|
|
8006bdc: 687b ldr r3, [r7, #4]
|
|
8006bde: 681b ldr r3, [r3, #0]
|
|
8006be0: 689b ldr r3, [r3, #8]
|
|
8006be2: 2204 movs r2, #4
|
|
8006be4: 4013 ands r3, r2
|
|
8006be6: d000 beq.n 8006bea <HAL_ADC_ConfigChannel+0x6a>
|
|
8006be8: e0b4 b.n 8006d54 <HAL_ADC_ConfigChannel+0x1d4>
|
|
{
|
|
/* Configure channel: depending on rank setting, add it or remove it from */
|
|
/* ADC conversion sequencer. */
|
|
if (sConfig->Rank != ADC_RANK_NONE)
|
|
8006bea: 683b ldr r3, [r7, #0]
|
|
8006bec: 685b ldr r3, [r3, #4]
|
|
8006bee: 4a64 ldr r2, [pc, #400] @ (8006d80 <HAL_ADC_ConfigChannel+0x200>)
|
|
8006bf0: 4293 cmp r3, r2
|
|
8006bf2: d100 bne.n 8006bf6 <HAL_ADC_ConfigChannel+0x76>
|
|
8006bf4: e082 b.n 8006cfc <HAL_ADC_ConfigChannel+0x17c>
|
|
{
|
|
/* Regular sequence configuration */
|
|
/* Set the channel selection register from the selected channel */
|
|
hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
|
|
8006bf6: 687b ldr r3, [r7, #4]
|
|
8006bf8: 681b ldr r3, [r3, #0]
|
|
8006bfa: 6a99 ldr r1, [r3, #40] @ 0x28
|
|
8006bfc: 683b ldr r3, [r7, #0]
|
|
8006bfe: 681b ldr r3, [r3, #0]
|
|
8006c00: 2201 movs r2, #1
|
|
8006c02: 409a lsls r2, r3
|
|
8006c04: 687b ldr r3, [r7, #4]
|
|
8006c06: 681b ldr r3, [r3, #0]
|
|
8006c08: 430a orrs r2, r1
|
|
8006c0a: 629a str r2, [r3, #40] @ 0x28
|
|
/* Channel sampling time configuration */
|
|
/* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
|
|
/* (obsolete): sampling time set in this function with */
|
|
/* parameter "SamplingTime" (obsolete) only if not already set into */
|
|
/* ADC initialization structure with parameter "SamplingTimeCommon". */
|
|
if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
|
|
8006c0c: 687b ldr r3, [r7, #4]
|
|
8006c0e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006c10: 2380 movs r3, #128 @ 0x80
|
|
8006c12: 055b lsls r3, r3, #21
|
|
8006c14: 429a cmp r2, r3
|
|
8006c16: d037 beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c18: 687b ldr r3, [r7, #4]
|
|
8006c1a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c1c: 2b01 cmp r3, #1
|
|
8006c1e: d033 beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c20: 687b ldr r3, [r7, #4]
|
|
8006c22: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c24: 2b02 cmp r3, #2
|
|
8006c26: d02f beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c28: 687b ldr r3, [r7, #4]
|
|
8006c2a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c2c: 2b03 cmp r3, #3
|
|
8006c2e: d02b beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c30: 687b ldr r3, [r7, #4]
|
|
8006c32: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c34: 2b04 cmp r3, #4
|
|
8006c36: d027 beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c38: 687b ldr r3, [r7, #4]
|
|
8006c3a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c3c: 2b05 cmp r3, #5
|
|
8006c3e: d023 beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c40: 687b ldr r3, [r7, #4]
|
|
8006c42: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c44: 2b06 cmp r3, #6
|
|
8006c46: d01f beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
8006c48: 687b ldr r3, [r7, #4]
|
|
8006c4a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006c4c: 2b07 cmp r3, #7
|
|
8006c4e: d01b beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
{
|
|
/* Modify sampling time if needed (not needed in case of reoccurrence */
|
|
/* for several channels programmed consecutively into the sequencer) */
|
|
if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
|
|
8006c50: 683b ldr r3, [r7, #0]
|
|
8006c52: 689a ldr r2, [r3, #8]
|
|
8006c54: 687b ldr r3, [r7, #4]
|
|
8006c56: 681b ldr r3, [r3, #0]
|
|
8006c58: 695b ldr r3, [r3, #20]
|
|
8006c5a: 2107 movs r1, #7
|
|
8006c5c: 400b ands r3, r1
|
|
8006c5e: 429a cmp r2, r3
|
|
8006c60: d012 beq.n 8006c88 <HAL_ADC_ConfigChannel+0x108>
|
|
{
|
|
/* Channel sampling time configuration */
|
|
/* Clear the old sample time */
|
|
hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
|
|
8006c62: 687b ldr r3, [r7, #4]
|
|
8006c64: 681b ldr r3, [r3, #0]
|
|
8006c66: 695a ldr r2, [r3, #20]
|
|
8006c68: 687b ldr r3, [r7, #4]
|
|
8006c6a: 681b ldr r3, [r3, #0]
|
|
8006c6c: 2107 movs r1, #7
|
|
8006c6e: 438a bics r2, r1
|
|
8006c70: 615a str r2, [r3, #20]
|
|
|
|
/* Set the new sample time */
|
|
hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
|
|
8006c72: 687b ldr r3, [r7, #4]
|
|
8006c74: 681b ldr r3, [r3, #0]
|
|
8006c76: 6959 ldr r1, [r3, #20]
|
|
8006c78: 683b ldr r3, [r7, #0]
|
|
8006c7a: 689b ldr r3, [r3, #8]
|
|
8006c7c: 2207 movs r2, #7
|
|
8006c7e: 401a ands r2, r3
|
|
8006c80: 687b ldr r3, [r7, #4]
|
|
8006c82: 681b ldr r3, [r3, #0]
|
|
8006c84: 430a orrs r2, r1
|
|
8006c86: 615a str r2, [r3, #20]
|
|
/* internal measurement paths enable: If internal channel selected, */
|
|
/* enable dedicated internal buffers and path. */
|
|
/* Note: these internal measurement paths can be disabled using */
|
|
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
|
|
/* channel configuration parameter "Rank". */
|
|
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
|
8006c88: 683b ldr r3, [r7, #0]
|
|
8006c8a: 681b ldr r3, [r3, #0]
|
|
8006c8c: 2b10 cmp r3, #16
|
|
8006c8e: d007 beq.n 8006ca0 <HAL_ADC_ConfigChannel+0x120>
|
|
8006c90: 683b ldr r3, [r7, #0]
|
|
8006c92: 681b ldr r3, [r3, #0]
|
|
8006c94: 2b11 cmp r3, #17
|
|
8006c96: d003 beq.n 8006ca0 <HAL_ADC_ConfigChannel+0x120>
|
|
8006c98: 683b ldr r3, [r7, #0]
|
|
8006c9a: 681b ldr r3, [r3, #0]
|
|
8006c9c: 2b12 cmp r3, #18
|
|
8006c9e: d163 bne.n 8006d68 <HAL_ADC_ConfigChannel+0x1e8>
|
|
{
|
|
/* If Channel_16 is selected, enable Temp. sensor measurement path. */
|
|
/* If Channel_17 is selected, enable VREFINT measurement path. */
|
|
/* If Channel_18 is selected, enable VBAT measurement path. */
|
|
ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
|
|
8006ca0: 4b38 ldr r3, [pc, #224] @ (8006d84 <HAL_ADC_ConfigChannel+0x204>)
|
|
8006ca2: 6819 ldr r1, [r3, #0]
|
|
8006ca4: 683b ldr r3, [r7, #0]
|
|
8006ca6: 681b ldr r3, [r3, #0]
|
|
8006ca8: 2b10 cmp r3, #16
|
|
8006caa: d009 beq.n 8006cc0 <HAL_ADC_ConfigChannel+0x140>
|
|
8006cac: 683b ldr r3, [r7, #0]
|
|
8006cae: 681b ldr r3, [r3, #0]
|
|
8006cb0: 2b11 cmp r3, #17
|
|
8006cb2: d102 bne.n 8006cba <HAL_ADC_ConfigChannel+0x13a>
|
|
8006cb4: 2380 movs r3, #128 @ 0x80
|
|
8006cb6: 03db lsls r3, r3, #15
|
|
8006cb8: e004 b.n 8006cc4 <HAL_ADC_ConfigChannel+0x144>
|
|
8006cba: 2380 movs r3, #128 @ 0x80
|
|
8006cbc: 045b lsls r3, r3, #17
|
|
8006cbe: e001 b.n 8006cc4 <HAL_ADC_ConfigChannel+0x144>
|
|
8006cc0: 2380 movs r3, #128 @ 0x80
|
|
8006cc2: 041b lsls r3, r3, #16
|
|
8006cc4: 4a2f ldr r2, [pc, #188] @ (8006d84 <HAL_ADC_ConfigChannel+0x204>)
|
|
8006cc6: 430b orrs r3, r1
|
|
8006cc8: 6013 str r3, [r2, #0]
|
|
|
|
/* If Temp. sensor is selected, wait for stabilization delay */
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
8006cca: 683b ldr r3, [r7, #0]
|
|
8006ccc: 681b ldr r3, [r3, #0]
|
|
8006cce: 2b10 cmp r3, #16
|
|
8006cd0: d14a bne.n 8006d68 <HAL_ADC_ConfigChannel+0x1e8>
|
|
{
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
|
|
8006cd2: 4b2d ldr r3, [pc, #180] @ (8006d88 <HAL_ADC_ConfigChannel+0x208>)
|
|
8006cd4: 681b ldr r3, [r3, #0]
|
|
8006cd6: 492d ldr r1, [pc, #180] @ (8006d8c <HAL_ADC_ConfigChannel+0x20c>)
|
|
8006cd8: 0018 movs r0, r3
|
|
8006cda: f7f9 fa15 bl 8000108 <__udivsi3>
|
|
8006cde: 0003 movs r3, r0
|
|
8006ce0: 001a movs r2, r3
|
|
8006ce2: 0013 movs r3, r2
|
|
8006ce4: 009b lsls r3, r3, #2
|
|
8006ce6: 189b adds r3, r3, r2
|
|
8006ce8: 005b lsls r3, r3, #1
|
|
8006cea: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8006cec: e002 b.n 8006cf4 <HAL_ADC_ConfigChannel+0x174>
|
|
{
|
|
wait_loop_index--;
|
|
8006cee: 68bb ldr r3, [r7, #8]
|
|
8006cf0: 3b01 subs r3, #1
|
|
8006cf2: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8006cf4: 68bb ldr r3, [r7, #8]
|
|
8006cf6: 2b00 cmp r3, #0
|
|
8006cf8: d1f9 bne.n 8006cee <HAL_ADC_ConfigChannel+0x16e>
|
|
8006cfa: e035 b.n 8006d68 <HAL_ADC_ConfigChannel+0x1e8>
|
|
}
|
|
else
|
|
{
|
|
/* Regular sequence configuration */
|
|
/* Reset the channel selection register from the selected channel */
|
|
hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
|
|
8006cfc: 687b ldr r3, [r7, #4]
|
|
8006cfe: 681b ldr r3, [r3, #0]
|
|
8006d00: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8006d02: 683b ldr r3, [r7, #0]
|
|
8006d04: 681b ldr r3, [r3, #0]
|
|
8006d06: 2101 movs r1, #1
|
|
8006d08: 4099 lsls r1, r3
|
|
8006d0a: 000b movs r3, r1
|
|
8006d0c: 43d9 mvns r1, r3
|
|
8006d0e: 687b ldr r3, [r7, #4]
|
|
8006d10: 681b ldr r3, [r3, #0]
|
|
8006d12: 400a ands r2, r1
|
|
8006d14: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
|
|
/* internal measurement paths disable: If internal channel selected, */
|
|
/* disable dedicated internal buffers and path. */
|
|
if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
|
8006d16: 683b ldr r3, [r7, #0]
|
|
8006d18: 681b ldr r3, [r3, #0]
|
|
8006d1a: 2b10 cmp r3, #16
|
|
8006d1c: d007 beq.n 8006d2e <HAL_ADC_ConfigChannel+0x1ae>
|
|
8006d1e: 683b ldr r3, [r7, #0]
|
|
8006d20: 681b ldr r3, [r3, #0]
|
|
8006d22: 2b11 cmp r3, #17
|
|
8006d24: d003 beq.n 8006d2e <HAL_ADC_ConfigChannel+0x1ae>
|
|
8006d26: 683b ldr r3, [r7, #0]
|
|
8006d28: 681b ldr r3, [r3, #0]
|
|
8006d2a: 2b12 cmp r3, #18
|
|
8006d2c: d11c bne.n 8006d68 <HAL_ADC_ConfigChannel+0x1e8>
|
|
{
|
|
/* If Channel_16 is selected, disable Temp. sensor measurement path. */
|
|
/* If Channel_17 is selected, disable VREFINT measurement path. */
|
|
/* If Channel_18 is selected, disable VBAT measurement path. */
|
|
ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
|
|
8006d2e: 4b15 ldr r3, [pc, #84] @ (8006d84 <HAL_ADC_ConfigChannel+0x204>)
|
|
8006d30: 6819 ldr r1, [r3, #0]
|
|
8006d32: 683b ldr r3, [r7, #0]
|
|
8006d34: 681b ldr r3, [r3, #0]
|
|
8006d36: 2b10 cmp r3, #16
|
|
8006d38: d007 beq.n 8006d4a <HAL_ADC_ConfigChannel+0x1ca>
|
|
8006d3a: 683b ldr r3, [r7, #0]
|
|
8006d3c: 681b ldr r3, [r3, #0]
|
|
8006d3e: 2b11 cmp r3, #17
|
|
8006d40: d101 bne.n 8006d46 <HAL_ADC_ConfigChannel+0x1c6>
|
|
8006d42: 4b13 ldr r3, [pc, #76] @ (8006d90 <HAL_ADC_ConfigChannel+0x210>)
|
|
8006d44: e002 b.n 8006d4c <HAL_ADC_ConfigChannel+0x1cc>
|
|
8006d46: 4b13 ldr r3, [pc, #76] @ (8006d94 <HAL_ADC_ConfigChannel+0x214>)
|
|
8006d48: e000 b.n 8006d4c <HAL_ADC_ConfigChannel+0x1cc>
|
|
8006d4a: 4b13 ldr r3, [pc, #76] @ (8006d98 <HAL_ADC_ConfigChannel+0x218>)
|
|
8006d4c: 4a0d ldr r2, [pc, #52] @ (8006d84 <HAL_ADC_ConfigChannel+0x204>)
|
|
8006d4e: 400b ands r3, r1
|
|
8006d50: 6013 str r3, [r2, #0]
|
|
8006d52: e009 b.n 8006d68 <HAL_ADC_ConfigChannel+0x1e8>
|
|
/* channel could be done on neither of the channel configuration structure */
|
|
/* parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8006d54: 687b ldr r3, [r7, #4]
|
|
8006d56: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006d58: 2220 movs r2, #32
|
|
8006d5a: 431a orrs r2, r3
|
|
8006d5c: 687b ldr r3, [r7, #4]
|
|
8006d5e: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8006d60: 230f movs r3, #15
|
|
8006d62: 18fb adds r3, r7, r3
|
|
8006d64: 2201 movs r2, #1
|
|
8006d66: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8006d68: 687b ldr r3, [r7, #4]
|
|
8006d6a: 2234 movs r2, #52 @ 0x34
|
|
8006d6c: 2100 movs r1, #0
|
|
8006d6e: 5499 strb r1, [r3, r2]
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8006d70: 230f movs r3, #15
|
|
8006d72: 18fb adds r3, r7, r3
|
|
8006d74: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8006d76: 0018 movs r0, r3
|
|
8006d78: 46bd mov sp, r7
|
|
8006d7a: b004 add sp, #16
|
|
8006d7c: bd80 pop {r7, pc}
|
|
8006d7e: 46c0 nop @ (mov r8, r8)
|
|
8006d80: 00001001 .word 0x00001001
|
|
8006d84: 40012708 .word 0x40012708
|
|
8006d88: 20000004 .word 0x20000004
|
|
8006d8c: 000f4240 .word 0x000f4240
|
|
8006d90: ffbfffff .word 0xffbfffff
|
|
8006d94: feffffff .word 0xfeffffff
|
|
8006d98: ff7fffff .word 0xff7fffff
|
|
|
|
08006d9c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8006d9c: b590 push {r4, r7, lr}
|
|
8006d9e: b083 sub sp, #12
|
|
8006da0: af00 add r7, sp, #0
|
|
8006da2: 0002 movs r2, r0
|
|
8006da4: 6039 str r1, [r7, #0]
|
|
8006da6: 1dfb adds r3, r7, #7
|
|
8006da8: 701a strb r2, [r3, #0]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006daa: 1dfb adds r3, r7, #7
|
|
8006dac: 781b ldrb r3, [r3, #0]
|
|
8006dae: 2b7f cmp r3, #127 @ 0x7f
|
|
8006db0: d828 bhi.n 8006e04 <__NVIC_SetPriority+0x68>
|
|
{
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8006db2: 4a2f ldr r2, [pc, #188] @ (8006e70 <__NVIC_SetPriority+0xd4>)
|
|
8006db4: 1dfb adds r3, r7, #7
|
|
8006db6: 781b ldrb r3, [r3, #0]
|
|
8006db8: b25b sxtb r3, r3
|
|
8006dba: 089b lsrs r3, r3, #2
|
|
8006dbc: 33c0 adds r3, #192 @ 0xc0
|
|
8006dbe: 009b lsls r3, r3, #2
|
|
8006dc0: 589b ldr r3, [r3, r2]
|
|
8006dc2: 1dfa adds r2, r7, #7
|
|
8006dc4: 7812 ldrb r2, [r2, #0]
|
|
8006dc6: 0011 movs r1, r2
|
|
8006dc8: 2203 movs r2, #3
|
|
8006dca: 400a ands r2, r1
|
|
8006dcc: 00d2 lsls r2, r2, #3
|
|
8006dce: 21ff movs r1, #255 @ 0xff
|
|
8006dd0: 4091 lsls r1, r2
|
|
8006dd2: 000a movs r2, r1
|
|
8006dd4: 43d2 mvns r2, r2
|
|
8006dd6: 401a ands r2, r3
|
|
8006dd8: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8006dda: 683b ldr r3, [r7, #0]
|
|
8006ddc: 019b lsls r3, r3, #6
|
|
8006dde: 22ff movs r2, #255 @ 0xff
|
|
8006de0: 401a ands r2, r3
|
|
8006de2: 1dfb adds r3, r7, #7
|
|
8006de4: 781b ldrb r3, [r3, #0]
|
|
8006de6: 0018 movs r0, r3
|
|
8006de8: 2303 movs r3, #3
|
|
8006dea: 4003 ands r3, r0
|
|
8006dec: 00db lsls r3, r3, #3
|
|
8006dee: 409a lsls r2, r3
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8006df0: 481f ldr r0, [pc, #124] @ (8006e70 <__NVIC_SetPriority+0xd4>)
|
|
8006df2: 1dfb adds r3, r7, #7
|
|
8006df4: 781b ldrb r3, [r3, #0]
|
|
8006df6: b25b sxtb r3, r3
|
|
8006df8: 089b lsrs r3, r3, #2
|
|
8006dfa: 430a orrs r2, r1
|
|
8006dfc: 33c0 adds r3, #192 @ 0xc0
|
|
8006dfe: 009b lsls r3, r3, #2
|
|
8006e00: 501a str r2, [r3, r0]
|
|
else
|
|
{
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
}
|
|
}
|
|
8006e02: e031 b.n 8006e68 <__NVIC_SetPriority+0xcc>
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8006e04: 4a1b ldr r2, [pc, #108] @ (8006e74 <__NVIC_SetPriority+0xd8>)
|
|
8006e06: 1dfb adds r3, r7, #7
|
|
8006e08: 781b ldrb r3, [r3, #0]
|
|
8006e0a: 0019 movs r1, r3
|
|
8006e0c: 230f movs r3, #15
|
|
8006e0e: 400b ands r3, r1
|
|
8006e10: 3b08 subs r3, #8
|
|
8006e12: 089b lsrs r3, r3, #2
|
|
8006e14: 3306 adds r3, #6
|
|
8006e16: 009b lsls r3, r3, #2
|
|
8006e18: 18d3 adds r3, r2, r3
|
|
8006e1a: 3304 adds r3, #4
|
|
8006e1c: 681b ldr r3, [r3, #0]
|
|
8006e1e: 1dfa adds r2, r7, #7
|
|
8006e20: 7812 ldrb r2, [r2, #0]
|
|
8006e22: 0011 movs r1, r2
|
|
8006e24: 2203 movs r2, #3
|
|
8006e26: 400a ands r2, r1
|
|
8006e28: 00d2 lsls r2, r2, #3
|
|
8006e2a: 21ff movs r1, #255 @ 0xff
|
|
8006e2c: 4091 lsls r1, r2
|
|
8006e2e: 000a movs r2, r1
|
|
8006e30: 43d2 mvns r2, r2
|
|
8006e32: 401a ands r2, r3
|
|
8006e34: 0011 movs r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8006e36: 683b ldr r3, [r7, #0]
|
|
8006e38: 019b lsls r3, r3, #6
|
|
8006e3a: 22ff movs r2, #255 @ 0xff
|
|
8006e3c: 401a ands r2, r3
|
|
8006e3e: 1dfb adds r3, r7, #7
|
|
8006e40: 781b ldrb r3, [r3, #0]
|
|
8006e42: 0018 movs r0, r3
|
|
8006e44: 2303 movs r3, #3
|
|
8006e46: 4003 ands r3, r0
|
|
8006e48: 00db lsls r3, r3, #3
|
|
8006e4a: 409a lsls r2, r3
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8006e4c: 4809 ldr r0, [pc, #36] @ (8006e74 <__NVIC_SetPriority+0xd8>)
|
|
8006e4e: 1dfb adds r3, r7, #7
|
|
8006e50: 781b ldrb r3, [r3, #0]
|
|
8006e52: 001c movs r4, r3
|
|
8006e54: 230f movs r3, #15
|
|
8006e56: 4023 ands r3, r4
|
|
8006e58: 3b08 subs r3, #8
|
|
8006e5a: 089b lsrs r3, r3, #2
|
|
8006e5c: 430a orrs r2, r1
|
|
8006e5e: 3306 adds r3, #6
|
|
8006e60: 009b lsls r3, r3, #2
|
|
8006e62: 18c3 adds r3, r0, r3
|
|
8006e64: 3304 adds r3, #4
|
|
8006e66: 601a str r2, [r3, #0]
|
|
}
|
|
8006e68: 46c0 nop @ (mov r8, r8)
|
|
8006e6a: 46bd mov sp, r7
|
|
8006e6c: b003 add sp, #12
|
|
8006e6e: bd90 pop {r4, r7, pc}
|
|
8006e70: e000e100 .word 0xe000e100
|
|
8006e74: e000ed00 .word 0xe000ed00
|
|
|
|
08006e78 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8006e78: b580 push {r7, lr}
|
|
8006e7a: b082 sub sp, #8
|
|
8006e7c: af00 add r7, sp, #0
|
|
8006e7e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8006e80: 687b ldr r3, [r7, #4]
|
|
8006e82: 1e5a subs r2, r3, #1
|
|
8006e84: 2380 movs r3, #128 @ 0x80
|
|
8006e86: 045b lsls r3, r3, #17
|
|
8006e88: 429a cmp r2, r3
|
|
8006e8a: d301 bcc.n 8006e90 <SysTick_Config+0x18>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8006e8c: 2301 movs r3, #1
|
|
8006e8e: e010 b.n 8006eb2 <SysTick_Config+0x3a>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8006e90: 4b0a ldr r3, [pc, #40] @ (8006ebc <SysTick_Config+0x44>)
|
|
8006e92: 687a ldr r2, [r7, #4]
|
|
8006e94: 3a01 subs r2, #1
|
|
8006e96: 605a str r2, [r3, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8006e98: 2301 movs r3, #1
|
|
8006e9a: 425b negs r3, r3
|
|
8006e9c: 2103 movs r1, #3
|
|
8006e9e: 0018 movs r0, r3
|
|
8006ea0: f7ff ff7c bl 8006d9c <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8006ea4: 4b05 ldr r3, [pc, #20] @ (8006ebc <SysTick_Config+0x44>)
|
|
8006ea6: 2200 movs r2, #0
|
|
8006ea8: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8006eaa: 4b04 ldr r3, [pc, #16] @ (8006ebc <SysTick_Config+0x44>)
|
|
8006eac: 2207 movs r2, #7
|
|
8006eae: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8006eb0: 2300 movs r3, #0
|
|
}
|
|
8006eb2: 0018 movs r0, r3
|
|
8006eb4: 46bd mov sp, r7
|
|
8006eb6: b002 add sp, #8
|
|
8006eb8: bd80 pop {r7, pc}
|
|
8006eba: 46c0 nop @ (mov r8, r8)
|
|
8006ebc: e000e010 .word 0xe000e010
|
|
|
|
08006ec0 <HAL_NVIC_SetPriority>:
|
|
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
|
|
* no subpriority supported in Cortex M0 based products.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8006ec0: b580 push {r7, lr}
|
|
8006ec2: b084 sub sp, #16
|
|
8006ec4: af00 add r7, sp, #0
|
|
8006ec6: 60b9 str r1, [r7, #8]
|
|
8006ec8: 607a str r2, [r7, #4]
|
|
8006eca: 210f movs r1, #15
|
|
8006ecc: 187b adds r3, r7, r1
|
|
8006ece: 1c02 adds r2, r0, #0
|
|
8006ed0: 701a strb r2, [r3, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
NVIC_SetPriority(IRQn,PreemptPriority);
|
|
8006ed2: 68ba ldr r2, [r7, #8]
|
|
8006ed4: 187b adds r3, r7, r1
|
|
8006ed6: 781b ldrb r3, [r3, #0]
|
|
8006ed8: b25b sxtb r3, r3
|
|
8006eda: 0011 movs r1, r2
|
|
8006edc: 0018 movs r0, r3
|
|
8006ede: f7ff ff5d bl 8006d9c <__NVIC_SetPriority>
|
|
}
|
|
8006ee2: 46c0 nop @ (mov r8, r8)
|
|
8006ee4: 46bd mov sp, r7
|
|
8006ee6: b004 add sp, #16
|
|
8006ee8: bd80 pop {r7, pc}
|
|
|
|
08006eea <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8006eea: b580 push {r7, lr}
|
|
8006eec: b082 sub sp, #8
|
|
8006eee: af00 add r7, sp, #0
|
|
8006ef0: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8006ef2: 687b ldr r3, [r7, #4]
|
|
8006ef4: 0018 movs r0, r3
|
|
8006ef6: f7ff ffbf bl 8006e78 <SysTick_Config>
|
|
8006efa: 0003 movs r3, r0
|
|
}
|
|
8006efc: 0018 movs r0, r3
|
|
8006efe: 46bd mov sp, r7
|
|
8006f00: b002 add sp, #8
|
|
8006f02: bd80 pop {r7, pc}
|
|
|
|
08006f04 <HAL_FLASH_Program>:
|
|
* @param Data Specifie the data to be programmed
|
|
*
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
|
{
|
|
8006f04: b5f0 push {r4, r5, r6, r7, lr}
|
|
8006f06: b087 sub sp, #28
|
|
8006f08: af00 add r7, sp, #0
|
|
8006f0a: 60f8 str r0, [r7, #12]
|
|
8006f0c: 60b9 str r1, [r7, #8]
|
|
8006f0e: 603a str r2, [r7, #0]
|
|
8006f10: 607b str r3, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|
8006f12: 2317 movs r3, #23
|
|
8006f14: 18fb adds r3, r7, r3
|
|
8006f16: 2201 movs r2, #1
|
|
8006f18: 701a strb r2, [r3, #0]
|
|
uint8_t index = 0U;
|
|
8006f1a: 2316 movs r3, #22
|
|
8006f1c: 18fb adds r3, r7, r3
|
|
8006f1e: 2200 movs r2, #0
|
|
8006f20: 701a strb r2, [r3, #0]
|
|
uint8_t nbiterations = 0U;
|
|
8006f22: 2315 movs r3, #21
|
|
8006f24: 18fb adds r3, r7, r3
|
|
8006f26: 2200 movs r2, #0
|
|
8006f28: 701a strb r2, [r3, #0]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
8006f2a: 4b3e ldr r3, [pc, #248] @ (8007024 <HAL_FLASH_Program+0x120>)
|
|
8006f2c: 7e1b ldrb r3, [r3, #24]
|
|
8006f2e: 2b01 cmp r3, #1
|
|
8006f30: d101 bne.n 8006f36 <HAL_FLASH_Program+0x32>
|
|
8006f32: 2302 movs r3, #2
|
|
8006f34: e072 b.n 800701c <HAL_FLASH_Program+0x118>
|
|
8006f36: 4b3b ldr r3, [pc, #236] @ (8007024 <HAL_FLASH_Program+0x120>)
|
|
8006f38: 2201 movs r2, #1
|
|
8006f3a: 761a strb r2, [r3, #24]
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
|
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
8006f3c: 2317 movs r3, #23
|
|
8006f3e: 18fe adds r6, r7, r3
|
|
8006f40: 4b39 ldr r3, [pc, #228] @ (8007028 <HAL_FLASH_Program+0x124>)
|
|
8006f42: 0018 movs r0, r3
|
|
8006f44: f000 f8c4 bl 80070d0 <FLASH_WaitForLastOperation>
|
|
8006f48: 0003 movs r3, r0
|
|
8006f4a: 7033 strb r3, [r6, #0]
|
|
|
|
if(status == HAL_OK)
|
|
8006f4c: 2317 movs r3, #23
|
|
8006f4e: 18fb adds r3, r7, r3
|
|
8006f50: 781b ldrb r3, [r3, #0]
|
|
8006f52: 2b00 cmp r3, #0
|
|
8006f54: d15c bne.n 8007010 <HAL_FLASH_Program+0x10c>
|
|
{
|
|
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
|
8006f56: 68fb ldr r3, [r7, #12]
|
|
8006f58: 2b01 cmp r3, #1
|
|
8006f5a: d104 bne.n 8006f66 <HAL_FLASH_Program+0x62>
|
|
{
|
|
/* Program halfword (16-bit) at a specified address. */
|
|
nbiterations = 1U;
|
|
8006f5c: 2315 movs r3, #21
|
|
8006f5e: 18fb adds r3, r7, r3
|
|
8006f60: 2201 movs r2, #1
|
|
8006f62: 701a strb r2, [r3, #0]
|
|
8006f64: e00b b.n 8006f7e <HAL_FLASH_Program+0x7a>
|
|
}
|
|
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
|
8006f66: 68fb ldr r3, [r7, #12]
|
|
8006f68: 2b02 cmp r3, #2
|
|
8006f6a: d104 bne.n 8006f76 <HAL_FLASH_Program+0x72>
|
|
{
|
|
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
|
nbiterations = 2U;
|
|
8006f6c: 2315 movs r3, #21
|
|
8006f6e: 18fb adds r3, r7, r3
|
|
8006f70: 2202 movs r2, #2
|
|
8006f72: 701a strb r2, [r3, #0]
|
|
8006f74: e003 b.n 8006f7e <HAL_FLASH_Program+0x7a>
|
|
}
|
|
else
|
|
{
|
|
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
|
nbiterations = 4U;
|
|
8006f76: 2315 movs r3, #21
|
|
8006f78: 18fb adds r3, r7, r3
|
|
8006f7a: 2204 movs r2, #4
|
|
8006f7c: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
for (index = 0U; index < nbiterations; index++)
|
|
8006f7e: 2316 movs r3, #22
|
|
8006f80: 18fb adds r3, r7, r3
|
|
8006f82: 2200 movs r2, #0
|
|
8006f84: 701a strb r2, [r3, #0]
|
|
8006f86: e039 b.n 8006ffc <HAL_FLASH_Program+0xf8>
|
|
{
|
|
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
|
|
8006f88: 2116 movs r1, #22
|
|
8006f8a: 187b adds r3, r7, r1
|
|
8006f8c: 781b ldrb r3, [r3, #0]
|
|
8006f8e: 005a lsls r2, r3, #1
|
|
8006f90: 68bb ldr r3, [r7, #8]
|
|
8006f92: 18d0 adds r0, r2, r3
|
|
8006f94: 187b adds r3, r7, r1
|
|
8006f96: 781b ldrb r3, [r3, #0]
|
|
8006f98: 011b lsls r3, r3, #4
|
|
8006f9a: 001a movs r2, r3
|
|
8006f9c: 3a20 subs r2, #32
|
|
8006f9e: 2a00 cmp r2, #0
|
|
8006fa0: db03 blt.n 8006faa <HAL_FLASH_Program+0xa6>
|
|
8006fa2: 6879 ldr r1, [r7, #4]
|
|
8006fa4: 40d1 lsrs r1, r2
|
|
8006fa6: 000c movs r4, r1
|
|
8006fa8: e008 b.n 8006fbc <HAL_FLASH_Program+0xb8>
|
|
8006faa: 2220 movs r2, #32
|
|
8006fac: 1ad2 subs r2, r2, r3
|
|
8006fae: 6879 ldr r1, [r7, #4]
|
|
8006fb0: 4091 lsls r1, r2
|
|
8006fb2: 000a movs r2, r1
|
|
8006fb4: 6839 ldr r1, [r7, #0]
|
|
8006fb6: 40d9 lsrs r1, r3
|
|
8006fb8: 000c movs r4, r1
|
|
8006fba: 4314 orrs r4, r2
|
|
8006fbc: 687a ldr r2, [r7, #4]
|
|
8006fbe: 40da lsrs r2, r3
|
|
8006fc0: 0015 movs r5, r2
|
|
8006fc2: b2a3 uxth r3, r4
|
|
8006fc4: 0019 movs r1, r3
|
|
8006fc6: f000 f867 bl 8007098 <FLASH_Program_HalfWord>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
|
8006fca: 2317 movs r3, #23
|
|
8006fcc: 18fe adds r6, r7, r3
|
|
8006fce: 4b16 ldr r3, [pc, #88] @ (8007028 <HAL_FLASH_Program+0x124>)
|
|
8006fd0: 0018 movs r0, r3
|
|
8006fd2: f000 f87d bl 80070d0 <FLASH_WaitForLastOperation>
|
|
8006fd6: 0003 movs r3, r0
|
|
8006fd8: 7033 strb r3, [r6, #0]
|
|
|
|
/* If the program operation is completed, disable the PG Bit */
|
|
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
|
8006fda: 4b14 ldr r3, [pc, #80] @ (800702c <HAL_FLASH_Program+0x128>)
|
|
8006fdc: 691a ldr r2, [r3, #16]
|
|
8006fde: 4b13 ldr r3, [pc, #76] @ (800702c <HAL_FLASH_Program+0x128>)
|
|
8006fe0: 2101 movs r1, #1
|
|
8006fe2: 438a bics r2, r1
|
|
8006fe4: 611a str r2, [r3, #16]
|
|
/* In case of error, stop programming procedure */
|
|
if (status != HAL_OK)
|
|
8006fe6: 2317 movs r3, #23
|
|
8006fe8: 18fb adds r3, r7, r3
|
|
8006fea: 781b ldrb r3, [r3, #0]
|
|
8006fec: 2b00 cmp r3, #0
|
|
8006fee: d10e bne.n 800700e <HAL_FLASH_Program+0x10a>
|
|
for (index = 0U; index < nbiterations; index++)
|
|
8006ff0: 2116 movs r1, #22
|
|
8006ff2: 187b adds r3, r7, r1
|
|
8006ff4: 781a ldrb r2, [r3, #0]
|
|
8006ff6: 187b adds r3, r7, r1
|
|
8006ff8: 3201 adds r2, #1
|
|
8006ffa: 701a strb r2, [r3, #0]
|
|
8006ffc: 2316 movs r3, #22
|
|
8006ffe: 18fa adds r2, r7, r3
|
|
8007000: 2315 movs r3, #21
|
|
8007002: 18fb adds r3, r7, r3
|
|
8007004: 7812 ldrb r2, [r2, #0]
|
|
8007006: 781b ldrb r3, [r3, #0]
|
|
8007008: 429a cmp r2, r3
|
|
800700a: d3bd bcc.n 8006f88 <HAL_FLASH_Program+0x84>
|
|
800700c: e000 b.n 8007010 <HAL_FLASH_Program+0x10c>
|
|
{
|
|
break;
|
|
800700e: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
8007010: 4b04 ldr r3, [pc, #16] @ (8007024 <HAL_FLASH_Program+0x120>)
|
|
8007012: 2200 movs r2, #0
|
|
8007014: 761a strb r2, [r3, #24]
|
|
|
|
return status;
|
|
8007016: 2317 movs r3, #23
|
|
8007018: 18fb adds r3, r7, r3
|
|
800701a: 781b ldrb r3, [r3, #0]
|
|
}
|
|
800701c: 0018 movs r0, r3
|
|
800701e: 46bd mov sp, r7
|
|
8007020: b007 add sp, #28
|
|
8007022: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8007024: 20000db0 .word 0x20000db0
|
|
8007028: 0000c350 .word 0x0000c350
|
|
800702c: 40022000 .word 0x40022000
|
|
|
|
08007030 <HAL_FLASH_Unlock>:
|
|
/**
|
|
* @brief Unlock the FLASH control register access
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
|
{
|
|
8007030: b580 push {r7, lr}
|
|
8007032: b082 sub sp, #8
|
|
8007034: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8007036: 1dfb adds r3, r7, #7
|
|
8007038: 2200 movs r2, #0
|
|
800703a: 701a strb r2, [r3, #0]
|
|
|
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
|
800703c: 4b0c ldr r3, [pc, #48] @ (8007070 <HAL_FLASH_Unlock+0x40>)
|
|
800703e: 691b ldr r3, [r3, #16]
|
|
8007040: 2280 movs r2, #128 @ 0x80
|
|
8007042: 4013 ands r3, r2
|
|
8007044: d00d beq.n 8007062 <HAL_FLASH_Unlock+0x32>
|
|
{
|
|
/* Authorize the FLASH Registers access */
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
|
8007046: 4b0a ldr r3, [pc, #40] @ (8007070 <HAL_FLASH_Unlock+0x40>)
|
|
8007048: 4a0a ldr r2, [pc, #40] @ (8007074 <HAL_FLASH_Unlock+0x44>)
|
|
800704a: 605a str r2, [r3, #4]
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
|
800704c: 4b08 ldr r3, [pc, #32] @ (8007070 <HAL_FLASH_Unlock+0x40>)
|
|
800704e: 4a0a ldr r2, [pc, #40] @ (8007078 <HAL_FLASH_Unlock+0x48>)
|
|
8007050: 605a str r2, [r3, #4]
|
|
|
|
/* Verify Flash is unlocked */
|
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
|
8007052: 4b07 ldr r3, [pc, #28] @ (8007070 <HAL_FLASH_Unlock+0x40>)
|
|
8007054: 691b ldr r3, [r3, #16]
|
|
8007056: 2280 movs r2, #128 @ 0x80
|
|
8007058: 4013 ands r3, r2
|
|
800705a: d002 beq.n 8007062 <HAL_FLASH_Unlock+0x32>
|
|
{
|
|
status = HAL_ERROR;
|
|
800705c: 1dfb adds r3, r7, #7
|
|
800705e: 2201 movs r2, #1
|
|
8007060: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8007062: 1dfb adds r3, r7, #7
|
|
8007064: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8007066: 0018 movs r0, r3
|
|
8007068: 46bd mov sp, r7
|
|
800706a: b002 add sp, #8
|
|
800706c: bd80 pop {r7, pc}
|
|
800706e: 46c0 nop @ (mov r8, r8)
|
|
8007070: 40022000 .word 0x40022000
|
|
8007074: 45670123 .word 0x45670123
|
|
8007078: cdef89ab .word 0xcdef89ab
|
|
|
|
0800707c <HAL_FLASH_Lock>:
|
|
/**
|
|
* @brief Locks the FLASH control register access
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
|
{
|
|
800707c: b580 push {r7, lr}
|
|
800707e: af00 add r7, sp, #0
|
|
/* Set the LOCK Bit to lock the FLASH Registers access */
|
|
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
|
8007080: 4b04 ldr r3, [pc, #16] @ (8007094 <HAL_FLASH_Lock+0x18>)
|
|
8007082: 691a ldr r2, [r3, #16]
|
|
8007084: 4b03 ldr r3, [pc, #12] @ (8007094 <HAL_FLASH_Lock+0x18>)
|
|
8007086: 2180 movs r1, #128 @ 0x80
|
|
8007088: 430a orrs r2, r1
|
|
800708a: 611a str r2, [r3, #16]
|
|
|
|
return HAL_OK;
|
|
800708c: 2300 movs r3, #0
|
|
}
|
|
800708e: 0018 movs r0, r3
|
|
8007090: 46bd mov sp, r7
|
|
8007092: bd80 pop {r7, pc}
|
|
8007094: 40022000 .word 0x40022000
|
|
|
|
08007098 <FLASH_Program_HalfWord>:
|
|
* @param Address specify the address to be programmed.
|
|
* @param Data specify the data to be programmed.
|
|
* @retval None
|
|
*/
|
|
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
|
{
|
|
8007098: b580 push {r7, lr}
|
|
800709a: b082 sub sp, #8
|
|
800709c: af00 add r7, sp, #0
|
|
800709e: 6078 str r0, [r7, #4]
|
|
80070a0: 000a movs r2, r1
|
|
80070a2: 1cbb adds r3, r7, #2
|
|
80070a4: 801a strh r2, [r3, #0]
|
|
/* Clean the error context */
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
80070a6: 4b08 ldr r3, [pc, #32] @ (80070c8 <FLASH_Program_HalfWord+0x30>)
|
|
80070a8: 2200 movs r2, #0
|
|
80070aa: 61da str r2, [r3, #28]
|
|
|
|
/* Proceed to program the new data */
|
|
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
|
80070ac: 4b07 ldr r3, [pc, #28] @ (80070cc <FLASH_Program_HalfWord+0x34>)
|
|
80070ae: 691a ldr r2, [r3, #16]
|
|
80070b0: 4b06 ldr r3, [pc, #24] @ (80070cc <FLASH_Program_HalfWord+0x34>)
|
|
80070b2: 2101 movs r1, #1
|
|
80070b4: 430a orrs r2, r1
|
|
80070b6: 611a str r2, [r3, #16]
|
|
|
|
/* Write data in the address */
|
|
*(__IO uint16_t*)Address = Data;
|
|
80070b8: 687b ldr r3, [r7, #4]
|
|
80070ba: 1cba adds r2, r7, #2
|
|
80070bc: 8812 ldrh r2, [r2, #0]
|
|
80070be: 801a strh r2, [r3, #0]
|
|
}
|
|
80070c0: 46c0 nop @ (mov r8, r8)
|
|
80070c2: 46bd mov sp, r7
|
|
80070c4: b002 add sp, #8
|
|
80070c6: bd80 pop {r7, pc}
|
|
80070c8: 20000db0 .word 0x20000db0
|
|
80070cc: 40022000 .word 0x40022000
|
|
|
|
080070d0 <FLASH_WaitForLastOperation>:
|
|
* @brief Wait for a FLASH operation to complete.
|
|
* @param Timeout maximum flash operation timeout
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|
{
|
|
80070d0: b580 push {r7, lr}
|
|
80070d2: b084 sub sp, #16
|
|
80070d4: af00 add r7, sp, #0
|
|
80070d6: 6078 str r0, [r7, #4]
|
|
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
|
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
|
flag will be set */
|
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
80070d8: f7ff fc08 bl 80068ec <HAL_GetTick>
|
|
80070dc: 0003 movs r3, r0
|
|
80070de: 60fb str r3, [r7, #12]
|
|
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|
80070e0: e00f b.n 8007102 <FLASH_WaitForLastOperation+0x32>
|
|
{
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80070e2: 687b ldr r3, [r7, #4]
|
|
80070e4: 3301 adds r3, #1
|
|
80070e6: d00c beq.n 8007102 <FLASH_WaitForLastOperation+0x32>
|
|
{
|
|
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|
80070e8: 687b ldr r3, [r7, #4]
|
|
80070ea: 2b00 cmp r3, #0
|
|
80070ec: d007 beq.n 80070fe <FLASH_WaitForLastOperation+0x2e>
|
|
80070ee: f7ff fbfd bl 80068ec <HAL_GetTick>
|
|
80070f2: 0002 movs r2, r0
|
|
80070f4: 68fb ldr r3, [r7, #12]
|
|
80070f6: 1ad3 subs r3, r2, r3
|
|
80070f8: 687a ldr r2, [r7, #4]
|
|
80070fa: 429a cmp r2, r3
|
|
80070fc: d201 bcs.n 8007102 <FLASH_WaitForLastOperation+0x32>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80070fe: 2303 movs r3, #3
|
|
8007100: e01f b.n 8007142 <FLASH_WaitForLastOperation+0x72>
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|
8007102: 4b12 ldr r3, [pc, #72] @ (800714c <FLASH_WaitForLastOperation+0x7c>)
|
|
8007104: 68db ldr r3, [r3, #12]
|
|
8007106: 2201 movs r2, #1
|
|
8007108: 4013 ands r3, r2
|
|
800710a: 2b01 cmp r3, #1
|
|
800710c: d0e9 beq.n 80070e2 <FLASH_WaitForLastOperation+0x12>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check FLASH End of Operation flag */
|
|
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
|
800710e: 4b0f ldr r3, [pc, #60] @ (800714c <FLASH_WaitForLastOperation+0x7c>)
|
|
8007110: 68db ldr r3, [r3, #12]
|
|
8007112: 2220 movs r2, #32
|
|
8007114: 4013 ands r3, r2
|
|
8007116: 2b20 cmp r3, #32
|
|
8007118: d102 bne.n 8007120 <FLASH_WaitForLastOperation+0x50>
|
|
{
|
|
/* Clear FLASH End of Operation pending bit */
|
|
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
|
800711a: 4b0c ldr r3, [pc, #48] @ (800714c <FLASH_WaitForLastOperation+0x7c>)
|
|
800711c: 2220 movs r2, #32
|
|
800711e: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
|
8007120: 4b0a ldr r3, [pc, #40] @ (800714c <FLASH_WaitForLastOperation+0x7c>)
|
|
8007122: 68db ldr r3, [r3, #12]
|
|
8007124: 2210 movs r2, #16
|
|
8007126: 4013 ands r3, r2
|
|
8007128: 2b10 cmp r3, #16
|
|
800712a: d005 beq.n 8007138 <FLASH_WaitForLastOperation+0x68>
|
|
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
|
800712c: 4b07 ldr r3, [pc, #28] @ (800714c <FLASH_WaitForLastOperation+0x7c>)
|
|
800712e: 68db ldr r3, [r3, #12]
|
|
8007130: 2204 movs r2, #4
|
|
8007132: 4013 ands r3, r2
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
|
8007134: 2b04 cmp r3, #4
|
|
8007136: d103 bne.n 8007140 <FLASH_WaitForLastOperation+0x70>
|
|
{
|
|
/*Save the error code*/
|
|
FLASH_SetErrorCode();
|
|
8007138: f000 f80a bl 8007150 <FLASH_SetErrorCode>
|
|
return HAL_ERROR;
|
|
800713c: 2301 movs r3, #1
|
|
800713e: e000 b.n 8007142 <FLASH_WaitForLastOperation+0x72>
|
|
}
|
|
|
|
/* There is no error flag set */
|
|
return HAL_OK;
|
|
8007140: 2300 movs r3, #0
|
|
}
|
|
8007142: 0018 movs r0, r3
|
|
8007144: 46bd mov sp, r7
|
|
8007146: b004 add sp, #16
|
|
8007148: bd80 pop {r7, pc}
|
|
800714a: 46c0 nop @ (mov r8, r8)
|
|
800714c: 40022000 .word 0x40022000
|
|
|
|
08007150 <FLASH_SetErrorCode>:
|
|
/**
|
|
* @brief Set the specific FLASH error flag.
|
|
* @retval None
|
|
*/
|
|
static void FLASH_SetErrorCode(void)
|
|
{
|
|
8007150: b580 push {r7, lr}
|
|
8007152: b082 sub sp, #8
|
|
8007154: af00 add r7, sp, #0
|
|
uint32_t flags = 0U;
|
|
8007156: 2300 movs r3, #0
|
|
8007158: 607b str r3, [r7, #4]
|
|
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
|
800715a: 4b13 ldr r3, [pc, #76] @ (80071a8 <FLASH_SetErrorCode+0x58>)
|
|
800715c: 68db ldr r3, [r3, #12]
|
|
800715e: 2210 movs r2, #16
|
|
8007160: 4013 ands r3, r2
|
|
8007162: 2b10 cmp r3, #16
|
|
8007164: d109 bne.n 800717a <FLASH_SetErrorCode+0x2a>
|
|
{
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
|
8007166: 4b11 ldr r3, [pc, #68] @ (80071ac <FLASH_SetErrorCode+0x5c>)
|
|
8007168: 69db ldr r3, [r3, #28]
|
|
800716a: 2202 movs r2, #2
|
|
800716c: 431a orrs r2, r3
|
|
800716e: 4b0f ldr r3, [pc, #60] @ (80071ac <FLASH_SetErrorCode+0x5c>)
|
|
8007170: 61da str r2, [r3, #28]
|
|
flags |= FLASH_FLAG_WRPERR;
|
|
8007172: 687b ldr r3, [r7, #4]
|
|
8007174: 2210 movs r2, #16
|
|
8007176: 4313 orrs r3, r2
|
|
8007178: 607b str r3, [r7, #4]
|
|
}
|
|
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
|
800717a: 4b0b ldr r3, [pc, #44] @ (80071a8 <FLASH_SetErrorCode+0x58>)
|
|
800717c: 68db ldr r3, [r3, #12]
|
|
800717e: 2204 movs r2, #4
|
|
8007180: 4013 ands r3, r2
|
|
8007182: 2b04 cmp r3, #4
|
|
8007184: d109 bne.n 800719a <FLASH_SetErrorCode+0x4a>
|
|
{
|
|
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
|
|
8007186: 4b09 ldr r3, [pc, #36] @ (80071ac <FLASH_SetErrorCode+0x5c>)
|
|
8007188: 69db ldr r3, [r3, #28]
|
|
800718a: 2201 movs r2, #1
|
|
800718c: 431a orrs r2, r3
|
|
800718e: 4b07 ldr r3, [pc, #28] @ (80071ac <FLASH_SetErrorCode+0x5c>)
|
|
8007190: 61da str r2, [r3, #28]
|
|
flags |= FLASH_FLAG_PGERR;
|
|
8007192: 687b ldr r3, [r7, #4]
|
|
8007194: 2204 movs r2, #4
|
|
8007196: 4313 orrs r3, r2
|
|
8007198: 607b str r3, [r7, #4]
|
|
}
|
|
/* Clear FLASH error pending bits */
|
|
__HAL_FLASH_CLEAR_FLAG(flags);
|
|
800719a: 4b03 ldr r3, [pc, #12] @ (80071a8 <FLASH_SetErrorCode+0x58>)
|
|
800719c: 687a ldr r2, [r7, #4]
|
|
800719e: 60da str r2, [r3, #12]
|
|
}
|
|
80071a0: 46c0 nop @ (mov r8, r8)
|
|
80071a2: 46bd mov sp, r7
|
|
80071a4: b002 add sp, #8
|
|
80071a6: bd80 pop {r7, pc}
|
|
80071a8: 40022000 .word 0x40022000
|
|
80071ac: 20000db0 .word 0x20000db0
|
|
|
|
080071b0 <HAL_FLASHEx_Erase>:
|
|
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
|
*
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
|
{
|
|
80071b0: b5b0 push {r4, r5, r7, lr}
|
|
80071b2: b084 sub sp, #16
|
|
80071b4: af00 add r7, sp, #0
|
|
80071b6: 6078 str r0, [r7, #4]
|
|
80071b8: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|
80071ba: 230f movs r3, #15
|
|
80071bc: 18fb adds r3, r7, r3
|
|
80071be: 2201 movs r2, #1
|
|
80071c0: 701a strb r2, [r3, #0]
|
|
uint32_t address = 0U;
|
|
80071c2: 2300 movs r3, #0
|
|
80071c4: 60bb str r3, [r7, #8]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
80071c6: 4b32 ldr r3, [pc, #200] @ (8007290 <HAL_FLASHEx_Erase+0xe0>)
|
|
80071c8: 7e1b ldrb r3, [r3, #24]
|
|
80071ca: 2b01 cmp r3, #1
|
|
80071cc: d101 bne.n 80071d2 <HAL_FLASHEx_Erase+0x22>
|
|
80071ce: 2302 movs r3, #2
|
|
80071d0: e05a b.n 8007288 <HAL_FLASHEx_Erase+0xd8>
|
|
80071d2: 4b2f ldr r3, [pc, #188] @ (8007290 <HAL_FLASHEx_Erase+0xe0>)
|
|
80071d4: 2201 movs r2, #1
|
|
80071d6: 761a strb r2, [r3, #24]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
|
|
|
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
|
80071d8: 687b ldr r3, [r7, #4]
|
|
80071da: 681b ldr r3, [r3, #0]
|
|
80071dc: 2b01 cmp r3, #1
|
|
80071de: d116 bne.n 800720e <HAL_FLASHEx_Erase+0x5e>
|
|
{
|
|
/* Mass Erase requested for Bank1 */
|
|
/* Wait for last operation to be completed */
|
|
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
|
80071e0: 4b2c ldr r3, [pc, #176] @ (8007294 <HAL_FLASHEx_Erase+0xe4>)
|
|
80071e2: 0018 movs r0, r3
|
|
80071e4: f7ff ff74 bl 80070d0 <FLASH_WaitForLastOperation>
|
|
80071e8: 1e03 subs r3, r0, #0
|
|
80071ea: d147 bne.n 800727c <HAL_FLASHEx_Erase+0xcc>
|
|
{
|
|
/*Mass erase to be done*/
|
|
FLASH_MassErase();
|
|
80071ec: f000 f856 bl 800729c <FLASH_MassErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
80071f0: 230f movs r3, #15
|
|
80071f2: 18fc adds r4, r7, r3
|
|
80071f4: 4b27 ldr r3, [pc, #156] @ (8007294 <HAL_FLASHEx_Erase+0xe4>)
|
|
80071f6: 0018 movs r0, r3
|
|
80071f8: f7ff ff6a bl 80070d0 <FLASH_WaitForLastOperation>
|
|
80071fc: 0003 movs r3, r0
|
|
80071fe: 7023 strb r3, [r4, #0]
|
|
|
|
/* If the erase operation is completed, disable the MER Bit */
|
|
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
|
8007200: 4b25 ldr r3, [pc, #148] @ (8007298 <HAL_FLASHEx_Erase+0xe8>)
|
|
8007202: 691a ldr r2, [r3, #16]
|
|
8007204: 4b24 ldr r3, [pc, #144] @ (8007298 <HAL_FLASHEx_Erase+0xe8>)
|
|
8007206: 2104 movs r1, #4
|
|
8007208: 438a bics r2, r1
|
|
800720a: 611a str r2, [r3, #16]
|
|
800720c: e036 b.n 800727c <HAL_FLASHEx_Erase+0xcc>
|
|
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
|
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
|
|
|
/* Page Erase requested on address located on bank1 */
|
|
/* Wait for last operation to be completed */
|
|
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
|
800720e: 4b21 ldr r3, [pc, #132] @ (8007294 <HAL_FLASHEx_Erase+0xe4>)
|
|
8007210: 0018 movs r0, r3
|
|
8007212: f7ff ff5d bl 80070d0 <FLASH_WaitForLastOperation>
|
|
8007216: 1e03 subs r3, r0, #0
|
|
8007218: d130 bne.n 800727c <HAL_FLASHEx_Erase+0xcc>
|
|
{
|
|
/*Initialization of PageError variable*/
|
|
*PageError = 0xFFFFFFFFU;
|
|
800721a: 683b ldr r3, [r7, #0]
|
|
800721c: 2201 movs r2, #1
|
|
800721e: 4252 negs r2, r2
|
|
8007220: 601a str r2, [r3, #0]
|
|
|
|
/* Erase page by page to be done*/
|
|
for(address = pEraseInit->PageAddress;
|
|
8007222: 687b ldr r3, [r7, #4]
|
|
8007224: 685b ldr r3, [r3, #4]
|
|
8007226: 60bb str r3, [r7, #8]
|
|
8007228: e01f b.n 800726a <HAL_FLASHEx_Erase+0xba>
|
|
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
|
|
address += FLASH_PAGE_SIZE)
|
|
{
|
|
FLASH_PageErase(address);
|
|
800722a: 68bb ldr r3, [r7, #8]
|
|
800722c: 0018 movs r0, r3
|
|
800722e: f000 f84d bl 80072cc <FLASH_PageErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
8007232: 250f movs r5, #15
|
|
8007234: 197c adds r4, r7, r5
|
|
8007236: 4b17 ldr r3, [pc, #92] @ (8007294 <HAL_FLASHEx_Erase+0xe4>)
|
|
8007238: 0018 movs r0, r3
|
|
800723a: f7ff ff49 bl 80070d0 <FLASH_WaitForLastOperation>
|
|
800723e: 0003 movs r3, r0
|
|
8007240: 7023 strb r3, [r4, #0]
|
|
|
|
/* If the erase operation is completed, disable the PER Bit */
|
|
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
|
8007242: 4b15 ldr r3, [pc, #84] @ (8007298 <HAL_FLASHEx_Erase+0xe8>)
|
|
8007244: 691a ldr r2, [r3, #16]
|
|
8007246: 4b14 ldr r3, [pc, #80] @ (8007298 <HAL_FLASHEx_Erase+0xe8>)
|
|
8007248: 2102 movs r1, #2
|
|
800724a: 438a bics r2, r1
|
|
800724c: 611a str r2, [r3, #16]
|
|
|
|
if (status != HAL_OK)
|
|
800724e: 197b adds r3, r7, r5
|
|
8007250: 781b ldrb r3, [r3, #0]
|
|
8007252: 2b00 cmp r3, #0
|
|
8007254: d003 beq.n 800725e <HAL_FLASHEx_Erase+0xae>
|
|
{
|
|
/* In case of error, stop erase procedure and return the faulty address */
|
|
*PageError = address;
|
|
8007256: 683b ldr r3, [r7, #0]
|
|
8007258: 68ba ldr r2, [r7, #8]
|
|
800725a: 601a str r2, [r3, #0]
|
|
break;
|
|
800725c: e00e b.n 800727c <HAL_FLASHEx_Erase+0xcc>
|
|
address += FLASH_PAGE_SIZE)
|
|
800725e: 68bb ldr r3, [r7, #8]
|
|
8007260: 2280 movs r2, #128 @ 0x80
|
|
8007262: 0112 lsls r2, r2, #4
|
|
8007264: 4694 mov ip, r2
|
|
8007266: 4463 add r3, ip
|
|
8007268: 60bb str r3, [r7, #8]
|
|
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
|
|
800726a: 687b ldr r3, [r7, #4]
|
|
800726c: 689b ldr r3, [r3, #8]
|
|
800726e: 02da lsls r2, r3, #11
|
|
8007270: 687b ldr r3, [r7, #4]
|
|
8007272: 685b ldr r3, [r3, #4]
|
|
8007274: 18d3 adds r3, r2, r3
|
|
8007276: 68ba ldr r2, [r7, #8]
|
|
8007278: 429a cmp r2, r3
|
|
800727a: d3d6 bcc.n 800722a <HAL_FLASHEx_Erase+0x7a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
800727c: 4b04 ldr r3, [pc, #16] @ (8007290 <HAL_FLASHEx_Erase+0xe0>)
|
|
800727e: 2200 movs r2, #0
|
|
8007280: 761a strb r2, [r3, #24]
|
|
|
|
return status;
|
|
8007282: 230f movs r3, #15
|
|
8007284: 18fb adds r3, r7, r3
|
|
8007286: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8007288: 0018 movs r0, r3
|
|
800728a: 46bd mov sp, r7
|
|
800728c: b004 add sp, #16
|
|
800728e: bdb0 pop {r4, r5, r7, pc}
|
|
8007290: 20000db0 .word 0x20000db0
|
|
8007294: 0000c350 .word 0x0000c350
|
|
8007298: 40022000 .word 0x40022000
|
|
|
|
0800729c <FLASH_MassErase>:
|
|
* @brief Full erase of FLASH memory Bank
|
|
*
|
|
* @retval None
|
|
*/
|
|
static void FLASH_MassErase(void)
|
|
{
|
|
800729c: b580 push {r7, lr}
|
|
800729e: af00 add r7, sp, #0
|
|
/* Clean the error context */
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
80072a0: 4b08 ldr r3, [pc, #32] @ (80072c4 <FLASH_MassErase+0x28>)
|
|
80072a2: 2200 movs r2, #0
|
|
80072a4: 61da str r2, [r3, #28]
|
|
|
|
/* Only bank1 will be erased*/
|
|
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
|
80072a6: 4b08 ldr r3, [pc, #32] @ (80072c8 <FLASH_MassErase+0x2c>)
|
|
80072a8: 691a ldr r2, [r3, #16]
|
|
80072aa: 4b07 ldr r3, [pc, #28] @ (80072c8 <FLASH_MassErase+0x2c>)
|
|
80072ac: 2104 movs r1, #4
|
|
80072ae: 430a orrs r2, r1
|
|
80072b0: 611a str r2, [r3, #16]
|
|
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
80072b2: 4b05 ldr r3, [pc, #20] @ (80072c8 <FLASH_MassErase+0x2c>)
|
|
80072b4: 691a ldr r2, [r3, #16]
|
|
80072b6: 4b04 ldr r3, [pc, #16] @ (80072c8 <FLASH_MassErase+0x2c>)
|
|
80072b8: 2140 movs r1, #64 @ 0x40
|
|
80072ba: 430a orrs r2, r1
|
|
80072bc: 611a str r2, [r3, #16]
|
|
}
|
|
80072be: 46c0 nop @ (mov r8, r8)
|
|
80072c0: 46bd mov sp, r7
|
|
80072c2: bd80 pop {r7, pc}
|
|
80072c4: 20000db0 .word 0x20000db0
|
|
80072c8: 40022000 .word 0x40022000
|
|
|
|
080072cc <FLASH_PageErase>:
|
|
* The value of this parameter depend on device used within the same series
|
|
*
|
|
* @retval None
|
|
*/
|
|
void FLASH_PageErase(uint32_t PageAddress)
|
|
{
|
|
80072cc: b580 push {r7, lr}
|
|
80072ce: b082 sub sp, #8
|
|
80072d0: af00 add r7, sp, #0
|
|
80072d2: 6078 str r0, [r7, #4]
|
|
/* Clean the error context */
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
80072d4: 4b0a ldr r3, [pc, #40] @ (8007300 <FLASH_PageErase+0x34>)
|
|
80072d6: 2200 movs r2, #0
|
|
80072d8: 61da str r2, [r3, #28]
|
|
|
|
/* Proceed to erase the page */
|
|
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
|
80072da: 4b0a ldr r3, [pc, #40] @ (8007304 <FLASH_PageErase+0x38>)
|
|
80072dc: 691a ldr r2, [r3, #16]
|
|
80072de: 4b09 ldr r3, [pc, #36] @ (8007304 <FLASH_PageErase+0x38>)
|
|
80072e0: 2102 movs r1, #2
|
|
80072e2: 430a orrs r2, r1
|
|
80072e4: 611a str r2, [r3, #16]
|
|
WRITE_REG(FLASH->AR, PageAddress);
|
|
80072e6: 4b07 ldr r3, [pc, #28] @ (8007304 <FLASH_PageErase+0x38>)
|
|
80072e8: 687a ldr r2, [r7, #4]
|
|
80072ea: 615a str r2, [r3, #20]
|
|
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
80072ec: 4b05 ldr r3, [pc, #20] @ (8007304 <FLASH_PageErase+0x38>)
|
|
80072ee: 691a ldr r2, [r3, #16]
|
|
80072f0: 4b04 ldr r3, [pc, #16] @ (8007304 <FLASH_PageErase+0x38>)
|
|
80072f2: 2140 movs r1, #64 @ 0x40
|
|
80072f4: 430a orrs r2, r1
|
|
80072f6: 611a str r2, [r3, #16]
|
|
}
|
|
80072f8: 46c0 nop @ (mov r8, r8)
|
|
80072fa: 46bd mov sp, r7
|
|
80072fc: b002 add sp, #8
|
|
80072fe: bd80 pop {r7, pc}
|
|
8007300: 20000db0 .word 0x20000db0
|
|
8007304: 40022000 .word 0x40022000
|
|
|
|
08007308 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8007308: b580 push {r7, lr}
|
|
800730a: b086 sub sp, #24
|
|
800730c: af00 add r7, sp, #0
|
|
800730e: 6078 str r0, [r7, #4]
|
|
8007310: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8007312: 2300 movs r3, #0
|
|
8007314: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8007316: e155 b.n 80075c4 <HAL_GPIO_Init+0x2bc>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
8007318: 683b ldr r3, [r7, #0]
|
|
800731a: 681b ldr r3, [r3, #0]
|
|
800731c: 2101 movs r1, #1
|
|
800731e: 697a ldr r2, [r7, #20]
|
|
8007320: 4091 lsls r1, r2
|
|
8007322: 000a movs r2, r1
|
|
8007324: 4013 ands r3, r2
|
|
8007326: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8007328: 68fb ldr r3, [r7, #12]
|
|
800732a: 2b00 cmp r3, #0
|
|
800732c: d100 bne.n 8007330 <HAL_GPIO_Init+0x28>
|
|
800732e: e146 b.n 80075be <HAL_GPIO_Init+0x2b6>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8007330: 683b ldr r3, [r7, #0]
|
|
8007332: 685b ldr r3, [r3, #4]
|
|
8007334: 2b01 cmp r3, #1
|
|
8007336: d00b beq.n 8007350 <HAL_GPIO_Init+0x48>
|
|
8007338: 683b ldr r3, [r7, #0]
|
|
800733a: 685b ldr r3, [r3, #4]
|
|
800733c: 2b02 cmp r3, #2
|
|
800733e: d007 beq.n 8007350 <HAL_GPIO_Init+0x48>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8007340: 683b ldr r3, [r7, #0]
|
|
8007342: 685b ldr r3, [r3, #4]
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8007344: 2b11 cmp r3, #17
|
|
8007346: d003 beq.n 8007350 <HAL_GPIO_Init+0x48>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8007348: 683b ldr r3, [r7, #0]
|
|
800734a: 685b ldr r3, [r3, #4]
|
|
800734c: 2b12 cmp r3, #18
|
|
800734e: d130 bne.n 80073b2 <HAL_GPIO_Init+0xaa>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8007350: 687b ldr r3, [r7, #4]
|
|
8007352: 689b ldr r3, [r3, #8]
|
|
8007354: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
|
8007356: 697b ldr r3, [r7, #20]
|
|
8007358: 005b lsls r3, r3, #1
|
|
800735a: 2203 movs r2, #3
|
|
800735c: 409a lsls r2, r3
|
|
800735e: 0013 movs r3, r2
|
|
8007360: 43da mvns r2, r3
|
|
8007362: 693b ldr r3, [r7, #16]
|
|
8007364: 4013 ands r3, r2
|
|
8007366: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8007368: 683b ldr r3, [r7, #0]
|
|
800736a: 68da ldr r2, [r3, #12]
|
|
800736c: 697b ldr r3, [r7, #20]
|
|
800736e: 005b lsls r3, r3, #1
|
|
8007370: 409a lsls r2, r3
|
|
8007372: 0013 movs r3, r2
|
|
8007374: 693a ldr r2, [r7, #16]
|
|
8007376: 4313 orrs r3, r2
|
|
8007378: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
800737a: 687b ldr r3, [r7, #4]
|
|
800737c: 693a ldr r2, [r7, #16]
|
|
800737e: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8007380: 687b ldr r3, [r7, #4]
|
|
8007382: 685b ldr r3, [r3, #4]
|
|
8007384: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8007386: 2201 movs r2, #1
|
|
8007388: 697b ldr r3, [r7, #20]
|
|
800738a: 409a lsls r2, r3
|
|
800738c: 0013 movs r3, r2
|
|
800738e: 43da mvns r2, r3
|
|
8007390: 693b ldr r3, [r7, #16]
|
|
8007392: 4013 ands r3, r2
|
|
8007394: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
|
|
8007396: 683b ldr r3, [r7, #0]
|
|
8007398: 685b ldr r3, [r3, #4]
|
|
800739a: 091b lsrs r3, r3, #4
|
|
800739c: 2201 movs r2, #1
|
|
800739e: 401a ands r2, r3
|
|
80073a0: 697b ldr r3, [r7, #20]
|
|
80073a2: 409a lsls r2, r3
|
|
80073a4: 0013 movs r3, r2
|
|
80073a6: 693a ldr r2, [r7, #16]
|
|
80073a8: 4313 orrs r3, r2
|
|
80073aa: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
80073ac: 687b ldr r3, [r7, #4]
|
|
80073ae: 693a ldr r2, [r7, #16]
|
|
80073b0: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
80073b2: 687b ldr r3, [r7, #4]
|
|
80073b4: 68db ldr r3, [r3, #12]
|
|
80073b6: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
|
80073b8: 697b ldr r3, [r7, #20]
|
|
80073ba: 005b lsls r3, r3, #1
|
|
80073bc: 2203 movs r2, #3
|
|
80073be: 409a lsls r2, r3
|
|
80073c0: 0013 movs r3, r2
|
|
80073c2: 43da mvns r2, r3
|
|
80073c4: 693b ldr r3, [r7, #16]
|
|
80073c6: 4013 ands r3, r2
|
|
80073c8: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
80073ca: 683b ldr r3, [r7, #0]
|
|
80073cc: 689a ldr r2, [r3, #8]
|
|
80073ce: 697b ldr r3, [r7, #20]
|
|
80073d0: 005b lsls r3, r3, #1
|
|
80073d2: 409a lsls r2, r3
|
|
80073d4: 0013 movs r3, r2
|
|
80073d6: 693a ldr r2, [r7, #16]
|
|
80073d8: 4313 orrs r3, r2
|
|
80073da: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
80073dc: 687b ldr r3, [r7, #4]
|
|
80073de: 693a ldr r2, [r7, #16]
|
|
80073e0: 60da str r2, [r3, #12]
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
80073e2: 683b ldr r3, [r7, #0]
|
|
80073e4: 685b ldr r3, [r3, #4]
|
|
80073e6: 2b02 cmp r3, #2
|
|
80073e8: d003 beq.n 80073f2 <HAL_GPIO_Init+0xea>
|
|
80073ea: 683b ldr r3, [r7, #0]
|
|
80073ec: 685b ldr r3, [r3, #4]
|
|
80073ee: 2b12 cmp r3, #18
|
|
80073f0: d123 bne.n 800743a <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
80073f2: 697b ldr r3, [r7, #20]
|
|
80073f4: 08da lsrs r2, r3, #3
|
|
80073f6: 687b ldr r3, [r7, #4]
|
|
80073f8: 3208 adds r2, #8
|
|
80073fa: 0092 lsls r2, r2, #2
|
|
80073fc: 58d3 ldr r3, [r2, r3]
|
|
80073fe: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8007400: 697b ldr r3, [r7, #20]
|
|
8007402: 2207 movs r2, #7
|
|
8007404: 4013 ands r3, r2
|
|
8007406: 009b lsls r3, r3, #2
|
|
8007408: 220f movs r2, #15
|
|
800740a: 409a lsls r2, r3
|
|
800740c: 0013 movs r3, r2
|
|
800740e: 43da mvns r2, r3
|
|
8007410: 693b ldr r3, [r7, #16]
|
|
8007412: 4013 ands r3, r2
|
|
8007414: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8007416: 683b ldr r3, [r7, #0]
|
|
8007418: 691a ldr r2, [r3, #16]
|
|
800741a: 697b ldr r3, [r7, #20]
|
|
800741c: 2107 movs r1, #7
|
|
800741e: 400b ands r3, r1
|
|
8007420: 009b lsls r3, r3, #2
|
|
8007422: 409a lsls r2, r3
|
|
8007424: 0013 movs r3, r2
|
|
8007426: 693a ldr r2, [r7, #16]
|
|
8007428: 4313 orrs r3, r2
|
|
800742a: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
800742c: 697b ldr r3, [r7, #20]
|
|
800742e: 08da lsrs r2, r3, #3
|
|
8007430: 687b ldr r3, [r7, #4]
|
|
8007432: 3208 adds r2, #8
|
|
8007434: 0092 lsls r2, r2, #2
|
|
8007436: 6939 ldr r1, [r7, #16]
|
|
8007438: 50d1 str r1, [r2, r3]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
800743a: 687b ldr r3, [r7, #4]
|
|
800743c: 681b ldr r3, [r3, #0]
|
|
800743e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
|
8007440: 697b ldr r3, [r7, #20]
|
|
8007442: 005b lsls r3, r3, #1
|
|
8007444: 2203 movs r2, #3
|
|
8007446: 409a lsls r2, r3
|
|
8007448: 0013 movs r3, r2
|
|
800744a: 43da mvns r2, r3
|
|
800744c: 693b ldr r3, [r7, #16]
|
|
800744e: 4013 ands r3, r2
|
|
8007450: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8007452: 683b ldr r3, [r7, #0]
|
|
8007454: 685b ldr r3, [r3, #4]
|
|
8007456: 2203 movs r2, #3
|
|
8007458: 401a ands r2, r3
|
|
800745a: 697b ldr r3, [r7, #20]
|
|
800745c: 005b lsls r3, r3, #1
|
|
800745e: 409a lsls r2, r3
|
|
8007460: 0013 movs r3, r2
|
|
8007462: 693a ldr r2, [r7, #16]
|
|
8007464: 4313 orrs r3, r2
|
|
8007466: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8007468: 687b ldr r3, [r7, #4]
|
|
800746a: 693a ldr r2, [r7, #16]
|
|
800746c: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
800746e: 683b ldr r3, [r7, #0]
|
|
8007470: 685a ldr r2, [r3, #4]
|
|
8007472: 2380 movs r3, #128 @ 0x80
|
|
8007474: 055b lsls r3, r3, #21
|
|
8007476: 4013 ands r3, r2
|
|
8007478: d100 bne.n 800747c <HAL_GPIO_Init+0x174>
|
|
800747a: e0a0 b.n 80075be <HAL_GPIO_Init+0x2b6>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800747c: 4b57 ldr r3, [pc, #348] @ (80075dc <HAL_GPIO_Init+0x2d4>)
|
|
800747e: 699a ldr r2, [r3, #24]
|
|
8007480: 4b56 ldr r3, [pc, #344] @ (80075dc <HAL_GPIO_Init+0x2d4>)
|
|
8007482: 2101 movs r1, #1
|
|
8007484: 430a orrs r2, r1
|
|
8007486: 619a str r2, [r3, #24]
|
|
8007488: 4b54 ldr r3, [pc, #336] @ (80075dc <HAL_GPIO_Init+0x2d4>)
|
|
800748a: 699b ldr r3, [r3, #24]
|
|
800748c: 2201 movs r2, #1
|
|
800748e: 4013 ands r3, r2
|
|
8007490: 60bb str r3, [r7, #8]
|
|
8007492: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8007494: 4a52 ldr r2, [pc, #328] @ (80075e0 <HAL_GPIO_Init+0x2d8>)
|
|
8007496: 697b ldr r3, [r7, #20]
|
|
8007498: 089b lsrs r3, r3, #2
|
|
800749a: 3302 adds r3, #2
|
|
800749c: 009b lsls r3, r3, #2
|
|
800749e: 589b ldr r3, [r3, r2]
|
|
80074a0: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
80074a2: 697b ldr r3, [r7, #20]
|
|
80074a4: 2203 movs r2, #3
|
|
80074a6: 4013 ands r3, r2
|
|
80074a8: 009b lsls r3, r3, #2
|
|
80074aa: 220f movs r2, #15
|
|
80074ac: 409a lsls r2, r3
|
|
80074ae: 0013 movs r3, r2
|
|
80074b0: 43da mvns r2, r3
|
|
80074b2: 693b ldr r3, [r7, #16]
|
|
80074b4: 4013 ands r3, r2
|
|
80074b6: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
80074b8: 687a ldr r2, [r7, #4]
|
|
80074ba: 2390 movs r3, #144 @ 0x90
|
|
80074bc: 05db lsls r3, r3, #23
|
|
80074be: 429a cmp r2, r3
|
|
80074c0: d019 beq.n 80074f6 <HAL_GPIO_Init+0x1ee>
|
|
80074c2: 687b ldr r3, [r7, #4]
|
|
80074c4: 4a47 ldr r2, [pc, #284] @ (80075e4 <HAL_GPIO_Init+0x2dc>)
|
|
80074c6: 4293 cmp r3, r2
|
|
80074c8: d013 beq.n 80074f2 <HAL_GPIO_Init+0x1ea>
|
|
80074ca: 687b ldr r3, [r7, #4]
|
|
80074cc: 4a46 ldr r2, [pc, #280] @ (80075e8 <HAL_GPIO_Init+0x2e0>)
|
|
80074ce: 4293 cmp r3, r2
|
|
80074d0: d00d beq.n 80074ee <HAL_GPIO_Init+0x1e6>
|
|
80074d2: 687b ldr r3, [r7, #4]
|
|
80074d4: 4a45 ldr r2, [pc, #276] @ (80075ec <HAL_GPIO_Init+0x2e4>)
|
|
80074d6: 4293 cmp r3, r2
|
|
80074d8: d007 beq.n 80074ea <HAL_GPIO_Init+0x1e2>
|
|
80074da: 687b ldr r3, [r7, #4]
|
|
80074dc: 4a44 ldr r2, [pc, #272] @ (80075f0 <HAL_GPIO_Init+0x2e8>)
|
|
80074de: 4293 cmp r3, r2
|
|
80074e0: d101 bne.n 80074e6 <HAL_GPIO_Init+0x1de>
|
|
80074e2: 2304 movs r3, #4
|
|
80074e4: e008 b.n 80074f8 <HAL_GPIO_Init+0x1f0>
|
|
80074e6: 2305 movs r3, #5
|
|
80074e8: e006 b.n 80074f8 <HAL_GPIO_Init+0x1f0>
|
|
80074ea: 2303 movs r3, #3
|
|
80074ec: e004 b.n 80074f8 <HAL_GPIO_Init+0x1f0>
|
|
80074ee: 2302 movs r3, #2
|
|
80074f0: e002 b.n 80074f8 <HAL_GPIO_Init+0x1f0>
|
|
80074f2: 2301 movs r3, #1
|
|
80074f4: e000 b.n 80074f8 <HAL_GPIO_Init+0x1f0>
|
|
80074f6: 2300 movs r3, #0
|
|
80074f8: 697a ldr r2, [r7, #20]
|
|
80074fa: 2103 movs r1, #3
|
|
80074fc: 400a ands r2, r1
|
|
80074fe: 0092 lsls r2, r2, #2
|
|
8007500: 4093 lsls r3, r2
|
|
8007502: 693a ldr r2, [r7, #16]
|
|
8007504: 4313 orrs r3, r2
|
|
8007506: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8007508: 4935 ldr r1, [pc, #212] @ (80075e0 <HAL_GPIO_Init+0x2d8>)
|
|
800750a: 697b ldr r3, [r7, #20]
|
|
800750c: 089b lsrs r3, r3, #2
|
|
800750e: 3302 adds r3, #2
|
|
8007510: 009b lsls r3, r3, #2
|
|
8007512: 693a ldr r2, [r7, #16]
|
|
8007514: 505a str r2, [r3, r1]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8007516: 4b37 ldr r3, [pc, #220] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
8007518: 681b ldr r3, [r3, #0]
|
|
800751a: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800751c: 68fb ldr r3, [r7, #12]
|
|
800751e: 43da mvns r2, r3
|
|
8007520: 693b ldr r3, [r7, #16]
|
|
8007522: 4013 ands r3, r2
|
|
8007524: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8007526: 683b ldr r3, [r7, #0]
|
|
8007528: 685a ldr r2, [r3, #4]
|
|
800752a: 2380 movs r3, #128 @ 0x80
|
|
800752c: 025b lsls r3, r3, #9
|
|
800752e: 4013 ands r3, r2
|
|
8007530: d003 beq.n 800753a <HAL_GPIO_Init+0x232>
|
|
{
|
|
temp |= iocurrent;
|
|
8007532: 693a ldr r2, [r7, #16]
|
|
8007534: 68fb ldr r3, [r7, #12]
|
|
8007536: 4313 orrs r3, r2
|
|
8007538: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR = temp;
|
|
800753a: 4b2e ldr r3, [pc, #184] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
800753c: 693a ldr r2, [r7, #16]
|
|
800753e: 601a str r2, [r3, #0]
|
|
|
|
temp = EXTI->EMR;
|
|
8007540: 4b2c ldr r3, [pc, #176] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
8007542: 685b ldr r3, [r3, #4]
|
|
8007544: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8007546: 68fb ldr r3, [r7, #12]
|
|
8007548: 43da mvns r2, r3
|
|
800754a: 693b ldr r3, [r7, #16]
|
|
800754c: 4013 ands r3, r2
|
|
800754e: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8007550: 683b ldr r3, [r7, #0]
|
|
8007552: 685a ldr r2, [r3, #4]
|
|
8007554: 2380 movs r3, #128 @ 0x80
|
|
8007556: 029b lsls r3, r3, #10
|
|
8007558: 4013 ands r3, r2
|
|
800755a: d003 beq.n 8007564 <HAL_GPIO_Init+0x25c>
|
|
{
|
|
temp |= iocurrent;
|
|
800755c: 693a ldr r2, [r7, #16]
|
|
800755e: 68fb ldr r3, [r7, #12]
|
|
8007560: 4313 orrs r3, r2
|
|
8007562: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8007564: 4b23 ldr r3, [pc, #140] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
8007566: 693a ldr r2, [r7, #16]
|
|
8007568: 605a str r2, [r3, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
800756a: 4b22 ldr r3, [pc, #136] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
800756c: 689b ldr r3, [r3, #8]
|
|
800756e: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8007570: 68fb ldr r3, [r7, #12]
|
|
8007572: 43da mvns r2, r3
|
|
8007574: 693b ldr r3, [r7, #16]
|
|
8007576: 4013 ands r3, r2
|
|
8007578: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
800757a: 683b ldr r3, [r7, #0]
|
|
800757c: 685a ldr r2, [r3, #4]
|
|
800757e: 2380 movs r3, #128 @ 0x80
|
|
8007580: 035b lsls r3, r3, #13
|
|
8007582: 4013 ands r3, r2
|
|
8007584: d003 beq.n 800758e <HAL_GPIO_Init+0x286>
|
|
{
|
|
temp |= iocurrent;
|
|
8007586: 693a ldr r2, [r7, #16]
|
|
8007588: 68fb ldr r3, [r7, #12]
|
|
800758a: 4313 orrs r3, r2
|
|
800758c: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
800758e: 4b19 ldr r3, [pc, #100] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
8007590: 693a ldr r2, [r7, #16]
|
|
8007592: 609a str r2, [r3, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8007594: 4b17 ldr r3, [pc, #92] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
8007596: 68db ldr r3, [r3, #12]
|
|
8007598: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800759a: 68fb ldr r3, [r7, #12]
|
|
800759c: 43da mvns r2, r3
|
|
800759e: 693b ldr r3, [r7, #16]
|
|
80075a0: 4013 ands r3, r2
|
|
80075a2: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
80075a4: 683b ldr r3, [r7, #0]
|
|
80075a6: 685a ldr r2, [r3, #4]
|
|
80075a8: 2380 movs r3, #128 @ 0x80
|
|
80075aa: 039b lsls r3, r3, #14
|
|
80075ac: 4013 ands r3, r2
|
|
80075ae: d003 beq.n 80075b8 <HAL_GPIO_Init+0x2b0>
|
|
{
|
|
temp |= iocurrent;
|
|
80075b0: 693a ldr r2, [r7, #16]
|
|
80075b2: 68fb ldr r3, [r7, #12]
|
|
80075b4: 4313 orrs r3, r2
|
|
80075b6: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
80075b8: 4b0e ldr r3, [pc, #56] @ (80075f4 <HAL_GPIO_Init+0x2ec>)
|
|
80075ba: 693a ldr r2, [r7, #16]
|
|
80075bc: 60da str r2, [r3, #12]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
80075be: 697b ldr r3, [r7, #20]
|
|
80075c0: 3301 adds r3, #1
|
|
80075c2: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80075c4: 683b ldr r3, [r7, #0]
|
|
80075c6: 681a ldr r2, [r3, #0]
|
|
80075c8: 697b ldr r3, [r7, #20]
|
|
80075ca: 40da lsrs r2, r3
|
|
80075cc: 1e13 subs r3, r2, #0
|
|
80075ce: d000 beq.n 80075d2 <HAL_GPIO_Init+0x2ca>
|
|
80075d0: e6a2 b.n 8007318 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
80075d2: 46c0 nop @ (mov r8, r8)
|
|
80075d4: 46c0 nop @ (mov r8, r8)
|
|
80075d6: 46bd mov sp, r7
|
|
80075d8: b006 add sp, #24
|
|
80075da: bd80 pop {r7, pc}
|
|
80075dc: 40021000 .word 0x40021000
|
|
80075e0: 40010000 .word 0x40010000
|
|
80075e4: 48000400 .word 0x48000400
|
|
80075e8: 48000800 .word 0x48000800
|
|
80075ec: 48000c00 .word 0x48000c00
|
|
80075f0: 48001000 .word 0x48001000
|
|
80075f4: 40010400 .word 0x40010400
|
|
|
|
080075f8 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80075f8: b580 push {r7, lr}
|
|
80075fa: b082 sub sp, #8
|
|
80075fc: af00 add r7, sp, #0
|
|
80075fe: 6078 str r0, [r7, #4]
|
|
8007600: 0008 movs r0, r1
|
|
8007602: 0011 movs r1, r2
|
|
8007604: 1cbb adds r3, r7, #2
|
|
8007606: 1c02 adds r2, r0, #0
|
|
8007608: 801a strh r2, [r3, #0]
|
|
800760a: 1c7b adds r3, r7, #1
|
|
800760c: 1c0a adds r2, r1, #0
|
|
800760e: 701a strb r2, [r3, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8007610: 1c7b adds r3, r7, #1
|
|
8007612: 781b ldrb r3, [r3, #0]
|
|
8007614: 2b00 cmp r3, #0
|
|
8007616: d004 beq.n 8007622 <HAL_GPIO_WritePin+0x2a>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8007618: 1cbb adds r3, r7, #2
|
|
800761a: 881a ldrh r2, [r3, #0]
|
|
800761c: 687b ldr r3, [r7, #4]
|
|
800761e: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8007620: e003 b.n 800762a <HAL_GPIO_WritePin+0x32>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8007622: 1cbb adds r3, r7, #2
|
|
8007624: 881a ldrh r2, [r3, #0]
|
|
8007626: 687b ldr r3, [r7, #4]
|
|
8007628: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
800762a: 46c0 nop @ (mov r8, r8)
|
|
800762c: 46bd mov sp, r7
|
|
800762e: b002 add sp, #8
|
|
8007630: bd80 pop {r7, pc}
|
|
|
|
08007632 <HAL_GPIO_TogglePin>:
|
|
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
|
* @param GPIO_Pin specifies the pin to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8007632: b580 push {r7, lr}
|
|
8007634: b084 sub sp, #16
|
|
8007636: af00 add r7, sp, #0
|
|
8007638: 6078 str r0, [r7, #4]
|
|
800763a: 000a movs r2, r1
|
|
800763c: 1cbb adds r3, r7, #2
|
|
800763e: 801a strh r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Ouput Data Register value */
|
|
odr = GPIOx->ODR;
|
|
8007640: 687b ldr r3, [r7, #4]
|
|
8007642: 695b ldr r3, [r3, #20]
|
|
8007644: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
8007646: 1cbb adds r3, r7, #2
|
|
8007648: 881b ldrh r3, [r3, #0]
|
|
800764a: 68fa ldr r2, [r7, #12]
|
|
800764c: 4013 ands r3, r2
|
|
800764e: 041a lsls r2, r3, #16
|
|
8007650: 68fb ldr r3, [r7, #12]
|
|
8007652: 43db mvns r3, r3
|
|
8007654: 1cb9 adds r1, r7, #2
|
|
8007656: 8809 ldrh r1, [r1, #0]
|
|
8007658: 400b ands r3, r1
|
|
800765a: 431a orrs r2, r3
|
|
800765c: 687b ldr r3, [r7, #4]
|
|
800765e: 619a str r2, [r3, #24]
|
|
}
|
|
8007660: 46c0 nop @ (mov r8, r8)
|
|
8007662: 46bd mov sp, r7
|
|
8007664: b004 add sp, #16
|
|
8007666: bd80 pop {r7, pc}
|
|
|
|
08007668 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8007668: b580 push {r7, lr}
|
|
800766a: b088 sub sp, #32
|
|
800766c: af00 add r7, sp, #0
|
|
800766e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
uint32_t pll_config2;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8007670: 687b ldr r3, [r7, #4]
|
|
8007672: 2b00 cmp r3, #0
|
|
8007674: d102 bne.n 800767c <HAL_RCC_OscConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8007676: 2301 movs r3, #1
|
|
8007678: f000 fb76 bl 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800767c: 687b ldr r3, [r7, #4]
|
|
800767e: 681b ldr r3, [r3, #0]
|
|
8007680: 2201 movs r2, #1
|
|
8007682: 4013 ands r3, r2
|
|
8007684: d100 bne.n 8007688 <HAL_RCC_OscConfig+0x20>
|
|
8007686: e08e b.n 80077a6 <HAL_RCC_OscConfig+0x13e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8007688: 4bc5 ldr r3, [pc, #788] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800768a: 685b ldr r3, [r3, #4]
|
|
800768c: 220c movs r2, #12
|
|
800768e: 4013 ands r3, r2
|
|
8007690: 2b04 cmp r3, #4
|
|
8007692: d00e beq.n 80076b2 <HAL_RCC_OscConfig+0x4a>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8007694: 4bc2 ldr r3, [pc, #776] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007696: 685b ldr r3, [r3, #4]
|
|
8007698: 220c movs r2, #12
|
|
800769a: 4013 ands r3, r2
|
|
800769c: 2b08 cmp r3, #8
|
|
800769e: d117 bne.n 80076d0 <HAL_RCC_OscConfig+0x68>
|
|
80076a0: 4bbf ldr r3, [pc, #764] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076a2: 685a ldr r2, [r3, #4]
|
|
80076a4: 23c0 movs r3, #192 @ 0xc0
|
|
80076a6: 025b lsls r3, r3, #9
|
|
80076a8: 401a ands r2, r3
|
|
80076aa: 2380 movs r3, #128 @ 0x80
|
|
80076ac: 025b lsls r3, r3, #9
|
|
80076ae: 429a cmp r2, r3
|
|
80076b0: d10e bne.n 80076d0 <HAL_RCC_OscConfig+0x68>
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80076b2: 4bbb ldr r3, [pc, #748] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076b4: 681a ldr r2, [r3, #0]
|
|
80076b6: 2380 movs r3, #128 @ 0x80
|
|
80076b8: 029b lsls r3, r3, #10
|
|
80076ba: 4013 ands r3, r2
|
|
80076bc: d100 bne.n 80076c0 <HAL_RCC_OscConfig+0x58>
|
|
80076be: e071 b.n 80077a4 <HAL_RCC_OscConfig+0x13c>
|
|
80076c0: 687b ldr r3, [r7, #4]
|
|
80076c2: 685b ldr r3, [r3, #4]
|
|
80076c4: 2b00 cmp r3, #0
|
|
80076c6: d000 beq.n 80076ca <HAL_RCC_OscConfig+0x62>
|
|
80076c8: e06c b.n 80077a4 <HAL_RCC_OscConfig+0x13c>
|
|
{
|
|
return HAL_ERROR;
|
|
80076ca: 2301 movs r3, #1
|
|
80076cc: f000 fb4c bl 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80076d0: 687b ldr r3, [r7, #4]
|
|
80076d2: 685b ldr r3, [r3, #4]
|
|
80076d4: 2b01 cmp r3, #1
|
|
80076d6: d107 bne.n 80076e8 <HAL_RCC_OscConfig+0x80>
|
|
80076d8: 4bb1 ldr r3, [pc, #708] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076da: 681a ldr r2, [r3, #0]
|
|
80076dc: 4bb0 ldr r3, [pc, #704] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076de: 2180 movs r1, #128 @ 0x80
|
|
80076e0: 0249 lsls r1, r1, #9
|
|
80076e2: 430a orrs r2, r1
|
|
80076e4: 601a str r2, [r3, #0]
|
|
80076e6: e02f b.n 8007748 <HAL_RCC_OscConfig+0xe0>
|
|
80076e8: 687b ldr r3, [r7, #4]
|
|
80076ea: 685b ldr r3, [r3, #4]
|
|
80076ec: 2b00 cmp r3, #0
|
|
80076ee: d10c bne.n 800770a <HAL_RCC_OscConfig+0xa2>
|
|
80076f0: 4bab ldr r3, [pc, #684] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076f2: 681a ldr r2, [r3, #0]
|
|
80076f4: 4baa ldr r3, [pc, #680] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076f6: 49ab ldr r1, [pc, #684] @ (80079a4 <HAL_RCC_OscConfig+0x33c>)
|
|
80076f8: 400a ands r2, r1
|
|
80076fa: 601a str r2, [r3, #0]
|
|
80076fc: 4ba8 ldr r3, [pc, #672] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80076fe: 681a ldr r2, [r3, #0]
|
|
8007700: 4ba7 ldr r3, [pc, #668] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007702: 49a9 ldr r1, [pc, #676] @ (80079a8 <HAL_RCC_OscConfig+0x340>)
|
|
8007704: 400a ands r2, r1
|
|
8007706: 601a str r2, [r3, #0]
|
|
8007708: e01e b.n 8007748 <HAL_RCC_OscConfig+0xe0>
|
|
800770a: 687b ldr r3, [r7, #4]
|
|
800770c: 685b ldr r3, [r3, #4]
|
|
800770e: 2b05 cmp r3, #5
|
|
8007710: d10e bne.n 8007730 <HAL_RCC_OscConfig+0xc8>
|
|
8007712: 4ba3 ldr r3, [pc, #652] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007714: 681a ldr r2, [r3, #0]
|
|
8007716: 4ba2 ldr r3, [pc, #648] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007718: 2180 movs r1, #128 @ 0x80
|
|
800771a: 02c9 lsls r1, r1, #11
|
|
800771c: 430a orrs r2, r1
|
|
800771e: 601a str r2, [r3, #0]
|
|
8007720: 4b9f ldr r3, [pc, #636] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007722: 681a ldr r2, [r3, #0]
|
|
8007724: 4b9e ldr r3, [pc, #632] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007726: 2180 movs r1, #128 @ 0x80
|
|
8007728: 0249 lsls r1, r1, #9
|
|
800772a: 430a orrs r2, r1
|
|
800772c: 601a str r2, [r3, #0]
|
|
800772e: e00b b.n 8007748 <HAL_RCC_OscConfig+0xe0>
|
|
8007730: 4b9b ldr r3, [pc, #620] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007732: 681a ldr r2, [r3, #0]
|
|
8007734: 4b9a ldr r3, [pc, #616] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007736: 499b ldr r1, [pc, #620] @ (80079a4 <HAL_RCC_OscConfig+0x33c>)
|
|
8007738: 400a ands r2, r1
|
|
800773a: 601a str r2, [r3, #0]
|
|
800773c: 4b98 ldr r3, [pc, #608] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800773e: 681a ldr r2, [r3, #0]
|
|
8007740: 4b97 ldr r3, [pc, #604] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007742: 4999 ldr r1, [pc, #612] @ (80079a8 <HAL_RCC_OscConfig+0x340>)
|
|
8007744: 400a ands r2, r1
|
|
8007746: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8007748: 687b ldr r3, [r7, #4]
|
|
800774a: 685b ldr r3, [r3, #4]
|
|
800774c: 2b00 cmp r3, #0
|
|
800774e: d014 beq.n 800777a <HAL_RCC_OscConfig+0x112>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007750: f7ff f8cc bl 80068ec <HAL_GetTick>
|
|
8007754: 0003 movs r3, r0
|
|
8007756: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8007758: e008 b.n 800776c <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
800775a: f7ff f8c7 bl 80068ec <HAL_GetTick>
|
|
800775e: 0002 movs r2, r0
|
|
8007760: 69bb ldr r3, [r7, #24]
|
|
8007762: 1ad3 subs r3, r2, r3
|
|
8007764: 2b64 cmp r3, #100 @ 0x64
|
|
8007766: d901 bls.n 800776c <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007768: 2303 movs r3, #3
|
|
800776a: e2fd b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800776c: 4b8c ldr r3, [pc, #560] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800776e: 681a ldr r2, [r3, #0]
|
|
8007770: 2380 movs r3, #128 @ 0x80
|
|
8007772: 029b lsls r3, r3, #10
|
|
8007774: 4013 ands r3, r2
|
|
8007776: d0f0 beq.n 800775a <HAL_RCC_OscConfig+0xf2>
|
|
8007778: e015 b.n 80077a6 <HAL_RCC_OscConfig+0x13e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800777a: f7ff f8b7 bl 80068ec <HAL_GetTick>
|
|
800777e: 0003 movs r3, r0
|
|
8007780: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8007782: e008 b.n 8007796 <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8007784: f7ff f8b2 bl 80068ec <HAL_GetTick>
|
|
8007788: 0002 movs r2, r0
|
|
800778a: 69bb ldr r3, [r7, #24]
|
|
800778c: 1ad3 subs r3, r2, r3
|
|
800778e: 2b64 cmp r3, #100 @ 0x64
|
|
8007790: d901 bls.n 8007796 <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007792: 2303 movs r3, #3
|
|
8007794: e2e8 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8007796: 4b82 ldr r3, [pc, #520] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007798: 681a ldr r2, [r3, #0]
|
|
800779a: 2380 movs r3, #128 @ 0x80
|
|
800779c: 029b lsls r3, r3, #10
|
|
800779e: 4013 ands r3, r2
|
|
80077a0: d1f0 bne.n 8007784 <HAL_RCC_OscConfig+0x11c>
|
|
80077a2: e000 b.n 80077a6 <HAL_RCC_OscConfig+0x13e>
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80077a4: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80077a6: 687b ldr r3, [r7, #4]
|
|
80077a8: 681b ldr r3, [r3, #0]
|
|
80077aa: 2202 movs r2, #2
|
|
80077ac: 4013 ands r3, r2
|
|
80077ae: d100 bne.n 80077b2 <HAL_RCC_OscConfig+0x14a>
|
|
80077b0: e06c b.n 800788c <HAL_RCC_OscConfig+0x224>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80077b2: 4b7b ldr r3, [pc, #492] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80077b4: 685b ldr r3, [r3, #4]
|
|
80077b6: 220c movs r2, #12
|
|
80077b8: 4013 ands r3, r2
|
|
80077ba: d00e beq.n 80077da <HAL_RCC_OscConfig+0x172>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
|
|
80077bc: 4b78 ldr r3, [pc, #480] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80077be: 685b ldr r3, [r3, #4]
|
|
80077c0: 220c movs r2, #12
|
|
80077c2: 4013 ands r3, r2
|
|
80077c4: 2b08 cmp r3, #8
|
|
80077c6: d11f bne.n 8007808 <HAL_RCC_OscConfig+0x1a0>
|
|
80077c8: 4b75 ldr r3, [pc, #468] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80077ca: 685a ldr r2, [r3, #4]
|
|
80077cc: 23c0 movs r3, #192 @ 0xc0
|
|
80077ce: 025b lsls r3, r3, #9
|
|
80077d0: 401a ands r2, r3
|
|
80077d2: 2380 movs r3, #128 @ 0x80
|
|
80077d4: 021b lsls r3, r3, #8
|
|
80077d6: 429a cmp r2, r3
|
|
80077d8: d116 bne.n 8007808 <HAL_RCC_OscConfig+0x1a0>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
80077da: 4b71 ldr r3, [pc, #452] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80077dc: 681b ldr r3, [r3, #0]
|
|
80077de: 2202 movs r2, #2
|
|
80077e0: 4013 ands r3, r2
|
|
80077e2: d005 beq.n 80077f0 <HAL_RCC_OscConfig+0x188>
|
|
80077e4: 687b ldr r3, [r7, #4]
|
|
80077e6: 68db ldr r3, [r3, #12]
|
|
80077e8: 2b01 cmp r3, #1
|
|
80077ea: d001 beq.n 80077f0 <HAL_RCC_OscConfig+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
80077ec: 2301 movs r3, #1
|
|
80077ee: e2bb b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80077f0: 4b6b ldr r3, [pc, #428] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80077f2: 681b ldr r3, [r3, #0]
|
|
80077f4: 22f8 movs r2, #248 @ 0xf8
|
|
80077f6: 4393 bics r3, r2
|
|
80077f8: 0019 movs r1, r3
|
|
80077fa: 687b ldr r3, [r7, #4]
|
|
80077fc: 691b ldr r3, [r3, #16]
|
|
80077fe: 00da lsls r2, r3, #3
|
|
8007800: 4b67 ldr r3, [pc, #412] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007802: 430a orrs r2, r1
|
|
8007804: 601a str r2, [r3, #0]
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8007806: e041 b.n 800788c <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8007808: 687b ldr r3, [r7, #4]
|
|
800780a: 68db ldr r3, [r3, #12]
|
|
800780c: 2b00 cmp r3, #0
|
|
800780e: d024 beq.n 800785a <HAL_RCC_OscConfig+0x1f2>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8007810: 4b63 ldr r3, [pc, #396] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007812: 681a ldr r2, [r3, #0]
|
|
8007814: 4b62 ldr r3, [pc, #392] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007816: 2101 movs r1, #1
|
|
8007818: 430a orrs r2, r1
|
|
800781a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800781c: f7ff f866 bl 80068ec <HAL_GetTick>
|
|
8007820: 0003 movs r3, r0
|
|
8007822: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8007824: e008 b.n 8007838 <HAL_RCC_OscConfig+0x1d0>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
8007826: f7ff f861 bl 80068ec <HAL_GetTick>
|
|
800782a: 0002 movs r2, r0
|
|
800782c: 69bb ldr r3, [r7, #24]
|
|
800782e: 1ad3 subs r3, r2, r3
|
|
8007830: 2b02 cmp r3, #2
|
|
8007832: d901 bls.n 8007838 <HAL_RCC_OscConfig+0x1d0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007834: 2303 movs r3, #3
|
|
8007836: e297 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8007838: 4b59 ldr r3, [pc, #356] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800783a: 681b ldr r3, [r3, #0]
|
|
800783c: 2202 movs r2, #2
|
|
800783e: 4013 ands r3, r2
|
|
8007840: d0f1 beq.n 8007826 <HAL_RCC_OscConfig+0x1be>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8007842: 4b57 ldr r3, [pc, #348] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007844: 681b ldr r3, [r3, #0]
|
|
8007846: 22f8 movs r2, #248 @ 0xf8
|
|
8007848: 4393 bics r3, r2
|
|
800784a: 0019 movs r1, r3
|
|
800784c: 687b ldr r3, [r7, #4]
|
|
800784e: 691b ldr r3, [r3, #16]
|
|
8007850: 00da lsls r2, r3, #3
|
|
8007852: 4b53 ldr r3, [pc, #332] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007854: 430a orrs r2, r1
|
|
8007856: 601a str r2, [r3, #0]
|
|
8007858: e018 b.n 800788c <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800785a: 4b51 ldr r3, [pc, #324] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800785c: 681a ldr r2, [r3, #0]
|
|
800785e: 4b50 ldr r3, [pc, #320] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007860: 2101 movs r1, #1
|
|
8007862: 438a bics r2, r1
|
|
8007864: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007866: f7ff f841 bl 80068ec <HAL_GetTick>
|
|
800786a: 0003 movs r3, r0
|
|
800786c: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800786e: e008 b.n 8007882 <HAL_RCC_OscConfig+0x21a>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
8007870: f7ff f83c bl 80068ec <HAL_GetTick>
|
|
8007874: 0002 movs r2, r0
|
|
8007876: 69bb ldr r3, [r7, #24]
|
|
8007878: 1ad3 subs r3, r2, r3
|
|
800787a: 2b02 cmp r3, #2
|
|
800787c: d901 bls.n 8007882 <HAL_RCC_OscConfig+0x21a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800787e: 2303 movs r3, #3
|
|
8007880: e272 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8007882: 4b47 ldr r3, [pc, #284] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007884: 681b ldr r3, [r3, #0]
|
|
8007886: 2202 movs r2, #2
|
|
8007888: 4013 ands r3, r2
|
|
800788a: d1f1 bne.n 8007870 <HAL_RCC_OscConfig+0x208>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
800788c: 687b ldr r3, [r7, #4]
|
|
800788e: 681b ldr r3, [r3, #0]
|
|
8007890: 2208 movs r2, #8
|
|
8007892: 4013 ands r3, r2
|
|
8007894: d036 beq.n 8007904 <HAL_RCC_OscConfig+0x29c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8007896: 687b ldr r3, [r7, #4]
|
|
8007898: 69db ldr r3, [r3, #28]
|
|
800789a: 2b00 cmp r3, #0
|
|
800789c: d019 beq.n 80078d2 <HAL_RCC_OscConfig+0x26a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
800789e: 4b40 ldr r3, [pc, #256] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078a0: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80078a2: 4b3f ldr r3, [pc, #252] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078a4: 2101 movs r1, #1
|
|
80078a6: 430a orrs r2, r1
|
|
80078a8: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80078aa: f7ff f81f bl 80068ec <HAL_GetTick>
|
|
80078ae: 0003 movs r3, r0
|
|
80078b0: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80078b2: e008 b.n 80078c6 <HAL_RCC_OscConfig+0x25e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
80078b4: f7ff f81a bl 80068ec <HAL_GetTick>
|
|
80078b8: 0002 movs r2, r0
|
|
80078ba: 69bb ldr r3, [r7, #24]
|
|
80078bc: 1ad3 subs r3, r2, r3
|
|
80078be: 2b02 cmp r3, #2
|
|
80078c0: d901 bls.n 80078c6 <HAL_RCC_OscConfig+0x25e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80078c2: 2303 movs r3, #3
|
|
80078c4: e250 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80078c6: 4b36 ldr r3, [pc, #216] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078c8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80078ca: 2202 movs r2, #2
|
|
80078cc: 4013 ands r3, r2
|
|
80078ce: d0f1 beq.n 80078b4 <HAL_RCC_OscConfig+0x24c>
|
|
80078d0: e018 b.n 8007904 <HAL_RCC_OscConfig+0x29c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80078d2: 4b33 ldr r3, [pc, #204] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078d4: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80078d6: 4b32 ldr r3, [pc, #200] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078d8: 2101 movs r1, #1
|
|
80078da: 438a bics r2, r1
|
|
80078dc: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80078de: f7ff f805 bl 80068ec <HAL_GetTick>
|
|
80078e2: 0003 movs r3, r0
|
|
80078e4: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
80078e6: e008 b.n 80078fa <HAL_RCC_OscConfig+0x292>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
80078e8: f7ff f800 bl 80068ec <HAL_GetTick>
|
|
80078ec: 0002 movs r2, r0
|
|
80078ee: 69bb ldr r3, [r7, #24]
|
|
80078f0: 1ad3 subs r3, r2, r3
|
|
80078f2: 2b02 cmp r3, #2
|
|
80078f4: d901 bls.n 80078fa <HAL_RCC_OscConfig+0x292>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80078f6: 2303 movs r3, #3
|
|
80078f8: e236 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
80078fa: 4b29 ldr r3, [pc, #164] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
80078fc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80078fe: 2202 movs r2, #2
|
|
8007900: 4013 ands r3, r2
|
|
8007902: d1f1 bne.n 80078e8 <HAL_RCC_OscConfig+0x280>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8007904: 687b ldr r3, [r7, #4]
|
|
8007906: 681b ldr r3, [r3, #0]
|
|
8007908: 2204 movs r2, #4
|
|
800790a: 4013 ands r3, r2
|
|
800790c: d100 bne.n 8007910 <HAL_RCC_OscConfig+0x2a8>
|
|
800790e: e0b5 b.n 8007a7c <HAL_RCC_OscConfig+0x414>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8007910: 201f movs r0, #31
|
|
8007912: 183b adds r3, r7, r0
|
|
8007914: 2200 movs r2, #0
|
|
8007916: 701a strb r2, [r3, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8007918: 4b21 ldr r3, [pc, #132] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800791a: 69da ldr r2, [r3, #28]
|
|
800791c: 2380 movs r3, #128 @ 0x80
|
|
800791e: 055b lsls r3, r3, #21
|
|
8007920: 4013 ands r3, r2
|
|
8007922: d110 bne.n 8007946 <HAL_RCC_OscConfig+0x2de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8007924: 4b1e ldr r3, [pc, #120] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007926: 69da ldr r2, [r3, #28]
|
|
8007928: 4b1d ldr r3, [pc, #116] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
800792a: 2180 movs r1, #128 @ 0x80
|
|
800792c: 0549 lsls r1, r1, #21
|
|
800792e: 430a orrs r2, r1
|
|
8007930: 61da str r2, [r3, #28]
|
|
8007932: 4b1b ldr r3, [pc, #108] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007934: 69da ldr r2, [r3, #28]
|
|
8007936: 2380 movs r3, #128 @ 0x80
|
|
8007938: 055b lsls r3, r3, #21
|
|
800793a: 4013 ands r3, r2
|
|
800793c: 60fb str r3, [r7, #12]
|
|
800793e: 68fb ldr r3, [r7, #12]
|
|
pwrclkchanged = SET;
|
|
8007940: 183b adds r3, r7, r0
|
|
8007942: 2201 movs r2, #1
|
|
8007944: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8007946: 4b19 ldr r3, [pc, #100] @ (80079ac <HAL_RCC_OscConfig+0x344>)
|
|
8007948: 681a ldr r2, [r3, #0]
|
|
800794a: 2380 movs r3, #128 @ 0x80
|
|
800794c: 005b lsls r3, r3, #1
|
|
800794e: 4013 ands r3, r2
|
|
8007950: d11a bne.n 8007988 <HAL_RCC_OscConfig+0x320>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8007952: 4b16 ldr r3, [pc, #88] @ (80079ac <HAL_RCC_OscConfig+0x344>)
|
|
8007954: 681a ldr r2, [r3, #0]
|
|
8007956: 4b15 ldr r3, [pc, #84] @ (80079ac <HAL_RCC_OscConfig+0x344>)
|
|
8007958: 2180 movs r1, #128 @ 0x80
|
|
800795a: 0049 lsls r1, r1, #1
|
|
800795c: 430a orrs r2, r1
|
|
800795e: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8007960: f7fe ffc4 bl 80068ec <HAL_GetTick>
|
|
8007964: 0003 movs r3, r0
|
|
8007966: 61bb str r3, [r7, #24]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8007968: e008 b.n 800797c <HAL_RCC_OscConfig+0x314>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800796a: f7fe ffbf bl 80068ec <HAL_GetTick>
|
|
800796e: 0002 movs r2, r0
|
|
8007970: 69bb ldr r3, [r7, #24]
|
|
8007972: 1ad3 subs r3, r2, r3
|
|
8007974: 2b64 cmp r3, #100 @ 0x64
|
|
8007976: d901 bls.n 800797c <HAL_RCC_OscConfig+0x314>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007978: 2303 movs r3, #3
|
|
800797a: e1f5 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800797c: 4b0b ldr r3, [pc, #44] @ (80079ac <HAL_RCC_OscConfig+0x344>)
|
|
800797e: 681a ldr r2, [r3, #0]
|
|
8007980: 2380 movs r3, #128 @ 0x80
|
|
8007982: 005b lsls r3, r3, #1
|
|
8007984: 4013 ands r3, r2
|
|
8007986: d0f0 beq.n 800796a <HAL_RCC_OscConfig+0x302>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8007988: 687b ldr r3, [r7, #4]
|
|
800798a: 689b ldr r3, [r3, #8]
|
|
800798c: 2b01 cmp r3, #1
|
|
800798e: d10f bne.n 80079b0 <HAL_RCC_OscConfig+0x348>
|
|
8007990: 4b03 ldr r3, [pc, #12] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007992: 6a1a ldr r2, [r3, #32]
|
|
8007994: 4b02 ldr r3, [pc, #8] @ (80079a0 <HAL_RCC_OscConfig+0x338>)
|
|
8007996: 2101 movs r1, #1
|
|
8007998: 430a orrs r2, r1
|
|
800799a: 621a str r2, [r3, #32]
|
|
800799c: e036 b.n 8007a0c <HAL_RCC_OscConfig+0x3a4>
|
|
800799e: 46c0 nop @ (mov r8, r8)
|
|
80079a0: 40021000 .word 0x40021000
|
|
80079a4: fffeffff .word 0xfffeffff
|
|
80079a8: fffbffff .word 0xfffbffff
|
|
80079ac: 40007000 .word 0x40007000
|
|
80079b0: 687b ldr r3, [r7, #4]
|
|
80079b2: 689b ldr r3, [r3, #8]
|
|
80079b4: 2b00 cmp r3, #0
|
|
80079b6: d10c bne.n 80079d2 <HAL_RCC_OscConfig+0x36a>
|
|
80079b8: 4bca ldr r3, [pc, #808] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079ba: 6a1a ldr r2, [r3, #32]
|
|
80079bc: 4bc9 ldr r3, [pc, #804] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079be: 2101 movs r1, #1
|
|
80079c0: 438a bics r2, r1
|
|
80079c2: 621a str r2, [r3, #32]
|
|
80079c4: 4bc7 ldr r3, [pc, #796] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079c6: 6a1a ldr r2, [r3, #32]
|
|
80079c8: 4bc6 ldr r3, [pc, #792] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079ca: 2104 movs r1, #4
|
|
80079cc: 438a bics r2, r1
|
|
80079ce: 621a str r2, [r3, #32]
|
|
80079d0: e01c b.n 8007a0c <HAL_RCC_OscConfig+0x3a4>
|
|
80079d2: 687b ldr r3, [r7, #4]
|
|
80079d4: 689b ldr r3, [r3, #8]
|
|
80079d6: 2b05 cmp r3, #5
|
|
80079d8: d10c bne.n 80079f4 <HAL_RCC_OscConfig+0x38c>
|
|
80079da: 4bc2 ldr r3, [pc, #776] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079dc: 6a1a ldr r2, [r3, #32]
|
|
80079de: 4bc1 ldr r3, [pc, #772] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079e0: 2104 movs r1, #4
|
|
80079e2: 430a orrs r2, r1
|
|
80079e4: 621a str r2, [r3, #32]
|
|
80079e6: 4bbf ldr r3, [pc, #764] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079e8: 6a1a ldr r2, [r3, #32]
|
|
80079ea: 4bbe ldr r3, [pc, #760] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079ec: 2101 movs r1, #1
|
|
80079ee: 430a orrs r2, r1
|
|
80079f0: 621a str r2, [r3, #32]
|
|
80079f2: e00b b.n 8007a0c <HAL_RCC_OscConfig+0x3a4>
|
|
80079f4: 4bbb ldr r3, [pc, #748] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079f6: 6a1a ldr r2, [r3, #32]
|
|
80079f8: 4bba ldr r3, [pc, #744] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
80079fa: 2101 movs r1, #1
|
|
80079fc: 438a bics r2, r1
|
|
80079fe: 621a str r2, [r3, #32]
|
|
8007a00: 4bb8 ldr r3, [pc, #736] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a02: 6a1a ldr r2, [r3, #32]
|
|
8007a04: 4bb7 ldr r3, [pc, #732] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a06: 2104 movs r1, #4
|
|
8007a08: 438a bics r2, r1
|
|
8007a0a: 621a str r2, [r3, #32]
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8007a0c: 687b ldr r3, [r7, #4]
|
|
8007a0e: 689b ldr r3, [r3, #8]
|
|
8007a10: 2b00 cmp r3, #0
|
|
8007a12: d014 beq.n 8007a3e <HAL_RCC_OscConfig+0x3d6>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007a14: f7fe ff6a bl 80068ec <HAL_GetTick>
|
|
8007a18: 0003 movs r3, r0
|
|
8007a1a: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8007a1c: e009 b.n 8007a32 <HAL_RCC_OscConfig+0x3ca>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
8007a1e: f7fe ff65 bl 80068ec <HAL_GetTick>
|
|
8007a22: 0002 movs r2, r0
|
|
8007a24: 69bb ldr r3, [r7, #24]
|
|
8007a26: 1ad3 subs r3, r2, r3
|
|
8007a28: 4aaf ldr r2, [pc, #700] @ (8007ce8 <HAL_RCC_OscConfig+0x680>)
|
|
8007a2a: 4293 cmp r3, r2
|
|
8007a2c: d901 bls.n 8007a32 <HAL_RCC_OscConfig+0x3ca>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007a2e: 2303 movs r3, #3
|
|
8007a30: e19a b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8007a32: 4bac ldr r3, [pc, #688] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a34: 6a1b ldr r3, [r3, #32]
|
|
8007a36: 2202 movs r2, #2
|
|
8007a38: 4013 ands r3, r2
|
|
8007a3a: d0f0 beq.n 8007a1e <HAL_RCC_OscConfig+0x3b6>
|
|
8007a3c: e013 b.n 8007a66 <HAL_RCC_OscConfig+0x3fe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007a3e: f7fe ff55 bl 80068ec <HAL_GetTick>
|
|
8007a42: 0003 movs r3, r0
|
|
8007a44: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8007a46: e009 b.n 8007a5c <HAL_RCC_OscConfig+0x3f4>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
8007a48: f7fe ff50 bl 80068ec <HAL_GetTick>
|
|
8007a4c: 0002 movs r2, r0
|
|
8007a4e: 69bb ldr r3, [r7, #24]
|
|
8007a50: 1ad3 subs r3, r2, r3
|
|
8007a52: 4aa5 ldr r2, [pc, #660] @ (8007ce8 <HAL_RCC_OscConfig+0x680>)
|
|
8007a54: 4293 cmp r3, r2
|
|
8007a56: d901 bls.n 8007a5c <HAL_RCC_OscConfig+0x3f4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007a58: 2303 movs r3, #3
|
|
8007a5a: e185 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8007a5c: 4ba1 ldr r3, [pc, #644] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a5e: 6a1b ldr r3, [r3, #32]
|
|
8007a60: 2202 movs r2, #2
|
|
8007a62: 4013 ands r3, r2
|
|
8007a64: d1f0 bne.n 8007a48 <HAL_RCC_OscConfig+0x3e0>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
8007a66: 231f movs r3, #31
|
|
8007a68: 18fb adds r3, r7, r3
|
|
8007a6a: 781b ldrb r3, [r3, #0]
|
|
8007a6c: 2b01 cmp r3, #1
|
|
8007a6e: d105 bne.n 8007a7c <HAL_RCC_OscConfig+0x414>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8007a70: 4b9c ldr r3, [pc, #624] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a72: 69da ldr r2, [r3, #28]
|
|
8007a74: 4b9b ldr r3, [pc, #620] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a76: 499d ldr r1, [pc, #628] @ (8007cec <HAL_RCC_OscConfig+0x684>)
|
|
8007a78: 400a ands r2, r1
|
|
8007a7a: 61da str r2, [r3, #28]
|
|
}
|
|
}
|
|
|
|
/*----------------------------- HSI14 Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
|
|
8007a7c: 687b ldr r3, [r7, #4]
|
|
8007a7e: 681b ldr r3, [r3, #0]
|
|
8007a80: 2210 movs r2, #16
|
|
8007a82: 4013 ands r3, r2
|
|
8007a84: d063 beq.n 8007b4e <HAL_RCC_OscConfig+0x4e6>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
|
|
|
|
/* Check the HSI14 State */
|
|
if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
|
|
8007a86: 687b ldr r3, [r7, #4]
|
|
8007a88: 695b ldr r3, [r3, #20]
|
|
8007a8a: 2b01 cmp r3, #1
|
|
8007a8c: d12a bne.n 8007ae4 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
|
|
__HAL_RCC_HSI14ADC_DISABLE();
|
|
8007a8e: 4b95 ldr r3, [pc, #596] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a90: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007a92: 4b94 ldr r3, [pc, #592] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a94: 2104 movs r1, #4
|
|
8007a96: 430a orrs r2, r1
|
|
8007a98: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI14_ENABLE();
|
|
8007a9a: 4b92 ldr r3, [pc, #584] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007a9c: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007a9e: 4b91 ldr r3, [pc, #580] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007aa0: 2101 movs r1, #1
|
|
8007aa2: 430a orrs r2, r1
|
|
8007aa4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007aa6: f7fe ff21 bl 80068ec <HAL_GetTick>
|
|
8007aaa: 0003 movs r3, r0
|
|
8007aac: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
|
|
8007aae: e008 b.n 8007ac2 <HAL_RCC_OscConfig+0x45a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
|
|
8007ab0: f7fe ff1c bl 80068ec <HAL_GetTick>
|
|
8007ab4: 0002 movs r2, r0
|
|
8007ab6: 69bb ldr r3, [r7, #24]
|
|
8007ab8: 1ad3 subs r3, r2, r3
|
|
8007aba: 2b02 cmp r3, #2
|
|
8007abc: d901 bls.n 8007ac2 <HAL_RCC_OscConfig+0x45a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007abe: 2303 movs r3, #3
|
|
8007ac0: e152 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
|
|
8007ac2: 4b88 ldr r3, [pc, #544] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007ac4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007ac6: 2202 movs r2, #2
|
|
8007ac8: 4013 ands r3, r2
|
|
8007aca: d0f1 beq.n 8007ab0 <HAL_RCC_OscConfig+0x448>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
|
|
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
|
|
8007acc: 4b85 ldr r3, [pc, #532] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007ace: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007ad0: 22f8 movs r2, #248 @ 0xf8
|
|
8007ad2: 4393 bics r3, r2
|
|
8007ad4: 0019 movs r1, r3
|
|
8007ad6: 687b ldr r3, [r7, #4]
|
|
8007ad8: 699b ldr r3, [r3, #24]
|
|
8007ada: 00da lsls r2, r3, #3
|
|
8007adc: 4b81 ldr r3, [pc, #516] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007ade: 430a orrs r2, r1
|
|
8007ae0: 635a str r2, [r3, #52] @ 0x34
|
|
8007ae2: e034 b.n 8007b4e <HAL_RCC_OscConfig+0x4e6>
|
|
}
|
|
else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
|
|
8007ae4: 687b ldr r3, [r7, #4]
|
|
8007ae6: 695b ldr r3, [r3, #20]
|
|
8007ae8: 3305 adds r3, #5
|
|
8007aea: d111 bne.n 8007b10 <HAL_RCC_OscConfig+0x4a8>
|
|
{
|
|
/* Enable ADC control of the Internal High Speed oscillator HSI14 */
|
|
__HAL_RCC_HSI14ADC_ENABLE();
|
|
8007aec: 4b7d ldr r3, [pc, #500] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007aee: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007af0: 4b7c ldr r3, [pc, #496] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007af2: 2104 movs r1, #4
|
|
8007af4: 438a bics r2, r1
|
|
8007af6: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
|
|
__HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
|
|
8007af8: 4b7a ldr r3, [pc, #488] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007afa: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007afc: 22f8 movs r2, #248 @ 0xf8
|
|
8007afe: 4393 bics r3, r2
|
|
8007b00: 0019 movs r1, r3
|
|
8007b02: 687b ldr r3, [r7, #4]
|
|
8007b04: 699b ldr r3, [r3, #24]
|
|
8007b06: 00da lsls r2, r3, #3
|
|
8007b08: 4b76 ldr r3, [pc, #472] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b0a: 430a orrs r2, r1
|
|
8007b0c: 635a str r2, [r3, #52] @ 0x34
|
|
8007b0e: e01e b.n 8007b4e <HAL_RCC_OscConfig+0x4e6>
|
|
}
|
|
else
|
|
{
|
|
/* Disable ADC control of the Internal High Speed oscillator HSI14 */
|
|
__HAL_RCC_HSI14ADC_DISABLE();
|
|
8007b10: 4b74 ldr r3, [pc, #464] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b12: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007b14: 4b73 ldr r3, [pc, #460] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b16: 2104 movs r1, #4
|
|
8007b18: 430a orrs r2, r1
|
|
8007b1a: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI14_DISABLE();
|
|
8007b1c: 4b71 ldr r3, [pc, #452] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b1e: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007b20: 4b70 ldr r3, [pc, #448] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b22: 2101 movs r1, #1
|
|
8007b24: 438a bics r2, r1
|
|
8007b26: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007b28: f7fe fee0 bl 80068ec <HAL_GetTick>
|
|
8007b2c: 0003 movs r3, r0
|
|
8007b2e: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
|
|
8007b30: e008 b.n 8007b44 <HAL_RCC_OscConfig+0x4dc>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
|
|
8007b32: f7fe fedb bl 80068ec <HAL_GetTick>
|
|
8007b36: 0002 movs r2, r0
|
|
8007b38: 69bb ldr r3, [r7, #24]
|
|
8007b3a: 1ad3 subs r3, r2, r3
|
|
8007b3c: 2b02 cmp r3, #2
|
|
8007b3e: d901 bls.n 8007b44 <HAL_RCC_OscConfig+0x4dc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007b40: 2303 movs r3, #3
|
|
8007b42: e111 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
|
|
8007b44: 4b67 ldr r3, [pc, #412] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b46: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8007b48: 2202 movs r2, #2
|
|
8007b4a: 4013 ands r3, r2
|
|
8007b4c: d1f1 bne.n 8007b32 <HAL_RCC_OscConfig+0x4ca>
|
|
}
|
|
}
|
|
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|
/*----------------------------- HSI48 Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
8007b4e: 687b ldr r3, [r7, #4]
|
|
8007b50: 681b ldr r3, [r3, #0]
|
|
8007b52: 2220 movs r2, #32
|
|
8007b54: 4013 ands r3, r2
|
|
8007b56: d05c beq.n 8007c12 <HAL_RCC_OscConfig+0x5aa>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
/* When the HSI48 is used as system clock it is not allowed to be disabled */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
|
|
8007b58: 4b62 ldr r3, [pc, #392] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b5a: 685b ldr r3, [r3, #4]
|
|
8007b5c: 220c movs r2, #12
|
|
8007b5e: 4013 ands r3, r2
|
|
8007b60: 2b0c cmp r3, #12
|
|
8007b62: d00e beq.n 8007b82 <HAL_RCC_OscConfig+0x51a>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
|
|
8007b64: 4b5f ldr r3, [pc, #380] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b66: 685b ldr r3, [r3, #4]
|
|
8007b68: 220c movs r2, #12
|
|
8007b6a: 4013 ands r3, r2
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
|
|
8007b6c: 2b08 cmp r3, #8
|
|
8007b6e: d114 bne.n 8007b9a <HAL_RCC_OscConfig+0x532>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
|
|
8007b70: 4b5c ldr r3, [pc, #368] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b72: 685a ldr r2, [r3, #4]
|
|
8007b74: 23c0 movs r3, #192 @ 0xc0
|
|
8007b76: 025b lsls r3, r3, #9
|
|
8007b78: 401a ands r2, r3
|
|
8007b7a: 23c0 movs r3, #192 @ 0xc0
|
|
8007b7c: 025b lsls r3, r3, #9
|
|
8007b7e: 429a cmp r2, r3
|
|
8007b80: d10b bne.n 8007b9a <HAL_RCC_OscConfig+0x532>
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
|
|
8007b82: 4b58 ldr r3, [pc, #352] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007b84: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007b86: 2380 movs r3, #128 @ 0x80
|
|
8007b88: 025b lsls r3, r3, #9
|
|
8007b8a: 4013 ands r3, r2
|
|
8007b8c: d040 beq.n 8007c10 <HAL_RCC_OscConfig+0x5a8>
|
|
8007b8e: 687b ldr r3, [r7, #4]
|
|
8007b90: 6a1b ldr r3, [r3, #32]
|
|
8007b92: 2b01 cmp r3, #1
|
|
8007b94: d03c beq.n 8007c10 <HAL_RCC_OscConfig+0x5a8>
|
|
{
|
|
return HAL_ERROR;
|
|
8007b96: 2301 movs r3, #1
|
|
8007b98: e0e6 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI48 State */
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
8007b9a: 687b ldr r3, [r7, #4]
|
|
8007b9c: 6a1b ldr r3, [r3, #32]
|
|
8007b9e: 2b00 cmp r3, #0
|
|
8007ba0: d01b beq.n 8007bda <HAL_RCC_OscConfig+0x572>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
8007ba2: 4b50 ldr r3, [pc, #320] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007ba4: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007ba6: 4b4f ldr r3, [pc, #316] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007ba8: 2180 movs r1, #128 @ 0x80
|
|
8007baa: 0249 lsls r1, r1, #9
|
|
8007bac: 430a orrs r2, r1
|
|
8007bae: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007bb0: f7fe fe9c bl 80068ec <HAL_GetTick>
|
|
8007bb4: 0003 movs r3, r0
|
|
8007bb6: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
|
|
8007bb8: e008 b.n 8007bcc <HAL_RCC_OscConfig+0x564>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
8007bba: f7fe fe97 bl 80068ec <HAL_GetTick>
|
|
8007bbe: 0002 movs r2, r0
|
|
8007bc0: 69bb ldr r3, [r7, #24]
|
|
8007bc2: 1ad3 subs r3, r2, r3
|
|
8007bc4: 2b02 cmp r3, #2
|
|
8007bc6: d901 bls.n 8007bcc <HAL_RCC_OscConfig+0x564>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007bc8: 2303 movs r3, #3
|
|
8007bca: e0cd b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
|
|
8007bcc: 4b45 ldr r3, [pc, #276] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007bce: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007bd0: 2380 movs r3, #128 @ 0x80
|
|
8007bd2: 025b lsls r3, r3, #9
|
|
8007bd4: 4013 ands r3, r2
|
|
8007bd6: d0f0 beq.n 8007bba <HAL_RCC_OscConfig+0x552>
|
|
8007bd8: e01b b.n 8007c12 <HAL_RCC_OscConfig+0x5aa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
8007bda: 4b42 ldr r3, [pc, #264] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007bdc: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007bde: 4b41 ldr r3, [pc, #260] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007be0: 4943 ldr r1, [pc, #268] @ (8007cf0 <HAL_RCC_OscConfig+0x688>)
|
|
8007be2: 400a ands r2, r1
|
|
8007be4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007be6: f7fe fe81 bl 80068ec <HAL_GetTick>
|
|
8007bea: 0003 movs r3, r0
|
|
8007bec: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
|
|
8007bee: e008 b.n 8007c02 <HAL_RCC_OscConfig+0x59a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
8007bf0: f7fe fe7c bl 80068ec <HAL_GetTick>
|
|
8007bf4: 0002 movs r2, r0
|
|
8007bf6: 69bb ldr r3, [r7, #24]
|
|
8007bf8: 1ad3 subs r3, r2, r3
|
|
8007bfa: 2b02 cmp r3, #2
|
|
8007bfc: d901 bls.n 8007c02 <HAL_RCC_OscConfig+0x59a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007bfe: 2303 movs r3, #3
|
|
8007c00: e0b2 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
|
|
8007c02: 4b38 ldr r3, [pc, #224] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c04: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007c06: 2380 movs r3, #128 @ 0x80
|
|
8007c08: 025b lsls r3, r3, #9
|
|
8007c0a: 4013 ands r3, r2
|
|
8007c0c: d1f0 bne.n 8007bf0 <HAL_RCC_OscConfig+0x588>
|
|
8007c0e: e000 b.n 8007c12 <HAL_RCC_OscConfig+0x5aa>
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
|
|
8007c10: 46c0 nop @ (mov r8, r8)
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8007c12: 687b ldr r3, [r7, #4]
|
|
8007c14: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007c16: 2b00 cmp r3, #0
|
|
8007c18: d100 bne.n 8007c1c <HAL_RCC_OscConfig+0x5b4>
|
|
8007c1a: e0a4 b.n 8007d66 <HAL_RCC_OscConfig+0x6fe>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8007c1c: 4b31 ldr r3, [pc, #196] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c1e: 685b ldr r3, [r3, #4]
|
|
8007c20: 220c movs r2, #12
|
|
8007c22: 4013 ands r3, r2
|
|
8007c24: 2b08 cmp r3, #8
|
|
8007c26: d100 bne.n 8007c2a <HAL_RCC_OscConfig+0x5c2>
|
|
8007c28: e078 b.n 8007d1c <HAL_RCC_OscConfig+0x6b4>
|
|
{
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8007c2a: 687b ldr r3, [r7, #4]
|
|
8007c2c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007c2e: 2b02 cmp r3, #2
|
|
8007c30: d14c bne.n 8007ccc <HAL_RCC_OscConfig+0x664>
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8007c32: 4b2c ldr r3, [pc, #176] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c34: 681a ldr r2, [r3, #0]
|
|
8007c36: 4b2b ldr r3, [pc, #172] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c38: 492e ldr r1, [pc, #184] @ (8007cf4 <HAL_RCC_OscConfig+0x68c>)
|
|
8007c3a: 400a ands r2, r1
|
|
8007c3c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007c3e: f7fe fe55 bl 80068ec <HAL_GetTick>
|
|
8007c42: 0003 movs r3, r0
|
|
8007c44: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8007c46: e008 b.n 8007c5a <HAL_RCC_OscConfig+0x5f2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8007c48: f7fe fe50 bl 80068ec <HAL_GetTick>
|
|
8007c4c: 0002 movs r2, r0
|
|
8007c4e: 69bb ldr r3, [r7, #24]
|
|
8007c50: 1ad3 subs r3, r2, r3
|
|
8007c52: 2b02 cmp r3, #2
|
|
8007c54: d901 bls.n 8007c5a <HAL_RCC_OscConfig+0x5f2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007c56: 2303 movs r3, #3
|
|
8007c58: e086 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8007c5a: 4b22 ldr r3, [pc, #136] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c5c: 681a ldr r2, [r3, #0]
|
|
8007c5e: 2380 movs r3, #128 @ 0x80
|
|
8007c60: 049b lsls r3, r3, #18
|
|
8007c62: 4013 ands r3, r2
|
|
8007c64: d1f0 bne.n 8007c48 <HAL_RCC_OscConfig+0x5e0>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, predivider and multiplication factor. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8007c66: 4b1f ldr r3, [pc, #124] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c68: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007c6a: 220f movs r2, #15
|
|
8007c6c: 4393 bics r3, r2
|
|
8007c6e: 0019 movs r1, r3
|
|
8007c70: 687b ldr r3, [r7, #4]
|
|
8007c72: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8007c74: 4b1b ldr r3, [pc, #108] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c76: 430a orrs r2, r1
|
|
8007c78: 62da str r2, [r3, #44] @ 0x2c
|
|
8007c7a: 4b1a ldr r3, [pc, #104] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c7c: 685b ldr r3, [r3, #4]
|
|
8007c7e: 4a1e ldr r2, [pc, #120] @ (8007cf8 <HAL_RCC_OscConfig+0x690>)
|
|
8007c80: 4013 ands r3, r2
|
|
8007c82: 0019 movs r1, r3
|
|
8007c84: 687b ldr r3, [r7, #4]
|
|
8007c86: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8007c88: 687b ldr r3, [r7, #4]
|
|
8007c8a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007c8c: 431a orrs r2, r3
|
|
8007c8e: 4b15 ldr r3, [pc, #84] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c90: 430a orrs r2, r1
|
|
8007c92: 605a str r2, [r3, #4]
|
|
RCC_OscInitStruct->PLL.PREDIV,
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8007c94: 4b13 ldr r3, [pc, #76] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c96: 681a ldr r2, [r3, #0]
|
|
8007c98: 4b12 ldr r3, [pc, #72] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007c9a: 2180 movs r1, #128 @ 0x80
|
|
8007c9c: 0449 lsls r1, r1, #17
|
|
8007c9e: 430a orrs r2, r1
|
|
8007ca0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007ca2: f7fe fe23 bl 80068ec <HAL_GetTick>
|
|
8007ca6: 0003 movs r3, r0
|
|
8007ca8: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8007caa: e008 b.n 8007cbe <HAL_RCC_OscConfig+0x656>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8007cac: f7fe fe1e bl 80068ec <HAL_GetTick>
|
|
8007cb0: 0002 movs r2, r0
|
|
8007cb2: 69bb ldr r3, [r7, #24]
|
|
8007cb4: 1ad3 subs r3, r2, r3
|
|
8007cb6: 2b02 cmp r3, #2
|
|
8007cb8: d901 bls.n 8007cbe <HAL_RCC_OscConfig+0x656>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007cba: 2303 movs r3, #3
|
|
8007cbc: e054 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8007cbe: 4b09 ldr r3, [pc, #36] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007cc0: 681a ldr r2, [r3, #0]
|
|
8007cc2: 2380 movs r3, #128 @ 0x80
|
|
8007cc4: 049b lsls r3, r3, #18
|
|
8007cc6: 4013 ands r3, r2
|
|
8007cc8: d0f0 beq.n 8007cac <HAL_RCC_OscConfig+0x644>
|
|
8007cca: e04c b.n 8007d66 <HAL_RCC_OscConfig+0x6fe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8007ccc: 4b05 ldr r3, [pc, #20] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007cce: 681a ldr r2, [r3, #0]
|
|
8007cd0: 4b04 ldr r3, [pc, #16] @ (8007ce4 <HAL_RCC_OscConfig+0x67c>)
|
|
8007cd2: 4908 ldr r1, [pc, #32] @ (8007cf4 <HAL_RCC_OscConfig+0x68c>)
|
|
8007cd4: 400a ands r2, r1
|
|
8007cd6: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007cd8: f7fe fe08 bl 80068ec <HAL_GetTick>
|
|
8007cdc: 0003 movs r3, r0
|
|
8007cde: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8007ce0: e015 b.n 8007d0e <HAL_RCC_OscConfig+0x6a6>
|
|
8007ce2: 46c0 nop @ (mov r8, r8)
|
|
8007ce4: 40021000 .word 0x40021000
|
|
8007ce8: 00001388 .word 0x00001388
|
|
8007cec: efffffff .word 0xefffffff
|
|
8007cf0: fffeffff .word 0xfffeffff
|
|
8007cf4: feffffff .word 0xfeffffff
|
|
8007cf8: ffc27fff .word 0xffc27fff
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8007cfc: f7fe fdf6 bl 80068ec <HAL_GetTick>
|
|
8007d00: 0002 movs r2, r0
|
|
8007d02: 69bb ldr r3, [r7, #24]
|
|
8007d04: 1ad3 subs r3, r2, r3
|
|
8007d06: 2b02 cmp r3, #2
|
|
8007d08: d901 bls.n 8007d0e <HAL_RCC_OscConfig+0x6a6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007d0a: 2303 movs r3, #3
|
|
8007d0c: e02c b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8007d0e: 4b18 ldr r3, [pc, #96] @ (8007d70 <HAL_RCC_OscConfig+0x708>)
|
|
8007d10: 681a ldr r2, [r3, #0]
|
|
8007d12: 2380 movs r3, #128 @ 0x80
|
|
8007d14: 049b lsls r3, r3, #18
|
|
8007d16: 4013 ands r3, r2
|
|
8007d18: d1f0 bne.n 8007cfc <HAL_RCC_OscConfig+0x694>
|
|
8007d1a: e024 b.n 8007d66 <HAL_RCC_OscConfig+0x6fe>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8007d1c: 687b ldr r3, [r7, #4]
|
|
8007d1e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007d20: 2b01 cmp r3, #1
|
|
8007d22: d101 bne.n 8007d28 <HAL_RCC_OscConfig+0x6c0>
|
|
{
|
|
return HAL_ERROR;
|
|
8007d24: 2301 movs r3, #1
|
|
8007d26: e01f b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8007d28: 4b11 ldr r3, [pc, #68] @ (8007d70 <HAL_RCC_OscConfig+0x708>)
|
|
8007d2a: 685b ldr r3, [r3, #4]
|
|
8007d2c: 617b str r3, [r7, #20]
|
|
pll_config2 = RCC->CFGR2;
|
|
8007d2e: 4b10 ldr r3, [pc, #64] @ (8007d70 <HAL_RCC_OscConfig+0x708>)
|
|
8007d30: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007d32: 613b str r3, [r7, #16]
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8007d34: 697a ldr r2, [r7, #20]
|
|
8007d36: 23c0 movs r3, #192 @ 0xc0
|
|
8007d38: 025b lsls r3, r3, #9
|
|
8007d3a: 401a ands r2, r3
|
|
8007d3c: 687b ldr r3, [r7, #4]
|
|
8007d3e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007d40: 429a cmp r2, r3
|
|
8007d42: d10e bne.n 8007d62 <HAL_RCC_OscConfig+0x6fa>
|
|
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
|
|
8007d44: 693b ldr r3, [r7, #16]
|
|
8007d46: 220f movs r2, #15
|
|
8007d48: 401a ands r2, r3
|
|
8007d4a: 687b ldr r3, [r7, #4]
|
|
8007d4c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8007d4e: 429a cmp r2, r3
|
|
8007d50: d107 bne.n 8007d62 <HAL_RCC_OscConfig+0x6fa>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8007d52: 697a ldr r2, [r7, #20]
|
|
8007d54: 23f0 movs r3, #240 @ 0xf0
|
|
8007d56: 039b lsls r3, r3, #14
|
|
8007d58: 401a ands r2, r3
|
|
8007d5a: 687b ldr r3, [r7, #4]
|
|
8007d5c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
|
|
8007d5e: 429a cmp r2, r3
|
|
8007d60: d001 beq.n 8007d66 <HAL_RCC_OscConfig+0x6fe>
|
|
{
|
|
return HAL_ERROR;
|
|
8007d62: 2301 movs r3, #1
|
|
8007d64: e000 b.n 8007d68 <HAL_RCC_OscConfig+0x700>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007d66: 2300 movs r3, #0
|
|
}
|
|
8007d68: 0018 movs r0, r3
|
|
8007d6a: 46bd mov sp, r7
|
|
8007d6c: b008 add sp, #32
|
|
8007d6e: bd80 pop {r7, pc}
|
|
8007d70: 40021000 .word 0x40021000
|
|
|
|
08007d74 <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8007d74: b580 push {r7, lr}
|
|
8007d76: b084 sub sp, #16
|
|
8007d78: af00 add r7, sp, #0
|
|
8007d7a: 6078 str r0, [r7, #4]
|
|
8007d7c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
8007d7e: 687b ldr r3, [r7, #4]
|
|
8007d80: 2b00 cmp r3, #0
|
|
8007d82: d101 bne.n 8007d88 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8007d84: 2301 movs r3, #1
|
|
8007d86: e0bf b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8007d88: 4b61 ldr r3, [pc, #388] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007d8a: 681b ldr r3, [r3, #0]
|
|
8007d8c: 2201 movs r2, #1
|
|
8007d8e: 4013 ands r3, r2
|
|
8007d90: 683a ldr r2, [r7, #0]
|
|
8007d92: 429a cmp r2, r3
|
|
8007d94: d911 bls.n 8007dba <HAL_RCC_ClockConfig+0x46>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8007d96: 4b5e ldr r3, [pc, #376] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007d98: 681b ldr r3, [r3, #0]
|
|
8007d9a: 2201 movs r2, #1
|
|
8007d9c: 4393 bics r3, r2
|
|
8007d9e: 0019 movs r1, r3
|
|
8007da0: 4b5b ldr r3, [pc, #364] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007da2: 683a ldr r2, [r7, #0]
|
|
8007da4: 430a orrs r2, r1
|
|
8007da6: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8007da8: 4b59 ldr r3, [pc, #356] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007daa: 681b ldr r3, [r3, #0]
|
|
8007dac: 2201 movs r2, #1
|
|
8007dae: 4013 ands r3, r2
|
|
8007db0: 683a ldr r2, [r7, #0]
|
|
8007db2: 429a cmp r2, r3
|
|
8007db4: d001 beq.n 8007dba <HAL_RCC_ClockConfig+0x46>
|
|
{
|
|
return HAL_ERROR;
|
|
8007db6: 2301 movs r3, #1
|
|
8007db8: e0a6 b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8007dba: 687b ldr r3, [r7, #4]
|
|
8007dbc: 681b ldr r3, [r3, #0]
|
|
8007dbe: 2202 movs r2, #2
|
|
8007dc0: 4013 ands r3, r2
|
|
8007dc2: d015 beq.n 8007df0 <HAL_RCC_ClockConfig+0x7c>
|
|
{
|
|
/* Set the highest APB divider in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8007dc4: 687b ldr r3, [r7, #4]
|
|
8007dc6: 681b ldr r3, [r3, #0]
|
|
8007dc8: 2204 movs r2, #4
|
|
8007dca: 4013 ands r3, r2
|
|
8007dcc: d006 beq.n 8007ddc <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
|
|
8007dce: 4b51 ldr r3, [pc, #324] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007dd0: 685a ldr r2, [r3, #4]
|
|
8007dd2: 4b50 ldr r3, [pc, #320] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007dd4: 21e0 movs r1, #224 @ 0xe0
|
|
8007dd6: 00c9 lsls r1, r1, #3
|
|
8007dd8: 430a orrs r2, r1
|
|
8007dda: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8007ddc: 4b4d ldr r3, [pc, #308] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007dde: 685b ldr r3, [r3, #4]
|
|
8007de0: 22f0 movs r2, #240 @ 0xf0
|
|
8007de2: 4393 bics r3, r2
|
|
8007de4: 0019 movs r1, r3
|
|
8007de6: 687b ldr r3, [r7, #4]
|
|
8007de8: 689a ldr r2, [r3, #8]
|
|
8007dea: 4b4a ldr r3, [pc, #296] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007dec: 430a orrs r2, r1
|
|
8007dee: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8007df0: 687b ldr r3, [r7, #4]
|
|
8007df2: 681b ldr r3, [r3, #0]
|
|
8007df4: 2201 movs r2, #1
|
|
8007df6: 4013 ands r3, r2
|
|
8007df8: d04c beq.n 8007e94 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8007dfa: 687b ldr r3, [r7, #4]
|
|
8007dfc: 685b ldr r3, [r3, #4]
|
|
8007dfe: 2b01 cmp r3, #1
|
|
8007e00: d107 bne.n 8007e12 <HAL_RCC_ClockConfig+0x9e>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8007e02: 4b44 ldr r3, [pc, #272] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e04: 681a ldr r2, [r3, #0]
|
|
8007e06: 2380 movs r3, #128 @ 0x80
|
|
8007e08: 029b lsls r3, r3, #10
|
|
8007e0a: 4013 ands r3, r2
|
|
8007e0c: d120 bne.n 8007e50 <HAL_RCC_ClockConfig+0xdc>
|
|
{
|
|
return HAL_ERROR;
|
|
8007e0e: 2301 movs r3, #1
|
|
8007e10: e07a b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8007e12: 687b ldr r3, [r7, #4]
|
|
8007e14: 685b ldr r3, [r3, #4]
|
|
8007e16: 2b02 cmp r3, #2
|
|
8007e18: d107 bne.n 8007e2a <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8007e1a: 4b3e ldr r3, [pc, #248] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e1c: 681a ldr r2, [r3, #0]
|
|
8007e1e: 2380 movs r3, #128 @ 0x80
|
|
8007e20: 049b lsls r3, r3, #18
|
|
8007e22: 4013 ands r3, r2
|
|
8007e24: d114 bne.n 8007e50 <HAL_RCC_ClockConfig+0xdc>
|
|
{
|
|
return HAL_ERROR;
|
|
8007e26: 2301 movs r3, #1
|
|
8007e28: e06e b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
}
|
|
}
|
|
#if defined(RCC_CFGR_SWS_HSI48)
|
|
/* HSI48 is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
|
|
8007e2a: 687b ldr r3, [r7, #4]
|
|
8007e2c: 685b ldr r3, [r3, #4]
|
|
8007e2e: 2b03 cmp r3, #3
|
|
8007e30: d107 bne.n 8007e42 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the HSI48 ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
|
|
8007e32: 4b38 ldr r3, [pc, #224] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e34: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8007e36: 2380 movs r3, #128 @ 0x80
|
|
8007e38: 025b lsls r3, r3, #9
|
|
8007e3a: 4013 ands r3, r2
|
|
8007e3c: d108 bne.n 8007e50 <HAL_RCC_ClockConfig+0xdc>
|
|
{
|
|
return HAL_ERROR;
|
|
8007e3e: 2301 movs r3, #1
|
|
8007e40: e062 b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
#endif /* RCC_CFGR_SWS_HSI48 */
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8007e42: 4b34 ldr r3, [pc, #208] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e44: 681b ldr r3, [r3, #0]
|
|
8007e46: 2202 movs r2, #2
|
|
8007e48: 4013 ands r3, r2
|
|
8007e4a: d101 bne.n 8007e50 <HAL_RCC_ClockConfig+0xdc>
|
|
{
|
|
return HAL_ERROR;
|
|
8007e4c: 2301 movs r3, #1
|
|
8007e4e: e05b b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8007e50: 4b30 ldr r3, [pc, #192] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e52: 685b ldr r3, [r3, #4]
|
|
8007e54: 2203 movs r2, #3
|
|
8007e56: 4393 bics r3, r2
|
|
8007e58: 0019 movs r1, r3
|
|
8007e5a: 687b ldr r3, [r7, #4]
|
|
8007e5c: 685a ldr r2, [r3, #4]
|
|
8007e5e: 4b2d ldr r3, [pc, #180] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e60: 430a orrs r2, r1
|
|
8007e62: 605a str r2, [r3, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8007e64: f7fe fd42 bl 80068ec <HAL_GetTick>
|
|
8007e68: 0003 movs r3, r0
|
|
8007e6a: 60fb str r3, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8007e6c: e009 b.n 8007e82 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8007e6e: f7fe fd3d bl 80068ec <HAL_GetTick>
|
|
8007e72: 0002 movs r2, r0
|
|
8007e74: 68fb ldr r3, [r7, #12]
|
|
8007e76: 1ad3 subs r3, r2, r3
|
|
8007e78: 4a27 ldr r2, [pc, #156] @ (8007f18 <HAL_RCC_ClockConfig+0x1a4>)
|
|
8007e7a: 4293 cmp r3, r2
|
|
8007e7c: d901 bls.n 8007e82 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007e7e: 2303 movs r3, #3
|
|
8007e80: e042 b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8007e82: 4b24 ldr r3, [pc, #144] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007e84: 685b ldr r3, [r3, #4]
|
|
8007e86: 220c movs r2, #12
|
|
8007e88: 401a ands r2, r3
|
|
8007e8a: 687b ldr r3, [r7, #4]
|
|
8007e8c: 685b ldr r3, [r3, #4]
|
|
8007e8e: 009b lsls r3, r3, #2
|
|
8007e90: 429a cmp r2, r3
|
|
8007e92: d1ec bne.n 8007e6e <HAL_RCC_ClockConfig+0xfa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8007e94: 4b1e ldr r3, [pc, #120] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007e96: 681b ldr r3, [r3, #0]
|
|
8007e98: 2201 movs r2, #1
|
|
8007e9a: 4013 ands r3, r2
|
|
8007e9c: 683a ldr r2, [r7, #0]
|
|
8007e9e: 429a cmp r2, r3
|
|
8007ea0: d211 bcs.n 8007ec6 <HAL_RCC_ClockConfig+0x152>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8007ea2: 4b1b ldr r3, [pc, #108] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007ea4: 681b ldr r3, [r3, #0]
|
|
8007ea6: 2201 movs r2, #1
|
|
8007ea8: 4393 bics r3, r2
|
|
8007eaa: 0019 movs r1, r3
|
|
8007eac: 4b18 ldr r3, [pc, #96] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007eae: 683a ldr r2, [r7, #0]
|
|
8007eb0: 430a orrs r2, r1
|
|
8007eb2: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8007eb4: 4b16 ldr r3, [pc, #88] @ (8007f10 <HAL_RCC_ClockConfig+0x19c>)
|
|
8007eb6: 681b ldr r3, [r3, #0]
|
|
8007eb8: 2201 movs r2, #1
|
|
8007eba: 4013 ands r3, r2
|
|
8007ebc: 683a ldr r2, [r7, #0]
|
|
8007ebe: 429a cmp r2, r3
|
|
8007ec0: d001 beq.n 8007ec6 <HAL_RCC_ClockConfig+0x152>
|
|
{
|
|
return HAL_ERROR;
|
|
8007ec2: 2301 movs r3, #1
|
|
8007ec4: e020 b.n 8007f08 <HAL_RCC_ClockConfig+0x194>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8007ec6: 687b ldr r3, [r7, #4]
|
|
8007ec8: 681b ldr r3, [r3, #0]
|
|
8007eca: 2204 movs r2, #4
|
|
8007ecc: 4013 ands r3, r2
|
|
8007ece: d009 beq.n 8007ee4 <HAL_RCC_ClockConfig+0x170>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8007ed0: 4b10 ldr r3, [pc, #64] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007ed2: 685b ldr r3, [r3, #4]
|
|
8007ed4: 4a11 ldr r2, [pc, #68] @ (8007f1c <HAL_RCC_ClockConfig+0x1a8>)
|
|
8007ed6: 4013 ands r3, r2
|
|
8007ed8: 0019 movs r1, r3
|
|
8007eda: 687b ldr r3, [r7, #4]
|
|
8007edc: 68da ldr r2, [r3, #12]
|
|
8007ede: 4b0d ldr r3, [pc, #52] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007ee0: 430a orrs r2, r1
|
|
8007ee2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
|
|
8007ee4: f000 f820 bl 8007f28 <HAL_RCC_GetSysClockFreq>
|
|
8007ee8: 0001 movs r1, r0
|
|
8007eea: 4b0a ldr r3, [pc, #40] @ (8007f14 <HAL_RCC_ClockConfig+0x1a0>)
|
|
8007eec: 685b ldr r3, [r3, #4]
|
|
8007eee: 091b lsrs r3, r3, #4
|
|
8007ef0: 220f movs r2, #15
|
|
8007ef2: 4013 ands r3, r2
|
|
8007ef4: 4a0a ldr r2, [pc, #40] @ (8007f20 <HAL_RCC_ClockConfig+0x1ac>)
|
|
8007ef6: 5cd3 ldrb r3, [r2, r3]
|
|
8007ef8: 000a movs r2, r1
|
|
8007efa: 40da lsrs r2, r3
|
|
8007efc: 4b09 ldr r3, [pc, #36] @ (8007f24 <HAL_RCC_ClockConfig+0x1b0>)
|
|
8007efe: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick (TICK_INT_PRIORITY);
|
|
8007f00: 2000 movs r0, #0
|
|
8007f02: f7fe fcad bl 8006860 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8007f06: 2300 movs r3, #0
|
|
}
|
|
8007f08: 0018 movs r0, r3
|
|
8007f0a: 46bd mov sp, r7
|
|
8007f0c: b004 add sp, #16
|
|
8007f0e: bd80 pop {r7, pc}
|
|
8007f10: 40022000 .word 0x40022000
|
|
8007f14: 40021000 .word 0x40021000
|
|
8007f18: 00001388 .word 0x00001388
|
|
8007f1c: fffff8ff .word 0xfffff8ff
|
|
8007f20: 08008ae0 .word 0x08008ae0
|
|
8007f24: 20000004 .word 0x20000004
|
|
|
|
08007f28 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8007f28: b590 push {r4, r7, lr}
|
|
8007f2a: b08f sub sp, #60 @ 0x3c
|
|
8007f2c: af00 add r7, sp, #0
|
|
const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
|
|
8007f2e: 2314 movs r3, #20
|
|
8007f30: 18fb adds r3, r7, r3
|
|
8007f32: 4a38 ldr r2, [pc, #224] @ (8008014 <HAL_RCC_GetSysClockFreq+0xec>)
|
|
8007f34: ca13 ldmia r2!, {r0, r1, r4}
|
|
8007f36: c313 stmia r3!, {r0, r1, r4}
|
|
8007f38: 6812 ldr r2, [r2, #0]
|
|
8007f3a: 601a str r2, [r3, #0]
|
|
10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
|
|
const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
|
|
8007f3c: 1d3b adds r3, r7, #4
|
|
8007f3e: 4a36 ldr r2, [pc, #216] @ (8008018 <HAL_RCC_GetSysClockFreq+0xf0>)
|
|
8007f40: ca13 ldmia r2!, {r0, r1, r4}
|
|
8007f42: c313 stmia r3!, {r0, r1, r4}
|
|
8007f44: 6812 ldr r2, [r2, #0]
|
|
8007f46: 601a str r2, [r3, #0]
|
|
9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
|
|
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
8007f48: 2300 movs r3, #0
|
|
8007f4a: 62fb str r3, [r7, #44] @ 0x2c
|
|
8007f4c: 2300 movs r3, #0
|
|
8007f4e: 62bb str r3, [r7, #40] @ 0x28
|
|
8007f50: 2300 movs r3, #0
|
|
8007f52: 637b str r3, [r7, #52] @ 0x34
|
|
8007f54: 2300 movs r3, #0
|
|
8007f56: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t sysclockfreq = 0U;
|
|
8007f58: 2300 movs r3, #0
|
|
8007f5a: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
tmpreg = RCC->CFGR;
|
|
8007f5c: 4b2f ldr r3, [pc, #188] @ (800801c <HAL_RCC_GetSysClockFreq+0xf4>)
|
|
8007f5e: 685b ldr r3, [r3, #4]
|
|
8007f60: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8007f62: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8007f64: 220c movs r2, #12
|
|
8007f66: 4013 ands r3, r2
|
|
8007f68: 2b0c cmp r3, #12
|
|
8007f6a: d047 beq.n 8007ffc <HAL_RCC_GetSysClockFreq+0xd4>
|
|
8007f6c: d849 bhi.n 8008002 <HAL_RCC_GetSysClockFreq+0xda>
|
|
8007f6e: 2b04 cmp r3, #4
|
|
8007f70: d002 beq.n 8007f78 <HAL_RCC_GetSysClockFreq+0x50>
|
|
8007f72: 2b08 cmp r3, #8
|
|
8007f74: d003 beq.n 8007f7e <HAL_RCC_GetSysClockFreq+0x56>
|
|
8007f76: e044 b.n 8008002 <HAL_RCC_GetSysClockFreq+0xda>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8007f78: 4b29 ldr r3, [pc, #164] @ (8008020 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8007f7a: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8007f7c: e044 b.n 8008008 <HAL_RCC_GetSysClockFreq+0xe0>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
|
|
8007f7e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8007f80: 0c9b lsrs r3, r3, #18
|
|
8007f82: 220f movs r2, #15
|
|
8007f84: 4013 ands r3, r2
|
|
8007f86: 2214 movs r2, #20
|
|
8007f88: 18ba adds r2, r7, r2
|
|
8007f8a: 5cd3 ldrb r3, [r2, r3]
|
|
8007f8c: 627b str r3, [r7, #36] @ 0x24
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
|
|
8007f8e: 4b23 ldr r3, [pc, #140] @ (800801c <HAL_RCC_GetSysClockFreq+0xf4>)
|
|
8007f90: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007f92: 220f movs r2, #15
|
|
8007f94: 4013 ands r3, r2
|
|
8007f96: 1d3a adds r2, r7, #4
|
|
8007f98: 5cd3 ldrb r3, [r2, r3]
|
|
8007f9a: 62bb str r3, [r7, #40] @ 0x28
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
|
|
8007f9c: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8007f9e: 23c0 movs r3, #192 @ 0xc0
|
|
8007fa0: 025b lsls r3, r3, #9
|
|
8007fa2: 401a ands r2, r3
|
|
8007fa4: 2380 movs r3, #128 @ 0x80
|
|
8007fa6: 025b lsls r3, r3, #9
|
|
8007fa8: 429a cmp r2, r3
|
|
8007faa: d109 bne.n 8007fc0 <HAL_RCC_GetSysClockFreq+0x98>
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
8007fac: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8007fae: 481c ldr r0, [pc, #112] @ (8008020 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8007fb0: f7f8 f8aa bl 8000108 <__udivsi3>
|
|
8007fb4: 0003 movs r3, r0
|
|
8007fb6: 001a movs r2, r3
|
|
8007fb8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007fba: 4353 muls r3, r2
|
|
8007fbc: 637b str r3, [r7, #52] @ 0x34
|
|
8007fbe: e01a b.n 8007ff6 <HAL_RCC_GetSysClockFreq+0xce>
|
|
}
|
|
#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
|
else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
|
|
8007fc0: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8007fc2: 23c0 movs r3, #192 @ 0xc0
|
|
8007fc4: 025b lsls r3, r3, #9
|
|
8007fc6: 401a ands r2, r3
|
|
8007fc8: 23c0 movs r3, #192 @ 0xc0
|
|
8007fca: 025b lsls r3, r3, #9
|
|
8007fcc: 429a cmp r2, r3
|
|
8007fce: d109 bne.n 8007fe4 <HAL_RCC_GetSysClockFreq+0xbc>
|
|
{
|
|
/* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
8007fd0: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8007fd2: 4814 ldr r0, [pc, #80] @ (8008024 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
8007fd4: f7f8 f898 bl 8000108 <__udivsi3>
|
|
8007fd8: 0003 movs r3, r0
|
|
8007fda: 001a movs r2, r3
|
|
8007fdc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007fde: 4353 muls r3, r2
|
|
8007fe0: 637b str r3, [r7, #52] @ 0x34
|
|
8007fe2: e008 b.n 8007ff6 <HAL_RCC_GetSysClockFreq+0xce>
|
|
#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
|
|
else
|
|
{
|
|
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
8007fe4: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8007fe6: 480e ldr r0, [pc, #56] @ (8008020 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8007fe8: f7f8 f88e bl 8000108 <__udivsi3>
|
|
8007fec: 0003 movs r3, r0
|
|
8007fee: 001a movs r2, r3
|
|
8007ff0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007ff2: 4353 muls r3, r2
|
|
8007ff4: 637b str r3, [r7, #52] @ 0x34
|
|
#else
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
|
|
#endif
|
|
}
|
|
sysclockfreq = pllclk;
|
|
8007ff6: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8007ff8: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8007ffa: e005 b.n 8008008 <HAL_RCC_GetSysClockFreq+0xe0>
|
|
}
|
|
#if defined(RCC_CFGR_SWS_HSI48)
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
|
|
{
|
|
sysclockfreq = HSI48_VALUE;
|
|
8007ffc: 4b09 ldr r3, [pc, #36] @ (8008024 <HAL_RCC_GetSysClockFreq+0xfc>)
|
|
8007ffe: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8008000: e002 b.n 8008008 <HAL_RCC_GetSysClockFreq+0xe0>
|
|
}
|
|
#endif /* RCC_CFGR_SWS_HSI48 */
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8008002: 4b07 ldr r3, [pc, #28] @ (8008020 <HAL_RCC_GetSysClockFreq+0xf8>)
|
|
8008004: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8008006: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8008008: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
}
|
|
800800a: 0018 movs r0, r3
|
|
800800c: 46bd mov sp, r7
|
|
800800e: b00f add sp, #60 @ 0x3c
|
|
8008010: bd90 pop {r4, r7, pc}
|
|
8008012: 46c0 nop @ (mov r8, r8)
|
|
8008014: 08008994 .word 0x08008994
|
|
8008018: 080089a4 .word 0x080089a4
|
|
800801c: 40021000 .word 0x40021000
|
|
8008020: 007a1200 .word 0x007a1200
|
|
8008024: 02dc6c00 .word 0x02dc6c00
|
|
|
|
08008028 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8008028: b580 push {r7, lr}
|
|
800802a: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
800802c: 4b02 ldr r3, [pc, #8] @ (8008038 <HAL_RCC_GetHCLKFreq+0x10>)
|
|
800802e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8008030: 0018 movs r0, r3
|
|
8008032: 46bd mov sp, r7
|
|
8008034: bd80 pop {r7, pc}
|
|
8008036: 46c0 nop @ (mov r8, r8)
|
|
8008038: 20000004 .word 0x20000004
|
|
|
|
0800803c <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
800803c: b580 push {r7, lr}
|
|
800803e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
|
|
8008040: f7ff fff2 bl 8008028 <HAL_RCC_GetHCLKFreq>
|
|
8008044: 0001 movs r1, r0
|
|
8008046: 4b06 ldr r3, [pc, #24] @ (8008060 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8008048: 685b ldr r3, [r3, #4]
|
|
800804a: 0a1b lsrs r3, r3, #8
|
|
800804c: 2207 movs r2, #7
|
|
800804e: 4013 ands r3, r2
|
|
8008050: 4a04 ldr r2, [pc, #16] @ (8008064 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
8008052: 5cd3 ldrb r3, [r2, r3]
|
|
8008054: 40d9 lsrs r1, r3
|
|
8008056: 000b movs r3, r1
|
|
}
|
|
8008058: 0018 movs r0, r3
|
|
800805a: 46bd mov sp, r7
|
|
800805c: bd80 pop {r7, pc}
|
|
800805e: 46c0 nop @ (mov r8, r8)
|
|
8008060: 40021000 .word 0x40021000
|
|
8008064: 08008af0 .word 0x08008af0
|
|
|
|
08008068 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8008068: b580 push {r7, lr}
|
|
800806a: b086 sub sp, #24
|
|
800806c: af00 add r7, sp, #0
|
|
800806e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8008070: 2300 movs r3, #0
|
|
8008072: 613b str r3, [r7, #16]
|
|
uint32_t temp_reg = 0U;
|
|
8008074: 2300 movs r3, #0
|
|
8008076: 60fb str r3, [r7, #12]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*---------------------------- RTC configuration -------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
8008078: 687b ldr r3, [r7, #4]
|
|
800807a: 681a ldr r2, [r3, #0]
|
|
800807c: 2380 movs r3, #128 @ 0x80
|
|
800807e: 025b lsls r3, r3, #9
|
|
8008080: 4013 ands r3, r2
|
|
8008082: d100 bne.n 8008086 <HAL_RCCEx_PeriphCLKConfig+0x1e>
|
|
8008084: e08e b.n 80081a4 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
{
|
|
/* check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8008086: 2017 movs r0, #23
|
|
8008088: 183b adds r3, r7, r0
|
|
800808a: 2200 movs r2, #0
|
|
800808c: 701a strb r2, [r3, #0]
|
|
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|
power domain is done. */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800808e: 4b6e ldr r3, [pc, #440] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008090: 69da ldr r2, [r3, #28]
|
|
8008092: 2380 movs r3, #128 @ 0x80
|
|
8008094: 055b lsls r3, r3, #21
|
|
8008096: 4013 ands r3, r2
|
|
8008098: d110 bne.n 80080bc <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800809a: 4b6b ldr r3, [pc, #428] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800809c: 69da ldr r2, [r3, #28]
|
|
800809e: 4b6a ldr r3, [pc, #424] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80080a0: 2180 movs r1, #128 @ 0x80
|
|
80080a2: 0549 lsls r1, r1, #21
|
|
80080a4: 430a orrs r2, r1
|
|
80080a6: 61da str r2, [r3, #28]
|
|
80080a8: 4b67 ldr r3, [pc, #412] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80080aa: 69da ldr r2, [r3, #28]
|
|
80080ac: 2380 movs r3, #128 @ 0x80
|
|
80080ae: 055b lsls r3, r3, #21
|
|
80080b0: 4013 ands r3, r2
|
|
80080b2: 60bb str r3, [r7, #8]
|
|
80080b4: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
80080b6: 183b adds r3, r7, r0
|
|
80080b8: 2201 movs r2, #1
|
|
80080ba: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80080bc: 4b63 ldr r3, [pc, #396] @ (800824c <HAL_RCCEx_PeriphCLKConfig+0x1e4>)
|
|
80080be: 681a ldr r2, [r3, #0]
|
|
80080c0: 2380 movs r3, #128 @ 0x80
|
|
80080c2: 005b lsls r3, r3, #1
|
|
80080c4: 4013 ands r3, r2
|
|
80080c6: d11a bne.n 80080fe <HAL_RCCEx_PeriphCLKConfig+0x96>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
80080c8: 4b60 ldr r3, [pc, #384] @ (800824c <HAL_RCCEx_PeriphCLKConfig+0x1e4>)
|
|
80080ca: 681a ldr r2, [r3, #0]
|
|
80080cc: 4b5f ldr r3, [pc, #380] @ (800824c <HAL_RCCEx_PeriphCLKConfig+0x1e4>)
|
|
80080ce: 2180 movs r1, #128 @ 0x80
|
|
80080d0: 0049 lsls r1, r1, #1
|
|
80080d2: 430a orrs r2, r1
|
|
80080d4: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80080d6: f7fe fc09 bl 80068ec <HAL_GetTick>
|
|
80080da: 0003 movs r3, r0
|
|
80080dc: 613b str r3, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80080de: e008 b.n 80080f2 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80080e0: f7fe fc04 bl 80068ec <HAL_GetTick>
|
|
80080e4: 0002 movs r2, r0
|
|
80080e6: 693b ldr r3, [r7, #16]
|
|
80080e8: 1ad3 subs r3, r2, r3
|
|
80080ea: 2b64 cmp r3, #100 @ 0x64
|
|
80080ec: d901 bls.n 80080f2 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80080ee: 2303 movs r3, #3
|
|
80080f0: e0a6 b.n 8008240 <HAL_RCCEx_PeriphCLKConfig+0x1d8>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80080f2: 4b56 ldr r3, [pc, #344] @ (800824c <HAL_RCCEx_PeriphCLKConfig+0x1e4>)
|
|
80080f4: 681a ldr r2, [r3, #0]
|
|
80080f6: 2380 movs r3, #128 @ 0x80
|
|
80080f8: 005b lsls r3, r3, #1
|
|
80080fa: 4013 ands r3, r2
|
|
80080fc: d0f0 beq.n 80080e0 <HAL_RCCEx_PeriphCLKConfig+0x78>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80080fe: 4b52 ldr r3, [pc, #328] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008100: 6a1a ldr r2, [r3, #32]
|
|
8008102: 23c0 movs r3, #192 @ 0xc0
|
|
8008104: 009b lsls r3, r3, #2
|
|
8008106: 4013 ands r3, r2
|
|
8008108: 60fb str r3, [r7, #12]
|
|
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
800810a: 68fb ldr r3, [r7, #12]
|
|
800810c: 2b00 cmp r3, #0
|
|
800810e: d034 beq.n 800817a <HAL_RCCEx_PeriphCLKConfig+0x112>
|
|
8008110: 687b ldr r3, [r7, #4]
|
|
8008112: 685a ldr r2, [r3, #4]
|
|
8008114: 23c0 movs r3, #192 @ 0xc0
|
|
8008116: 009b lsls r3, r3, #2
|
|
8008118: 4013 ands r3, r2
|
|
800811a: 68fa ldr r2, [r7, #12]
|
|
800811c: 429a cmp r2, r3
|
|
800811e: d02c beq.n 800817a <HAL_RCCEx_PeriphCLKConfig+0x112>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8008120: 4b49 ldr r3, [pc, #292] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008122: 6a1b ldr r3, [r3, #32]
|
|
8008124: 4a4a ldr r2, [pc, #296] @ (8008250 <HAL_RCCEx_PeriphCLKConfig+0x1e8>)
|
|
8008126: 4013 ands r3, r2
|
|
8008128: 60fb str r3, [r7, #12]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
800812a: 4b47 ldr r3, [pc, #284] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800812c: 6a1a ldr r2, [r3, #32]
|
|
800812e: 4b46 ldr r3, [pc, #280] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008130: 2180 movs r1, #128 @ 0x80
|
|
8008132: 0249 lsls r1, r1, #9
|
|
8008134: 430a orrs r2, r1
|
|
8008136: 621a str r2, [r3, #32]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8008138: 4b43 ldr r3, [pc, #268] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800813a: 6a1a ldr r2, [r3, #32]
|
|
800813c: 4b42 ldr r3, [pc, #264] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800813e: 4945 ldr r1, [pc, #276] @ (8008254 <HAL_RCCEx_PeriphCLKConfig+0x1ec>)
|
|
8008140: 400a ands r2, r1
|
|
8008142: 621a str r2, [r3, #32]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = temp_reg;
|
|
8008144: 4b40 ldr r3, [pc, #256] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008146: 68fa ldr r2, [r7, #12]
|
|
8008148: 621a str r2, [r3, #32]
|
|
|
|
/* Wait for LSERDY if LSE was enabled */
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
|
800814a: 68fb ldr r3, [r7, #12]
|
|
800814c: 2201 movs r2, #1
|
|
800814e: 4013 ands r3, r2
|
|
8008150: d013 beq.n 800817a <HAL_RCCEx_PeriphCLKConfig+0x112>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8008152: f7fe fbcb bl 80068ec <HAL_GetTick>
|
|
8008156: 0003 movs r3, r0
|
|
8008158: 613b str r3, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800815a: e009 b.n 8008170 <HAL_RCCEx_PeriphCLKConfig+0x108>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800815c: f7fe fbc6 bl 80068ec <HAL_GetTick>
|
|
8008160: 0002 movs r2, r0
|
|
8008162: 693b ldr r3, [r7, #16]
|
|
8008164: 1ad3 subs r3, r2, r3
|
|
8008166: 4a3c ldr r2, [pc, #240] @ (8008258 <HAL_RCCEx_PeriphCLKConfig+0x1f0>)
|
|
8008168: 4293 cmp r3, r2
|
|
800816a: d901 bls.n 8008170 <HAL_RCCEx_PeriphCLKConfig+0x108>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800816c: 2303 movs r3, #3
|
|
800816e: e067 b.n 8008240 <HAL_RCCEx_PeriphCLKConfig+0x1d8>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8008170: 4b35 ldr r3, [pc, #212] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
8008172: 6a1b ldr r3, [r3, #32]
|
|
8008174: 2202 movs r2, #2
|
|
8008176: 4013 ands r3, r2
|
|
8008178: d0f0 beq.n 800815c <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
800817a: 4b33 ldr r3, [pc, #204] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800817c: 6a1b ldr r3, [r3, #32]
|
|
800817e: 4a34 ldr r2, [pc, #208] @ (8008250 <HAL_RCCEx_PeriphCLKConfig+0x1e8>)
|
|
8008180: 4013 ands r3, r2
|
|
8008182: 0019 movs r1, r3
|
|
8008184: 687b ldr r3, [r7, #4]
|
|
8008186: 685a ldr r2, [r3, #4]
|
|
8008188: 4b2f ldr r3, [pc, #188] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800818a: 430a orrs r2, r1
|
|
800818c: 621a str r2, [r3, #32]
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
800818e: 2317 movs r3, #23
|
|
8008190: 18fb adds r3, r7, r3
|
|
8008192: 781b ldrb r3, [r3, #0]
|
|
8008194: 2b01 cmp r3, #1
|
|
8008196: d105 bne.n 80081a4 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8008198: 4b2b ldr r3, [pc, #172] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800819a: 69da ldr r2, [r3, #28]
|
|
800819c: 4b2a ldr r3, [pc, #168] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800819e: 492f ldr r1, [pc, #188] @ (800825c <HAL_RCCEx_PeriphCLKConfig+0x1f4>)
|
|
80081a0: 400a ands r2, r1
|
|
80081a2: 61da str r2, [r3, #28]
|
|
}
|
|
}
|
|
|
|
/*------------------------------- USART1 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80081a4: 687b ldr r3, [r7, #4]
|
|
80081a6: 681b ldr r3, [r3, #0]
|
|
80081a8: 2201 movs r2, #1
|
|
80081aa: 4013 ands r3, r2
|
|
80081ac: d009 beq.n 80081c2 <HAL_RCCEx_PeriphCLKConfig+0x15a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
80081ae: 4b26 ldr r3, [pc, #152] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081b0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80081b2: 2203 movs r2, #3
|
|
80081b4: 4393 bics r3, r2
|
|
80081b6: 0019 movs r1, r3
|
|
80081b8: 687b ldr r3, [r7, #4]
|
|
80081ba: 689a ldr r2, [r3, #8]
|
|
80081bc: 4b22 ldr r3, [pc, #136] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081be: 430a orrs r2, r1
|
|
80081c0: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
|
|| defined(STM32F091xC) || defined(STM32F098xx)
|
|
/*----------------------------- USART2 Configuration --------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
80081c2: 687b ldr r3, [r7, #4]
|
|
80081c4: 681b ldr r3, [r3, #0]
|
|
80081c6: 2202 movs r2, #2
|
|
80081c8: 4013 ands r3, r2
|
|
80081ca: d009 beq.n 80081e0 <HAL_RCCEx_PeriphCLKConfig+0x178>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
80081cc: 4b1e ldr r3, [pc, #120] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081ce: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80081d0: 4a23 ldr r2, [pc, #140] @ (8008260 <HAL_RCCEx_PeriphCLKConfig+0x1f8>)
|
|
80081d2: 4013 ands r3, r2
|
|
80081d4: 0019 movs r1, r3
|
|
80081d6: 687b ldr r3, [r7, #4]
|
|
80081d8: 68da ldr r2, [r3, #12]
|
|
80081da: 4b1b ldr r3, [pc, #108] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081dc: 430a orrs r2, r1
|
|
80081de: 631a str r2, [r3, #48] @ 0x30
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
}
|
|
#endif /* STM32F091xC || STM32F098xx */
|
|
|
|
/*------------------------------ I2C1 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
80081e0: 687b ldr r3, [r7, #4]
|
|
80081e2: 681b ldr r3, [r3, #0]
|
|
80081e4: 2220 movs r2, #32
|
|
80081e6: 4013 ands r3, r2
|
|
80081e8: d009 beq.n 80081fe <HAL_RCCEx_PeriphCLKConfig+0x196>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
80081ea: 4b17 ldr r3, [pc, #92] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081ec: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80081ee: 2210 movs r2, #16
|
|
80081f0: 4393 bics r3, r2
|
|
80081f2: 0019 movs r1, r3
|
|
80081f4: 687b ldr r3, [r7, #4]
|
|
80081f6: 691a ldr r2, [r3, #16]
|
|
80081f8: 4b13 ldr r3, [pc, #76] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
80081fa: 430a orrs r2, r1
|
|
80081fc: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
|
|
/*------------------------------ USB Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
|
80081fe: 687b ldr r3, [r7, #4]
|
|
8008200: 681a ldr r2, [r3, #0]
|
|
8008202: 2380 movs r3, #128 @ 0x80
|
|
8008204: 029b lsls r3, r3, #10
|
|
8008206: 4013 ands r3, r2
|
|
8008208: d009 beq.n 800821e <HAL_RCCEx_PeriphCLKConfig+0x1b6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
|
|
/* Configure the USB clock source */
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
800820a: 4b0f ldr r3, [pc, #60] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800820c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800820e: 2280 movs r2, #128 @ 0x80
|
|
8008210: 4393 bics r3, r2
|
|
8008212: 0019 movs r1, r3
|
|
8008214: 687b ldr r3, [r7, #4]
|
|
8008216: 699a ldr r2, [r3, #24]
|
|
8008218: 4b0b ldr r3, [pc, #44] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800821a: 430a orrs r2, r1
|
|
800821c: 631a str r2, [r3, #48] @ 0x30
|
|
#if defined(STM32F042x6) || defined(STM32F048xx)\
|
|
|| defined(STM32F051x8) || defined(STM32F058xx)\
|
|
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
|
|| defined(STM32F091xC) || defined(STM32F098xx)
|
|
/*------------------------------ CEC clock Configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
800821e: 687b ldr r3, [r7, #4]
|
|
8008220: 681a ldr r2, [r3, #0]
|
|
8008222: 2380 movs r3, #128 @ 0x80
|
|
8008224: 00db lsls r3, r3, #3
|
|
8008226: 4013 ands r3, r2
|
|
8008228: d009 beq.n 800823e <HAL_RCCEx_PeriphCLKConfig+0x1d6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
800822a: 4b07 ldr r3, [pc, #28] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800822c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800822e: 2240 movs r2, #64 @ 0x40
|
|
8008230: 4393 bics r3, r2
|
|
8008232: 0019 movs r1, r3
|
|
8008234: 687b ldr r3, [r7, #4]
|
|
8008236: 695a ldr r2, [r3, #20]
|
|
8008238: 4b03 ldr r3, [pc, #12] @ (8008248 <HAL_RCCEx_PeriphCLKConfig+0x1e0>)
|
|
800823a: 430a orrs r2, r1
|
|
800823c: 631a str r2, [r3, #48] @ 0x30
|
|
#endif /* STM32F042x6 || STM32F048xx || */
|
|
/* STM32F051x8 || STM32F058xx || */
|
|
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
|
/* STM32F091xC || STM32F098xx */
|
|
|
|
return HAL_OK;
|
|
800823e: 2300 movs r3, #0
|
|
}
|
|
8008240: 0018 movs r0, r3
|
|
8008242: 46bd mov sp, r7
|
|
8008244: b006 add sp, #24
|
|
8008246: bd80 pop {r7, pc}
|
|
8008248: 40021000 .word 0x40021000
|
|
800824c: 40007000 .word 0x40007000
|
|
8008250: fffffcff .word 0xfffffcff
|
|
8008254: fffeffff .word 0xfffeffff
|
|
8008258: 00001388 .word 0x00001388
|
|
800825c: efffffff .word 0xefffffff
|
|
8008260: fffcffff .word 0xfffcffff
|
|
|
|
08008264 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8008264: b580 push {r7, lr}
|
|
8008266: b082 sub sp, #8
|
|
8008268: af00 add r7, sp, #0
|
|
800826a: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
800826c: 687b ldr r3, [r7, #4]
|
|
800826e: 2b00 cmp r3, #0
|
|
8008270: d101 bne.n 8008276 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8008272: 2301 movs r3, #1
|
|
8008274: e044 b.n 8008300 <HAL_UART_Init+0x9c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8008276: 687b ldr r3, [r7, #4]
|
|
8008278: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
800827a: 2b00 cmp r3, #0
|
|
800827c: d107 bne.n 800828e <HAL_UART_Init+0x2a>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800827e: 687b ldr r3, [r7, #4]
|
|
8008280: 2274 movs r2, #116 @ 0x74
|
|
8008282: 2100 movs r1, #0
|
|
8008284: 5499 strb r1, [r3, r2]
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8008286: 687b ldr r3, [r7, #4]
|
|
8008288: 0018 movs r0, r3
|
|
800828a: f7fd fdcd bl 8005e28 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800828e: 687b ldr r3, [r7, #4]
|
|
8008290: 2224 movs r2, #36 @ 0x24
|
|
8008292: 679a str r2, [r3, #120] @ 0x78
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8008294: 687b ldr r3, [r7, #4]
|
|
8008296: 681b ldr r3, [r3, #0]
|
|
8008298: 681a ldr r2, [r3, #0]
|
|
800829a: 687b ldr r3, [r7, #4]
|
|
800829c: 681b ldr r3, [r3, #0]
|
|
800829e: 2101 movs r1, #1
|
|
80082a0: 438a bics r2, r1
|
|
80082a2: 601a str r2, [r3, #0]
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
80082a4: 687b ldr r3, [r7, #4]
|
|
80082a6: 0018 movs r0, r3
|
|
80082a8: f000 f830 bl 800830c <UART_SetConfig>
|
|
80082ac: 0003 movs r3, r0
|
|
80082ae: 2b01 cmp r3, #1
|
|
80082b0: d101 bne.n 80082b6 <HAL_UART_Init+0x52>
|
|
{
|
|
return HAL_ERROR;
|
|
80082b2: 2301 movs r3, #1
|
|
80082b4: e024 b.n 8008300 <HAL_UART_Init+0x9c>
|
|
}
|
|
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
80082b6: 687b ldr r3, [r7, #4]
|
|
80082b8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80082ba: 2b00 cmp r3, #0
|
|
80082bc: d003 beq.n 80082c6 <HAL_UART_Init+0x62>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
80082be: 687b ldr r3, [r7, #4]
|
|
80082c0: 0018 movs r0, r3
|
|
80082c2: f000 f9ab bl 800861c <UART_AdvFeatureConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
|
|
- SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
|
|
#if defined (USART_CR2_LINEN)
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
80082c6: 687b ldr r3, [r7, #4]
|
|
80082c8: 681b ldr r3, [r3, #0]
|
|
80082ca: 685a ldr r2, [r3, #4]
|
|
80082cc: 687b ldr r3, [r7, #4]
|
|
80082ce: 681b ldr r3, [r3, #0]
|
|
80082d0: 490d ldr r1, [pc, #52] @ (8008308 <HAL_UART_Init+0xa4>)
|
|
80082d2: 400a ands r2, r1
|
|
80082d4: 605a str r2, [r3, #4]
|
|
#else
|
|
CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
|
|
#endif /* USART_CR2_LINEN */
|
|
#if defined (USART_CR3_SCEN)
|
|
#if defined (USART_CR3_IREN)
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
80082d6: 687b ldr r3, [r7, #4]
|
|
80082d8: 681b ldr r3, [r3, #0]
|
|
80082da: 689a ldr r2, [r3, #8]
|
|
80082dc: 687b ldr r3, [r7, #4]
|
|
80082de: 681b ldr r3, [r3, #0]
|
|
80082e0: 212a movs r1, #42 @ 0x2a
|
|
80082e2: 438a bics r2, r1
|
|
80082e4: 609a str r2, [r3, #8]
|
|
#else
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
|
|
#endif /* USART_CR3_IREN*/
|
|
#endif /* USART_CR3_SCEN */
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
80082e6: 687b ldr r3, [r7, #4]
|
|
80082e8: 681b ldr r3, [r3, #0]
|
|
80082ea: 681a ldr r2, [r3, #0]
|
|
80082ec: 687b ldr r3, [r7, #4]
|
|
80082ee: 681b ldr r3, [r3, #0]
|
|
80082f0: 2101 movs r1, #1
|
|
80082f2: 430a orrs r2, r1
|
|
80082f4: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
80082f6: 687b ldr r3, [r7, #4]
|
|
80082f8: 0018 movs r0, r3
|
|
80082fa: f000 fa43 bl 8008784 <UART_CheckIdleState>
|
|
80082fe: 0003 movs r3, r0
|
|
}
|
|
8008300: 0018 movs r0, r3
|
|
8008302: 46bd mov sp, r7
|
|
8008304: b002 add sp, #8
|
|
8008306: bd80 pop {r7, pc}
|
|
8008308: ffffb7ff .word 0xffffb7ff
|
|
|
|
0800830c <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800830c: b580 push {r7, lr}
|
|
800830e: b088 sub sp, #32
|
|
8008310: af00 add r7, sp, #0
|
|
8008312: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8008314: 231e movs r3, #30
|
|
8008316: 18fb adds r3, r7, r3
|
|
8008318: 2200 movs r2, #0
|
|
800831a: 701a strb r2, [r3, #0]
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
800831c: 687b ldr r3, [r7, #4]
|
|
800831e: 689a ldr r2, [r3, #8]
|
|
8008320: 687b ldr r3, [r7, #4]
|
|
8008322: 691b ldr r3, [r3, #16]
|
|
8008324: 431a orrs r2, r3
|
|
8008326: 687b ldr r3, [r7, #4]
|
|
8008328: 695b ldr r3, [r3, #20]
|
|
800832a: 431a orrs r2, r3
|
|
800832c: 687b ldr r3, [r7, #4]
|
|
800832e: 69db ldr r3, [r3, #28]
|
|
8008330: 4313 orrs r3, r2
|
|
8008332: 617b str r3, [r7, #20]
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8008334: 687b ldr r3, [r7, #4]
|
|
8008336: 681b ldr r3, [r3, #0]
|
|
8008338: 681b ldr r3, [r3, #0]
|
|
800833a: 4aaf ldr r2, [pc, #700] @ (80085f8 <UART_SetConfig+0x2ec>)
|
|
800833c: 4013 ands r3, r2
|
|
800833e: 0019 movs r1, r3
|
|
8008340: 687b ldr r3, [r7, #4]
|
|
8008342: 681b ldr r3, [r3, #0]
|
|
8008344: 697a ldr r2, [r7, #20]
|
|
8008346: 430a orrs r2, r1
|
|
8008348: 601a str r2, [r3, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
800834a: 687b ldr r3, [r7, #4]
|
|
800834c: 681b ldr r3, [r3, #0]
|
|
800834e: 685b ldr r3, [r3, #4]
|
|
8008350: 4aaa ldr r2, [pc, #680] @ (80085fc <UART_SetConfig+0x2f0>)
|
|
8008352: 4013 ands r3, r2
|
|
8008354: 0019 movs r1, r3
|
|
8008356: 687b ldr r3, [r7, #4]
|
|
8008358: 68da ldr r2, [r3, #12]
|
|
800835a: 687b ldr r3, [r7, #4]
|
|
800835c: 681b ldr r3, [r3, #0]
|
|
800835e: 430a orrs r2, r1
|
|
8008360: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
8008362: 687b ldr r3, [r7, #4]
|
|
8008364: 699b ldr r3, [r3, #24]
|
|
8008366: 617b str r3, [r7, #20]
|
|
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8008368: 687b ldr r3, [r7, #4]
|
|
800836a: 6a1b ldr r3, [r3, #32]
|
|
800836c: 697a ldr r2, [r7, #20]
|
|
800836e: 4313 orrs r3, r2
|
|
8008370: 617b str r3, [r7, #20]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8008372: 687b ldr r3, [r7, #4]
|
|
8008374: 681b ldr r3, [r3, #0]
|
|
8008376: 689b ldr r3, [r3, #8]
|
|
8008378: 4aa1 ldr r2, [pc, #644] @ (8008600 <UART_SetConfig+0x2f4>)
|
|
800837a: 4013 ands r3, r2
|
|
800837c: 0019 movs r1, r3
|
|
800837e: 687b ldr r3, [r7, #4]
|
|
8008380: 681b ldr r3, [r3, #0]
|
|
8008382: 697a ldr r2, [r7, #20]
|
|
8008384: 430a orrs r2, r1
|
|
8008386: 609a str r2, [r3, #8]
|
|
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8008388: 687b ldr r3, [r7, #4]
|
|
800838a: 681b ldr r3, [r3, #0]
|
|
800838c: 4a9d ldr r2, [pc, #628] @ (8008604 <UART_SetConfig+0x2f8>)
|
|
800838e: 4293 cmp r3, r2
|
|
8008390: d127 bne.n 80083e2 <UART_SetConfig+0xd6>
|
|
8008392: 4b9d ldr r3, [pc, #628] @ (8008608 <UART_SetConfig+0x2fc>)
|
|
8008394: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8008396: 2203 movs r2, #3
|
|
8008398: 4013 ands r3, r2
|
|
800839a: 2b03 cmp r3, #3
|
|
800839c: d00d beq.n 80083ba <UART_SetConfig+0xae>
|
|
800839e: d81b bhi.n 80083d8 <UART_SetConfig+0xcc>
|
|
80083a0: 2b02 cmp r3, #2
|
|
80083a2: d014 beq.n 80083ce <UART_SetConfig+0xc2>
|
|
80083a4: d818 bhi.n 80083d8 <UART_SetConfig+0xcc>
|
|
80083a6: 2b00 cmp r3, #0
|
|
80083a8: d002 beq.n 80083b0 <UART_SetConfig+0xa4>
|
|
80083aa: 2b01 cmp r3, #1
|
|
80083ac: d00a beq.n 80083c4 <UART_SetConfig+0xb8>
|
|
80083ae: e013 b.n 80083d8 <UART_SetConfig+0xcc>
|
|
80083b0: 231f movs r3, #31
|
|
80083b2: 18fb adds r3, r7, r3
|
|
80083b4: 2200 movs r2, #0
|
|
80083b6: 701a strb r2, [r3, #0]
|
|
80083b8: e065 b.n 8008486 <UART_SetConfig+0x17a>
|
|
80083ba: 231f movs r3, #31
|
|
80083bc: 18fb adds r3, r7, r3
|
|
80083be: 2202 movs r2, #2
|
|
80083c0: 701a strb r2, [r3, #0]
|
|
80083c2: e060 b.n 8008486 <UART_SetConfig+0x17a>
|
|
80083c4: 231f movs r3, #31
|
|
80083c6: 18fb adds r3, r7, r3
|
|
80083c8: 2204 movs r2, #4
|
|
80083ca: 701a strb r2, [r3, #0]
|
|
80083cc: e05b b.n 8008486 <UART_SetConfig+0x17a>
|
|
80083ce: 231f movs r3, #31
|
|
80083d0: 18fb adds r3, r7, r3
|
|
80083d2: 2208 movs r2, #8
|
|
80083d4: 701a strb r2, [r3, #0]
|
|
80083d6: e056 b.n 8008486 <UART_SetConfig+0x17a>
|
|
80083d8: 231f movs r3, #31
|
|
80083da: 18fb adds r3, r7, r3
|
|
80083dc: 2210 movs r2, #16
|
|
80083de: 701a strb r2, [r3, #0]
|
|
80083e0: e051 b.n 8008486 <UART_SetConfig+0x17a>
|
|
80083e2: 687b ldr r3, [r7, #4]
|
|
80083e4: 681b ldr r3, [r3, #0]
|
|
80083e6: 4a89 ldr r2, [pc, #548] @ (800860c <UART_SetConfig+0x300>)
|
|
80083e8: 4293 cmp r3, r2
|
|
80083ea: d134 bne.n 8008456 <UART_SetConfig+0x14a>
|
|
80083ec: 4b86 ldr r3, [pc, #536] @ (8008608 <UART_SetConfig+0x2fc>)
|
|
80083ee: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
80083f0: 23c0 movs r3, #192 @ 0xc0
|
|
80083f2: 029b lsls r3, r3, #10
|
|
80083f4: 4013 ands r3, r2
|
|
80083f6: 22c0 movs r2, #192 @ 0xc0
|
|
80083f8: 0292 lsls r2, r2, #10
|
|
80083fa: 4293 cmp r3, r2
|
|
80083fc: d017 beq.n 800842e <UART_SetConfig+0x122>
|
|
80083fe: 22c0 movs r2, #192 @ 0xc0
|
|
8008400: 0292 lsls r2, r2, #10
|
|
8008402: 4293 cmp r3, r2
|
|
8008404: d822 bhi.n 800844c <UART_SetConfig+0x140>
|
|
8008406: 2280 movs r2, #128 @ 0x80
|
|
8008408: 0292 lsls r2, r2, #10
|
|
800840a: 4293 cmp r3, r2
|
|
800840c: d019 beq.n 8008442 <UART_SetConfig+0x136>
|
|
800840e: 2280 movs r2, #128 @ 0x80
|
|
8008410: 0292 lsls r2, r2, #10
|
|
8008412: 4293 cmp r3, r2
|
|
8008414: d81a bhi.n 800844c <UART_SetConfig+0x140>
|
|
8008416: 2b00 cmp r3, #0
|
|
8008418: d004 beq.n 8008424 <UART_SetConfig+0x118>
|
|
800841a: 2280 movs r2, #128 @ 0x80
|
|
800841c: 0252 lsls r2, r2, #9
|
|
800841e: 4293 cmp r3, r2
|
|
8008420: d00a beq.n 8008438 <UART_SetConfig+0x12c>
|
|
8008422: e013 b.n 800844c <UART_SetConfig+0x140>
|
|
8008424: 231f movs r3, #31
|
|
8008426: 18fb adds r3, r7, r3
|
|
8008428: 2200 movs r2, #0
|
|
800842a: 701a strb r2, [r3, #0]
|
|
800842c: e02b b.n 8008486 <UART_SetConfig+0x17a>
|
|
800842e: 231f movs r3, #31
|
|
8008430: 18fb adds r3, r7, r3
|
|
8008432: 2202 movs r2, #2
|
|
8008434: 701a strb r2, [r3, #0]
|
|
8008436: e026 b.n 8008486 <UART_SetConfig+0x17a>
|
|
8008438: 231f movs r3, #31
|
|
800843a: 18fb adds r3, r7, r3
|
|
800843c: 2204 movs r2, #4
|
|
800843e: 701a strb r2, [r3, #0]
|
|
8008440: e021 b.n 8008486 <UART_SetConfig+0x17a>
|
|
8008442: 231f movs r3, #31
|
|
8008444: 18fb adds r3, r7, r3
|
|
8008446: 2208 movs r2, #8
|
|
8008448: 701a strb r2, [r3, #0]
|
|
800844a: e01c b.n 8008486 <UART_SetConfig+0x17a>
|
|
800844c: 231f movs r3, #31
|
|
800844e: 18fb adds r3, r7, r3
|
|
8008450: 2210 movs r2, #16
|
|
8008452: 701a strb r2, [r3, #0]
|
|
8008454: e017 b.n 8008486 <UART_SetConfig+0x17a>
|
|
8008456: 687b ldr r3, [r7, #4]
|
|
8008458: 681b ldr r3, [r3, #0]
|
|
800845a: 4a6d ldr r2, [pc, #436] @ (8008610 <UART_SetConfig+0x304>)
|
|
800845c: 4293 cmp r3, r2
|
|
800845e: d104 bne.n 800846a <UART_SetConfig+0x15e>
|
|
8008460: 231f movs r3, #31
|
|
8008462: 18fb adds r3, r7, r3
|
|
8008464: 2200 movs r2, #0
|
|
8008466: 701a strb r2, [r3, #0]
|
|
8008468: e00d b.n 8008486 <UART_SetConfig+0x17a>
|
|
800846a: 687b ldr r3, [r7, #4]
|
|
800846c: 681b ldr r3, [r3, #0]
|
|
800846e: 4a69 ldr r2, [pc, #420] @ (8008614 <UART_SetConfig+0x308>)
|
|
8008470: 4293 cmp r3, r2
|
|
8008472: d104 bne.n 800847e <UART_SetConfig+0x172>
|
|
8008474: 231f movs r3, #31
|
|
8008476: 18fb adds r3, r7, r3
|
|
8008478: 2200 movs r2, #0
|
|
800847a: 701a strb r2, [r3, #0]
|
|
800847c: e003 b.n 8008486 <UART_SetConfig+0x17a>
|
|
800847e: 231f movs r3, #31
|
|
8008480: 18fb adds r3, r7, r3
|
|
8008482: 2210 movs r2, #16
|
|
8008484: 701a strb r2, [r3, #0]
|
|
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8008486: 687b ldr r3, [r7, #4]
|
|
8008488: 69da ldr r2, [r3, #28]
|
|
800848a: 2380 movs r3, #128 @ 0x80
|
|
800848c: 021b lsls r3, r3, #8
|
|
800848e: 429a cmp r2, r3
|
|
8008490: d15d bne.n 800854e <UART_SetConfig+0x242>
|
|
{
|
|
switch (clocksource)
|
|
8008492: 231f movs r3, #31
|
|
8008494: 18fb adds r3, r7, r3
|
|
8008496: 781b ldrb r3, [r3, #0]
|
|
8008498: 2b08 cmp r3, #8
|
|
800849a: d015 beq.n 80084c8 <UART_SetConfig+0x1bc>
|
|
800849c: dc18 bgt.n 80084d0 <UART_SetConfig+0x1c4>
|
|
800849e: 2b04 cmp r3, #4
|
|
80084a0: d00d beq.n 80084be <UART_SetConfig+0x1b2>
|
|
80084a2: dc15 bgt.n 80084d0 <UART_SetConfig+0x1c4>
|
|
80084a4: 2b00 cmp r3, #0
|
|
80084a6: d002 beq.n 80084ae <UART_SetConfig+0x1a2>
|
|
80084a8: 2b02 cmp r3, #2
|
|
80084aa: d005 beq.n 80084b8 <UART_SetConfig+0x1ac>
|
|
80084ac: e010 b.n 80084d0 <UART_SetConfig+0x1c4>
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80084ae: f7ff fdc5 bl 800803c <HAL_RCC_GetPCLK1Freq>
|
|
80084b2: 0003 movs r3, r0
|
|
80084b4: 61bb str r3, [r7, #24]
|
|
break;
|
|
80084b6: e012 b.n 80084de <UART_SetConfig+0x1d2>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
80084b8: 4b57 ldr r3, [pc, #348] @ (8008618 <UART_SetConfig+0x30c>)
|
|
80084ba: 61bb str r3, [r7, #24]
|
|
break;
|
|
80084bc: e00f b.n 80084de <UART_SetConfig+0x1d2>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
80084be: f7ff fd33 bl 8007f28 <HAL_RCC_GetSysClockFreq>
|
|
80084c2: 0003 movs r3, r0
|
|
80084c4: 61bb str r3, [r7, #24]
|
|
break;
|
|
80084c6: e00a b.n 80084de <UART_SetConfig+0x1d2>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
80084c8: 2380 movs r3, #128 @ 0x80
|
|
80084ca: 021b lsls r3, r3, #8
|
|
80084cc: 61bb str r3, [r7, #24]
|
|
break;
|
|
80084ce: e006 b.n 80084de <UART_SetConfig+0x1d2>
|
|
default:
|
|
pclk = 0U;
|
|
80084d0: 2300 movs r3, #0
|
|
80084d2: 61bb str r3, [r7, #24]
|
|
ret = HAL_ERROR;
|
|
80084d4: 231e movs r3, #30
|
|
80084d6: 18fb adds r3, r7, r3
|
|
80084d8: 2201 movs r2, #1
|
|
80084da: 701a strb r2, [r3, #0]
|
|
break;
|
|
80084dc: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
80084de: 69bb ldr r3, [r7, #24]
|
|
80084e0: 2b00 cmp r3, #0
|
|
80084e2: d100 bne.n 80084e6 <UART_SetConfig+0x1da>
|
|
80084e4: e07b b.n 80085de <UART_SetConfig+0x2d2>
|
|
{
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
80084e6: 69bb ldr r3, [r7, #24]
|
|
80084e8: 005a lsls r2, r3, #1
|
|
80084ea: 687b ldr r3, [r7, #4]
|
|
80084ec: 685b ldr r3, [r3, #4]
|
|
80084ee: 085b lsrs r3, r3, #1
|
|
80084f0: 18d2 adds r2, r2, r3
|
|
80084f2: 687b ldr r3, [r7, #4]
|
|
80084f4: 685b ldr r3, [r3, #4]
|
|
80084f6: 0019 movs r1, r3
|
|
80084f8: 0010 movs r0, r2
|
|
80084fa: f7f7 fe05 bl 8000108 <__udivsi3>
|
|
80084fe: 0003 movs r3, r0
|
|
8008500: b29b uxth r3, r3
|
|
8008502: 613b str r3, [r7, #16]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8008504: 693b ldr r3, [r7, #16]
|
|
8008506: 2b0f cmp r3, #15
|
|
8008508: d91c bls.n 8008544 <UART_SetConfig+0x238>
|
|
800850a: 693a ldr r2, [r7, #16]
|
|
800850c: 2380 movs r3, #128 @ 0x80
|
|
800850e: 025b lsls r3, r3, #9
|
|
8008510: 429a cmp r2, r3
|
|
8008512: d217 bcs.n 8008544 <UART_SetConfig+0x238>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8008514: 693b ldr r3, [r7, #16]
|
|
8008516: b29a uxth r2, r3
|
|
8008518: 200e movs r0, #14
|
|
800851a: 183b adds r3, r7, r0
|
|
800851c: 210f movs r1, #15
|
|
800851e: 438a bics r2, r1
|
|
8008520: 801a strh r2, [r3, #0]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8008522: 693b ldr r3, [r7, #16]
|
|
8008524: 085b lsrs r3, r3, #1
|
|
8008526: b29b uxth r3, r3
|
|
8008528: 2207 movs r2, #7
|
|
800852a: 4013 ands r3, r2
|
|
800852c: b299 uxth r1, r3
|
|
800852e: 183b adds r3, r7, r0
|
|
8008530: 183a adds r2, r7, r0
|
|
8008532: 8812 ldrh r2, [r2, #0]
|
|
8008534: 430a orrs r2, r1
|
|
8008536: 801a strh r2, [r3, #0]
|
|
huart->Instance->BRR = brrtemp;
|
|
8008538: 687b ldr r3, [r7, #4]
|
|
800853a: 681b ldr r3, [r3, #0]
|
|
800853c: 183a adds r2, r7, r0
|
|
800853e: 8812 ldrh r2, [r2, #0]
|
|
8008540: 60da str r2, [r3, #12]
|
|
8008542: e04c b.n 80085de <UART_SetConfig+0x2d2>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8008544: 231e movs r3, #30
|
|
8008546: 18fb adds r3, r7, r3
|
|
8008548: 2201 movs r2, #1
|
|
800854a: 701a strb r2, [r3, #0]
|
|
800854c: e047 b.n 80085de <UART_SetConfig+0x2d2>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
800854e: 231f movs r3, #31
|
|
8008550: 18fb adds r3, r7, r3
|
|
8008552: 781b ldrb r3, [r3, #0]
|
|
8008554: 2b08 cmp r3, #8
|
|
8008556: d015 beq.n 8008584 <UART_SetConfig+0x278>
|
|
8008558: dc18 bgt.n 800858c <UART_SetConfig+0x280>
|
|
800855a: 2b04 cmp r3, #4
|
|
800855c: d00d beq.n 800857a <UART_SetConfig+0x26e>
|
|
800855e: dc15 bgt.n 800858c <UART_SetConfig+0x280>
|
|
8008560: 2b00 cmp r3, #0
|
|
8008562: d002 beq.n 800856a <UART_SetConfig+0x25e>
|
|
8008564: 2b02 cmp r3, #2
|
|
8008566: d005 beq.n 8008574 <UART_SetConfig+0x268>
|
|
8008568: e010 b.n 800858c <UART_SetConfig+0x280>
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800856a: f7ff fd67 bl 800803c <HAL_RCC_GetPCLK1Freq>
|
|
800856e: 0003 movs r3, r0
|
|
8008570: 61bb str r3, [r7, #24]
|
|
break;
|
|
8008572: e012 b.n 800859a <UART_SetConfig+0x28e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8008574: 4b28 ldr r3, [pc, #160] @ (8008618 <UART_SetConfig+0x30c>)
|
|
8008576: 61bb str r3, [r7, #24]
|
|
break;
|
|
8008578: e00f b.n 800859a <UART_SetConfig+0x28e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800857a: f7ff fcd5 bl 8007f28 <HAL_RCC_GetSysClockFreq>
|
|
800857e: 0003 movs r3, r0
|
|
8008580: 61bb str r3, [r7, #24]
|
|
break;
|
|
8008582: e00a b.n 800859a <UART_SetConfig+0x28e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8008584: 2380 movs r3, #128 @ 0x80
|
|
8008586: 021b lsls r3, r3, #8
|
|
8008588: 61bb str r3, [r7, #24]
|
|
break;
|
|
800858a: e006 b.n 800859a <UART_SetConfig+0x28e>
|
|
default:
|
|
pclk = 0U;
|
|
800858c: 2300 movs r3, #0
|
|
800858e: 61bb str r3, [r7, #24]
|
|
ret = HAL_ERROR;
|
|
8008590: 231e movs r3, #30
|
|
8008592: 18fb adds r3, r7, r3
|
|
8008594: 2201 movs r2, #1
|
|
8008596: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008598: 46c0 nop @ (mov r8, r8)
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
800859a: 69bb ldr r3, [r7, #24]
|
|
800859c: 2b00 cmp r3, #0
|
|
800859e: d01e beq.n 80085de <UART_SetConfig+0x2d2>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
80085a0: 687b ldr r3, [r7, #4]
|
|
80085a2: 685b ldr r3, [r3, #4]
|
|
80085a4: 085a lsrs r2, r3, #1
|
|
80085a6: 69bb ldr r3, [r7, #24]
|
|
80085a8: 18d2 adds r2, r2, r3
|
|
80085aa: 687b ldr r3, [r7, #4]
|
|
80085ac: 685b ldr r3, [r3, #4]
|
|
80085ae: 0019 movs r1, r3
|
|
80085b0: 0010 movs r0, r2
|
|
80085b2: f7f7 fda9 bl 8000108 <__udivsi3>
|
|
80085b6: 0003 movs r3, r0
|
|
80085b8: b29b uxth r3, r3
|
|
80085ba: 613b str r3, [r7, #16]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
80085bc: 693b ldr r3, [r7, #16]
|
|
80085be: 2b0f cmp r3, #15
|
|
80085c0: d909 bls.n 80085d6 <UART_SetConfig+0x2ca>
|
|
80085c2: 693a ldr r2, [r7, #16]
|
|
80085c4: 2380 movs r3, #128 @ 0x80
|
|
80085c6: 025b lsls r3, r3, #9
|
|
80085c8: 429a cmp r2, r3
|
|
80085ca: d204 bcs.n 80085d6 <UART_SetConfig+0x2ca>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
80085cc: 687b ldr r3, [r7, #4]
|
|
80085ce: 681b ldr r3, [r3, #0]
|
|
80085d0: 693a ldr r2, [r7, #16]
|
|
80085d2: 60da str r2, [r3, #12]
|
|
80085d4: e003 b.n 80085de <UART_SetConfig+0x2d2>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
80085d6: 231e movs r3, #30
|
|
80085d8: 18fb adds r3, r7, r3
|
|
80085da: 2201 movs r2, #1
|
|
80085dc: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
80085de: 687b ldr r3, [r7, #4]
|
|
80085e0: 2200 movs r2, #0
|
|
80085e2: 665a str r2, [r3, #100] @ 0x64
|
|
huart->TxISR = NULL;
|
|
80085e4: 687b ldr r3, [r7, #4]
|
|
80085e6: 2200 movs r2, #0
|
|
80085e8: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
return ret;
|
|
80085ea: 231e movs r3, #30
|
|
80085ec: 18fb adds r3, r7, r3
|
|
80085ee: 781b ldrb r3, [r3, #0]
|
|
}
|
|
80085f0: 0018 movs r0, r3
|
|
80085f2: 46bd mov sp, r7
|
|
80085f4: b008 add sp, #32
|
|
80085f6: bd80 pop {r7, pc}
|
|
80085f8: efff69f3 .word 0xefff69f3
|
|
80085fc: ffffcfff .word 0xffffcfff
|
|
8008600: fffff4ff .word 0xfffff4ff
|
|
8008604: 40013800 .word 0x40013800
|
|
8008608: 40021000 .word 0x40021000
|
|
800860c: 40004400 .word 0x40004400
|
|
8008610: 40004800 .word 0x40004800
|
|
8008614: 40004c00 .word 0x40004c00
|
|
8008618: 007a1200 .word 0x007a1200
|
|
|
|
0800861c <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800861c: b580 push {r7, lr}
|
|
800861e: b082 sub sp, #8
|
|
8008620: af00 add r7, sp, #0
|
|
8008622: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8008624: 687b ldr r3, [r7, #4]
|
|
8008626: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008628: 2201 movs r2, #1
|
|
800862a: 4013 ands r3, r2
|
|
800862c: d00b beq.n 8008646 <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
800862e: 687b ldr r3, [r7, #4]
|
|
8008630: 681b ldr r3, [r3, #0]
|
|
8008632: 685b ldr r3, [r3, #4]
|
|
8008634: 4a4a ldr r2, [pc, #296] @ (8008760 <UART_AdvFeatureConfig+0x144>)
|
|
8008636: 4013 ands r3, r2
|
|
8008638: 0019 movs r1, r3
|
|
800863a: 687b ldr r3, [r7, #4]
|
|
800863c: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
800863e: 687b ldr r3, [r7, #4]
|
|
8008640: 681b ldr r3, [r3, #0]
|
|
8008642: 430a orrs r2, r1
|
|
8008644: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8008646: 687b ldr r3, [r7, #4]
|
|
8008648: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800864a: 2202 movs r2, #2
|
|
800864c: 4013 ands r3, r2
|
|
800864e: d00b beq.n 8008668 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8008650: 687b ldr r3, [r7, #4]
|
|
8008652: 681b ldr r3, [r3, #0]
|
|
8008654: 685b ldr r3, [r3, #4]
|
|
8008656: 4a43 ldr r2, [pc, #268] @ (8008764 <UART_AdvFeatureConfig+0x148>)
|
|
8008658: 4013 ands r3, r2
|
|
800865a: 0019 movs r1, r3
|
|
800865c: 687b ldr r3, [r7, #4]
|
|
800865e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8008660: 687b ldr r3, [r7, #4]
|
|
8008662: 681b ldr r3, [r3, #0]
|
|
8008664: 430a orrs r2, r1
|
|
8008666: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8008668: 687b ldr r3, [r7, #4]
|
|
800866a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800866c: 2204 movs r2, #4
|
|
800866e: 4013 ands r3, r2
|
|
8008670: d00b beq.n 800868a <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8008672: 687b ldr r3, [r7, #4]
|
|
8008674: 681b ldr r3, [r3, #0]
|
|
8008676: 685b ldr r3, [r3, #4]
|
|
8008678: 4a3b ldr r2, [pc, #236] @ (8008768 <UART_AdvFeatureConfig+0x14c>)
|
|
800867a: 4013 ands r3, r2
|
|
800867c: 0019 movs r1, r3
|
|
800867e: 687b ldr r3, [r7, #4]
|
|
8008680: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8008682: 687b ldr r3, [r7, #4]
|
|
8008684: 681b ldr r3, [r3, #0]
|
|
8008686: 430a orrs r2, r1
|
|
8008688: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
800868a: 687b ldr r3, [r7, #4]
|
|
800868c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800868e: 2208 movs r2, #8
|
|
8008690: 4013 ands r3, r2
|
|
8008692: d00b beq.n 80086ac <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8008694: 687b ldr r3, [r7, #4]
|
|
8008696: 681b ldr r3, [r3, #0]
|
|
8008698: 685b ldr r3, [r3, #4]
|
|
800869a: 4a34 ldr r2, [pc, #208] @ (800876c <UART_AdvFeatureConfig+0x150>)
|
|
800869c: 4013 ands r3, r2
|
|
800869e: 0019 movs r1, r3
|
|
80086a0: 687b ldr r3, [r7, #4]
|
|
80086a2: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80086a4: 687b ldr r3, [r7, #4]
|
|
80086a6: 681b ldr r3, [r3, #0]
|
|
80086a8: 430a orrs r2, r1
|
|
80086aa: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
80086ac: 687b ldr r3, [r7, #4]
|
|
80086ae: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80086b0: 2210 movs r2, #16
|
|
80086b2: 4013 ands r3, r2
|
|
80086b4: d00b beq.n 80086ce <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
80086b6: 687b ldr r3, [r7, #4]
|
|
80086b8: 681b ldr r3, [r3, #0]
|
|
80086ba: 689b ldr r3, [r3, #8]
|
|
80086bc: 4a2c ldr r2, [pc, #176] @ (8008770 <UART_AdvFeatureConfig+0x154>)
|
|
80086be: 4013 ands r3, r2
|
|
80086c0: 0019 movs r1, r3
|
|
80086c2: 687b ldr r3, [r7, #4]
|
|
80086c4: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80086c6: 687b ldr r3, [r7, #4]
|
|
80086c8: 681b ldr r3, [r3, #0]
|
|
80086ca: 430a orrs r2, r1
|
|
80086cc: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
80086ce: 687b ldr r3, [r7, #4]
|
|
80086d0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80086d2: 2220 movs r2, #32
|
|
80086d4: 4013 ands r3, r2
|
|
80086d6: d00b beq.n 80086f0 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
80086d8: 687b ldr r3, [r7, #4]
|
|
80086da: 681b ldr r3, [r3, #0]
|
|
80086dc: 689b ldr r3, [r3, #8]
|
|
80086de: 4a25 ldr r2, [pc, #148] @ (8008774 <UART_AdvFeatureConfig+0x158>)
|
|
80086e0: 4013 ands r3, r2
|
|
80086e2: 0019 movs r1, r3
|
|
80086e4: 687b ldr r3, [r7, #4]
|
|
80086e6: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
80086e8: 687b ldr r3, [r7, #4]
|
|
80086ea: 681b ldr r3, [r3, #0]
|
|
80086ec: 430a orrs r2, r1
|
|
80086ee: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
80086f0: 687b ldr r3, [r7, #4]
|
|
80086f2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80086f4: 2240 movs r2, #64 @ 0x40
|
|
80086f6: 4013 ands r3, r2
|
|
80086f8: d01d beq.n 8008736 <UART_AdvFeatureConfig+0x11a>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
80086fa: 687b ldr r3, [r7, #4]
|
|
80086fc: 681b ldr r3, [r3, #0]
|
|
80086fe: 685b ldr r3, [r3, #4]
|
|
8008700: 4a1d ldr r2, [pc, #116] @ (8008778 <UART_AdvFeatureConfig+0x15c>)
|
|
8008702: 4013 ands r3, r2
|
|
8008704: 0019 movs r1, r3
|
|
8008706: 687b ldr r3, [r7, #4]
|
|
8008708: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800870a: 687b ldr r3, [r7, #4]
|
|
800870c: 681b ldr r3, [r3, #0]
|
|
800870e: 430a orrs r2, r1
|
|
8008710: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8008712: 687b ldr r3, [r7, #4]
|
|
8008714: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8008716: 2380 movs r3, #128 @ 0x80
|
|
8008718: 035b lsls r3, r3, #13
|
|
800871a: 429a cmp r2, r3
|
|
800871c: d10b bne.n 8008736 <UART_AdvFeatureConfig+0x11a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
800871e: 687b ldr r3, [r7, #4]
|
|
8008720: 681b ldr r3, [r3, #0]
|
|
8008722: 685b ldr r3, [r3, #4]
|
|
8008724: 4a15 ldr r2, [pc, #84] @ (800877c <UART_AdvFeatureConfig+0x160>)
|
|
8008726: 4013 ands r3, r2
|
|
8008728: 0019 movs r1, r3
|
|
800872a: 687b ldr r3, [r7, #4]
|
|
800872c: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
800872e: 687b ldr r3, [r7, #4]
|
|
8008730: 681b ldr r3, [r3, #0]
|
|
8008732: 430a orrs r2, r1
|
|
8008734: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8008736: 687b ldr r3, [r7, #4]
|
|
8008738: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800873a: 2280 movs r2, #128 @ 0x80
|
|
800873c: 4013 ands r3, r2
|
|
800873e: d00b beq.n 8008758 <UART_AdvFeatureConfig+0x13c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8008740: 687b ldr r3, [r7, #4]
|
|
8008742: 681b ldr r3, [r3, #0]
|
|
8008744: 685b ldr r3, [r3, #4]
|
|
8008746: 4a0e ldr r2, [pc, #56] @ (8008780 <UART_AdvFeatureConfig+0x164>)
|
|
8008748: 4013 ands r3, r2
|
|
800874a: 0019 movs r1, r3
|
|
800874c: 687b ldr r3, [r7, #4]
|
|
800874e: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8008750: 687b ldr r3, [r7, #4]
|
|
8008752: 681b ldr r3, [r3, #0]
|
|
8008754: 430a orrs r2, r1
|
|
8008756: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8008758: 46c0 nop @ (mov r8, r8)
|
|
800875a: 46bd mov sp, r7
|
|
800875c: b002 add sp, #8
|
|
800875e: bd80 pop {r7, pc}
|
|
8008760: fffdffff .word 0xfffdffff
|
|
8008764: fffeffff .word 0xfffeffff
|
|
8008768: fffbffff .word 0xfffbffff
|
|
800876c: ffff7fff .word 0xffff7fff
|
|
8008770: ffffefff .word 0xffffefff
|
|
8008774: ffffdfff .word 0xffffdfff
|
|
8008778: ffefffff .word 0xffefffff
|
|
800877c: ff9fffff .word 0xff9fffff
|
|
8008780: fff7ffff .word 0xfff7ffff
|
|
|
|
08008784 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8008784: b580 push {r7, lr}
|
|
8008786: b086 sub sp, #24
|
|
8008788: af02 add r7, sp, #8
|
|
800878a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800878c: 687b ldr r3, [r7, #4]
|
|
800878e: 2280 movs r2, #128 @ 0x80
|
|
8008790: 2100 movs r1, #0
|
|
8008792: 5099 str r1, [r3, r2]
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8008794: f7fe f8aa bl 80068ec <HAL_GetTick>
|
|
8008798: 0003 movs r3, r0
|
|
800879a: 60fb str r3, [r7, #12]
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
800879c: 687b ldr r3, [r7, #4]
|
|
800879e: 681b ldr r3, [r3, #0]
|
|
80087a0: 681b ldr r3, [r3, #0]
|
|
80087a2: 2208 movs r2, #8
|
|
80087a4: 4013 ands r3, r2
|
|
80087a6: 2b08 cmp r3, #8
|
|
80087a8: d10c bne.n 80087c4 <UART_CheckIdleState+0x40>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
80087aa: 68fb ldr r3, [r7, #12]
|
|
80087ac: 2280 movs r2, #128 @ 0x80
|
|
80087ae: 0391 lsls r1, r2, #14
|
|
80087b0: 6878 ldr r0, [r7, #4]
|
|
80087b2: 4a17 ldr r2, [pc, #92] @ (8008810 <UART_CheckIdleState+0x8c>)
|
|
80087b4: 9200 str r2, [sp, #0]
|
|
80087b6: 2200 movs r2, #0
|
|
80087b8: f000 f82c bl 8008814 <UART_WaitOnFlagUntilTimeout>
|
|
80087bc: 1e03 subs r3, r0, #0
|
|
80087be: d001 beq.n 80087c4 <UART_CheckIdleState+0x40>
|
|
{
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
80087c0: 2303 movs r3, #3
|
|
80087c2: e021 b.n 8008808 <UART_CheckIdleState+0x84>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
80087c4: 687b ldr r3, [r7, #4]
|
|
80087c6: 681b ldr r3, [r3, #0]
|
|
80087c8: 681b ldr r3, [r3, #0]
|
|
80087ca: 2204 movs r2, #4
|
|
80087cc: 4013 ands r3, r2
|
|
80087ce: 2b04 cmp r3, #4
|
|
80087d0: d10c bne.n 80087ec <UART_CheckIdleState+0x68>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
80087d2: 68fb ldr r3, [r7, #12]
|
|
80087d4: 2280 movs r2, #128 @ 0x80
|
|
80087d6: 03d1 lsls r1, r2, #15
|
|
80087d8: 6878 ldr r0, [r7, #4]
|
|
80087da: 4a0d ldr r2, [pc, #52] @ (8008810 <UART_CheckIdleState+0x8c>)
|
|
80087dc: 9200 str r2, [sp, #0]
|
|
80087de: 2200 movs r2, #0
|
|
80087e0: f000 f818 bl 8008814 <UART_WaitOnFlagUntilTimeout>
|
|
80087e4: 1e03 subs r3, r0, #0
|
|
80087e6: d001 beq.n 80087ec <UART_CheckIdleState+0x68>
|
|
{
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
80087e8: 2303 movs r3, #3
|
|
80087ea: e00d b.n 8008808 <UART_CheckIdleState+0x84>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80087ec: 687b ldr r3, [r7, #4]
|
|
80087ee: 2220 movs r2, #32
|
|
80087f0: 679a str r2, [r3, #120] @ 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80087f2: 687b ldr r3, [r7, #4]
|
|
80087f4: 2220 movs r2, #32
|
|
80087f6: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80087f8: 687b ldr r3, [r7, #4]
|
|
80087fa: 2200 movs r2, #0
|
|
80087fc: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
__HAL_UNLOCK(huart);
|
|
80087fe: 687b ldr r3, [r7, #4]
|
|
8008800: 2274 movs r2, #116 @ 0x74
|
|
8008802: 2100 movs r1, #0
|
|
8008804: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_OK;
|
|
8008806: 2300 movs r3, #0
|
|
}
|
|
8008808: 0018 movs r0, r3
|
|
800880a: 46bd mov sp, r7
|
|
800880c: b004 add sp, #16
|
|
800880e: bd80 pop {r7, pc}
|
|
8008810: 01ffffff .word 0x01ffffff
|
|
|
|
08008814 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8008814: b580 push {r7, lr}
|
|
8008816: b084 sub sp, #16
|
|
8008818: af00 add r7, sp, #0
|
|
800881a: 60f8 str r0, [r7, #12]
|
|
800881c: 60b9 str r1, [r7, #8]
|
|
800881e: 603b str r3, [r7, #0]
|
|
8008820: 1dfb adds r3, r7, #7
|
|
8008822: 701a strb r2, [r3, #0]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8008824: e05e b.n 80088e4 <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8008826: 69bb ldr r3, [r7, #24]
|
|
8008828: 3301 adds r3, #1
|
|
800882a: d05b beq.n 80088e4 <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800882c: f7fe f85e bl 80068ec <HAL_GetTick>
|
|
8008830: 0002 movs r2, r0
|
|
8008832: 683b ldr r3, [r7, #0]
|
|
8008834: 1ad3 subs r3, r2, r3
|
|
8008836: 69ba ldr r2, [r7, #24]
|
|
8008838: 429a cmp r2, r3
|
|
800883a: d302 bcc.n 8008842 <UART_WaitOnFlagUntilTimeout+0x2e>
|
|
800883c: 69bb ldr r3, [r7, #24]
|
|
800883e: 2b00 cmp r3, #0
|
|
8008840: d11b bne.n 800887a <UART_WaitOnFlagUntilTimeout+0x66>
|
|
{
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
8008842: 68fb ldr r3, [r7, #12]
|
|
8008844: 681b ldr r3, [r3, #0]
|
|
8008846: 681a ldr r2, [r3, #0]
|
|
8008848: 68fb ldr r3, [r7, #12]
|
|
800884a: 681b ldr r3, [r3, #0]
|
|
800884c: 492f ldr r1, [pc, #188] @ (800890c <UART_WaitOnFlagUntilTimeout+0xf8>)
|
|
800884e: 400a ands r2, r1
|
|
8008850: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8008852: 68fb ldr r3, [r7, #12]
|
|
8008854: 681b ldr r3, [r3, #0]
|
|
8008856: 689a ldr r2, [r3, #8]
|
|
8008858: 68fb ldr r3, [r7, #12]
|
|
800885a: 681b ldr r3, [r3, #0]
|
|
800885c: 2101 movs r1, #1
|
|
800885e: 438a bics r2, r1
|
|
8008860: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8008862: 68fb ldr r3, [r7, #12]
|
|
8008864: 2220 movs r2, #32
|
|
8008866: 679a str r2, [r3, #120] @ 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8008868: 68fb ldr r3, [r7, #12]
|
|
800886a: 2220 movs r2, #32
|
|
800886c: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800886e: 68fb ldr r3, [r7, #12]
|
|
8008870: 2274 movs r2, #116 @ 0x74
|
|
8008872: 2100 movs r1, #0
|
|
8008874: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_TIMEOUT;
|
|
8008876: 2303 movs r3, #3
|
|
8008878: e044 b.n 8008904 <UART_WaitOnFlagUntilTimeout+0xf0>
|
|
}
|
|
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
|
800887a: 68fb ldr r3, [r7, #12]
|
|
800887c: 681b ldr r3, [r3, #0]
|
|
800887e: 681b ldr r3, [r3, #0]
|
|
8008880: 2204 movs r2, #4
|
|
8008882: 4013 ands r3, r2
|
|
8008884: d02e beq.n 80088e4 <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8008886: 68fb ldr r3, [r7, #12]
|
|
8008888: 681b ldr r3, [r3, #0]
|
|
800888a: 69da ldr r2, [r3, #28]
|
|
800888c: 2380 movs r3, #128 @ 0x80
|
|
800888e: 011b lsls r3, r3, #4
|
|
8008890: 401a ands r2, r3
|
|
8008892: 2380 movs r3, #128 @ 0x80
|
|
8008894: 011b lsls r3, r3, #4
|
|
8008896: 429a cmp r2, r3
|
|
8008898: d124 bne.n 80088e4 <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
800889a: 68fb ldr r3, [r7, #12]
|
|
800889c: 681b ldr r3, [r3, #0]
|
|
800889e: 2280 movs r2, #128 @ 0x80
|
|
80088a0: 0112 lsls r2, r2, #4
|
|
80088a2: 621a str r2, [r3, #32]
|
|
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
80088a4: 68fb ldr r3, [r7, #12]
|
|
80088a6: 681b ldr r3, [r3, #0]
|
|
80088a8: 681a ldr r2, [r3, #0]
|
|
80088aa: 68fb ldr r3, [r7, #12]
|
|
80088ac: 681b ldr r3, [r3, #0]
|
|
80088ae: 4917 ldr r1, [pc, #92] @ (800890c <UART_WaitOnFlagUntilTimeout+0xf8>)
|
|
80088b0: 400a ands r2, r1
|
|
80088b2: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80088b4: 68fb ldr r3, [r7, #12]
|
|
80088b6: 681b ldr r3, [r3, #0]
|
|
80088b8: 689a ldr r2, [r3, #8]
|
|
80088ba: 68fb ldr r3, [r7, #12]
|
|
80088bc: 681b ldr r3, [r3, #0]
|
|
80088be: 2101 movs r1, #1
|
|
80088c0: 438a bics r2, r1
|
|
80088c2: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80088c4: 68fb ldr r3, [r7, #12]
|
|
80088c6: 2220 movs r2, #32
|
|
80088c8: 679a str r2, [r3, #120] @ 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80088ca: 68fb ldr r3, [r7, #12]
|
|
80088cc: 2220 movs r2, #32
|
|
80088ce: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
80088d0: 68fb ldr r3, [r7, #12]
|
|
80088d2: 2280 movs r2, #128 @ 0x80
|
|
80088d4: 2120 movs r1, #32
|
|
80088d6: 5099 str r1, [r3, r2]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80088d8: 68fb ldr r3, [r7, #12]
|
|
80088da: 2274 movs r2, #116 @ 0x74
|
|
80088dc: 2100 movs r1, #0
|
|
80088de: 5499 strb r1, [r3, r2]
|
|
|
|
return HAL_TIMEOUT;
|
|
80088e0: 2303 movs r3, #3
|
|
80088e2: e00f b.n 8008904 <UART_WaitOnFlagUntilTimeout+0xf0>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
80088e4: 68fb ldr r3, [r7, #12]
|
|
80088e6: 681b ldr r3, [r3, #0]
|
|
80088e8: 69db ldr r3, [r3, #28]
|
|
80088ea: 68ba ldr r2, [r7, #8]
|
|
80088ec: 4013 ands r3, r2
|
|
80088ee: 68ba ldr r2, [r7, #8]
|
|
80088f0: 1ad3 subs r3, r2, r3
|
|
80088f2: 425a negs r2, r3
|
|
80088f4: 4153 adcs r3, r2
|
|
80088f6: b2db uxtb r3, r3
|
|
80088f8: 001a movs r2, r3
|
|
80088fa: 1dfb adds r3, r7, #7
|
|
80088fc: 781b ldrb r3, [r3, #0]
|
|
80088fe: 429a cmp r2, r3
|
|
8008900: d091 beq.n 8008826 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8008902: 2300 movs r3, #0
|
|
}
|
|
8008904: 0018 movs r0, r3
|
|
8008906: 46bd mov sp, r7
|
|
8008908: b004 add sp, #16
|
|
800890a: bd80 pop {r7, pc}
|
|
800890c: fffffe5f .word 0xfffffe5f
|
|
|
|
08008910 <memset>:
|
|
8008910: 0003 movs r3, r0
|
|
8008912: 1882 adds r2, r0, r2
|
|
8008914: 4293 cmp r3, r2
|
|
8008916: d100 bne.n 800891a <memset+0xa>
|
|
8008918: 4770 bx lr
|
|
800891a: 7019 strb r1, [r3, #0]
|
|
800891c: 3301 adds r3, #1
|
|
800891e: e7f9 b.n 8008914 <memset+0x4>
|
|
|
|
08008920 <__libc_init_array>:
|
|
8008920: b570 push {r4, r5, r6, lr}
|
|
8008922: 2600 movs r6, #0
|
|
8008924: 4c0c ldr r4, [pc, #48] @ (8008958 <__libc_init_array+0x38>)
|
|
8008926: 4d0d ldr r5, [pc, #52] @ (800895c <__libc_init_array+0x3c>)
|
|
8008928: 1b64 subs r4, r4, r5
|
|
800892a: 10a4 asrs r4, r4, #2
|
|
800892c: 42a6 cmp r6, r4
|
|
800892e: d109 bne.n 8008944 <__libc_init_array+0x24>
|
|
8008930: 2600 movs r6, #0
|
|
8008932: f000 f823 bl 800897c <_init>
|
|
8008936: 4c0a ldr r4, [pc, #40] @ (8008960 <__libc_init_array+0x40>)
|
|
8008938: 4d0a ldr r5, [pc, #40] @ (8008964 <__libc_init_array+0x44>)
|
|
800893a: 1b64 subs r4, r4, r5
|
|
800893c: 10a4 asrs r4, r4, #2
|
|
800893e: 42a6 cmp r6, r4
|
|
8008940: d105 bne.n 800894e <__libc_init_array+0x2e>
|
|
8008942: bd70 pop {r4, r5, r6, pc}
|
|
8008944: 00b3 lsls r3, r6, #2
|
|
8008946: 58eb ldr r3, [r5, r3]
|
|
8008948: 4798 blx r3
|
|
800894a: 3601 adds r6, #1
|
|
800894c: e7ee b.n 800892c <__libc_init_array+0xc>
|
|
800894e: 00b3 lsls r3, r6, #2
|
|
8008950: 58eb ldr r3, [r5, r3]
|
|
8008952: 4798 blx r3
|
|
8008954: 3601 adds r6, #1
|
|
8008956: e7f2 b.n 800893e <__libc_init_array+0x1e>
|
|
8008958: 08008b20 .word 0x08008b20
|
|
800895c: 08008b20 .word 0x08008b20
|
|
8008960: 08008b24 .word 0x08008b24
|
|
8008964: 08008b20 .word 0x08008b20
|
|
|
|
08008968 <memcpy>:
|
|
8008968: 2300 movs r3, #0
|
|
800896a: b510 push {r4, lr}
|
|
800896c: 429a cmp r2, r3
|
|
800896e: d100 bne.n 8008972 <memcpy+0xa>
|
|
8008970: bd10 pop {r4, pc}
|
|
8008972: 5ccc ldrb r4, [r1, r3]
|
|
8008974: 54c4 strb r4, [r0, r3]
|
|
8008976: 3301 adds r3, #1
|
|
8008978: e7f8 b.n 800896c <memcpy+0x4>
|
|
...
|
|
|
|
0800897c <_init>:
|
|
800897c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800897e: 46c0 nop @ (mov r8, r8)
|
|
8008980: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8008982: bc08 pop {r3}
|
|
8008984: 469e mov lr, r3
|
|
8008986: 4770 bx lr
|
|
|
|
08008988 <_fini>:
|
|
8008988: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800898a: 46c0 nop @ (mov r8, r8)
|
|
800898c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800898e: bc08 pop {r3}
|
|
8008990: 469e mov lr, r3
|
|
8008992: 4770 bx lr
|