120 lines
4.0 KiB
C
120 lines
4.0 KiB
C
/*
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* inputs.c
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*
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* Created on: Mar 15, 2022
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* Author: v0stap
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*/
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//Includes
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#include "main.h"
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//Variables
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uint32_t counter0 = 0, counter1 = 0, Counter = 0;
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uint8_t gap = 0;
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// idle in section
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void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3
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// PB4 AF1 TIM3 Input1
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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GPIOB->MODER &= ~(3 << (4 * 2));
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GPIOB->MODER |= (2 << (4 * 2));
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GPIOB->OTYPER &= ~(1 << 4 * 1);
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GPIOB->OSPEEDR &= ~(3 << (4 * 2));
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GPIOB->PUPDR &= ~(3 << (4 * 2));
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GPIOB->AFR[0] &= ~(15 << (4 * 4));
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GPIOB->AFR[0] |= (1 << (4 * 4));
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
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select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
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/* (2) Select TI1FP1 as valid trigger input (TS = 101)
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configure the slave mode in reset mode (SMS = 100) */
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/* (3) Enable capture by setting CC1E and CC2E
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select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
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value),
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select the falling edge on CC2 (CC2P = 1). */
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/* (4) Enable interrupt on Capture/Compare 1 */
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/* (5) Enable counter */
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TIM3->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
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TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
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TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
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TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */
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TIM3->CR1 |= TIM_CR1_CEN; /* (5) */
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NVIC_EnableIRQ(TIM3_IRQn);
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}
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void TIM14_Init(void) { //configure IN2 as rpm input PB1 TIM14
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// PB1 AF0 TIM14 Input1
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// prescaler 1:21 ->1/4uS tick (since APBx presc !=1, timer clocks = APBx_cls x 2)
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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GPIOB->MODER &= ~(3 << (1 * 2));
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GPIOB->MODER |= (2 << (1 * 2));
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GPIOB->OTYPER &= ~(1 << 1 * 1);
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GPIOB->OSPEEDR &= ~(3 << (1 * 2));
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GPIOB->PUPDR &= ~(3 << (1 * 2));
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GPIOB->AFR[0] &= ~(15 << (1 * 4));
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GPIOB->AFR[0] |= (0 << (1 * 4));
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RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
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TIM14->ARR = 0xFFFF;
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TIM14->PSC = 599;
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/* (1) Select the active input TI1 (CC1S = 01),
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program the input filter for 8 clock cycles (IC1F = 0011),
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select the rising edge on CC1 (CC1P = 0, reset value)
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and prescaler at each valid transition (IC1PS = 00, reset value) */
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/* (2) Enable capture by setting CC1E */
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/* (3) Enable interrupt on Capture/Compare */
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/* (4) Enable counter */
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TIM14->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
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TIM14->CCER |= TIM_CCER_CC1E; /* (2) */
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TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */
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TIM14->CR1 |= TIM_CR1_CEN; /* (4) */
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NVIC_EnableIRQ(TIM14_IRQn);
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}
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void TIM3_IRQHandler(void) {
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if ((TIM3->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
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{
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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return;
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} else {
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counter0 = TIM3->CCR1;
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var.idle_dc = (TIM3->CCR2) * 1000 / TIM3->CCR1; //Get DC
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// printf("data1 =%d; data2 =%d \n",counter0,counter1);
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}
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} else {
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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void TIM14_IRQHandler(void) {
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if ((TIM14->SR & TIM_SR_CC1IF) != 0) {
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if ((TIM14->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
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{
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/* Overflow error management */
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/* Reinitialize the laps computing */
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TIM14->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
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var.rpm = 0;
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gap = 0;
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return;
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}
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if (gap == 0) /* Test if it is the first rising edge */
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{
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counter0 = TIM14->CCR1; /* Read the capture counter which clears the
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CC1ICF */
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gap = 1; /* Indicate that the first rising edge has yet been detected */
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} else {
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counter1 = TIM14->CCR1; /* Read the capture counter which clears the
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CC1ICF */
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if (counter1 > counter0) /* Check capture counter overflow */
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{
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Counter = counter1 - counter0;
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} else {
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Counter = counter1 + 0xFFFF - counter0 + 1;
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}
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counter0 = counter1;
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var.rpm = Counter;
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}
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} else {
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/* Unexpected Interrupt */
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/* Manage an error for robust application */
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}
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}
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