commit 78e6a1b8aa49f0e05ccd7f06a223d53547294c3d Author: v0stap Date: Sun Apr 5 11:31:20 2026 +0200 base diff --git a/DBW_V2/.cproject b/DBW_V2/.cproject new file mode 100644 index 0000000..cc291e6 --- /dev/null +++ b/DBW_V2/.cproject @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/DBW_V2/.mxproject b/DBW_V2/.mxproject new file mode 100644 index 0000000..85f8d3b --- /dev/null +++ b/DBW_V2/.mxproject @@ -0,0 +1,25 @@ +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Inc/stm32f0xx_it.h +HeaderFiles#1=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Inc/stm32f0xx_hal_conf.h +HeaderFiles#2=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Inc +SourceFileListSize=3 +SourceFiles#0=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Src/stm32f0xx_it.c +SourceFiles#1=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Src/stm32f0xx_hal_msp.c +SourceFiles#2=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=C:/Users/Dmitrijs/STM32CubeIDE/workspace_1.2.0/DBW_V2/Core/Src +HeaderFiles=; +SourceFiles=; + +[PreviousLibFiles] +LibFiles=Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h;Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h;Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedCubeIDEFiles] +SourceFiles=Core\Src\main.c;Core\Src\stm32f0xx_it.c;Core\Src\stm32f0xx_hal_msp.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c;Core\Src/system_stm32f0xx.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c;Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c;Core\Src/system_stm32f0xx.c;Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c;; +HeaderPath=Drivers\STM32F0xx_HAL_Driver\Inc;Drivers\STM32F0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F0xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F072xB;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/DBW_V2/.project b/DBW_V2/.project new file mode 100644 index 0000000..60ec063 --- /dev/null +++ b/DBW_V2/.project @@ -0,0 +1,34 @@ + + + DBW_V2 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/DBW_V2/.settings/language.settings.xml b/DBW_V2/.settings/language.settings.xml new file mode 100644 index 0000000..6f0ca80 --- /dev/null +++ b/DBW_V2/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/DBW_V2/.settings/stm32cubeide.project.prefs b/DBW_V2/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..59f00f1 --- /dev/null +++ b/DBW_V2/.settings/stm32cubeide.project.prefs @@ -0,0 +1,4 @@ +2F62501ED4689FB349E356AB974DBE57=18280C8C640C052376B23E86B0287A0E +8DF89ED150041C4CBC7CB9A9CAA90856=18280C8C640C052376B23E86B0287A0E +DC22A860405A8BF2F2C095E5B6529F12=254AFEB1658AF80E9F167B4A9A0D9624 +eclipse.preferences.version=1 diff --git a/DBW_V2/Core/Inc/adc.h b/DBW_V2/Core/Inc/adc.h new file mode 100644 index 0000000..f5644ec --- /dev/null +++ b/DBW_V2/Core/Inc/adc.h @@ -0,0 +1,16 @@ +/* + * adc.h + * + * Created on: Sep 6, 2017 + * Author: dmitrijs + */ + +#ifndef ADC_H_ +#define ADC_H_ + +void Adc_Init(void); +unsigned short LPF(unsigned short lpf_c, unsigned short value, + unsigned short old_value); +unsigned short Adc_Read(unsigned char ch); + +#endif /* ADC_H_ */ diff --git a/DBW_V2/Core/Inc/can.h b/DBW_V2/Core/Inc/can.h new file mode 100644 index 0000000..f2e03c6 --- /dev/null +++ b/DBW_V2/Core/Inc/can.h @@ -0,0 +1,73 @@ +/* + * CAN.h + + * + * Created on: Dec 04, 2018 + * Author: v0stap + */ + +#ifndef _CAN_H_ +#define _CAN_H_ + +#define CAN_ID_STD 0x00000000U +#define CAN_ID_EXT 0x00000004U +#define CAN_RTR_DATA 0x00000000U +#define CAN_RTR_REMOTE 0x00000002U + +#define STD_FORMAT 0 +#define EXTD_FORMAT 1 + +#define DATA_FRAME 0 +#define REMOTE_FRAME 1 + +#define CAN_250KBS 0x031c000b +#define CAN_500KBS 0x031c0005 +#define CAN_1000KBS 0x031c0002 + +typedef struct { + uint32_t id; // 29 bit identifier + uint8_t data[8]; // Data field + uint8_t lenght; // Length of data field in bytes + uint8_t format; // 0 - STANDART, 1- EXTENDED + uint8_t frame; // 0 - DATA FRAME, 1 - REMOTE FRAME +} can_msg_typedef; +typedef struct { + can_msg_typedef data[16]; + uint8_t todo; + uint8_t corent; + uint8_t done; +} can_buffer_typedef; + +typedef struct { + CAN_TypeDef *can_port; + uint8_t mode; + uint32_t speed; + uint8_t filter; + uint8_t rx_pin; + uint8_t tx_pin; + GPIO_TypeDef *port; + uint8_t tx_ready; + uint8_t rx_ready; +} can_config_typedef; + +void CAN_Init(void); +void CAN_Setup(uint32_t speed); +void CAN_Start(void); +void CAN_Wait_Ready(void); +void CAN_Send_Msg(can_msg_typedef *msg); +void CAN_Recive_Msg(can_msg_typedef *msg); +void CAN_Write_Filter(uint32_t id, uint8_t format); +void CAN_Send_TX_Buffer(void); +void CAN_Add_TX_Buffer(can_msg_typedef *data); +void CAN_Add_RX_Buffer(void); +void CAN_Read_RX_Buffer(can_msg_typedef *data); + +extern can_msg_typedef CAN_TX_Msg; // CAN message for transmit +extern can_msg_typedef CAN_RX_Msg; // CAN received message +extern uint8_t CAN_TX_Rdy; // CAN hardware ready to transmit a message +extern uint8_t CAN_RX_Rdy; // CAN hardware received a message +extern uint32_t CAN_Speed; // CAN Speed / CAN BTR register +extern can_buffer_typedef CAN_TX_Buffer; +extern can_buffer_typedef CAN_RX_Buffer; +#endif // _CAN_H_ + diff --git a/DBW_V2/Core/Inc/dbw.h b/DBW_V2/Core/Inc/dbw.h new file mode 100644 index 0000000..e7f254a --- /dev/null +++ b/DBW_V2/Core/Inc/dbw.h @@ -0,0 +1,260 @@ +/* + * dbw.h + * + * Created on: May 5, 2021 + * Author: Dmitrijs + */ + + + + +#ifndef SRC_DBW_H_ +#define SRC_DBW_H_ + + +#define CONFIG_AGREEMENT_F 0x01 +#define CONFIG_SENSORS_CALIBRATED_F 0x02 +#define CONFIG_TESTMODE_F 0x04 +#define CONFIG_SAFETY_FEATURES_F 0x08 + + + + +#define DBW_STATUS0_READY_F 0x1 +#define DBW_STATUS0_AGREEMENT_F 0x2 +#define DBW_STATUS0_SENSOR_CAL_F 0x4 +#define DBW_STATUS0_FAULT_F 0x8 +#define DBW_STATUS0_CAN_MSDBW_F 0x10 +#define DBW_STATUS0_CAN_RX_BCST_F 0x20 +#define DBW_STATUS0_PWM_IDLE_F 0x40 +#define DBW_STATUS0_GPI1_F 0x80 +#define DBW_STATUS0_GPI2_F 0x100 +#define DBW_STATUS0_GPO1_F 0x200 +#define DBW_STATUS0_GPO2_F 0x400 +#define DBW_STATUS0_PPSTPS_CAL_F 0x800 +#define DBW_STATUS0_UNPROTECTED_F 0x1000 +#define DBW_STATUS0_CONF_ERROR_F 0x2000 +#define DBW_STATUS0_SENSOR_FAULT_F 0x4000 + +#define DBW_STATUS1_SAFETY_F 0x01 + + +#define PPS2_CALC_OPTION_LINEAR 0 +#define PPS2_CALC_OPTION_POLYNOMAL 1 +#define TPS2_CALC_OPTION_LINEAR 0 +#define TPS2_CALC_OPTION_POLYNOMAL 1 + +#define PPS2TPS_OPTION_CURVE 0 +#define PPS2TPS_OPTION_MS3_CAN 1 + +#define IDLE_OPTION_NO_IDLE_INPUT 0 +#define IDLE_OPTION_PWM_INPUT1 1 +#define IDLE_OPTION_PWM_INPUT2 2 +#define IDLE_OPTION_MS_CAN 3 + + +#define MOTOR_PID_OPTION_STATIC 0 +#define MOTOR_PID_OPTION_STATIC_FWRW 1 +#define MOTOR_PID_OPTION_TABLE 2 + + +typedef struct +{ +uint8_t pps_calc_option; +uint8_t tps_calc_option; + +uint16_t pps1_min; +uint16_t pps1_max; + +uint16_t pps2_min; +uint16_t pps2_mid; +uint16_t pps2_mid_pct; +uint16_t pps2_max; + +uint16_t tps1_min; +uint16_t tps1_max; + +uint16_t tps2_min; +uint16_t tps2_mid; +uint16_t tps2_mid_pct; +uint16_t tps2_max; + +uint8_t pps2tps_option; +uint8_t idle_input_option; + +// pps to tps target curve +int16_t pps_bins[16]; //[0.1%] +int16_t tps_bins[16]; //[0.1%] + +// Idle pps modifier curve. when Idle input is used. it modifies tps target +int16_t idle_input_bins[8]; //input pwm duty [0.1%] +int16_t idle_tps_adder_bins[8]; //tps target adder [0.1%] + + +uint16_t motor_pwm_fq; // frequency in Hz +uint16_t motor_ctl_period; // ctl_teriod in [100uS] +uint16_t motor_pid_option; // PID static coefs, static coef, but different for forward and backward moving + // 3D table + +// PID COEFICIENTS for forward and reward +int16_t motor_fw_p; +int16_t motor_fw_i; +int16_t motor_fw_d; +int16_t motor_rw_p; +int16_t motor_rw_i; +int16_t motor_rw_d; + +int16_t motor_p_tps_bins[16]; +int16_t motor_p_error_bins[16]; +int16_t motor_p_table[16][16]; + +//PID limmits +int16_t i_limmit; +int16_t motor_dc_max; +int16_t motor_dc_min; + + + +//DC offset curve +int16_t tps_dc_tps_bins[16]; // tps bins [0.1%] +int16_t tps_dc_offset_bins[16]; // motor pwm offset [0.01%PWM] + +//Battery voltage correction curve +uint16_t vbat_bins[8]; // battery voltage ADC bins [] +int16_t motor_pwm_corr_bins[8]; // motor pwm correction [0.1%] + +uint16_t pwm_deadtime; +uint16_t can_dbw_id; +uint16_t can_idle_base_id; +uint16_t config_bits; + +uint16_t pps1_margin; +uint16_t pps2_margin; +int16_t pps_delta_margin; + + + +uint16_t tps1_margin; +uint16_t tps2_margin; +uint16_t tps_delta_margin; + +int16_t tps_error_margin1; +uint16_t tps_error_time1; + +int16_t tps_error_margin2; +uint16_t tps_error_time2; + + +uint16_t can_dbw_poll_perod; + +//enable tuning over CAN; +uint8_t can_ms29bit_id; +uint8_t can_ms29bit_options; + + +//broadcast my data +uint8_t can_bcst_data_enable; +uint8_t can_bcst_data_period; +uint16_t can_bcst_canid; + + + + +}config_t; + +typedef struct +{ +uint32_t clock; +uint16_t status0; +uint16_t status1; +uint16_t status2; +uint16_t status3; + +uint16_t pps1_adc; +uint16_t pps2_adc; +uint16_t tps1_adc; +uint16_t tps2_adc; +uint16_t motor_current_adc; +uint16_t vbat_adc; + +int16_t pps1; +int16_t pps2; +int16_t tps1; +int16_t tps2; +int16_t pps; +int16_t tps; +int16_t tps_error; +int16_t motor_pwm; +uint16_t idle_dc; +int16_t pps_delta; +int16_t tps_delta; +int16_t tps_target; +uint16_t vss; +uint16_t rpm; +}var_t; + + + + +#define PWM_STATUS_DEFAULT 0 +#define PWM_STATUS_IDLE 1 +#define PWM_STATUS_STARTED 2 +#define PWM_STATUS_ERROR 3 + +#define PWM_STATE_POSITIVE_INACTIVE 0 +#define PWM_STATE_POSITIVE_ACTIVE 1 +#define PWM_STATE_NEGATIVE_INACTIVE 2 +#define PWM_STATE_NEGATIVE_ACTIVE 3 + + + +typedef struct +{ + unsigned char status; + unsigned char state; + GPIO_TypeDef *pos_port; + unsigned short pos_pin; + GPIO_TypeDef *neg_port; + unsigned short neg_pin; + unsigned int period_ticks; + unsigned int duty_ticks; + signed int pwm; + signed int pwm_t; + signed int single_pulse; +}pwm_t; + + +extern volatile float pps1_gain, pps1_offset, pps2_gain, pps2_offset, tps1_gain, tps2_offset; +extern volatile uint16_t dbw_fast_process_timer, dbw_slow_process_timer; +void Apply_Sensor_Calibration(void); +int DBW_Process(void); +void DBW_Pwm_Init(void); +void DBW_Pwm_Set_Duty(signed int duty, pwm_t* ttl); +void TIM2_IRQHandler (void); +int intrp_1dstable(signed short x, unsigned char n, signed short * x_table, char sgn,signed short * z_table); +signed short intrp_1d_ss_table(signed short x, unsigned char n, signed short * x_table, char sgn, signed short * z_table); +unsigned int intrp_1d_uitable(unsigned int x, unsigned char nx, unsigned int * x_table, unsigned int * z_table); +void DBW_Init(void); +void DBW_Start(void); +void DBW_Stop(void); +void DBW_TPS_AutoCal(void); +void DBW_Read_sensors(void); + + +extern volatile pwm_t ttl1_pwm; +extern volatile unsigned short ctl_period; + +extern volatile config_t config_ram; +extern volatile var_t var; +extern volatile config_t *config; +extern const config_t config_flash; +extern volatile int32_t vbat_corr, tps_slow_t, p_comp, i_comp, d_comp, tps_error_t, can_target, spring_preload, idle_adder; +extern volatile uint32_t ac_timer, ac_mode; + + + + + + + +#endif /* SRC_DBW_H_ */ diff --git a/DBW_V2/Core/Inc/inputs.h b/DBW_V2/Core/Inc/inputs.h new file mode 100644 index 0000000..8bbb51e --- /dev/null +++ b/DBW_V2/Core/Inc/inputs.h @@ -0,0 +1,14 @@ +/* + * inputs.h + * + * Created on: Mar 15, 2022 + * Author: v0stap + */ + +#ifndef SRC_INPUTS_H_ +#define SRC_INPUTS_H_ + +void TIM3_Init(void); //iddle pwm input 1 PB4 +void TIM14_Init(void); //rpm input 2 PB1 + +#endif /* SRC_INPUTS_H_ */ diff --git a/DBW_V2/Core/Inc/main.h b/DBW_V2/Core/Inc/main.h new file mode 100644 index 0000000..ade6eb8 --- /dev/null +++ b/DBW_V2/Core/Inc/main.h @@ -0,0 +1,112 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "ts_comms.h" +#include "dbw.h" +#include "adc.h" +#include "can.h" +#include "safety.h" +#include "inputs.h" +#include "outputs.h" +#include "mazda_can.h" +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define PPS1_Pin GPIO_PIN_0 +#define PPS1_GPIO_Port GPIOA +#define PPS2_Pin GPIO_PIN_1 +#define PPS2_GPIO_Port GPIOA +#define TPS1_Pin GPIO_PIN_2 +#define TPS1_GPIO_Port GPIOA +#define TPS2_Pin GPIO_PIN_3 +#define TPS2_GPIO_Port GPIOA +#define TTL_FB_Pin GPIO_PIN_4 +#define TTL_FB_GPIO_Port GPIOA +#define VBAT_SENSE_Pin GPIO_PIN_5 +#define VBAT_SENSE_GPIO_Port GPIOA +#define IN1_Pin GPIO_PIN_0 +#define IN1_GPIO_Port GPIOB +#define IN2_Pin GPIO_PIN_1 +#define IN2_GPIO_Port GPIOB +#define PWM1_Pin GPIO_PIN_10 +#define PWM1_GPIO_Port GPIOB +#define PWM2_Pin GPIO_PIN_11 +#define PWM2_GPIO_Port GPIOB +#define FAULT_Pin GPIO_PIN_12 +#define FAULT_GPIO_Port GPIOB +#define D2_Pin GPIO_PIN_13 +#define D2_GPIO_Port GPIOB +#define D1_Pin GPIO_PIN_14 +#define D1_GPIO_Port GPIOB +#define STATUS_FLAG_Pin GPIO_PIN_15 +#define STATUS_FLAG_GPIO_Port GPIOB +#define GPO1_Pin GPIO_PIN_5 +#define GPO1_GPIO_Port GPIOB +#define GPO2_1_Pin GPIO_PIN_6 +#define GPO2_1_GPIO_Port GPIOB +#define GPO2_2_Pin GPIO_PIN_7 +#define GPO2_2_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Inc/mazda_can.h b/DBW_V2/Core/Inc/mazda_can.h new file mode 100644 index 0000000..19f6003 --- /dev/null +++ b/DBW_V2/Core/Inc/mazda_can.h @@ -0,0 +1,14 @@ +/* + * mazda_can.h + * + * Created on: Mar 17, 2022 + * Author: v0stap + */ + +#ifndef INC_MAZDA_CAN_H_ +#define INC_MAZDA_CAN_H_ +void MAZDA_Send_Data(void); +void MAZDA_CAN_Read(void); + + +#endif /* INC_MAZDA_CAN_H_ */ diff --git a/DBW_V2/Core/Inc/outputs.h b/DBW_V2/Core/Inc/outputs.h new file mode 100644 index 0000000..c5dfa6c --- /dev/null +++ b/DBW_V2/Core/Inc/outputs.h @@ -0,0 +1,14 @@ +/* + * outputs.h + * + * Created on: Mar 16, 2022 + * Author: v0stap + */ + +#ifndef INC_OUTPUTS_H_ +#define INC_OUTPUTS_H_ + +void TIM16_Init (void); +void TIM17_Init (void); +void VSS_Set(uint8_t vss); +#endif /* INC_OUTPUTS_H_ */ diff --git a/DBW_V2/Core/Inc/safety.h b/DBW_V2/Core/Inc/safety.h new file mode 100644 index 0000000..38345e2 --- /dev/null +++ b/DBW_V2/Core/Inc/safety.h @@ -0,0 +1,31 @@ + +#ifndef SRC_SAFETY_H_ +#define SRC_SAFETY_H_ + +#define STATUS3_NO_FAULT 0 +#define STATUS3_PPS1_SS_GND 1 +#define STATUS3_PPS1_SS_VREF 2 +#define STATUS3_PPS2_SS_GND 3 +#define STATUS3_PPS2_SS_VREF 4 +#define STATUS3_PPS_DELTA 5 +#define STATUS3_TPS1_SS_GND 6 +#define STATUS3_TPS1_SS_VREF 7 +#define STATUS3_TPS2_SS_GND 8 +#define STATUS3_TPS2_SS_VREF 9 +#define STATUS3_TPS_DELTA 10 +#define STATUS3_TARGET1_FAULT 11 +#define STATUS3_TARGET2_FAULT 12 + +void Flash_Write_Protect(void); +void Flash_Write_Unprotect(void); +void Watch_Dog_Update(void); +void Watch_Dog_Init(void); +void Check_Adc_Range(void); +void Check_Safety_Limits(void); +void Check_TPS_Target(); +void Safety_TPS_Safety_Timer_Start(void); +void Safety_TPS_Safety_Timer(void); + +extern volatile int dbw_target_tmr1, dbw_target_tmr2; + +#endif diff --git a/DBW_V2/Core/Inc/stm32f0xx_hal_conf.h b/DBW_V2/Core/Inc/stm32f0xx_hal_conf.h new file mode 100644 index 0000000..15b6ce3 --- /dev/null +++ b/DBW_V2/Core/Inc/stm32f0xx_hal_conf.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CONF_H +#define __STM32F0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + #define HAL_ADC_MODULE_ENABLED +/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator for ADC (HSI14) value. + */ +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSI) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 +#define USE_SPI_CRC 0U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f0xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Inc/stm32f0xx_it.h b/DBW_V2/Core/Inc/stm32f0xx_it.h new file mode 100644 index 0000000..4ea192f --- /dev/null +++ b/DBW_V2/Core/Inc/stm32f0xx_it.h @@ -0,0 +1,65 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_IT_H +#define __STM32F0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Inc/ts_comms.h b/DBW_V2/Core/Inc/ts_comms.h new file mode 100644 index 0000000..2d744e4 --- /dev/null +++ b/DBW_V2/Core/Inc/ts_comms.h @@ -0,0 +1,108 @@ +/* + * ts_comms.h + * + * Created on: 22 Oct 2020 + * Author: Dmitrijs + */ + +#ifndef TS_COMMS_H_ +#define TS_COMMS_H_ + +#include + +typedef unsigned char crc_t; + +#define TS_CAN_ID 0 + +#ifndef TS_CAN_ID +#error Set CAN ID !!! ts_comms.h +#endif + +// Timeouts for comms: in mS +// Timeout for receive 2 bytes after +#define RECEIVE_INDEX_TIMEOUT 10 +//Timeout for receive 4 bytes of OFFSET and COUNT +#define RECEIVE_DATA_LOCATION_TIMEOUT 10 +//Time out for receive block of data +#define RECEIVE_DATA_TIMEOUT 255 +//Timeout for RESET sequence. +#define RECEIVE_RESET_TIMEOUT 1 +#define RECEIVE_TABLE_TIMEOUT 255 + +//Define SCI MODES +#define IDLE 0 +#define TRANSMISSION_IN_PROGRESS 1 +#define RECEIVE_INDEX 1 +#define RECEIVE_DATA_LOCATION 2 +#define RECEIVE_DATA 3 +#define RECEIVE_TABLE_DATA 4 +#define RECEIVE_CANID 5 +#define RECEIVE_RESET_CMD 10 + +//DEFINE ERROR CODES FOR TS COMMS +#define DATA_OVERRUN_ERROR 1 +#define FRAME_ERROR 2 +#define PARITY_ERROR 3 +#define UNRECOGNIZED_1_LETTER_CMD 4 +#define REQUEST_TO_TRANSMIT_WHILE_TRANSMITTING 5 +#define RESET_SEQUENCE_FAILED 6 +#define RESET_SEQUENCE_RECEIVED 7 +#define MEMORY_ACCESS_VIOLATION 8 +#define RX_TIMEOUT 9 +#define NOICE_ERROR 10 + +#define SCI_FLAGS_CRC32 1 +#define SCI_FLAGS_TX_VARIABLES 2 + +#define READ_DATA_FROM_ADC0 0 +#define READ_DATA_FROM_ADC1 1 +#define READ_DATA_FROM_CONFIG_ADC0 2 +#define READ_DATA_FROM_CONFIG_ADC1 3 +#define READ_DATA_FROM_Z0 4 +#define READ_DATA_FROM_Z1 5 + +typedef struct { + + unsigned char mode; //1 + unsigned char cmd; //2 + unsigned char CANid; //3 + unsigned char table_index; //4 + unsigned short offset; //5 + unsigned short data_size; //7 + unsigned short cnt; //9 + unsigned short bytes_done; //11 + unsigned char *address; //13 + unsigned char current_table_index; //15 + unsigned char error_cnt; //16 + unsigned char error_code; //17 + unsigned short timeout; //18 + unsigned char pause_flag; + unsigned char dummy; + unsigned long crc32; //19 + unsigned char can_bufer[256]; +} comms_status; + +void Rx_Char(unsigned char data); // pass RX byte stream here +void Poll_Tx(void); // function returns pointer to buffer and sets count + // of bytes to be transmitted +void TX_Done(void); // call this function when all data has been transmitted +void Comms_Init(void); + +void Write_Config(void); + +extern comms_status RX; +extern comms_status TX; +extern unsigned char SCI_flags; +extern const char Signature[20]; +extern const char Revision[20]; +extern char crc32_bufer[8]; +void Comms_Reset(comms_status *CS); +void TX_Schedule(unsigned char *data, unsigned short count); +void Copy_Tx_Vars(void); +void CRC32(void); +crc_t calc_crc(crc_t message[], int nBytes); +uint32_t crc32(void *buf, uint32_t size); +uint32_t crc32inc(void *buf, uint32_t crc, uint32_t size); +void TS_Comms_RX_Timeout(void); + +#endif /* TS_COMMS_H_ */ diff --git a/DBW_V2/Core/Src/adc.c b/DBW_V2/Core/Src/adc.c new file mode 100644 index 0000000..e3c8f4f --- /dev/null +++ b/DBW_V2/Core/Src/adc.c @@ -0,0 +1,80 @@ +/* + * adc.c + * + * Created on: Sep 6, 2017 + * Author: dmitrijs + */ + +#include "main.h" + +void Adc_Init(void) { + + RCC->APB2ENR |= RCC_APB2ENR_ADCEN; + ADC1->CFGR2 = (0x00000002 << 30); // pclk/4 -> 12Mhz + ADC1->SMPR = 0x00000001; // Sample 7.5 adc cycles + ADC1->CFGR1 = 0; + /* (1) Ensure that ADEN = 0 */ + /* (2) Clear ADEN by setting ADDIS*/ + /* (3) Clear DMAEN */ + /* (4) Launch the calibration by setting ADCAL */ + /* (5) Wait until ADCAL=0 */ + if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */ + { + ADC1->CR |= ADC_CR_ADDIS; /* (2) */ + } + while ((ADC1->CR & ADC_CR_ADEN) != 0) { + /* For robust implementation, add here time-out management */ + } + ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN; /* (3) */ + ADC1->CR |= ADC_CR_ADCAL; /* (4) */ + while ((ADC1->CR & ADC_CR_ADCAL) != 0) /* (5) */ + { + /* For robust implementation, add here time-out management */ + } + /* (1) Ensure that ADRDY = 0 */ + /* (2) Clear ADRDY */ + /* (3) Enable the ADC */ + /* (4) Wait until ADC ready */ + if ((ADC1->ISR & ADC_ISR_ADRDY) != 0) /* (1) */ + { + ADC1->ISR |= ADC_ISR_ADRDY; /* (2) */ + } + ADC1->CR |= ADC_CR_ADEN; /* (3) */ + while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (4) */ + { + /*TODO For robust implementation, add here time-out management */ + } + + ADC1->IER = 0; +//NVIC_EnableIRQ(ADC1_IRQn); +} + +unsigned short LPF(unsigned short lpf_c, unsigned short value, + unsigned short old_value) { + // Averageing filtering + + float tmp; + + tmp = ((float) (value - old_value) * ((float) (lpf_c) / (float) 1000.0)); // filter + if (tmp > 0) + tmp += (float) 0.5; // roundup + else + tmp -= (float) 0.5; + + return (unsigned short) ((signed int) old_value + (signed int) tmp); + +} + +unsigned short Adc_Read(unsigned char ch) { + unsigned short tmp; + if (ADC1->ISR & ADC_ISR_EOC) + tmp = ADC1->DR; //ADC1->ISR |= ADC_ISR_EOC; // clear EOC flag + ADC1->CHSELR = (1 << ch); // select channel + ADC1->CR |= ADC_CR_ADSTART; + while ((~ADC1->ISR) & ADC_ISR_EOC) + ; + ADC1->ISR |= ADC_ISR_EOC; + tmp = ADC1->DR; + return tmp; +} + diff --git a/DBW_V2/Core/Src/can.c b/DBW_V2/Core/Src/can.c new file mode 100644 index 0000000..3377d5a --- /dev/null +++ b/DBW_V2/Core/Src/can.c @@ -0,0 +1,281 @@ +/* + * CAN.c + + * + * Created on: Dec 04, 2018 + * Author: v0stap + */ + +#include "main.h" +#include "CAN.h" + +can_msg_typedef CAN_TX_Msg; // CAN message for transmit +can_msg_typedef CAN_RX_Msg; // CAN received message +uint8_t CAN_TX_Rdy = 0; // CAN hardware ready to transmit a message +uint8_t CAN_RX_Rdy = 0; // CAN hardware message received +uint32_t CAN_Speed = CAN_500KBS; // CAN Speed / CAN BTR register +can_buffer_typedef CAN_TX_Buffer, CAN_RX_Buffer; +uint8_t CAN_Filter_Idx = 0; // CAN filter index + +void CAN_Init(void) { + CAN_TX_Buffer.todo = 0; + CAN_TX_Buffer.corent = 0; + CAN_TX_Buffer.done = 0; + CAN_RX_Buffer.todo = 0; + CAN_RX_Buffer.corent = 0; + CAN_RX_Buffer.done = 0; + CAN_Setup(CAN_500KBS); + CAN_Write_Filter(0x212, STD_FORMAT); + CAN_Write_Filter(0x643, STD_FORMAT); + //CAN_Write_Filter(0x620, STD_FORMAT); + //CAN_Write_Filter(0x630, STD_FORMAT); + //CAN_Write_Filter(0x240, STD_FORMAT); + CAN_Start(); + CAN_Wait_Ready(); +} +/*---------------------------------------------------------------------------- + setup CAN interface + *----------------------------------------------------------------------------*/ +void CAN_Setup(uint32_t speed) { + + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + RCC->APB1ENR |= RCC_APB1ENR_CANEN; + GPIOB->MODER &= ~((3 << (8 * 2)) | (3 << (9 * 2))); + GPIOB->MODER |= ((2 << (8 * 2)) | (2 << (9 * 2))); + GPIOB->OTYPER &= ~((1 << 8) | (1 << 9)); + GPIOB->OSPEEDR &= ~((3 << (8 * 2)) | (3 << (9 * 2))); + GPIOB->PUPDR &= ~((3 << (8 * 2)) | (3 << (9 * 2))); + GPIOB->AFR[1] &= ~((15 << (0 * 4)) | (15 << (1 * 4))); + GPIOB->AFR[1] |= ((4 << 0) | (4 << (1 * 4))); + CAN->MCR |= CAN_MCR_INRQ; + while ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { + //some code + } + CAN->MCR &= ~ CAN_MCR_SLEEP; + CAN->BTR &= ~(((0x03) << 24) | ((0x07) << 20) | ((0x0F) << 16) | (0x1FF)); + CAN->BTR |= speed; + NVIC_EnableIRQ(CEC_CAN_IRQn); + CAN->IER |= CAN_IER_FMPIE0; +} + +/*---------------------------------------------------------------------------- + leave initialisation mode + *----------------------------------------------------------------------------*/ +void CAN_Start(void) { + CAN->MCR &= ~CAN_MCR_INRQ; + while ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { + + } + +} + +/*---------------------------------------------------------------------------- + check if transmit mailbox is empty + *----------------------------------------------------------------------------*/ +void CAN_Wait_Ready(void) { + while ((CAN->TSR & CAN_TSR_TME0) == 0) { // Transmit mailbox 0 is empty + + } + CAN_TX_Rdy = 1; +} + +// CAN send data +void CAN_Send_Msg(can_msg_typedef *msg) { + CAN_TX_Rdy = 0; + CAN->sTxMailBox[0].TIR = (uint32_t) 0; + if (msg->format == STD_FORMAT) { + CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 21) | CAN_ID_STD; + } else { + CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 3) | CAN_ID_EXT; + } + if (msg->frame == DATA_FRAME) { + CAN->sTxMailBox[0].TIR |= CAN_RTR_DATA; + } else { + CAN->sTxMailBox[0].TIR |= CAN_RTR_REMOTE; + } + CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24) + | ((uint32_t) msg->data[2] << 16) | ((uint32_t) msg->data[1] << 8) + | ((uint32_t) msg->data[0])); + CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24) + | ((uint32_t) msg->data[6] << 16) | ((uint32_t) msg->data[5] << 8) + | ((uint32_t) msg->data[4])); + CAN->sTxMailBox[0].TDTR &= ~CAN_TDT0R_DLC; + CAN->sTxMailBox[0].TDTR |= (msg->lenght & CAN_TDT0R_DLC); + CAN->IER |= CAN_IER_TMEIE; + CAN->sTxMailBox[0].TIR |= CAN_TI0R_TXRQ; +} +// Read CAN message +void CAN_Recive_Msg(can_msg_typedef *msg) { + if ((CAN->sFIFOMailBox[0].RIR & CAN_ID_EXT) == 0) { + msg->format = STD_FORMAT; + msg->id = (uint32_t) 0x000007FF & (CAN->sFIFOMailBox[0].RIR >> 21); + } else { + msg->format = EXTD_FORMAT; + msg->id = (uint32_t) 0x0003FFFF & (CAN->sFIFOMailBox[0].RIR >> 3); + } + if ((CAN->sFIFOMailBox[0].RIR & CAN_RTR_REMOTE) == 0) { + msg->frame = DATA_FRAME; + } else { + msg->frame = REMOTE_FRAME; + } + msg->lenght = (uint8_t) 0x0000000F & CAN->sFIFOMailBox[0].RDTR; + msg->data[0] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDLR); + msg->data[1] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDLR >> 8); + msg->data[2] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDLR >> 16); + msg->data[3] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDLR >> 24); + msg->data[4] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDHR); + msg->data[5] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDHR >> 8); + msg->data[6] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDHR >> 16); + msg->data[7] = (uint32_t) 0x000000FF & (CAN->sFIFOMailBox[0].RDHR >> 24); + CAN->RF0R |= CAN_RF0R_RFOM0; + + CAN_RX_Rdy = 0; +// if (msg->id == 0x643) +// printf( +// "CAN ID: 0x%X%X Data: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X \n", +// (uint16_t) (msg->id >> 16), (uint16_t) msg->id, msg->data[0], +// msg->data[1], msg->data[2], msg->data[3], msg->data[4], +// msg->data[5], msg->data[6], msg->data[7]); +// //(&canRxMsg); //TO DO not realy working +} +//Write CAN Filter +void CAN_Write_Filter(uint32_t id, uint8_t format) { + uint32_t CAN_msg_typedefId = 0; + if (CAN_Filter_Idx > 13) { + return; + } + if (format == STD_FORMAT) { + CAN_msg_typedefId |= (uint32_t) (id << 21) | CAN_ID_STD; + } else { + CAN_msg_typedefId |= (uint32_t) (id << 3) | CAN_ID_EXT; + } + CAN->FMR |= CAN_FMR_FINIT; + CAN->FA1R &= ~(uint32_t) (1 << CAN_Filter_Idx); + CAN->FS1R |= (uint32_t) (1 << CAN_Filter_Idx); + CAN->FM1R |= (uint32_t) (1 << CAN_Filter_Idx); + //Comment next to lines for no filter + if (id != 0) { + CAN->sFilterRegister[CAN_Filter_Idx].FR1 = CAN_msg_typedefId; + CAN->sFilterRegister[CAN_Filter_Idx].FR2 = CAN_msg_typedefId; + //Uncomment next to line for no filter + } else { + CAN->sFilterRegister[CAN_Filter_Idx].FR1 = 0; // 32-bit identifier + CAN->sFilterRegister[CAN_Filter_Idx].FR2 = 0; // 32-bit identifier + } + CAN->FFA1R &= ~(uint32_t) (1 << CAN_Filter_Idx); + CAN->FA1R |= (uint32_t) (1 << CAN_Filter_Idx); + CAN->FMR &= ~CAN_FMR_FINIT; + CAN_Filter_Idx++; +} +//CAN recive/transmit irq handler +void CEC_CAN_IRQHandler(void) { + if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) { + CAN->TSR |= CAN_TSR_RQCP0; + CAN->IER &= ~CAN_IER_TMEIE; + CAN_TX_Rdy = 1; + } + if ((CAN->RF0R & CAN_RF0R_FMP0) != 0) { + CAN_Add_RX_Buffer(); + // TO DO + CAN->RF0R |= CAN_RF0R_RFOM0; + CAN_RX_Rdy = 1; + } +} +void CAN_Send_TX_Buffer(void) { + + if (CAN_TX_Rdy) { + //HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1); + if (CAN_TX_Buffer.todo > 0) { + CAN_TX_Buffer.todo--; + //HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1); + CAN_Send_Msg(&CAN_TX_Buffer.data[CAN_TX_Buffer.done]); + if ((CAN_TX_Buffer.done++) > 14) { + CAN_TX_Buffer.done = 0; + } + } + } +} +void CAN_Add_TX_Buffer(can_msg_typedef *data) { + if ((CAN_TX_Buffer.todo++) < 15) { + if ((CAN_TX_Buffer.corent++) > 14) { + CAN_TX_Buffer.corent = 0; + } + //memcpy((void*) &canTX_buffer.data[canTX_buffer.corent], (void*) &data, sizeof(CAN_msg_typedef)); + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].id = data->id; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].format = data->format; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].frame = data->frame; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].lenght = data->lenght; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[0] = data->data[0]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[1] = data->data[1]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[2] = data->data[2]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[3] = data->data[3]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[4] = data->data[4]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[5] = data->data[5]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[6] = data->data[6]; + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[7] = data->data[7]; + } +} +void CAN_Add_RX_Buffer(void) { + if ((CAN_RX_Buffer.todo) < 16) { + CAN_RX_Buffer.todo++; + if ((CAN->sFIFOMailBox[0].RIR & CAN_ID_EXT) == 0) { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = STD_FORMAT; + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF + & (CAN->sFIFOMailBox[0].RIR >> 21); + } else { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = EXTD_FORMAT; + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF + & (CAN->sFIFOMailBox[0].RIR >> 3); + } + if ((CAN->sFIFOMailBox[0].RIR & CAN_RTR_REMOTE) == 0) { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = DATA_FRAME; + } else { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = REMOTE_FRAME; + } + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F + & CAN->sFIFOMailBox[0].RDTR; + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[0] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[1] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 8); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[2] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 16); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[3] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 24); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[4] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[5] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 8); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[6] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 16); + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[7] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 24); + if ((CAN_RX_Buffer.corent++) > 15) { + CAN_RX_Buffer.corent = 0; + } + + //canAddRXBuffer(&canRxMsg); //TO DO not realy working + } + CAN->RF0R |= CAN_RF0R_RFOM0; +} +void CAN_Read_RX_Buffer(can_msg_typedef *data) { + if (CAN_RX_Buffer.todo > 0) { + //memcpy((void*) &data, (void*) &canRX_buffer.data[canRX_buffer.done], sizeof(CAN_msg_typedef)); + data->id = CAN_RX_Buffer.data[CAN_RX_Buffer.done].id; + data->format = CAN_RX_Buffer.data[CAN_RX_Buffer.done].format; + data->frame = CAN_RX_Buffer.data[CAN_RX_Buffer.done].frame; + data->lenght = CAN_RX_Buffer.data[CAN_RX_Buffer.done].lenght; + data->data[0] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[0]; + data->data[1] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[1]; + data->data[2] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[2]; + data->data[3] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[3]; + data->data[4] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[4]; + data->data[5] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[5]; + data->data[6] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[6]; + data->data[7] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[7]; + if ((CAN_RX_Buffer.done++) > 15) { + CAN_RX_Buffer.done = 0; + } + CAN_RX_Buffer.todo--; + } +} diff --git a/DBW_V2/Core/Src/dbw.c b/DBW_V2/Core/Src/dbw.c new file mode 100644 index 0000000..f0c5ee5 --- /dev/null +++ b/DBW_V2/Core/Src/dbw.c @@ -0,0 +1,664 @@ +/* + * dbw.c + * + * Created on: May 5, 2021 + * Author: Dmitrijs + */ + +#include "main.h" + + +volatile config_t config_ram; +volatile var_t var; +volatile config_t *config; + +volatile uint32_t ac_timer = 100, ac_mode = 0; + +const config_t config_flash __attribute__((section(".config"), used)) = { +PPS2_CALC_OPTION_LINEAR, +TPS2_CALC_OPTION_LINEAR, + +100, 3990, + +100, 2048, 500, 3990, + +100, 3990, + +100, 2048, 500, 3990, + +PPS2TPS_OPTION_CURVE, +IDLE_OPTION_NO_IDLE_INPUT, + + { 0, 67, 132, 198, 264, 330, 396, 462, 528, 594, 660, 726, 792, 858, + 924, 1000 }, { 0, 67, 132, 198, 264, 330, 396, 462, 528, 594, + 660, 726, 792, 858, 924, 1000 }, + + // Idle pps modifier curve. when Idle input is used. it modifies tps target + { 0, 142, 284, 426, 568, 710, 852, 1000 }, //input pwm duty [0.1%] + { 0, 8, 17, 25, 34, 42, 51, 60 }, + + 1000, // frequency in Hz + 10, // ctl_teriod in [100uS] + MOTOR_PID_OPTION_STATIC,// PID static coefs, static coef, but different for forward and backward moving + // 3D table + + // PID COEFICIENTS for forward and reward + 700, 50, 10, 700, 50, 10, + + { 0, 67, 132, 198, 264, 330, 396, 462, 528, 594, 660, 726, 792, 858, + 924, 1000 }, { -325, -281, -239, -196, -153, -110, -67, -24, 18, + 61, 104, 146, 189, 232, 275, 325 }, { { 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, { 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700 }, { 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, { 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700 }, { 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700 }, + { 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, { + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, + { 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, { + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700 }, { 700, 700, 700, 700, 700, + 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700 }, + { 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, 700, + 700, 700, 700, 700 }, }, + + //PID limmits + 100, 10000, -10000, + + //DC offset curve + { 0, 67, 132, 198, 264, 330, 396, 462, 528, 594, 660, 726, 792, 858, + 924, 1000 }, // tps bins [0.1%] + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // DC + + //Battery voltage correction curve + { 0, 585, 1170, 1755, 2340, 2925, 3510, 4095 }, // battery voltage ADC bins [] + { 0, 0, 0, 0, 0, 0, 0, 0 }, // motor pwm correction [0.1%] + + 30, 0x100, 0x5e8, 0x00, + + //limmits + 30, 30, 15, 30, 30, 15, 100, 500, 10, 5000, + + 5, 7, // my MS CAN ID + 1, 0, 100, 0x300 }; + +volatile unsigned short ctl_period; +volatile pwm_t ttl1_pwm; +volatile float pps1_gain, pps1_offset, pps2_gain, pps2_offset, tps1_gain, + tps1_offset, tps2_gain, tps2_offset; +volatile uint16_t dbw_fast_process_timer, dbw_slow_process_timer; +volatile int32_t vbat_corr, tps_slow_t, p_comp, i_comp, d_comp, tps_error_t, + can_target, spring_preload, idle_adder; + +void Apply_Sensor_Calibration(void) { + pps1_gain = (1000.0F / (float) (config->pps1_max - config->pps1_min)); + pps1_offset = (config->pps1_min * 1000.0F + / (config->pps1_min - config->pps1_max)); + + pps2_gain = (1000.0F / (float) (config->pps2_max - config->pps2_min)); + pps2_offset = (config->pps2_min * 1000.0F + / (config->pps2_min - config->pps2_max)); + + tps1_gain = (1000.0F / (float) (config->tps1_max - config->tps1_min)); + tps1_offset = (short) (config->tps1_min * 1000.0F + / (config->tps1_min - config->tps1_max)); + + tps2_gain = (1000.0F / (float) (config->tps2_max - config->tps2_min)); + tps2_offset = (config->tps2_min * 1000.0F + / (config->tps2_min - config->tps2_max)); + +} + +void DBW_Init(void) { + dbw_fast_process_timer = 1; + dbw_slow_process_timer = config->motor_ctl_period; + vbat_corr = 0; + tps_slow_t = var.tps; + p_comp = 0; + i_comp = 0; + d_comp = 0; + tps_error_t = var.tps_error; + can_target = 0; + spring_preload = 0; + idle_adder = 0; +} + +int DBW_Process(void) { + + int32_t pwm_output = 0; + int32_t pct = 0; + if (dbw_fast_process_timer == 0) { + //process DBW every 1 mS + dbw_fast_process_timer = 1; + + // Read all sensors and calculate error + // calculate PPS sensor reading + var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc); + var.pps1 = var.pps1_adc * pps1_gain + pps1_offset; + + var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); //orig 1 + var.pps2 = var.pps2_adc * pps2_gain + pps2_offset; + + var.pps_delta = var.pps1 - var.pps2; + var.pps = (var.pps1 + var.pps2) >> 1; + + //Calculate TPS sensor reading + var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc); + var.tps1 = var.tps1_adc * tps1_gain + tps1_offset; + + var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //orig 3 + var.tps2 = var.tps2_adc * tps2_gain + tps2_offset; + + // calculate tps and pps delta and values + var.tps_delta = var.tps1 - var.tps2; + var.tps = (var.tps1 + var.tps2) >> 1; + + var.pps_delta = var.pps1 - var.pps2; + var.pps = (var.pps1 + var.pps2) >> 1; + + // set tps target + if (config->pps2tps_option == PPS2TPS_OPTION_CURVE) { + var.tps_target = intrp_1d_ss_table(var.pps, 16, + (signed short*) config->pps_bins, 1, + (signed short*) config->tps_bins); + } + // if MS3 DBW protocol is used + else if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) { + // if no RX errors + //if(var.status0 & DBW_STATUS0_CAN_MSDBW_F) + if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) { + // use MS3 TPS TARGET + var.tps_target = can_target; + } else { + // on CAN error fall back to internal curve + var.tps_target = intrp_1d_ss_table(var.pps, 16, + (signed short*) config->pps_bins, 1, + (signed short*) config->tps_bins); + } + } + + else { + // All other TPS target options are considered as fault + Error_Handler(); + } + + // add idle TPS target adder + var.tps_target += idle_adder; + //limit TPS target + if (var.tps_target > 1000) + var.tps_target = 1000; + if (var.tps_target < 0) + var.tps_target = 0; + + //calculate regulation error + var.tps_error = var.tps_target - var.tps; + + // Proportional regulator + p_comp = (((int32_t) var.tps_error) * (int32_t) config->motor_fw_p) + / 10; + + // calculate spring preload compensation using interpolation + spring_preload = intrp_1d_ss_table(var.tps_target, 16, + (signed short*) config->tps_dc_tps_bins, 1, + (signed short*) config->tps_dc_offset_bins); + + if (dbw_slow_process_timer > 0) { + dbw_slow_process_timer--; + if (dbw_slow_process_timer == 0) { + dbw_slow_process_timer = config->motor_ctl_period; + //calculate slow changing thinks + + //read Battery voltage and apply corrections + var.vbat_adc = LPF(700, Adc_Read(5), var.vbat_adc); + pct = intrp_1d_ss_table(var.vbat_adc, 8, + (signed short*) config->vbat_bins, 1, + (signed short*) config->motor_pwm_corr_bins); + + //read motor current + var.motor_current_adc = LPF(700, Adc_Read(4), + var.motor_current_adc); + + // calculate I component + + i_comp += ((int32_t) var.tps_error + * (int32_t) config->motor_fw_i) / 100; + if (i_comp > config->i_limmit) + i_comp = config->i_limmit; + if (i_comp < (-config->i_limmit)) + i_comp = (-config->i_limmit); + + // calculate D component + d_comp = (((int32_t) var.tps_error - tps_error_t) + * (int32_t) config->motor_fw_d) / 10; + tps_error_t = var.tps_error; + + // calculate single shot + //single_shot = var.tps_error * + + // Calculate Idle adder + if (config->idle_input_option == IDLE_OPTION_NO_IDLE_INPUT) + idle_adder = 0; + else if (config->idle_input_option == IDLE_OPTION_MS_CAN) { + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + (signed short*) config->idle_input_bins, 1, + (signed short*) config->idle_tps_adder_bins); + + } else if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) { + + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + (signed short*) config->idle_input_bins, 1, + (signed short*) config->idle_tps_adder_bins) + - (var.pps / 5); + if (idle_adder < 0) { + idle_adder = 0; + } + + } + + } + } + + pwm_output = p_comp + i_comp + d_comp + spring_preload; + + vbat_corr = (int16_t) (((int32_t) var.motor_pwm) * vbat_corr / 1000); + + pwm_output += pct; + + //limmit pwm + if (pwm_output > config->motor_dc_max) + pwm_output = config->motor_dc_max; + if (pwm_output < config->motor_dc_min) + pwm_output = config->motor_dc_min; + + //apply pwm + DBW_Pwm_Set_Duty((signed short) (pwm_output), (pwm_t*) &ttl1_pwm); + + } + + return 0; +} + +void DBW_Pwm_Init(void) { + +// Setup PWM ports + ttl1_pwm.pos_port = GPIOB; + ttl1_pwm.pos_pin = 10; + + ttl1_pwm.neg_port = GPIOB; + ttl1_pwm.neg_pin = 11; + +// setup pwm status default -> no drive + ttl1_pwm.status = PWM_STATUS_DEFAULT; + +// calculate how many tick are in given freq period + ttl1_pwm.period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq; + +// set initian pwm from current settings + ttl1_pwm.pwm = var.motor_pwm; + ttl1_pwm.pwm_t = var.motor_pwm; + ttl1_pwm.single_pulse = 0; + + //tmp = (float)ttl1_pwm.period_ticks * (float)ttl1_pwm.pwm/10000.0F; + //ttl1_pwm.duty_ticks = (unsigned int) tmp; + + DBW_Pwm_Set_Duty(var.motor_pwm, (pwm_t*) &ttl1_pwm); + + if (var.motor_pwm < 0) + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + else if (var.motor_pwm > 0) + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + else + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + + ttl1_pwm.status = PWM_STATUS_IDLE; + + DBW_Stop(); + + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + +// configure TIM2 to 1uS / tick timer +// setup CCR interrupt happen after sturtup delay is over + + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; + TIM2->CNT = 0xFFFFFFFE; + TIM2->PSC = 48; //2400; // (1uS precision) + + TIM2->ARR = 0xFFFFFFFF; + + TIM2->CR1 = (TIM_CR1_URS | TIM_CR1_CEN); + TIM2->CCER = 0x0000; + TIM2->CCMR1 = 0x0000; + + TIM2->CCR1 = (unsigned int) 20000; // startup delay + TIM2->CCR2 = 0; + TIM2->SR &= ~TIM_SR_CC1IF; + TIM2->DIER |= TIM_DIER_CC1IE; + NVIC_EnableIRQ(TIM2_IRQn); + +} + +void TIM2_IRQHandler(void) { + if (TIM2->SR & TIM_SR_CC1IF) { + // capture compare intrrupt + TIM2->SR &= ~TIM_SR_CC1IF; + if (ttl1_pwm.status == PWM_STATUS_DEFAULT) { + // here ends startup delay + // enable drive here + ttl1_pwm.status = PWM_STATUS_STARTED; + } + + //Set duty + if (ttl1_pwm.pwm > 0) { + // pwm > 0 + if ((ttl1_pwm.pwm > 0) && (ttl1_pwm.pwm_t < 0)) { + // if changeing PWM polarity insert dead time + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime; + } else if (ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) { + ttl1_pwm.state = PWM_STATE_POSITIVE_ACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << ttl1_pwm.pos_pin); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks; + } else { + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + TIM2->CCR1 = TIM2->CNT + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + + } + } else if (ttl1_pwm.pwm < 0) { + //pwm < 0 + //if((ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) && (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE)) + if ((ttl1_pwm.pwm < 0) && (ttl1_pwm.pwm_t > 0)) { + // if changeing PWM polarity insert dead time + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime; + } else if (ttl1_pwm.state == PWM_STATE_NEGATIVE_INACTIVE) { + ttl1_pwm.state = PWM_STATE_NEGATIVE_ACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << ttl1_pwm.neg_pin); + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks; + } else { + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + TIM2->CCR1 = TIM2->CNT + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + } + } else { + // if pwm == 0 + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.period_ticks; + if (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE + || ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) { + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + } else { + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + } + + } + // store new pwm value as old pwm value for the nex iteration + ttl1_pwm.pwm_t = ttl1_pwm.pwm; + } + if (TIM2->SR & TIM_SR_UIF) { + //TIM2 overflow interrupt jaust clear update interrupt flag + TIM2->SR &= ~TIM_SR_UIF; + + } + +} +void DBW_Pwm_Set_Duty(signed int duty, pwm_t *ttl) { + float tmp; + unsigned int period_ticks; + + //check limmits + if (duty > 10000) + duty = 10000; + else if (duty < -10000) + duty = -10000; + + //calculate period - needed to change frequency on-the-fly + period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq; + if (duty > 0) + tmp = (float) period_ticks * (float) duty / 10000.0F; + else if (duty < 0) + tmp = (float) period_ticks * (0 - ((float) duty)) / 10000.0F; + else + tmp = 20; + + // check minimum duty period; + + // do not allow duty cylce <20uS + if ((period_ticks - (unsigned int) tmp) < 20) { + tmp = period_ticks - 20; + if (duty > 0) + duty = (signed int) tmp * 10000.0F / ttl->period_ticks; + else if (duty < 0) + duty = 0 - (signed int) tmp * 10000.0F / ttl->period_ticks; + } else if (tmp < 20) { + tmp = 20; + duty = 0; + } + + //update variables + var.motor_pwm = duty; + + //apply new settings + __disable_irq(); + ttl->duty_ticks = (unsigned int) tmp; + ttl->period_ticks = period_ticks; + ttl->pwm = duty; + __enable_irq(); + +} + +unsigned int intrp_1d_uitable(unsigned int x, unsigned char nx, + unsigned int *x_table, unsigned int *z_table) { + int ix; + long interp, interp3; + // bound input arguments + + if (x > x_table[nx - 1]) + return (z_table[nx - 1]); + else if (x < x_table[0]) + return (z_table[0]); + // Find bounding indiex in table + for (ix = nx - 2; ix > -1; ix--) { // Start w highest index + // because will generally have least time for calculations at hi y + if (x > x_table[ix]) { + break; + } + } + if (ix < 0) + ix = 0; + // do 1D interpolate + interp = (long) (x_table[ix + 1] - x_table[ix]); + if (interp != 0) { + interp3 = (long) (x - x_table[ix]); + interp3 = (100 * interp3); + interp = interp3 / interp; + } + return ((unsigned int) (z_table[ix] + + interp * (int) (z_table[ix + 1] - z_table[ix]) / 100)); +} + +signed short intrp_1d_ss_table(signed short x, unsigned char n, + signed short *x_table, char sgn, signed short *z_table) { + int ix; + int interp, interp3; + // bound input arguments + if (x > x_table[n - 1]) + return z_table[n - 1]; + + if (x < x_table[0]) + return z_table[0]; + + for (ix = n - 2; ix > -1; ix--) { + if (x > x_table[ix]) { + break; + } + } + if (ix < 0) + ix = 0; + + interp = x_table[ix + 1] - x_table[ix]; + if (interp != 0) { + interp3 = (x - x_table[ix]); + interp3 = (100 * interp3); + interp = interp3 / interp; + } + + return ((short) ((int) z_table[ix] + + interp * ((int) z_table[ix + 1] - (int) z_table[ix]) / 100)); +} + +int intrp_1dstable(signed short x, unsigned char n, signed short *x_table, + char sgn, signed short *z_table) { + int ix; + long interp, interp3; + // bound input arguments + if (x > x_table[n - 1]) { + if (!sgn) + return ((int) z_table[n - 1]); + else + return ((signed int) ((signed short) z_table[n - 1])); + } + if (x < x_table[0]) { + if (!sgn) + return ((signed int) z_table[0]); + else + return ((signed int) ((signed short) z_table[0])); + } + for (ix = n - 2; ix > -1; ix--) { + if (x > x_table[ix]) { + break; + } + } + if (ix < 0) + ix = 0; + + interp = x_table[ix + 1] - x_table[ix]; + if (interp != 0) { + interp3 = (x - x_table[ix]); + interp3 = (100 * interp3); + interp = interp3 / interp; + } + if (!sgn) + return ((signed int) (z_table[ix] + + interp * (z_table[ix + 1] - z_table[ix]) / 100)); + else + return ((int) ((signed short) z_table[ix] + + interp + * ((signed short) z_table[ix + 1] + - (signed short) z_table[ix]) / 100)); +} + +void DBW_Start(void) { + GPIOB->ODR &= ~D1_Pin; + GPIOB->ODR |= D2_Pin; +} +void DBW_Stop(void) { + GPIOB->ODR |= D1_Pin; + GPIOB->ODR &= ~D2_Pin; + +} + +void DBW_TPS_AutoCal(void) { +// if time to process autocal + if ((ac_timer == 0) && (ac_mode != 0)) { + if (ac_mode == 1) { + var.status0 |= DBW_STATUS0_PPSTPS_CAL_F; + DBW_Pwm_Set_Duty((signed short) (-6000), (pwm_t*) &ttl1_pwm); + DBW_Start(); + ac_timer = 1500; + ac_mode = 2; + } else if (ac_mode == 2) { + uint32_t tmp = 0; + for (int i = 0; i < 16; i++) + tmp += Adc_Read(2); + config->tps1_min = tmp >> 4; + tmp = 0; + for (int i = 0; i < 16; i++) + tmp += Adc_Read(3); + config->tps2_min = tmp >> 4; + DBW_Stop(); + ac_timer = 2000; + ac_mode = 3; + } else if (ac_mode == 3) { + DBW_Pwm_Set_Duty((signed short) (9000), (pwm_t*) &ttl1_pwm); + DBW_Start(); + ac_timer = 1500; + ac_mode = 4; + } else if (ac_mode == 4) { + uint32_t tmp = 0; + for (int i = 0; i < 16; i++) + tmp += Adc_Read(2); + config->tps1_max = tmp >> 4; + tmp = 0; + for (int i = 0; i < 16; i++) + tmp += Adc_Read(3); + config->tps2_max = tmp >> 4; + DBW_Stop(); + DBW_Pwm_Set_Duty((signed short) (0), (pwm_t*) &ttl1_pwm); + Apply_Sensor_Calibration(); + Write_Config(); + ac_timer = 10000; + ac_mode = 5; + Comms_Reset(&RX); + Comms_Reset(&TX); + USART1->ICR &= ~USART_CR1_RXNEIE; + NVIC_DisableIRQ(USART1_IRQn); + + } else if (ac_mode == 5) { + ac_mode = 0; + var.status0 &= ~DBW_STATUS0_PPSTPS_CAL_F; + USART1->ICR |= USART_CR1_RXNEIE; + NVIC_EnableIRQ(USART1_IRQn); + + } + } + +} + +void DBW_Read_sensors(void) { + var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc); + var.pps1 = var.pps1_adc * pps1_gain + pps1_offset; + + var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); // 1 is orig + var.pps2 = var.pps2_adc * pps2_gain + pps2_offset; + + var.pps_delta = var.pps1 - var.pps2; + var.pps = (var.pps1 + var.pps2) >> 1; + + //Calculate TPS sensor reading + var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc); + var.tps1 = var.tps1_adc * tps1_gain + tps1_offset; + + var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //3 is orig + var.tps2 = var.tps2_adc * tps2_gain + tps2_offset; + + // calculate tps and pps delta and values + var.tps_delta = var.tps1 - var.tps2; + var.tps = (var.tps1 + var.tps2) >> 1; + + var.pps_delta = var.pps1 - var.pps2; + var.pps = (var.pps1 + var.pps2) >> 1; +} diff --git a/DBW_V2/Core/Src/inputs.c b/DBW_V2/Core/Src/inputs.c new file mode 100644 index 0000000..ffcdc12 --- /dev/null +++ b/DBW_V2/Core/Src/inputs.c @@ -0,0 +1,119 @@ +/* + * inputs.c + * + * Created on: Mar 15, 2022 + * Author: v0stap + */ + +//Includes +#include "main.h" +//Variables +uint32_t counter0 = 0, counter1 = 0, Counter = 0; +uint8_t gap = 0; +// idle in section +void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3 + // PB4 AF1 TIM3 Input1 + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + GPIOB->MODER &= ~(3 << (4 * 2)); + GPIOB->MODER |= (2 << (4 * 2)); + GPIOB->OTYPER &= ~(1 << 4 * 1); + GPIOB->OSPEEDR &= ~(3 << (4 * 2)); + GPIOB->PUPDR &= ~(3 << (4 * 2)); + GPIOB->AFR[0] &= ~(15 << (4 * 4)); + GPIOB->AFR[0] |= (1 << (4 * 4)); + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + /* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01), + select the active input TI1 for TIM3_CCR2 (CC2S = 10) */ + /* (2) Select TI1FP1 as valid trigger input (TS = 101) + configure the slave mode in reset mode (SMS = 100) */ + /* (3) Enable capture by setting CC1E and CC2E + select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset + value), + select the falling edge on CC2 (CC2P = 1). */ + /* (4) Enable interrupt on Capture/Compare 1 */ + /* (5) Enable counter */ + TIM3->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/ + TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */ + TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */ + TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */ + TIM3->CR1 |= TIM_CR1_CEN; /* (5) */ + NVIC_EnableIRQ(TIM3_IRQn); +} +void TIM14_Init(void) { //configure IN2 as rpm input PB1 TIM14 + // PB1 AF0 TIM14 Input1 + // prescaler 1:21 ->1/4uS tick (since APBx presc !=1, timer clocks = APBx_cls x 2) + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + GPIOB->MODER &= ~(3 << (1 * 2)); + GPIOB->MODER |= (2 << (1 * 2)); + GPIOB->OTYPER &= ~(1 << 1 * 1); + GPIOB->OSPEEDR &= ~(3 << (1 * 2)); + GPIOB->PUPDR &= ~(3 << (1 * 2)); + GPIOB->AFR[0] &= ~(15 << (1 * 4)); + GPIOB->AFR[0] |= (0 << (1 * 4)); + RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; + TIM14->ARR = 0xFFFF; + TIM14->PSC = 599; + /* (1) Select the active input TI1 (CC1S = 01), + program the input filter for 8 clock cycles (IC1F = 0011), + select the rising edge on CC1 (CC1P = 0, reset value) + and prescaler at each valid transition (IC1PS = 00, reset value) */ + /* (2) Enable capture by setting CC1E */ + /* (3) Enable interrupt on Capture/Compare */ + /* (4) Enable counter */ + TIM14->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/ + TIM14->CCER |= TIM_CCER_CC1E; /* (2) */ + TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */ + TIM14->CR1 |= TIM_CR1_CEN; /* (4) */ + NVIC_EnableIRQ(TIM14_IRQn); +} +void TIM3_IRQHandler(void) { + if ((TIM3->SR & TIM_SR_CC1IF) != 0) { + if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */ + { + /* Overflow error management */ + /* Reinitialize the laps computing */ + TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */ + return; + } else { + counter0 = TIM3->CCR1; + var.idle_dc = (TIM3->CCR2) * 1000 / TIM3->CCR1; //Get DC + // printf("data1 =%d; data2 =%d \n",counter0,counter1); + } + } else { + /* Unexpected Interrupt */ + /* Manage an error for robust application */ + } +} +void TIM14_IRQHandler(void) { + if ((TIM14->SR & TIM_SR_CC1IF) != 0) { + if ((TIM14->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */ + { + /* Overflow error management */ + /* Reinitialize the laps computing */ + TIM14->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */ + var.rpm = 0; + gap = 0; + return; + } + if (gap == 0) /* Test if it is the first rising edge */ + { + counter0 = TIM14->CCR1; /* Read the capture counter which clears the + CC1ICF */ + gap = 1; /* Indicate that the first rising edge has yet been detected */ + } else { + counter1 = TIM14->CCR1; /* Read the capture counter which clears the + CC1ICF */ + if (counter1 > counter0) /* Check capture counter overflow */ + { + Counter = counter1 - counter0; + } else { + Counter = counter1 + 0xFFFF - counter0 + 1; + } + counter0 = counter1; + var.rpm = Counter; + } + } else { + /* Unexpected Interrupt */ + /* Manage an error for robust application */ + } +} diff --git a/DBW_V2/Core/Src/main.c b/DBW_V2/Core/Src/main.c new file mode 100644 index 0000000..2386fd1 --- /dev/null +++ b/DBW_V2/Core/Src/main.c @@ -0,0 +1,466 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc; + +CAN_HandleTypeDef hcan; + +UART_HandleTypeDef huart1; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_ADC_Init(void); +//static void MX_CAN_Init(void); +static void MX_USART1_UART_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ADC_Init(); +// MX_CAN_Init(); + MX_USART1_UART_Init(); + /* USER CODE BEGIN 2 */ + + //load flash copy of config to RAM + // memcpy((void*)&config_ram,(void*)(0x0800F000), sizeof(config_t)); + memcpy((void*) &config_ram, (void*) &config_flash, sizeof(config_t)); + config = &config_ram; + + //calculate gain and offset for PPS and TPS calc + Apply_Sensor_Calibration(); + config->config_bits &= ~CONFIG_TESTMODE_F; + +//clear momms + memset((void*) &var, 0, sizeof(var_t)); + //Initialize TS Comms + Comms_Init(); + NVIC_EnableIRQ(USART1_IRQn); + +// check if safety features are enabled + if (config->config_bits & CONFIG_SAFETY_FEATURES_F) { + Check_Safety_Limits(); + Safety_TPS_Safety_Timer_Start(); + //TODO Watch_Dog_Init(); + // change status + var.status1 |= DBW_STATUS1_SAFETY_F; + } +// if not change status to safy disabled + else + var.status1 &= ~DBW_STATUS1_SAFETY_F; + +// Check if CAN has to be initialized + if ((config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) + || (config->idle_input_option == IDLE_OPTION_MS_CAN) + || config->can_ms29bit_options == 0x01) { +// Can_Init(); + + } + if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) { + TIM3_Init(); + } + if (1) { + TIM14_Init(); //rpm input init + TIM16_Init(); // vss out init + TIM17_Init(); //Mazda rx8 can message init + } + Adc_Init(); + DBW_Init(); + DBW_Pwm_Init(); + +//check if program flash is write protected and set status + if (FLASH->WRPR & 0x00003FFF) + var.status0 |= DBW_STATUS0_UNPROTECTED_F; + else + var.status0 &= ~DBW_STATUS0_UNPROTECTED_F; + +//check if agreement is set if so start DBW drive + if (config->config_bits & CONFIG_AGREEMENT_F) { + var.status0 |= DBW_STATUS0_AGREEMENT_F; + } else + var.status0 &= ~DBW_STATUS0_AGREEMENT_F; + +// check if TPS and PPS are calibrated + + if (config->config_bits & CONFIG_SENSORS_CALIBRATED_F) { + var.status0 |= DBW_STATUS0_SENSOR_CAL_F; + } + + else { + var.status0 &= ~DBW_STATUS0_SENSOR_CAL_F; + } + +// start DBW if sensors are calibrated and agreement is accepted + if ((var.status0 & DBW_STATUS0_AGREEMENT_F) + && (var.status0 & DBW_STATUS0_SENSOR_CAL_F)) { + DBW_Start(); + } else + DBW_Stop(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ + +// is something to be transmitted on serial + Poll_Tx(); + +// Update WDT and check ADC range if safety features are enabled + if ((var.status1 & DBW_STATUS1_SAFETY_F) && var.clock > 1000) { + //TODO Watch_Dog_Update(); + Check_Adc_Range(); + Check_TPS_Target(); + } + +//check if tesmode is turned on + if (config->config_bits & CONFIG_TESTMODE_F) { + var.status0 &= ~DBW_STATUS0_READY_F; + DBW_TPS_AutoCal(); + DBW_Read_sensors(); + } else { + DBW_Process(); + } + + CAN_Send_TX_Buffer(); + if (1) { + MAZDA_CAN_Read(); + } + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI14 + | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; + RCC_OscInitStruct.HSI14CalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief ADC Initialization Function + * @param None + * @retval None + */ +static void MX_ADC_Init(void) { + + /* USER CODE BEGIN ADC_Init 0 */ + + /* USER CODE END ADC_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = { 0 }; + + /* USER CODE BEGIN ADC_Init 1 */ + + /* USER CODE END ADC_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc.Instance = ADC1; + hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + hadc.Init.Resolution = ADC_RESOLUTION_12B; + hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + hadc.Init.LowPowerAutoWait = DISABLE; + hadc.Init.LowPowerAutoPowerOff = DISABLE; + hadc.Init.ContinuousConvMode = DISABLE; + hadc.Init.DiscontinuousConvMode = DISABLE; + hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc.Init.DMAContinuousRequests = DISABLE; + hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + if (HAL_ADC_Init(&hadc) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_0; + sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; + sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_1; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_2; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_3; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_4; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_5; + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN ADC_Init 2 */ + + /* USER CODE END ADC_Init 2 */ + +} + +/** + * @brief CAN Initialization Function + * @param None + * @retval None + */ +//static void MX_CAN_Init(void) { +// +// /* USER CODE BEGIN CAN_Init 0 */ +// +// /* USER CODE END CAN_Init 0 */ +// +// /* USER CODE BEGIN CAN_Init 1 */ +// +// /* USER CODE END CAN_Init 1 */ +// hcan.Instance = CAN; +// hcan.Init.Prescaler = 16; +// hcan.Init.Mode = CAN_MODE_NORMAL; +// hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; +// hcan.Init.TimeSeg1 = CAN_BS1_1TQ; +// hcan.Init.TimeSeg2 = CAN_BS2_1TQ; +// hcan.Init.TimeTriggeredMode = DISABLE; +// hcan.Init.AutoBusOff = DISABLE; +// hcan.Init.AutoWakeUp = DISABLE; +// hcan.Init.AutoRetransmission = DISABLE; +// hcan.Init.ReceiveFifoLocked = DISABLE; +// hcan.Init.TransmitFifoPriority = DISABLE; +// if (HAL_CAN_Init(&hcan) != HAL_OK) { +// Error_Handler(); +// } +// /* USER CODE BEGIN CAN_Init 2 */ +// +// /* USER CODE END CAN_Init 2 */ +// +//} +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) { + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, + PWM1_Pin | PWM2_Pin | FAULT_Pin | D2_Pin | D1_Pin | GPO1_Pin + | GPO2_1_Pin | GPO2_2_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : IN1_Pin IN2_Pin STATUS_FLAG_Pin */ +// GPIO_InitStruct.Pin = IN1_Pin|IN2_Pin|STATUS_FLAG_Pin; +// GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +// GPIO_InitStruct.Pull = GPIO_NOPULL; +// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pins : PWM1_Pin PWM2_Pin FAULT_Pin D2_Pin + D1_Pin GPO1_Pin GPO2_1_Pin GPO2_2_Pin */ + GPIO_InitStruct.Pin = PWM1_Pin | PWM2_Pin | FAULT_Pin | D2_Pin | D1_Pin + | GPO1_Pin | GPO2_1_Pin | GPO2_2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Src/mazda_can.c b/DBW_V2/Core/Src/mazda_can.c new file mode 100644 index 0000000..a2647d5 --- /dev/null +++ b/DBW_V2/Core/Src/mazda_can.c @@ -0,0 +1,171 @@ +/* + * mazda_can.c + * + * Created on: Mar 17, 2022 + * Author: v0stap + */ + +/* + * app.c + * + * Created on: Jul 25, 2020 + * Author: v0stap + */ +#include "main.h" +uint32_t var_time = 0, rpm_time = 0, can_tim = 0; +can_msg_typedef tmpCanMsg; +//https://www.chamberofunderstanding.co.uk/2021/06/11/rx8-project-part-21-canbus-6-working-code/ +void MAZDA_Send_Data(void) { + can_tim++; + tmpCanMsg.id = 0x201; // Send RPM = Actual RPM * 3.85 Throttle Pedal 0x00 - 0xC8 in 0.5% increments Send KPH = (Actual KPH * 100) + 10000 + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 7; + tmpCanMsg.data[0] = (((uint16_t) (var.rpm * 3.85)) >> 8); // RPM high + tmpCanMsg.data[1] = (uint8_t) ((var.rpm) * 3.85); // RPM low + tmpCanMsg.data[2] = 0xFF; + tmpCanMsg.data[3] = 0xFF; + tmpCanMsg.data[4] = (var.vss * 100 + 10000) >> 8; // VSS KPH high + tmpCanMsg.data[5] = (var.vss * 100 + 10000); // VSS KPH low + tmpCanMsg.data[6] = var.pps / 5; // TPS + tmpCanMsg.data[7] = 0xFF; + CAN_Add_TX_Buffer(&tmpCanMsg); + + tmpCanMsg.id = 0x250; + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 8; + tmpCanMsg.data[0] = 0x00; + tmpCanMsg.data[1] = 0x00; + tmpCanMsg.data[2] = 0xCF; + tmpCanMsg.data[3] = 0x87; + tmpCanMsg.data[4] = 0x7F; + tmpCanMsg.data[5] = 0x83; + tmpCanMsg.data[6] = 0x00; + tmpCanMsg.data[7] = 0x00; + CAN_Add_TX_Buffer(&tmpCanMsg); + + tmpCanMsg.id = 0x620; // Type of ABS + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 1; + tmpCanMsg.data[0] = 0x00; + tmpCanMsg.data[1] = 0x00; + tmpCanMsg.data[2] = 0x00; + tmpCanMsg.data[3] = 0x00; + tmpCanMsg.data[4] = 0x00; + tmpCanMsg.data[5] = 0x00; + tmpCanMsg.data[6] = 0x02; // ABS type 2,3 or 4 + tmpCanMsg.data[7] = 0x00; + CAN_Add_TX_Buffer(&tmpCanMsg); + tmpCanMsg.id = 0x630; // Type of Transmission and Wheel Size + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 1; + tmpCanMsg.data[0] = 0x08; //8 = MT, 2 = AT + tmpCanMsg.data[1] = 0x00; + tmpCanMsg.data[2] = 0x00; + tmpCanMsg.data[3] = 0x00; + tmpCanMsg.data[4] = 0x00; + tmpCanMsg.data[5] = 0x00; + tmpCanMsg.data[6] = 0x6A; // Wheel Size + tmpCanMsg.data[7] = 0x6A; // Wheel Size + CAN_Add_TX_Buffer(&tmpCanMsg); + tmpCanMsg.id = 0x650; // CRUISE CONTROL + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 1; + tmpCanMsg.data[0] = 0x00; // 0x40 Green 0x80 Yellow 0xC0 Both + //tmpCanMsg.data[1] = 0; + //tmpCanMsg.data[2] = 0xcf; + //tmpCanMsg.data[3] = 0x87; + //tmpCanMsg.data[4] = 0x7f; + //tmpCanMsg.data[5] = 0x83; + //tmpCanMsg.data[6] = 0; + //tmpCanMsg.data[7] = 0; + CAN_Add_TX_Buffer(&tmpCanMsg); + if (can_tim>4){ + can_tim = 0; + tmpCanMsg.id = 0x203; //This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 7; + tmpCanMsg.data[0] = 0x16; + tmpCanMsg.data[1] = 0x16; + tmpCanMsg.data[2] = 0x16; + tmpCanMsg.data[3] = 0x16; + tmpCanMsg.data[4] = 0xAF; + tmpCanMsg.data[5] = 3; + tmpCanMsg.data[6] = 0x16; + //tmpCanMsg.data[7] = ; + CAN_Add_TX_Buffer(&tmpCanMsg); + tmpCanMsg.id = 0x215; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 8; + tmpCanMsg.data[0] = 0x02; + tmpCanMsg.data[1] = 0x2D; + tmpCanMsg.data[2] = 0x02; + tmpCanMsg.data[3] = 0x2D; + tmpCanMsg.data[4] = 0x02; + tmpCanMsg.data[5] = 0x2A; + tmpCanMsg.data[6] = 0x06; + tmpCanMsg.data[7] = 0x81; + CAN_Add_TX_Buffer(&tmpCanMsg); + tmpCanMsg.id = 0x231; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 5; + tmpCanMsg.data[0] = 15; + tmpCanMsg.data[1] = 0; + tmpCanMsg.data[2] = 0xff; + tmpCanMsg.data[3] = 0xff; + tmpCanMsg.data[4] = 0x00; + //tmpCanMsg.data[5] = 0x37; + //tmpCanMsg.data[6] = 0x06; + //tmpCanMsg.data[7] = 0x81; + CAN_Add_TX_Buffer(&tmpCanMsg); + tmpCanMsg.id = 0x240; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 8; + tmpCanMsg.data[0] = 0x04; + tmpCanMsg.data[1] = 0; + tmpCanMsg.data[2] = 40; + tmpCanMsg.data[3] = 0x00; + tmpCanMsg.data[4] = 0x02; + tmpCanMsg.data[5] = 55; + tmpCanMsg.data[6] = 0x06; + tmpCanMsg.data[7] = 0x81; + CAN_Add_TX_Buffer(&tmpCanMsg); + } +} +void MAZDA_CAN_Read(void) { + CAN_Read_RX_Buffer(&tmpCanMsg); + if (tmpCanMsg.id == 0x4c0) { + tmpCanMsg.id = 0x420; // Engine Temp Odometer from 4c0 Oil Pressure Check Engine Low Water Bat Charge Oil Pressure + tmpCanMsg.format = STD_FORMAT; + tmpCanMsg.frame = DATA_FRAME; + tmpCanMsg.lenght = 8; + tmpCanMsg.data[0] = 0x00; // clt + tmpCanMsg.data[1] = tmpCanMsg.data[1]; // Odometer from 4c0 (pwm) + tmpCanMsg.data[2] = 0x00; + tmpCanMsg.data[3] = 0x00; + tmpCanMsg.data[4] = 0x00; //Oil Pressure 0x00 - 0x01 (pwm) + tmpCanMsg.data[5] = 0x00; // Check Engine Bit 7 MIL Check Engine Bit 8 BL + tmpCanMsg.data[6] = 0; + if (var.vbat_adc < 1200) { + tmpCanMsg.data[6] |= 1 << 2; + } else { + tmpCanMsg.data[6] &= ~(1 << 2); + } + //tmpCanMsg.data[6] = var.ic_status2; //Low Water Bit 2 MIL Bat Charge Bit 7 MIL Oil Pressure Bit 8 MIL + tmpCanMsg.data[7] = 0x00; + CAN_Add_TX_Buffer(&tmpCanMsg); + } else if (tmpCanMsg.id == 0x4B1) { + var.vss = ((tmpCanMsg.data[4] << 8) + tmpCanMsg.data[5] + (tmpCanMsg.data[6] << 8) + tmpCanMsg.data[7]) / 4; + //todo // add option to make vss output on/off + VSS_Set((uint8_t)var.vss); + } +} + diff --git a/DBW_V2/Core/Src/outputs.c b/DBW_V2/Core/Src/outputs.c new file mode 100644 index 0000000..7982384 --- /dev/null +++ b/DBW_V2/Core/Src/outputs.c @@ -0,0 +1,60 @@ +/* + * outputs.c + * + * Created on: Mar 16, 2022 + * Author: v0stap + */ + +#include "main.h" + +void TIM16_Init(void) { + RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; + TIM16->PSC = 480; + TIM16->ARR = 70287; + TIM16->CR1 |= 1 << 0 | 1 << 7; + TIM16->CR2 = 0; + TIM16->SMCR = 0; + TIM16->DIER = 1 << 0; + TIM16->CCMR1 = 0; + TIM16->CCMR2 = 0; + TIM16->CCER = 0x1111; + TIM16->SR = 0; + NVIC_EnableIRQ(TIM16_IRQn); +} + +void TIM17_Init(void) { + RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; + TIM17->PSC = 479; + TIM17->ARR = 10000; + TIM17->CR1 |= 1 << 0 | 1 << 7; + TIM17->CR2 = 0; + TIM17->SMCR = 0; + TIM17->DIER = 1 << 0; + TIM17->CCMR1 = 0; + TIM17->CCMR2 = 0; + TIM17->CCER = 0x1111; + TIM17->SR = 0; + NVIC_EnableIRQ(TIM17_IRQn); +} + +void VSS_Set(uint8_t vss) { + if (vss < 3) { + TIM16->CR1 &= ~(1 << 0); + } else { + TIM16->CR1 |= 1 << 0; + TIM16->ARR = 70287 / vss; + } +} + + +void TIM16_IRQHandler(void) { + TIM16->SR &= ~(1 << 0); + //TIM2->CNT = 600; + HAL_GPIO_TogglePin(GPIOB, GPO1_Pin); +} +void TIM17_IRQHandler(void) { + TIM17->SR &= ~(1 << 0); + //TIM2->CNT = 600; + MAZDA_Send_Data(); +} + diff --git a/DBW_V2/Core/Src/safety.c b/DBW_V2/Core/Src/safety.c new file mode 100644 index 0000000..c8499bb --- /dev/null +++ b/DBW_V2/Core/Src/safety.c @@ -0,0 +1,390 @@ +/* + * safety.c + * + * Created on: 12 May 2021 + * Author: Dmitrijs + */ + +#include "main.h" +#include "dbw.h" +#include "ts_comms.h" +#include "safety.h" + +const char msg1[42] = { "PPS1 Safety margin >4095 or less then 0\r\n" }; +const char msg2[42] = { "PPS2 Safety margin >4095 or less then 0\r\n" }; +const char msg3[42] = { "TPS1 Safety margin >4095 or less then 0\r\n" }; +const char msg4[42] = { "TPS2 Safety margin >4095 or less then 0\r\n" }; + +void Flash_Write_Protect(void) { + + FLASH_OBProgramInitTypeDef p; + p.OptionType = OPTIONBYTE_WRP; + p.WRPState = OB_WRPSTATE_ENABLE; + + HAL_FLASH_Unlock(); + HAL_FLASH_OB_Unlock(); + HAL_FLASHEx_OBErase(); + + p.WRPPage = 0x00003FFF; + + HAL_FLASHEx_OBProgram(&p); + FLASH_WaitForLastOperation((uint32_t) FLASH_TIMEOUT_VALUE); + + HAL_FLASH_OB_Lock(); + HAL_FLASH_Lock(); + HAL_FLASH_OB_Launch(); + +} + +void Flash_Write_Unprotect(void) { + + FLASH_OBProgramInitTypeDef p; + p.OptionType = OPTIONBYTE_WRP; + p.WRPState = OB_WRPSTATE_DISABLE; + + HAL_FLASH_Unlock(); + HAL_FLASH_OB_Unlock(); + HAL_FLASHEx_OBErase(); + + p.WRPPage = 0x00003FFF; + + HAL_FLASHEx_OBProgram(&p); + FLASH_WaitForLastOperation((uint32_t) FLASH_TIMEOUT_VALUE); + + HAL_FLASH_OB_Lock(); + HAL_FLASH_Lock(); + HAL_FLASH_OB_Launch(); + +} + +void Watch_Dog_Update(void) { + IWDG->KR = 0x0000AAAA; // update wd timer +} + +void Watch_Dog_Init(void) { + IWDG->KR = 0x0000CCCC; // enable watchdog + IWDG->KR = 0x00005555; // enable register access + while (IWDG->SR) + ; + IWDG->PR = 0x00000000; // prescaler LSI / 4 + while (IWDG->SR) + ; + IWDG->RLR = 1000; // set timeout to 100mS + while (IWDG->SR) + ; + IWDG->KR = 0x0000AAAA; // enable register access + while (IWDG->SR) + ; + +} + +void Check_Safety_Limits(void) { + +//PPS1 + + if (config->pps1_min < config->pps1_max) { + if ((config->pps1_margin > config->pps1_min) + || ((config->pps1_max + config->pps1_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg1, 42); + } + } else { + //config->pps1_min > config->pps1_max + if ((config->pps1_margin > config->pps1_max) + || ((config->pps1_min + config->pps1_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg1, 42); + } + } +//PPS2 + + if (config->pps2_min < config->pps2_max) { + if ((config->pps2_margin > config->pps2_min) + || ((config->pps2_max + config->pps2_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg2, 42); + } + } else { + //config->pps2_min > config->pps1_max + if ((config->pps2_margin > config->pps2_max) + || ((config->pps2_min + config->pps2_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg2, 42); + } + } + +//TPS1 + + if (config->tps1_min < config->tps1_max) { + if ((config->tps1_margin > config->tps1_min) + || ((config->tps1_max + config->tps1_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg3, 42); + } + } else { + //config->tps1_min > config->tps1_max + if ((config->tps1_margin > config->tps1_max) + || ((config->tps1_min + config->tps1_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg3, 42); + } + } +//TPS2 + + if (config->tps2_min < config->tps2_max) { + if ((config->tps2_margin > config->tps2_min) + || ((config->tps2_max + config->tps2_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg4, 42); + } + } else { + //config->tps2_min > config->tps1_max + if ((config->tps2_margin > config->tps2_max) + || ((config->tps2_min + config->tps2_margin) > 4095)) { + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + DBW_Stop(); + TX_Schedule((unsigned char*) msg4, 42); + } + } + +} + +void Check_Adc_Range(void) { + +//PPS1 + if (config->pps1_min < config->pps1_max) { + + if (var.pps1_adc < (config->pps1_min - config->pps1_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_GND; + } + + if (var.pps1_adc > (config->pps1_max + config->pps1_margin)) { + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_VREF; + } + } else { + //config->pps1_min < config->pps1_max + if (var.pps1_adc < (config->pps1_max - config->pps1_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_GND; + } + + if (var.pps1_adc > (config->pps1_min + config->pps1_margin)) { + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_VREF; + } + } + +//PPS2 + if (config->pps2_min < config->pps2_max) { + if (var.pps2_adc < (config->pps2_min - config->pps2_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS2_SS_GND; + } + + if (var.pps2_adc > (config->pps2_max + config->pps2_margin)) { + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_VREF; + } + } else { + + if (var.pps2_adc < (config->pps2_max - config->pps2_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS2_SS_GND; + } + + if (var.pps2_adc > (config->pps2_min + config->pps2_margin)) { + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS1_SS_VREF; + } + } + +//PPS Delta + if ((var.pps_delta > config->pps_delta_margin) + || (var.pps_delta < ((int16_t) -config->pps_delta_margin))) { + //Fault condition PPS DELTA + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_PPS_DELTA; + } + +//########################################## + //TPS1 + if (config->tps1_min < config->tps1_max) { + if (var.tps1_adc < (config->tps1_min - config->tps1_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS1_SS_GND; + } + + if (var.tps1_adc > (config->tps1_max + config->tps1_margin)) { + //Fault condition TPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS1_SS_VREF; + } + } else { + + if (var.tps1_adc < (config->tps1_max - config->tps1_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS1_SS_GND; + } + + if (var.tps1_adc > (config->tps1_min + config->tps1_margin)) { + //Fault condition TPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS1_SS_VREF; + } + } + + //TPS2 + if (config->tps2_min < config->tps2_max) { + if (var.tps2_adc < (config->tps2_min - config->tps2_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS2_SS_GND; + } + + if (var.tps2_adc > (config->tps2_max + config->tps2_margin)) { + //Fault condition TPS2 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS2_SS_VREF; + } + } else { + if (var.tps2_adc < (config->tps2_max - config->tps2_margin)) { + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS2_SS_GND; + } + + if (var.tps2_adc > (config->tps2_min + config->tps2_margin)) { + //Fault condition TPS2 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS2_SS_VREF; + } + } + + //TPS Delta + if ((var.tps_delta > config->tps_delta_margin) + || (var.tps_delta < ((int16_t) -config->tps_delta_margin))) { + //Fault condition PPS DELTA + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + DBW_Stop(); + var.status3 = STATUS3_TPS_DELTA; + } + +} + +volatile int dbw_target_tmr1, dbw_target_tmr2; + +void Safety_TPS_Safety_Timer(void) { + if (dbw_target_tmr1 > 0) + dbw_target_tmr1--; + if (dbw_target_tmr2 > 0) + dbw_target_tmr2--; +} + +void Safety_TPS_Safety_Timer_Start(void) { +//enable timers. add 1S time to start, because safety system starts in 1S after startup + dbw_target_tmr1 = config->tps_error_time1 + 1000; + dbw_target_tmr2 = config->tps_error_time2 + 1000; +} + +void Check_TPS_Target() { + if (var.tps_error > 0) { + //check if tps is within specified target + if (var.tps_error < config->tps_error_margin1) + dbw_target_tmr1 = config->tps_error_time1; + else { + // if not in range in specified time + if (dbw_target_tmr1 == 0) { + //fault + var.status0 |= DBW_STATUS0_FAULT_F; + DBW_Stop(); + var.status2 = STATUS3_TARGET1_FAULT; + } + } + + if (var.tps_error < config->tps_error_margin2) + dbw_target_tmr2 = config->tps_error_time2; + else { + // if not in range in specified time + if (dbw_target_tmr2 == 0) { + //fault + var.status0 |= DBW_STATUS0_FAULT_F; + DBW_Stop(); + var.status2 = STATUS3_TARGET2_FAULT; + } + } + } + + else { + //tps_error<0 + + //check if tps is within specified target + if (var.tps_error > (-config->tps_error_margin1)) + dbw_target_tmr1 = config->tps_error_time1; + else { + // if not in range in specified time + if (dbw_target_tmr1 == 0) { + //fault + var.status0 |= DBW_STATUS0_FAULT_F; + DBW_Stop(); + var.status2 = STATUS3_TARGET1_FAULT; + } + } + + if (var.tps_error > (-config->tps_error_margin2)) + dbw_target_tmr2 = config->tps_error_time2; + else { + // if not in range in specified time + if (dbw_target_tmr2 == 0) { + //fault + var.status0 |= DBW_STATUS0_FAULT_F; + DBW_Stop(); + var.status2 = STATUS3_TARGET2_FAULT; + } + } + } + +} diff --git a/DBW_V2/Core/Src/stm32f0xx_hal_msp.c b/DBW_V2/Core/Src/stm32f0xx_hal_msp.c new file mode 100644 index 0000000..e568dd2 --- /dev/null +++ b/DBW_V2/Core/Src/stm32f0xx_hal_msp.c @@ -0,0 +1,275 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) { + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** + * @brief ADC MSP Initialization + * This function configures the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (hadc->Instance == ADC1) { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC GPIO Configuration + PA0 ------> ADC_IN0 + PA1 ------> ADC_IN1 + PA2 ------> ADC_IN2 + PA3 ------> ADC_IN3 + PA4 ------> ADC_IN4 + PA5 ------> ADC_IN5 + */ + GPIO_InitStruct.Pin = PPS1_Pin | PPS2_Pin | TPS1_Pin | TPS2_Pin + | TTL_FB_Pin | VBAT_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** + * @brief ADC MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { + if (hadc->Instance == ADC1) { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC GPIO Configuration + PA0 ------> ADC_IN0 + PA1 ------> ADC_IN1 + PA2 ------> ADC_IN2 + PA3 ------> ADC_IN3 + PA4 ------> ADC_IN4 + PA5 ------> ADC_IN5 + */ + HAL_GPIO_DeInit(GPIOA, + PPS1_Pin | PPS2_Pin | TPS1_Pin | TPS2_Pin | TTL_FB_Pin + | VBAT_SENSE_Pin); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** + * @brief CAN MSP Initialization + * This function configures the hardware resources used in this example + * @param hcan: CAN handle pointer + * @retval None + */ +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (hcan->Instance == CAN) { + /* USER CODE BEGIN CAN_MspInit 0 */ + + /* USER CODE END CAN_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CAN1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_CAN; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN CAN_MspInit 1 */ + + /* USER CODE END CAN_MspInit 1 */ + } + +} + +/** + * @brief CAN MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hcan: CAN handle pointer + * @retval None + */ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { + if (hcan->Instance == CAN) { + /* USER CODE BEGIN CAN_MspDeInit 0 */ + + /* USER CODE END CAN_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CAN1_CLK_DISABLE(); + + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11 | GPIO_PIN_12); + + /* USER CODE BEGIN CAN_MspDeInit 1 */ + + /* USER CODE END CAN_MspDeInit 1 */ + } + +} + +/** + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef *huart) { + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + if (huart->Instance == USART1) { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** + * @brief UART MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { + if (huart->Instance == USART1) { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Src/stm32f0xx_it.c b/DBW_V2/Core/Src/stm32f0xx_it.c new file mode 100644 index 0000000..8cb81c1 --- /dev/null +++ b/DBW_V2/Core/Src/stm32f0xx_it.c @@ -0,0 +1,156 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "ts_comms.h" +#include "dbw.h" +#include "can.h" +#include "safety.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) { + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) { + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) { + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) { + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) { + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + var.clock++; + TS_Comms_RX_Timeout(); + + if (dbw_fast_process_timer) + dbw_fast_process_timer--; + + //Can_Timeouts(); + + if ((ac_mode != 0) && (config->config_bits & CONFIG_TESTMODE_F)) { + if (ac_timer) + ac_timer--; + } + + Safety_TPS_Safety_Timer(); + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Core/Src/syscalls.c b/DBW_V2/Core/Src/syscalls.c new file mode 100644 index 0000000..877afa8 --- /dev/null +++ b/DBW_V2/Core/Src/syscalls.c @@ -0,0 +1,162 @@ +/** + ***************************************************************************** + ** + ** File : syscalls.c + ** + ** Author : Auto-generated by STM32CubeIDE + ** + ** Abstract : STM32CubeIDE Minimal System calls file + ** + ** For more information about which c-functions + ** need which of these lowlevel functions + ** please consult the Newlib libc-manual + ** + ** Environment : STM32CubeIDE MCU + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ***************************************************************************** + ** + **

© COPYRIGHT(c) 2018 STMicroelectronics

+ ** + ** Redistribution and use in source and binary forms, with or without modification, + ** are permitted provided that the following conditions are met: + ** 1. Redistributions of source code must retain the above copyright notice, + ** this list of conditions and the following disclaimer. + ** 2. Redistributions in binary form must reproduce the above copyright notice, + ** this list of conditions and the following disclaimer in the documentation + ** and/or other materials provided with the distribution. + ** 3. Neither the name of STMicroelectronics nor the names of its contributors + ** may be used to endorse or promote products derived from this software + ** without specific prior written permission. + ** + ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ** + ** + ***************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char *stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + +/* Functions */ +void initialise_monitor_handles() { +} + +int _getpid(void) { + return 1; +} + +int _kill(int pid, int sig) { + errno = EINVAL; + return -1; +} + +void _exit(int status) { + _kill(status, -1); + while (1) { + } /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) { + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) { + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) { + return -1; +} + +int _fstat(int file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) { + return 1; +} + +int _lseek(int file, int ptr, int dir) { + return 0; +} + +int _open(char *path, int flags, ...) { + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) { + errno = ECHILD; + return -1; +} + +int _unlink(char *name) { + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) { + return -1; +} + +int _stat(char *file, struct stat *st) { + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) { + errno = EMLINK; + return -1; +} + +int _fork(void) { + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) { + errno = ENOMEM; + return -1; +} diff --git a/DBW_V2/Core/Src/sysmem.c b/DBW_V2/Core/Src/sysmem.c new file mode 100644 index 0000000..a750537 --- /dev/null +++ b/DBW_V2/Core/Src/sysmem.c @@ -0,0 +1,84 @@ +/** + ***************************************************************************** + ** + ** File : sysmem.c + ** + ** Author : Auto-generated by STM32CubeIDE + ** + ** Abstract : STM32CubeIDE Minimal System Memory calls file + ** + ** For more information about which c-functions + ** need which of these lowlevel functions + ** please consult the Newlib libc-manual + ** + ** Environment : STM32CubeIDE MCU + ** + ** Distribution: The file is distributed as is, without any warranty + ** of any kind. + ** + ***************************************************************************** + ** + **

© COPYRIGHT(c) 2018 STMicroelectronics

+ ** + ** Redistribution and use in source and binary forms, with or without modification, + ** are permitted provided that the following conditions are met: + ** 1. Redistributions of source code must retain the above copyright notice, + ** this list of conditions and the following disclaimer. + ** 2. Redistributions in binary form must reproduce the above copyright notice, + ** this list of conditions and the following disclaimer in the documentation + ** and/or other materials provided with the distribution. + ** 3. Neither the name of STMicroelectronics nor the names of its contributors + ** may be used to endorse or promote products derived from this software + ** without specific prior written permission. + ** + ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ** + ** + ***************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/* Variables */ +extern int errno; +register char *stack_ptr asm("sp"); + + +/* Functions */ + +/** + _sbrk + Increase program data space. Malloc and related functions depend on this + **/ +caddr_t _sbrk(int incr) { + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) { + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + + diff --git a/DBW_V2/Core/Src/system_stm32f0xx.c b/DBW_V2/Core/Src/system_stm32f0xx.c new file mode 100644 index 0000000..e97e6cc --- /dev/null +++ b/DBW_V2/Core/Src/system_stm32f0xx.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ +/* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, + 9 }; +const uint8_t APBPrescTable[8] = { 0, 0, 0, 0, 1, 2, 3, 4 }; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) { + /* NOTE :SystemInit(): This function is called at startup just after reset and + before branch to main program. This call is made inside + the "startup_stm32f0xx.s" file. + User can setups the default system clock (System clock source, PLL Multiplier + and Divider factors, AHB/APBx prescalers and Flash settings). + */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) { + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = (pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE / predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Core/Src/ts_comms.c b/DBW_V2/Core/Src/ts_comms.c new file mode 100644 index 0000000..5245591 --- /dev/null +++ b/DBW_V2/Core/Src/ts_comms.c @@ -0,0 +1,444 @@ +/* + * ts_comms.cpp + * + * Created on: 22 Oct 2020 + * Author: Dmitrijs + */ + +#include "main.h" +#include "dbw.h" + +comms_status RX; +comms_status TX; +unsigned char SCI_flags; +const char Signature[20]; +const char Revision[20]; +char crc32_bufer[8]; + +void (*Store_config)(void) = Write_Config; +const char Signature[20] = { "speeduino DBW 2.0.0" }; +const char Revision[20] = { "speeduino DBW 2.0.0" }; + +volatile var_t tx_bufer; + +void Comms_Init(void) { + Comms_Reset(&TX); + Comms_Reset(&RX); + + USART1->ISR &= ~USART_ISR_RXNE; + USART1->CR1 |= USART_CR1_RXNEIE; + +} + +void USART1_IRQHandler(void) { + uint8_t tmp; + if (USART1->ISR & USART_ISR_RXNE) { + tmp = USART1->RDR; + USART1->ISR &= ~USART_ISR_RXNE; + //if there are any RX errors reset comms else process data + if (USART1->ISR & 0x000F) { + Comms_Reset(&RX); + USART1->ISR &= ~0x000F; + } else { + Rx_Char(tmp); + } + } +//transmit interrupt + if (USART1->ISR & USART_ISR_TC) { + if (TX.bytes_done < TX.cnt) { + USART1->TDR = *TX.address; + TX.address++; + TX.bytes_done++; + } else + TX_Done(); + + } +} + +void Comms_Reset(comms_status *CS) { + + CS->mode = IDLE; //Mode Idle + CS->cnt = 0; //Nothing to receive + CS->bytes_done = 0; //Nothing received + CS->crc32 = 0; //Reset crc32 + CS->pause_flag = 0; + CS->address = &CS->cmd; //Point incoming characters to cmd_bufer + CS->timeout = 0; +} + +void Rx_Char(unsigned char data) { + + RX.bytes_done++; + + if (RX.bytes_done == 1) { + if (data == 'A') { + SCI_flags |= SCI_FLAGS_TX_VARIABLES; + Comms_Reset(&RX); + } else if (data == 'Q') { + TX_Schedule((unsigned char*) Revision, 20); + Comms_Reset(&RX); + } else if (data == 'S') { + TX_Schedule((unsigned char*) Signature, 20); + Comms_Reset(&RX); + } else if (data == 'B') { + Store_config(); + Comms_Reset(&RX); + } else if ((data == 'r') || (data == 'w') || (data == 'k') + || (data == 'b') || (data == 'z')) { + RX.timeout = 500; + RX.cmd = data; + } else { + Comms_Reset(&RX); + return; + } + + } else if (RX.bytes_done == 2) { + RX.CANid = data; + } else if (RX.bytes_done == 3) { + RX.table_index = data; + if (RX.cmd == 'b') { + Store_config(); + Comms_Reset(&RX); + return; + } + } else if (RX.bytes_done == 4) { + RX.offset = 0x00; + RX.offset = (unsigned short) data; + } else if (RX.bytes_done == 5) { + RX.offset |= ((unsigned short) data) << 8; + } else if (RX.bytes_done == 6) { + RX.data_size = 0x00; + RX.data_size = (unsigned short) data; + } else if (RX.bytes_done == 7) { + RX.data_size += ((unsigned short) data) << 8; + + if (RX.CANid == TS_CAN_ID) { + + if (RX.cmd == 'k') { + SCI_flags |= SCI_FLAGS_CRC32; + Comms_Reset(&RX); + return; + } else if (RX.cmd == 'z') { + // process command buttons + if (RX.data_size == 0x0100) { + Apply_Sensor_Calibration(); + } else if (RX.data_size == 0x0200) { + DBW_Stop(); + config->config_bits |= CONFIG_TESTMODE_F; + } else if (RX.data_size == 0x0300) { + config->config_bits &= ~CONFIG_TESTMODE_F; + } else if (RX.data_size == 0x0400) { + //Start TPS AUTOCAL + ac_timer = 200; + ac_mode = 1; + } + Comms_Reset(&RX); + } else if (RX.cmd == 'r') { + // Read different tables + if (RX.table_index == 0x01) { + TX_Schedule((unsigned char*) config + RX.offset, + RX.data_size); + } else if (RX.table_index == 0x07) { + Copy_Tx_Vars(); + TX_Schedule((unsigned char*) &tx_bufer + RX.offset, + RX.data_size); + } else if (RX.table_index == 0x0e) { + TX_Schedule((unsigned char*) Signature, 20); + } else if (RX.table_index == 0x0f) { + TX_Schedule((unsigned char*) Revision, 20); + } + Comms_Reset(&RX); + return; + } else { + //Comms are not reset for 'w' command + // setup write pointer + RX.cnt = RX.bytes_done + RX.data_size; + if (RX.table_index == 0x01) { + RX.address = (unsigned char*) config + RX.offset; + } else { + RX.address = (unsigned char*) RX.can_bufer; + // Do not allow more then 256 bytes to be written to CAN buffer + if (RX.data_size > 256) + Comms_Reset(&RX); + } + + return; + } + + } else { + // if received CANID != TS_CANID + if ((RX.cmd == 'k') || (RX.cmd == 'r')) { + //TODO pass data to CAN device + Comms_Reset(&RX); + return; + } + Comms_Reset(&RX); + return; + } + } else { + //receive data TX.bytes_done >7 + *(RX.address) = data; + RX.address++; + + if (RX.bytes_done >= RX.cnt) { + if (RX.table_index == 0x0d) { + //TODO Call command by index + Comms_Reset(&RX); + } else { + // Expecting here ends data write chain + Comms_Reset(&RX); + } + + } + + } + +} // RX Char + +void TX_Schedule(unsigned char *data, unsigned short count) { + //Schedule transmission + TX.mode = TRANSMISSION_IN_PROGRESS; // Set TX mode to transmit + + TX.cnt = count; // Set number of byte to be transmited + TX.bytes_done = 0; // Set number of bytes transmitted + TX.address = data; // Store updated address + + //transmit first data byte + USART1->ICR |= USART_ICR_TCCF; + USART1->TDR = *data; + USART1->CR1 |= USART_CR1_TCIE; + + TX.bytes_done++; + TX.address++; + +// if(TX.cnt==1) +// { +// TX_Done(); +// } +// else{ +// +// +// } + + return; +} + +void Poll_Tx(void) { + + if (TX.mode == TRANSMISSION_IN_PROGRESS) { + // do nothing because transmitter is busy; + } + // Check if variables should be transmitted + else if (SCI_flags & SCI_FLAGS_TX_VARIABLES) { + //Copy variables to tx_bufer + Copy_Tx_Vars(); + TX_Schedule((unsigned char*) &tx_bufer, sizeof(var_t)); + SCI_flags &= ~SCI_FLAGS_TX_VARIABLES; + return; + + } else if (SCI_flags & SCI_FLAGS_CRC32) { + SCI_flags &= ~SCI_FLAGS_CRC32; + CRC32(); + TX_Schedule((unsigned char*) &crc32_bufer[0], 4); + return; + + } + +} + +void TX_Done(void) { + Comms_Reset(&TX); + //disable TX interrupt + USART1->CR1 &= ~USART_CR1_TCIE; + USART1->ICR |= USART_ICR_TCCF; + +} + +void CRC32(void) { + unsigned int tmp; + + tmp = (unsigned int) crc32((void*) config, sizeof(config_t)); + crc32_bufer[0] = (unsigned char) ((tmp >> 24) & 0x000000ff); + crc32_bufer[1] = (unsigned char) ((tmp >> 16) & 0x000000ff); + crc32_bufer[2] = (unsigned char) ((tmp >> 8) & 0x000000ff); + crc32_bufer[3] = (unsigned char) ((tmp) & 0x000000ff); +} + +void Copy_Tx_Vars(void) { + +//TODO copy all variables from *var to tx_bufer to make sure +// nothing is changed while transmission is in progress +//tx_bufer.a = var->a; + + tx_bufer.clock = var.clock; + tx_bufer.status0 = var.rpm; + tx_bufer.status1 = var.status1; + tx_bufer.status2 = var.status2; + tx_bufer.status3 = var.status3; + + tx_bufer.pps1_adc = var.pps1_adc; + tx_bufer.pps2_adc = var.pps2_adc; + tx_bufer.tps1_adc = var.tps1_adc; + tx_bufer.tps2_adc = var.tps2_adc; + tx_bufer.motor_current_adc = var.motor_current_adc; + tx_bufer.vbat_adc = var.vbat_adc; + + tx_bufer.pps1 = var.pps1; + tx_bufer.pps2 = var.pps2; + tx_bufer.tps1 = var.tps1; + tx_bufer.tps2 = var.tps2; + tx_bufer.pps = var.pps; + tx_bufer.tps = var.tps; + tx_bufer.tps_error = var.tps_error; + tx_bufer.motor_pwm = var.motor_pwm; + tx_bufer.idle_dc = var.idle_dc; + tx_bufer.pps_delta = var.pps_delta; + tx_bufer.tps_delta = var.tps_delta; + tx_bufer.tps_target = var.tps_target; +} + +#define WIDTH (8) +#define TOPBIT (1 << (WIDTH - 1)) +#define POLYNOMIAL 0xD8 + +crc_t calc_crc(crc_t message[], int nBytes) { + crc_t remainder = 0; + + /* + * Perform modulo-2 division, a byte at a time. + */ + for (int byte = 0; byte < nBytes; ++byte) { + /* + * Bring the next byte into the remainder. + */ + remainder ^= (message[byte] << (WIDTH - 8)); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (unsigned char bit = 8; bit > 0; --bit) { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) { + remainder = (remainder << 1) ^ POLYNOMIAL; + } else { + remainder = (remainder << 1); + } + } + } + + /* + * The final remainder is the CRC result. + */ + return remainder; +} + +static uint32_t crc32_tab[] = { 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, + 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, + 0xf4d4b551, 0x83d385c7, 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, + 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, + 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, + 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, + 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, + 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, + 0x8cd37cf3, 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, + 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, + 0xb966d409, 0xce61e49f, 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, + 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, + 0x0a00ae27, 0x7d079eb1, 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, + 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, + 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, + 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, + 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, + 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, + 0x6fb077e1, 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, + 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, + 0x47b2cf7f, 0x30b5ffe9, 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, + 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d }; + +/** + * Online CRC calculator: + * http://www.zorc.breitbandkatze.de/crc.html + */ +uint32_t crc32(void *buf, uint32_t size) { + return crc32inc(buf, 0, size); +} + +uint32_t crc32inc(void *buf, uint32_t crc, uint32_t size) { + uint8_t *p; + + p = (uint8_t*) buf; + crc = crc ^ 0xFFFFFFFF; + + while (size--) { + crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + } + + return crc ^ 0xFFFFFFFF; +} + +void Write_Config(void) { + __disable_irq(); + uint32_t error; + FLASH_EraseInitTypeDef erase_pages; + erase_pages.NbPages = 2; + erase_pages.TypeErase = TYPEERASE_PAGES; + erase_pages.PageAddress = (uint32_t) &config_flash; + HAL_FLASH_Unlock(); + HAL_FLASHEx_Erase(&erase_pages, &error); + HAL_FLASH_Lock(); + + uint16_t num_wrt; + if (sizeof(config_t) & 0x0001) + num_wrt = (sizeof(config_t) << 1) + 1; + else + num_wrt = sizeof(config_t) << 1; + if (num_wrt > 2048) + Error_Handler(); + + HAL_FLASH_Unlock(); + uint16_t *data, *flash_address; + data = (uint16_t*) &config_ram; + flash_address = (uint16_t*) &config_flash; + for (int i = 0; i < num_wrt; i++) { + HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, (uint32_t) flash_address, + *data); + data++; + flash_address++; + } + HAL_FLASH_Lock(); + __enable_irq(); +} + +void TS_Comms_RX_Timeout(void) { + if (RX.mode != IDLE) { + if (RX.timeout) { + RX.timeout--; + if (RX.timeout == 0) { + Comms_Reset(&RX); + } + } + } +} diff --git a/DBW_V2/Core/Startup/startup_stm32f072c8tx.s b/DBW_V2/Core/Startup/startup_stm32f072c8tx.s new file mode 100644 index 0000000..9d431a9 --- /dev/null +++ b/DBW_V2/Core/Startup/startup_stm32f072c8tx.s @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file startup_stm32f072xb.s + * @author MCD Application Team + * @brief STM32F072x8/STM32F072xB devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3 and USART4 */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_6_7_IRQHandler + .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/DBW_v2 Debug.launch b/DBW_V2/DBW_v2 Debug.launch new file mode 100644 index 0000000..a510bc2 --- /dev/null +++ b/DBW_V2/DBW_v2 Debug.launch @@ -0,0 +1,83 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DBW_V2/DBW_v2.launch b/DBW_V2/DBW_v2.launch new file mode 100644 index 0000000..0eab2d5 --- /dev/null +++ b/DBW_V2/DBW_v2.launch @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DBW_V2/DBW_v2_1.ioc b/DBW_V2/DBW_v2_1.ioc new file mode 100644 index 0000000..4118135 --- /dev/null +++ b/DBW_V2/DBW_v2_1.ioc @@ -0,0 +1,176 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +KeepUserPlacement=false +Mcu.CPN=STM32F072C8T6 +Mcu.Family=STM32F0 +Mcu.IP0=ADC +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IP4=USART1 +Mcu.IPNb=5 +Mcu.Name=STM32F072C(8-B)Tx +Mcu.Package=LQFP48 +Mcu.Pin0=PF0-OSC_IN +Mcu.Pin1=PF1-OSC_OUT +Mcu.Pin10=PB12 +Mcu.Pin11=PB13 +Mcu.Pin12=PB14 +Mcu.Pin13=PB15 +Mcu.Pin14=PA9 +Mcu.Pin15=PA10 +Mcu.Pin16=PA13 +Mcu.Pin17=PA14 +Mcu.Pin18=PB5 +Mcu.Pin19=PB6 +Mcu.Pin2=PA0 +Mcu.Pin20=PB7 +Mcu.Pin21=VP_SYS_VS_Systick +Mcu.Pin3=PA1 +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=PA4 +Mcu.Pin7=PA5 +Mcu.Pin8=PB10 +Mcu.Pin9=PB11 +Mcu.PinsNb=22 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F072C8Tx +MxCube.Version=6.5.0 +MxDb.Version=DB.6.0.50 +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +PA0.GPIOParameters=GPIO_Label +PA0.GPIO_Label=PPS1 +PA0.Mode=IN0 +PA0.Signal=ADC_IN0 +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=PPS2 +PA1.Mode=IN1 +PA1.Signal=ADC_IN1 +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.Mode=Serial_Wire +PA13.Signal=SYS_SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_SWCLK +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=TPS1 +PA2.Mode=IN2 +PA2.Signal=ADC_IN2 +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=TPS2 +PA3.Mode=IN3 +PA3.Signal=ADC_IN3 +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=TTL_FB +PA4.Mode=IN4 +PA4.Signal=ADC_IN4 +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=VBAT_SENSE +PA5.Mode=IN5 +PA5.Signal=ADC_IN5 +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB10.GPIOParameters=GPIO_Label +PB10.GPIO_Label=PWM1 +PB10.Locked=true +PB10.Signal=GPIO_Output +PB11.GPIOParameters=GPIO_Label +PB11.GPIO_Label=PWM2 +PB11.Locked=true +PB11.Signal=GPIO_Output +PB12.GPIOParameters=GPIO_Label +PB12.GPIO_Label=FAULT +PB12.Locked=true +PB12.Signal=GPIO_Output +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=D2 +PB13.Locked=true +PB13.Signal=GPIO_Output +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=D1 +PB14.Locked=true +PB14.Signal=GPIO_Output +PB15.GPIOParameters=GPIO_Label +PB15.GPIO_Label=STATUS_FLAG +PB15.Locked=true +PB15.Signal=GPIO_Input +PB5.GPIOParameters=GPIO_Label +PB5.GPIO_Label=GPO1 +PB5.Locked=true +PB5.Signal=GPIO_Output +PB6.GPIOParameters=GPIO_Label +PB6.GPIO_Label=GPO2_1 +PB6.Locked=true +PB6.Signal=GPIO_Output +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=GPO2_2 +PB7.Locked=true +PB7.Signal=GPIO_Output +PF0-OSC_IN.Mode=HSE-External-Oscillator +PF0-OSC_IN.Signal=RCC_OSC_IN +PF1-OSC_OUT.Mode=HSE-External-Oscillator +PF1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F072C8Tx +ProjectManager.FirmwarePackage=STM32Cube FW_F0 V1.11.3 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=DBW_v2.ioc +ProjectManager.ProjectName=DBW_v2 +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC_Init-ADC-false-HAL-true,4-MX_CAN_Init-CAN-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-true +RCC.AHBFreq_Value=48000000 +RCC.APB1Freq_Value=48000000 +RCC.APB1TimFreq_Value=48000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.FCLKCortexFreq_Value=48000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=48000000 +RCC.HSICECFreq_Value=32786.88524590164 +RCC.I2SFreq_Value=48000000 +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,CECFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSICECFreq_Value,I2SFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLDivider,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USART1Freq_Value,USART2Freq_Value,VCOOutput2Freq_Value +RCC.MCOFreq_Value=48000000 +RCC.PLLCLKFreq_Value=48000000 +RCC.PLLDivider=RCC_PREDIV_DIV2 +RCC.PLLMCOFreq_Value=48000000 +RCC.PLLMUL=RCC_PLL_MUL12 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.SYSCLKFreq_VALUE=48000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.TimSysFreq_Value=48000000 +RCC.USART1Freq_Value=48000000 +RCC.USART2Freq_Value=48000000 +RCC.VCOOutput2Freq_Value=4000000 +USART1.BaudRate=115200 +USART1.IPParameters=VirtualMode-Asynchronous,BaudRate +USART1.VirtualMode-Asynchronous=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/DBW_V2/Debug/Core/Src/adc.cyclo b/DBW_V2/Debug/Core/Src/adc.cyclo new file mode 100644 index 0000000..4180316 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/adc.cyclo @@ -0,0 +1,3 @@ +../Core/Src/adc.c:10:6:Adc_Init 6 +../Core/Src/adc.c:52:16:LPF 2 +../Core/Src/adc.c:68:16:Adc_Read 3 diff --git a/DBW_V2/Debug/Core/Src/adc.d b/DBW_V2/Debug/Core/Src/adc.d new file mode 100644 index 0000000..8a8f0a4 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/adc.d @@ -0,0 +1,73 @@ +Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/adc.o b/DBW_V2/Debug/Core/Src/adc.o new file mode 100644 index 0000000..f0b0eec Binary files /dev/null and b/DBW_V2/Debug/Core/Src/adc.o differ diff --git a/DBW_V2/Debug/Core/Src/adc.su b/DBW_V2/Debug/Core/Src/adc.su new file mode 100644 index 0000000..b1e8fe1 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/adc.su @@ -0,0 +1,3 @@ +../Core/Src/adc.c:10:6:Adc_Init 8 static +../Core/Src/adc.c:52:16:LPF 32 static +../Core/Src/adc.c:68:16:Adc_Read 24 static diff --git a/DBW_V2/Debug/Core/Src/can.cyclo b/DBW_V2/Debug/Core/Src/can.cyclo new file mode 100644 index 0000000..96a648e --- /dev/null +++ b/DBW_V2/Debug/Core/Src/can.cyclo @@ -0,0 +1,13 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Core/Src/can.c:20:6:CAN_Init 1 +../Core/Src/can.c:39:6:CAN_Setup 2 +../Core/Src/can.c:64:6:CAN_Start 2 +../Core/Src/can.c:75:6:CAN_Wait_Ready 2 +../Core/Src/can.c:83:6:CAN_Send_Msg 3 +../Core/Src/can.c:108:6:CAN_Recive_Msg 3 +../Core/Src/can.c:142:6:CAN_Write_Filter 4 +../Core/Src/can.c:171:6:CEC_CAN_IRQHandler 3 +../Core/Src/can.c:184:6:CAN_Send_TX_Buffer 4 +../Core/Src/can.c:198:6:CAN_Add_TX_Buffer 3 +../Core/Src/can.c:218:6:CAN_Add_RX_Buffer 5 +../Core/Src/can.c:261:6:CAN_Read_RX_Buffer 3 diff --git a/DBW_V2/Debug/Core/Src/can.d b/DBW_V2/Debug/Core/Src/can.d new file mode 100644 index 0000000..3a638e8 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/can.d @@ -0,0 +1,74 @@ +Core/Src/can.o: ../Core/Src/can.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h ../Core/Inc/CAN.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: +../Core/Inc/CAN.h: diff --git a/DBW_V2/Debug/Core/Src/can.o b/DBW_V2/Debug/Core/Src/can.o new file mode 100644 index 0000000..6305a46 Binary files /dev/null and b/DBW_V2/Debug/Core/Src/can.o differ diff --git a/DBW_V2/Debug/Core/Src/can.su b/DBW_V2/Debug/Core/Src/can.su new file mode 100644 index 0000000..636e978 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/can.su @@ -0,0 +1,13 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Core/Src/can.c:20:6:CAN_Init 8 static +../Core/Src/can.c:39:6:CAN_Setup 16 static +../Core/Src/can.c:64:6:CAN_Start 8 static +../Core/Src/can.c:75:6:CAN_Wait_Ready 8 static +../Core/Src/can.c:83:6:CAN_Send_Msg 16 static +../Core/Src/can.c:108:6:CAN_Recive_Msg 16 static +../Core/Src/can.c:142:6:CAN_Write_Filter 24 static +../Core/Src/can.c:171:6:CEC_CAN_IRQHandler 8 static +../Core/Src/can.c:184:6:CAN_Send_TX_Buffer 8 static +../Core/Src/can.c:198:6:CAN_Add_TX_Buffer 16 static +../Core/Src/can.c:218:6:CAN_Add_RX_Buffer 8 static +../Core/Src/can.c:261:6:CAN_Read_RX_Buffer 16 static diff --git a/DBW_V2/Debug/Core/Src/dbw.cyclo b/DBW_V2/Debug/Core/Src/dbw.cyclo new file mode 100644 index 0000000..15a52ae --- /dev/null +++ b/DBW_V2/Debug/Core/Src/dbw.cyclo @@ -0,0 +1,15 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:659:22:__NVIC_DisableIRQ 2 +../Core/Src/dbw.c:103:6:Apply_Sensor_Calibration 1 +../Core/Src/dbw.c:122:6:DBW_Init 1 +../Core/Src/dbw.c:136:5:DBW_Process 17 +../Core/Src/dbw.c:291:6:DBW_Pwm_Init 3 +../Core/Src/dbw.c:351:6:TIM2_IRQHandler 14 +../Core/Src/dbw.c:428:6:DBW_Pwm_Set_Duty 9 +../Core/Src/dbw.c:473:14:intrp_1d_uitable 7 +../Core/Src/dbw.c:503:14:intrp_1d_ss_table 7 +../Core/Src/dbw.c:533:5:intrp_1dstable 10 +../Core/Src/dbw.c:574:6:DBW_Start 1 +../Core/Src/dbw.c:578:6:DBW_Stop 1 +../Core/Src/dbw.c:584:6:DBW_TPS_AutoCal 12 +../Core/Src/dbw.c:641:6:DBW_Read_sensors 1 diff --git a/DBW_V2/Debug/Core/Src/dbw.d b/DBW_V2/Debug/Core/Src/dbw.d new file mode 100644 index 0000000..f9ff658 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/dbw.d @@ -0,0 +1,73 @@ +Core/Src/dbw.o: ../Core/Src/dbw.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/dbw.o b/DBW_V2/Debug/Core/Src/dbw.o new file mode 100644 index 0000000..4585a8a Binary files /dev/null and b/DBW_V2/Debug/Core/Src/dbw.o differ diff --git a/DBW_V2/Debug/Core/Src/dbw.su b/DBW_V2/Debug/Core/Src/dbw.su new file mode 100644 index 0000000..aaf84a2 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/dbw.su @@ -0,0 +1,15 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Drivers/CMSIS/Include/core_cm0.h:659:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Core/Src/dbw.c:103:6:Apply_Sensor_Calibration 16 static +../Core/Src/dbw.c:122:6:DBW_Init 8 static +../Core/Src/dbw.c:136:5:DBW_Process 32 static +../Core/Src/dbw.c:291:6:DBW_Pwm_Init 8 static +../Core/Src/dbw.c:351:6:TIM2_IRQHandler 8 static +../Core/Src/dbw.c:428:6:DBW_Pwm_Set_Duty 32 static,ignoring_inline_asm +../Core/Src/dbw.c:473:14:intrp_1d_uitable 48 static +../Core/Src/dbw.c:503:14:intrp_1d_ss_table 40 static +../Core/Src/dbw.c:533:5:intrp_1dstable 40 static +../Core/Src/dbw.c:574:6:DBW_Start 8 static +../Core/Src/dbw.c:578:6:DBW_Stop 8 static +../Core/Src/dbw.c:584:6:DBW_TPS_AutoCal 32 static +../Core/Src/dbw.c:641:6:DBW_Read_sensors 8 static diff --git a/DBW_V2/Debug/Core/Src/inputs.cyclo b/DBW_V2/Debug/Core/Src/inputs.cyclo new file mode 100644 index 0000000..ac53cd6 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/inputs.cyclo @@ -0,0 +1,5 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Core/Src/inputs.c:14:6:TIM3_Init 1 +../Core/Src/inputs.c:42:6:TIM14_Init 1 +../Core/Src/inputs.c:69:6:TIM3_IRQHandler 3 +../Core/Src/inputs.c:87:6:TIM14_IRQHandler 5 diff --git a/DBW_V2/Debug/Core/Src/inputs.d b/DBW_V2/Debug/Core/Src/inputs.d new file mode 100644 index 0000000..9476383 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/inputs.d @@ -0,0 +1,73 @@ +Core/Src/inputs.o: ../Core/Src/inputs.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/inputs.o b/DBW_V2/Debug/Core/Src/inputs.o new file mode 100644 index 0000000..22431dc Binary files /dev/null and b/DBW_V2/Debug/Core/Src/inputs.o differ diff --git a/DBW_V2/Debug/Core/Src/inputs.su b/DBW_V2/Debug/Core/Src/inputs.su new file mode 100644 index 0000000..e89e693 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/inputs.su @@ -0,0 +1,5 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Core/Src/inputs.c:14:6:TIM3_Init 8 static +../Core/Src/inputs.c:42:6:TIM14_Init 8 static +../Core/Src/inputs.c:69:6:TIM3_IRQHandler 8 static +../Core/Src/inputs.c:87:6:TIM14_IRQHandler 8 static diff --git a/DBW_V2/Debug/Core/Src/main.cyclo b/DBW_V2/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..5486758 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/main.cyclo @@ -0,0 +1,7 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Core/Src/main.c:75:5:main 13 +../Core/Src/main.c:217:6:SystemClock_Config 4 +../Core/Src/main.c:259:13:MX_ADC_Init 8 +../Core/Src/main.c:372:13:MX_USART1_UART_Init 2 +../Core/Src/main.c:405:13:MX_GPIO_Init 1 +../Core/Src/main.c:442:6:Error_Handler 1 diff --git a/DBW_V2/Debug/Core/Src/main.d b/DBW_V2/Debug/Core/Src/main.d new file mode 100644 index 0000000..eb86160 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/main.d @@ -0,0 +1,73 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/main.o b/DBW_V2/Debug/Core/Src/main.o new file mode 100644 index 0000000..a978124 Binary files /dev/null and b/DBW_V2/Debug/Core/Src/main.o differ diff --git a/DBW_V2/Debug/Core/Src/main.su b/DBW_V2/Debug/Core/Src/main.su new file mode 100644 index 0000000..7862bb4 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/main.su @@ -0,0 +1,7 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Core/Src/main.c:75:5:main 8 static +../Core/Src/main.c:217:6:SystemClock_Config 112 static +../Core/Src/main.c:259:13:MX_ADC_Init 24 static +../Core/Src/main.c:372:13:MX_USART1_UART_Init 8 static +../Core/Src/main.c:405:13:MX_GPIO_Init 48 static +../Core/Src/main.c:442:6:Error_Handler 8 static diff --git a/DBW_V2/Debug/Core/Src/mazda_can.cyclo b/DBW_V2/Debug/Core/Src/mazda_can.cyclo new file mode 100644 index 0000000..d37cfa0 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/mazda_can.cyclo @@ -0,0 +1,2 @@ +../Core/Src/mazda_can.c:18:6:MAZDA_Send_Data 2 +../Core/Src/mazda_can.c:143:6:MAZDA_CAN_Read 5 diff --git a/DBW_V2/Debug/Core/Src/mazda_can.d b/DBW_V2/Debug/Core/Src/mazda_can.d new file mode 100644 index 0000000..86bd167 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/mazda_can.d @@ -0,0 +1,73 @@ +Core/Src/mazda_can.o: ../Core/Src/mazda_can.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/mazda_can.o b/DBW_V2/Debug/Core/Src/mazda_can.o new file mode 100644 index 0000000..79bd64c Binary files /dev/null and b/DBW_V2/Debug/Core/Src/mazda_can.o differ diff --git a/DBW_V2/Debug/Core/Src/mazda_can.su b/DBW_V2/Debug/Core/Src/mazda_can.su new file mode 100644 index 0000000..0bbc54a --- /dev/null +++ b/DBW_V2/Debug/Core/Src/mazda_can.su @@ -0,0 +1,2 @@ +../Core/Src/mazda_can.c:18:6:MAZDA_Send_Data 8 static +../Core/Src/mazda_can.c:143:6:MAZDA_CAN_Read 8 static diff --git a/DBW_V2/Debug/Core/Src/outputs.cyclo b/DBW_V2/Debug/Core/Src/outputs.cyclo new file mode 100644 index 0000000..a8669d5 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/outputs.cyclo @@ -0,0 +1,6 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Core/Src/outputs.c:10:6:TIM16_Init 1 +../Core/Src/outputs.c:25:6:TIM17_Init 1 +../Core/Src/outputs.c:40:6:VSS_Set 2 +../Core/Src/outputs.c:50:6:TIM16_IRQHandler 1 +../Core/Src/outputs.c:55:6:TIM17_IRQHandler 1 diff --git a/DBW_V2/Debug/Core/Src/outputs.d b/DBW_V2/Debug/Core/Src/outputs.d new file mode 100644 index 0000000..9b2710b --- /dev/null +++ b/DBW_V2/Debug/Core/Src/outputs.d @@ -0,0 +1,73 @@ +Core/Src/outputs.o: ../Core/Src/outputs.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/outputs.o b/DBW_V2/Debug/Core/Src/outputs.o new file mode 100644 index 0000000..8e37ff2 Binary files /dev/null and b/DBW_V2/Debug/Core/Src/outputs.o differ diff --git a/DBW_V2/Debug/Core/Src/outputs.su b/DBW_V2/Debug/Core/Src/outputs.su new file mode 100644 index 0000000..16ecc3a --- /dev/null +++ b/DBW_V2/Debug/Core/Src/outputs.su @@ -0,0 +1,6 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Core/Src/outputs.c:10:6:TIM16_Init 8 static +../Core/Src/outputs.c:25:6:TIM17_Init 8 static +../Core/Src/outputs.c:40:6:VSS_Set 16 static +../Core/Src/outputs.c:50:6:TIM16_IRQHandler 8 static +../Core/Src/outputs.c:55:6:TIM17_IRQHandler 8 static diff --git a/DBW_V2/Debug/Core/Src/safety.cyclo b/DBW_V2/Debug/Core/Src/safety.cyclo new file mode 100644 index 0000000..194385c --- /dev/null +++ b/DBW_V2/Debug/Core/Src/safety.cyclo @@ -0,0 +1,9 @@ +../Core/Src/safety.c:18:6:Flash_Write_Protect 1 +../Core/Src/safety.c:39:6:Flash_Write_Unprotect 1 +../Core/Src/safety.c:60:6:Watch_Dog_Update 1 +../Core/Src/safety.c:64:6:Watch_Dog_Init 5 +../Core/Src/safety.c:81:6:Check_Safety_Limits 21 +../Core/Src/safety.c:167:6:Check_Adc_Range 25 +../Core/Src/safety.c:320:6:Safety_TPS_Safety_Timer 3 +../Core/Src/safety.c:327:6:Safety_TPS_Safety_Timer_Start 1 +../Core/Src/safety.c:333:6:Check_TPS_Target 10 diff --git a/DBW_V2/Debug/Core/Src/safety.d b/DBW_V2/Debug/Core/Src/safety.d new file mode 100644 index 0000000..eeddfff --- /dev/null +++ b/DBW_V2/Debug/Core/Src/safety.d @@ -0,0 +1,77 @@ +Core/Src/safety.o: ../Core/Src/safety.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h ../Core/Inc/dbw.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/safety.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: +../Core/Inc/dbw.h: +../Core/Inc/ts_comms.h: +../Core/Inc/safety.h: diff --git a/DBW_V2/Debug/Core/Src/safety.o b/DBW_V2/Debug/Core/Src/safety.o new file mode 100644 index 0000000..d0c0ef0 Binary files /dev/null and b/DBW_V2/Debug/Core/Src/safety.o differ diff --git a/DBW_V2/Debug/Core/Src/safety.su b/DBW_V2/Debug/Core/Src/safety.su new file mode 100644 index 0000000..fcaf1d7 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/safety.su @@ -0,0 +1,9 @@ +../Core/Src/safety.c:18:6:Flash_Write_Protect 32 static +../Core/Src/safety.c:39:6:Flash_Write_Unprotect 32 static +../Core/Src/safety.c:60:6:Watch_Dog_Update 8 static +../Core/Src/safety.c:64:6:Watch_Dog_Init 8 static +../Core/Src/safety.c:81:6:Check_Safety_Limits 8 static +../Core/Src/safety.c:167:6:Check_Adc_Range 8 static +../Core/Src/safety.c:320:6:Safety_TPS_Safety_Timer 8 static +../Core/Src/safety.c:327:6:Safety_TPS_Safety_Timer_Start 8 static +../Core/Src/safety.c:333:6:Check_TPS_Target 8 static diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.cyclo b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.cyclo new file mode 100644 index 0000000..b3c8e4f --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.cyclo @@ -0,0 +1,7 @@ +../Core/Src/stm32f0xx_hal_msp.c:64:6:HAL_MspInit 1 +../Core/Src/stm32f0xx_hal_msp.c:85:6:HAL_ADC_MspInit 2 +../Core/Src/stm32f0xx_hal_msp.c:122:6:HAL_ADC_MspDeInit 2 +../Core/Src/stm32f0xx_hal_msp.c:155:6:HAL_CAN_MspInit 2 +../Core/Src/stm32f0xx_hal_msp.c:189:6:HAL_CAN_MspDeInit 2 +../Core/Src/stm32f0xx_hal_msp.c:216:6:HAL_UART_MspInit 2 +../Core/Src/stm32f0xx_hal_msp.c:250:6:HAL_UART_MspDeInit 2 diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.d b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.d new file mode 100644 index 0000000..5e288e5 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.d @@ -0,0 +1,73 @@ +Core/Src/stm32f0xx_hal_msp.o: ../Core/Src/stm32f0xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.o b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.o new file mode 100644 index 0000000..273036f Binary files /dev/null and b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.o differ diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.su b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.su new file mode 100644 index 0000000..5eb57ac --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_hal_msp.su @@ -0,0 +1,7 @@ +../Core/Src/stm32f0xx_hal_msp.c:64:6:HAL_MspInit 16 static +../Core/Src/stm32f0xx_hal_msp.c:85:6:HAL_ADC_MspInit 56 static +../Core/Src/stm32f0xx_hal_msp.c:122:6:HAL_ADC_MspDeInit 16 static +../Core/Src/stm32f0xx_hal_msp.c:155:6:HAL_CAN_MspInit 56 static +../Core/Src/stm32f0xx_hal_msp.c:189:6:HAL_CAN_MspDeInit 16 static +../Core/Src/stm32f0xx_hal_msp.c:216:6:HAL_UART_MspInit 56 static +../Core/Src/stm32f0xx_hal_msp.c:250:6:HAL_UART_MspDeInit 16 static diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_it.cyclo b/DBW_V2/Debug/Core/Src/stm32f0xx_it.cyclo new file mode 100644 index 0000000..6f712ca --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_it.cyclo @@ -0,0 +1,5 @@ +../Core/Src/stm32f0xx_it.c:74:6:NMI_Handler 1 +../Core/Src/stm32f0xx_it.c:86:6:HardFault_Handler 1 +../Core/Src/stm32f0xx_it.c:99:6:SVC_Handler 1 +../Core/Src/stm32f0xx_it.c:111:6:PendSV_Handler 1 +../Core/Src/stm32f0xx_it.c:123:6:SysTick_Handler 5 diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_it.d b/DBW_V2/Debug/Core/Src/stm32f0xx_it.d new file mode 100644 index 0000000..155e4c4 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_it.d @@ -0,0 +1,80 @@ +Core/Src/stm32f0xx_it.o: ../Core/Src/stm32f0xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h ../Core/Inc/stm32f0xx_it.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/can.h \ + ../Core/Inc/safety.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: +../Core/Inc/stm32f0xx_it.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_it.o b/DBW_V2/Debug/Core/Src/stm32f0xx_it.o new file mode 100644 index 0000000..2e8905f Binary files /dev/null and b/DBW_V2/Debug/Core/Src/stm32f0xx_it.o differ diff --git a/DBW_V2/Debug/Core/Src/stm32f0xx_it.su b/DBW_V2/Debug/Core/Src/stm32f0xx_it.su new file mode 100644 index 0000000..fd01764 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/stm32f0xx_it.su @@ -0,0 +1,5 @@ +../Core/Src/stm32f0xx_it.c:74:6:NMI_Handler 8 static +../Core/Src/stm32f0xx_it.c:86:6:HardFault_Handler 8 static +../Core/Src/stm32f0xx_it.c:99:6:SVC_Handler 8 static +../Core/Src/stm32f0xx_it.c:111:6:PendSV_Handler 8 static +../Core/Src/stm32f0xx_it.c:123:6:SysTick_Handler 8 static diff --git a/DBW_V2/Debug/Core/Src/subdir.mk b/DBW_V2/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..577f381 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/subdir.mk @@ -0,0 +1,66 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/adc.c \ +../Core/Src/can.c \ +../Core/Src/dbw.c \ +../Core/Src/inputs.c \ +../Core/Src/main.c \ +../Core/Src/mazda_can.c \ +../Core/Src/outputs.c \ +../Core/Src/safety.c \ +../Core/Src/stm32f0xx_hal_msp.c \ +../Core/Src/stm32f0xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f0xx.c \ +../Core/Src/ts_comms.c + +C_DEPS += \ +./Core/Src/adc.d \ +./Core/Src/can.d \ +./Core/Src/dbw.d \ +./Core/Src/inputs.d \ +./Core/Src/main.d \ +./Core/Src/mazda_can.d \ +./Core/Src/outputs.d \ +./Core/Src/safety.d \ +./Core/Src/stm32f0xx_hal_msp.d \ +./Core/Src/stm32f0xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f0xx.d \ +./Core/Src/ts_comms.d + +OBJS += \ +./Core/Src/adc.o \ +./Core/Src/can.o \ +./Core/Src/dbw.o \ +./Core/Src/inputs.o \ +./Core/Src/main.o \ +./Core/Src/mazda_can.o \ +./Core/Src/outputs.o \ +./Core/Src/safety.o \ +./Core/Src/stm32f0xx_hal_msp.o \ +./Core/Src/stm32f0xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f0xx.o \ +./Core/Src/ts_comms.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F072xB -DDEBUG -c -I../Drivers/STM32F0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Include -I../Core/Inc -I../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F0xx/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/can.cyclo ./Core/Src/can.d ./Core/Src/can.o ./Core/Src/can.su ./Core/Src/dbw.cyclo ./Core/Src/dbw.d ./Core/Src/dbw.o ./Core/Src/dbw.su ./Core/Src/inputs.cyclo ./Core/Src/inputs.d ./Core/Src/inputs.o ./Core/Src/inputs.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/mazda_can.cyclo ./Core/Src/mazda_can.d ./Core/Src/mazda_can.o ./Core/Src/mazda_can.su ./Core/Src/outputs.cyclo ./Core/Src/outputs.d ./Core/Src/outputs.o ./Core/Src/outputs.su ./Core/Src/safety.cyclo ./Core/Src/safety.d ./Core/Src/safety.o ./Core/Src/safety.su ./Core/Src/stm32f0xx_hal_msp.cyclo ./Core/Src/stm32f0xx_hal_msp.d ./Core/Src/stm32f0xx_hal_msp.o ./Core/Src/stm32f0xx_hal_msp.su ./Core/Src/stm32f0xx_it.cyclo ./Core/Src/stm32f0xx_it.d ./Core/Src/stm32f0xx_it.o ./Core/Src/stm32f0xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32f0xx.cyclo ./Core/Src/system_stm32f0xx.d ./Core/Src/system_stm32f0xx.o ./Core/Src/system_stm32f0xx.su ./Core/Src/ts_comms.cyclo ./Core/Src/ts_comms.d ./Core/Src/ts_comms.o ./Core/Src/ts_comms.su + +.PHONY: clean-Core-2f-Src + diff --git a/DBW_V2/Debug/Core/Src/syscalls.cyclo b/DBW_V2/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..caeeb0c --- /dev/null +++ b/DBW_V2/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:71:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:74:5:_getpid 1 +../Core/Src/syscalls.c:78:5:_kill 1 +../Core/Src/syscalls.c:83:6:_exit 1 +../Core/Src/syscalls.c:89:27:_read 2 +../Core/Src/syscalls.c:99:27:_write 2 +../Core/Src/syscalls.c:108:5:_close 1 +../Core/Src/syscalls.c:112:5:_fstat 1 +../Core/Src/syscalls.c:117:5:_isatty 1 +../Core/Src/syscalls.c:121:5:_lseek 1 +../Core/Src/syscalls.c:125:5:_open 1 +../Core/Src/syscalls.c:130:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:140:5:_times 1 +../Core/Src/syscalls.c:144:5:_stat 1 +../Core/Src/syscalls.c:149:5:_link 1 +../Core/Src/syscalls.c:154:5:_fork 1 +../Core/Src/syscalls.c:159:5:_execve 1 diff --git a/DBW_V2/Debug/Core/Src/syscalls.d b/DBW_V2/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..e14669a --- /dev/null +++ b/DBW_V2/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/DBW_V2/Debug/Core/Src/syscalls.o b/DBW_V2/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..b6bbebd Binary files /dev/null and b/DBW_V2/Debug/Core/Src/syscalls.o differ diff --git a/DBW_V2/Debug/Core/Src/syscalls.su b/DBW_V2/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..0c107d3 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:71:6:initialise_monitor_handles 8 static +../Core/Src/syscalls.c:74:5:_getpid 8 static +../Core/Src/syscalls.c:78:5:_kill 16 static +../Core/Src/syscalls.c:83:6:_exit 16 static +../Core/Src/syscalls.c:89:27:_read 32 static +../Core/Src/syscalls.c:99:27:_write 32 static +../Core/Src/syscalls.c:108:5:_close 16 static +../Core/Src/syscalls.c:112:5:_fstat 16 static +../Core/Src/syscalls.c:117:5:_isatty 16 static +../Core/Src/syscalls.c:121:5:_lseek 24 static +../Core/Src/syscalls.c:125:5:_open 20 static +../Core/Src/syscalls.c:130:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:140:5:_times 16 static +../Core/Src/syscalls.c:144:5:_stat 16 static +../Core/Src/syscalls.c:149:5:_link 16 static +../Core/Src/syscalls.c:154:5:_fork 8 static +../Core/Src/syscalls.c:159:5:_execve 24 static diff --git a/DBW_V2/Debug/Core/Src/sysmem.cyclo b/DBW_V2/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..7d2f18b --- /dev/null +++ b/DBW_V2/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:65:9:_sbrk 3 diff --git a/DBW_V2/Debug/Core/Src/sysmem.d b/DBW_V2/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..9492cfb --- /dev/null +++ b/DBW_V2/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/DBW_V2/Debug/Core/Src/sysmem.o b/DBW_V2/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..733a4b9 Binary files /dev/null and b/DBW_V2/Debug/Core/Src/sysmem.o differ diff --git a/DBW_V2/Debug/Core/Src/sysmem.su b/DBW_V2/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..72fd7c2 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:65:9:_sbrk 24 static diff --git a/DBW_V2/Debug/Core/Src/system_stm32f0xx.cyclo b/DBW_V2/Debug/Core/Src/system_stm32f0xx.cyclo new file mode 100644 index 0000000..ad0115b --- /dev/null +++ b/DBW_V2/Debug/Core/Src/system_stm32f0xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f0xx.c:129:6:SystemInit 1 +../Core/Src/system_stm32f0xx.c:174:6:SystemCoreClockUpdate 7 diff --git a/DBW_V2/Debug/Core/Src/system_stm32f0xx.d b/DBW_V2/Debug/Core/Src/system_stm32f0xx.d new file mode 100644 index 0000000..a045be5 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/system_stm32f0xx.d @@ -0,0 +1,61 @@ +Core/Src/system_stm32f0xx.o: ../Core/Src/system_stm32f0xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Core/Src/system_stm32f0xx.o b/DBW_V2/Debug/Core/Src/system_stm32f0xx.o new file mode 100644 index 0000000..f04bd3a Binary files /dev/null and b/DBW_V2/Debug/Core/Src/system_stm32f0xx.o differ diff --git a/DBW_V2/Debug/Core/Src/system_stm32f0xx.su b/DBW_V2/Debug/Core/Src/system_stm32f0xx.su new file mode 100644 index 0000000..8990c09 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/system_stm32f0xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32f0xx.c:129:6:SystemInit 8 static +../Core/Src/system_stm32f0xx.c:174:6:SystemCoreClockUpdate 24 static diff --git a/DBW_V2/Debug/Core/Src/ts_can.su b/DBW_V2/Debug/Core/Src/ts_can.su new file mode 100644 index 0000000..ba4cd9a --- /dev/null +++ b/DBW_V2/Debug/Core/Src/ts_can.su @@ -0,0 +1,3 @@ +ts_can.c:13:6:TS_CAN_CanId2TSId 16 static +ts_can.c:23:10:TS_CAN_TSId2CanId 24 static +ts_can.c:40:6:TS_CAN_Process 112 static diff --git a/DBW_V2/Debug/Core/Src/ts_comms.cyclo b/DBW_V2/Debug/Core/Src/ts_comms.cyclo new file mode 100644 index 0000000..1947634 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/ts_comms.cyclo @@ -0,0 +1,14 @@ +../Core/Src/ts_comms.c:24:6:Comms_Init 1 +../Core/Src/ts_comms.c:33:6:USART1_IRQHandler 5 +../Core/Src/ts_comms.c:58:6:Comms_Reset 1 +../Core/Src/ts_comms.c:69:6:Rx_Char 36 +../Core/Src/ts_comms.c:198:6:TX_Schedule 1 +../Core/Src/ts_comms.c:226:6:Poll_Tx 4 +../Core/Src/ts_comms.c:249:6:TX_Done 1 +../Core/Src/ts_comms.c:257:6:CRC32 1 +../Core/Src/ts_comms.c:267:6:Copy_Tx_Vars 1 +../Core/Src/ts_comms.c:304:7:calc_crc 4 +../Core/Src/ts_comms.c:385:10:crc32 1 +../Core/Src/ts_comms.c:389:10:crc32inc 2 +../Core/Src/ts_comms.c:402:6:Write_Config 3 +../Core/Src/ts_comms.c:435:6:TS_Comms_RX_Timeout 4 diff --git a/DBW_V2/Debug/Core/Src/ts_comms.d b/DBW_V2/Debug/Core/Src/ts_comms.d new file mode 100644 index 0000000..1ad3a5e --- /dev/null +++ b/DBW_V2/Debug/Core/Src/ts_comms.d @@ -0,0 +1,74 @@ +Core/Src/ts_comms.o: ../Core/Src/ts_comms.c ../Core/Inc/main.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h \ + ../Core/Inc/ts_comms.h ../Core/Inc/dbw.h ../Core/Inc/adc.h \ + ../Core/Inc/can.h ../Core/Inc/safety.h ../Core/Inc/inputs.h \ + ../Core/Inc/outputs.h ../Core/Inc/mazda_can.h ../Core/Inc/dbw.h +../Core/Inc/main.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: +../Core/Inc/ts_comms.h: +../Core/Inc/dbw.h: +../Core/Inc/adc.h: +../Core/Inc/can.h: +../Core/Inc/safety.h: +../Core/Inc/inputs.h: +../Core/Inc/outputs.h: +../Core/Inc/mazda_can.h: +../Core/Inc/dbw.h: diff --git a/DBW_V2/Debug/Core/Src/ts_comms.o b/DBW_V2/Debug/Core/Src/ts_comms.o new file mode 100644 index 0000000..482419e Binary files /dev/null and b/DBW_V2/Debug/Core/Src/ts_comms.o differ diff --git a/DBW_V2/Debug/Core/Src/ts_comms.su b/DBW_V2/Debug/Core/Src/ts_comms.su new file mode 100644 index 0000000..a9a8b78 --- /dev/null +++ b/DBW_V2/Debug/Core/Src/ts_comms.su @@ -0,0 +1,14 @@ +../Core/Src/ts_comms.c:24:6:Comms_Init 8 static +../Core/Src/ts_comms.c:33:6:USART1_IRQHandler 16 static +../Core/Src/ts_comms.c:58:6:Comms_Reset 16 static +../Core/Src/ts_comms.c:69:6:Rx_Char 16 static +../Core/Src/ts_comms.c:198:6:TX_Schedule 16 static +../Core/Src/ts_comms.c:226:6:Poll_Tx 8 static +../Core/Src/ts_comms.c:249:6:TX_Done 8 static +../Core/Src/ts_comms.c:257:6:CRC32 16 static +../Core/Src/ts_comms.c:267:6:Copy_Tx_Vars 8 static +../Core/Src/ts_comms.c:304:7:calc_crc 32 static +../Core/Src/ts_comms.c:385:10:crc32 16 static +../Core/Src/ts_comms.c:389:10:crc32inc 32 static +../Core/Src/ts_comms.c:402:6:Write_Config 48 static,ignoring_inline_asm +../Core/Src/ts_comms.c:435:6:TS_Comms_RX_Timeout 8 static diff --git a/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.d b/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.d new file mode 100644 index 0000000..a24b023 --- /dev/null +++ b/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f072c8tx.o: \ + ../Core/Startup/startup_stm32f072c8tx.s diff --git a/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.o b/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.o new file mode 100644 index 0000000..30c9c60 Binary files /dev/null and b/DBW_V2/Debug/Core/Startup/startup_stm32f072c8tx.o differ diff --git a/DBW_V2/Debug/Core/Startup/subdir.mk b/DBW_V2/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..e6b13be --- /dev/null +++ b/DBW_V2/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f072c8tx.s + +S_DEPS += \ +./Core/Startup/startup_stm32f072c8tx.d + +OBJS += \ +./Core/Startup/startup_stm32f072c8tx.o + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0 -g3 -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32f072c8tx.d ./Core/Startup/startup_stm32f072c8tx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/DBW_V2/Debug/DBW_V2.elf b/DBW_V2/Debug/DBW_V2.elf new file mode 100644 index 0000000..2067c32 Binary files /dev/null and b/DBW_V2/Debug/DBW_V2.elf differ diff --git a/DBW_V2/Debug/DBW_V2.list b/DBW_V2/Debug/DBW_V2.list new file mode 100644 index 0000000..30ab151 --- /dev/null +++ b/DBW_V2/Debug/DBW_V2.list @@ -0,0 +1,21338 @@ + +DBW_V2.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000c0 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .config 00000358 0800f000 0800f000 0000b000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .text 000088d4 080000c0 080000c0 000010c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 0000018c 08008994 08008994 00009994 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .ARM.extab 00000000 08008b20 08008b20 0000b358 2**0 + CONTENTS + 5 .ARM 00000000 08008b20 08008b20 0000b358 2**0 + CONTENTS + 6 .preinit_array 00000000 08008b20 08008b20 0000b358 2**0 + CONTENTS, ALLOC, LOAD, DATA + 7 .init_array 00000004 08008b20 08008b20 00009b20 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .fini_array 00000004 08008b24 08008b24 00009b24 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .data 00000414 20000000 08008b28 0000a000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 10 .bss 000009b8 20000418 08008f3c 0000a418 2**3 + ALLOC + 11 ._user_heap_stack 00000600 20000dd0 08008f3c 0000add0 2**0 + ALLOC + 12 .ARM.attributes 00000028 00000000 00000000 0000b358 2**0 + CONTENTS, READONLY + 13 .debug_info 0000c9d8 00000000 00000000 0000b380 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_abbrev 00002cfc 00000000 00000000 00017d58 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 00000b28 00000000 00000000 0001aa58 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_rnglists 00000882 00000000 00000000 0001b580 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 0001afcf 00000000 00000000 0001be02 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 000107b0 00000000 00000000 00036dd1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 0009656c 00000000 00000000 00047581 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .comment 00000043 00000000 00000000 000ddaed 2**0 + CONTENTS, READONLY + 21 .debug_frame 000028b8 00000000 00000000 000ddb30 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 22 .debug_line_str 0000005b 00000000 00000000 000e03e8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000c0 <__do_global_dtors_aux>: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 20000418 .word 0x20000418 + 80000e0: 00000000 .word 0x00000000 + 80000e4: 0800897c .word 0x0800897c + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] @ (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] @ (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop @ (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 2000041c .word 0x2000041c + 8000104: 0800897c .word 0x0800897c + +08000108 <__udivsi3>: + 8000108: 2200 movs r2, #0 + 800010a: 0843 lsrs r3, r0, #1 + 800010c: 428b cmp r3, r1 + 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> + 8000110: 0903 lsrs r3, r0, #4 + 8000112: 428b cmp r3, r1 + 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> + 8000116: 0a03 lsrs r3, r0, #8 + 8000118: 428b cmp r3, r1 + 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> + 800011c: 0b03 lsrs r3, r0, #12 + 800011e: 428b cmp r3, r1 + 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> + 8000122: 0c03 lsrs r3, r0, #16 + 8000124: 428b cmp r3, r1 + 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> + 8000128: 22ff movs r2, #255 @ 0xff + 800012a: 0209 lsls r1, r1, #8 + 800012c: ba12 rev r2, r2 + 800012e: 0c03 lsrs r3, r0, #16 + 8000130: 428b cmp r3, r1 + 8000132: d302 bcc.n 800013a <__udivsi3+0x32> + 8000134: 1212 asrs r2, r2, #8 + 8000136: 0209 lsls r1, r1, #8 + 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> + 800013a: 0b03 lsrs r3, r0, #12 + 800013c: 428b cmp r3, r1 + 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> + 8000140: e000 b.n 8000144 <__udivsi3+0x3c> + 8000142: 0a09 lsrs r1, r1, #8 + 8000144: 0bc3 lsrs r3, r0, #15 + 8000146: 428b cmp r3, r1 + 8000148: d301 bcc.n 800014e <__udivsi3+0x46> + 800014a: 03cb lsls r3, r1, #15 + 800014c: 1ac0 subs r0, r0, r3 + 800014e: 4152 adcs r2, r2 + 8000150: 0b83 lsrs r3, r0, #14 + 8000152: 428b cmp r3, r1 + 8000154: d301 bcc.n 800015a <__udivsi3+0x52> + 8000156: 038b lsls r3, r1, #14 + 8000158: 1ac0 subs r0, r0, r3 + 800015a: 4152 adcs r2, r2 + 800015c: 0b43 lsrs r3, r0, #13 + 800015e: 428b cmp r3, r1 + 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> + 8000162: 034b lsls r3, r1, #13 + 8000164: 1ac0 subs r0, r0, r3 + 8000166: 4152 adcs r2, r2 + 8000168: 0b03 lsrs r3, r0, #12 + 800016a: 428b cmp r3, r1 + 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> + 800016e: 030b lsls r3, r1, #12 + 8000170: 1ac0 subs r0, r0, r3 + 8000172: 4152 adcs r2, r2 + 8000174: 0ac3 lsrs r3, r0, #11 + 8000176: 428b cmp r3, r1 + 8000178: d301 bcc.n 800017e <__udivsi3+0x76> + 800017a: 02cb lsls r3, r1, #11 + 800017c: 1ac0 subs r0, r0, r3 + 800017e: 4152 adcs r2, r2 + 8000180: 0a83 lsrs r3, r0, #10 + 8000182: 428b cmp r3, r1 + 8000184: d301 bcc.n 800018a <__udivsi3+0x82> + 8000186: 028b lsls r3, r1, #10 + 8000188: 1ac0 subs r0, r0, r3 + 800018a: 4152 adcs r2, r2 + 800018c: 0a43 lsrs r3, r0, #9 + 800018e: 428b cmp r3, r1 + 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> + 8000192: 024b lsls r3, r1, #9 + 8000194: 1ac0 subs r0, r0, r3 + 8000196: 4152 adcs r2, r2 + 8000198: 0a03 lsrs r3, r0, #8 + 800019a: 428b cmp r3, r1 + 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> + 800019e: 020b lsls r3, r1, #8 + 80001a0: 1ac0 subs r0, r0, r3 + 80001a2: 4152 adcs r2, r2 + 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> + 80001a6: 09c3 lsrs r3, r0, #7 + 80001a8: 428b cmp r3, r1 + 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> + 80001ac: 01cb lsls r3, r1, #7 + 80001ae: 1ac0 subs r0, r0, r3 + 80001b0: 4152 adcs r2, r2 + 80001b2: 0983 lsrs r3, r0, #6 + 80001b4: 428b cmp r3, r1 + 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> + 80001b8: 018b lsls r3, r1, #6 + 80001ba: 1ac0 subs r0, r0, r3 + 80001bc: 4152 adcs r2, r2 + 80001be: 0943 lsrs r3, r0, #5 + 80001c0: 428b cmp r3, r1 + 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> + 80001c4: 014b lsls r3, r1, #5 + 80001c6: 1ac0 subs r0, r0, r3 + 80001c8: 4152 adcs r2, r2 + 80001ca: 0903 lsrs r3, r0, #4 + 80001cc: 428b cmp r3, r1 + 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> + 80001d0: 010b lsls r3, r1, #4 + 80001d2: 1ac0 subs r0, r0, r3 + 80001d4: 4152 adcs r2, r2 + 80001d6: 08c3 lsrs r3, r0, #3 + 80001d8: 428b cmp r3, r1 + 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> + 80001dc: 00cb lsls r3, r1, #3 + 80001de: 1ac0 subs r0, r0, r3 + 80001e0: 4152 adcs r2, r2 + 80001e2: 0883 lsrs r3, r0, #2 + 80001e4: 428b cmp r3, r1 + 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> + 80001e8: 008b lsls r3, r1, #2 + 80001ea: 1ac0 subs r0, r0, r3 + 80001ec: 4152 adcs r2, r2 + 80001ee: 0843 lsrs r3, r0, #1 + 80001f0: 428b cmp r3, r1 + 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> + 80001f4: 004b lsls r3, r1, #1 + 80001f6: 1ac0 subs r0, r0, r3 + 80001f8: 4152 adcs r2, r2 + 80001fa: 1a41 subs r1, r0, r1 + 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> + 80001fe: 4601 mov r1, r0 + 8000200: 4152 adcs r2, r2 + 8000202: 4610 mov r0, r2 + 8000204: 4770 bx lr + 8000206: e7ff b.n 8000208 <__udivsi3+0x100> + 8000208: b501 push {r0, lr} + 800020a: 2000 movs r0, #0 + 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> + 8000210: bd02 pop {r1, pc} + 8000212: 46c0 nop @ (mov r8, r8) + +08000214 <__aeabi_uidivmod>: + 8000214: 2900 cmp r1, #0 + 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> + 8000218: e776 b.n 8000108 <__udivsi3> + 800021a: 4770 bx lr + +0800021c <__divsi3>: + 800021c: 4603 mov r3, r0 + 800021e: 430b orrs r3, r1 + 8000220: d47f bmi.n 8000322 <__divsi3+0x106> + 8000222: 2200 movs r2, #0 + 8000224: 0843 lsrs r3, r0, #1 + 8000226: 428b cmp r3, r1 + 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> + 800022a: 0903 lsrs r3, r0, #4 + 800022c: 428b cmp r3, r1 + 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> + 8000230: 0a03 lsrs r3, r0, #8 + 8000232: 428b cmp r3, r1 + 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> + 8000236: 0b03 lsrs r3, r0, #12 + 8000238: 428b cmp r3, r1 + 800023a: d328 bcc.n 800028e <__divsi3+0x72> + 800023c: 0c03 lsrs r3, r0, #16 + 800023e: 428b cmp r3, r1 + 8000240: d30d bcc.n 800025e <__divsi3+0x42> + 8000242: 22ff movs r2, #255 @ 0xff + 8000244: 0209 lsls r1, r1, #8 + 8000246: ba12 rev r2, r2 + 8000248: 0c03 lsrs r3, r0, #16 + 800024a: 428b cmp r3, r1 + 800024c: d302 bcc.n 8000254 <__divsi3+0x38> + 800024e: 1212 asrs r2, r2, #8 + 8000250: 0209 lsls r1, r1, #8 + 8000252: d065 beq.n 8000320 <__divsi3+0x104> + 8000254: 0b03 lsrs r3, r0, #12 + 8000256: 428b cmp r3, r1 + 8000258: d319 bcc.n 800028e <__divsi3+0x72> + 800025a: e000 b.n 800025e <__divsi3+0x42> + 800025c: 0a09 lsrs r1, r1, #8 + 800025e: 0bc3 lsrs r3, r0, #15 + 8000260: 428b cmp r3, r1 + 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> + 8000264: 03cb lsls r3, r1, #15 + 8000266: 1ac0 subs r0, r0, r3 + 8000268: 4152 adcs r2, r2 + 800026a: 0b83 lsrs r3, r0, #14 + 800026c: 428b cmp r3, r1 + 800026e: d301 bcc.n 8000274 <__divsi3+0x58> + 8000270: 038b lsls r3, r1, #14 + 8000272: 1ac0 subs r0, r0, r3 + 8000274: 4152 adcs r2, r2 + 8000276: 0b43 lsrs r3, r0, #13 + 8000278: 428b cmp r3, r1 + 800027a: d301 bcc.n 8000280 <__divsi3+0x64> + 800027c: 034b lsls r3, r1, #13 + 800027e: 1ac0 subs r0, r0, r3 + 8000280: 4152 adcs r2, r2 + 8000282: 0b03 lsrs r3, r0, #12 + 8000284: 428b cmp r3, r1 + 8000286: d301 bcc.n 800028c <__divsi3+0x70> + 8000288: 030b lsls r3, r1, #12 + 800028a: 1ac0 subs r0, r0, r3 + 800028c: 4152 adcs r2, r2 + 800028e: 0ac3 lsrs r3, r0, #11 + 8000290: 428b cmp r3, r1 + 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> + 8000294: 02cb lsls r3, r1, #11 + 8000296: 1ac0 subs r0, r0, r3 + 8000298: 4152 adcs r2, r2 + 800029a: 0a83 lsrs r3, r0, #10 + 800029c: 428b cmp r3, r1 + 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> + 80002a0: 028b lsls r3, r1, #10 + 80002a2: 1ac0 subs r0, r0, r3 + 80002a4: 4152 adcs r2, r2 + 80002a6: 0a43 lsrs r3, r0, #9 + 80002a8: 428b cmp r3, r1 + 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> + 80002ac: 024b lsls r3, r1, #9 + 80002ae: 1ac0 subs r0, r0, r3 + 80002b0: 4152 adcs r2, r2 + 80002b2: 0a03 lsrs r3, r0, #8 + 80002b4: 428b cmp r3, r1 + 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> + 80002b8: 020b lsls r3, r1, #8 + 80002ba: 1ac0 subs r0, r0, r3 + 80002bc: 4152 adcs r2, r2 + 80002be: d2cd bcs.n 800025c <__divsi3+0x40> + 80002c0: 09c3 lsrs r3, r0, #7 + 80002c2: 428b cmp r3, r1 + 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> + 80002c6: 01cb lsls r3, r1, #7 + 80002c8: 1ac0 subs r0, r0, r3 + 80002ca: 4152 adcs r2, r2 + 80002cc: 0983 lsrs r3, r0, #6 + 80002ce: 428b cmp r3, r1 + 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> + 80002d2: 018b lsls r3, r1, #6 + 80002d4: 1ac0 subs r0, r0, r3 + 80002d6: 4152 adcs r2, r2 + 80002d8: 0943 lsrs r3, r0, #5 + 80002da: 428b cmp r3, r1 + 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> + 80002de: 014b lsls r3, r1, #5 + 80002e0: 1ac0 subs r0, r0, r3 + 80002e2: 4152 adcs r2, r2 + 80002e4: 0903 lsrs r3, r0, #4 + 80002e6: 428b cmp r3, r1 + 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> + 80002ea: 010b lsls r3, r1, #4 + 80002ec: 1ac0 subs r0, r0, r3 + 80002ee: 4152 adcs r2, r2 + 80002f0: 08c3 lsrs r3, r0, #3 + 80002f2: 428b cmp r3, r1 + 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> + 80002f6: 00cb lsls r3, r1, #3 + 80002f8: 1ac0 subs r0, r0, r3 + 80002fa: 4152 adcs r2, r2 + 80002fc: 0883 lsrs r3, r0, #2 + 80002fe: 428b cmp r3, r1 + 8000300: d301 bcc.n 8000306 <__divsi3+0xea> + 8000302: 008b lsls r3, r1, #2 + 8000304: 1ac0 subs r0, r0, r3 + 8000306: 4152 adcs r2, r2 + 8000308: 0843 lsrs r3, r0, #1 + 800030a: 428b cmp r3, r1 + 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> + 800030e: 004b lsls r3, r1, #1 + 8000310: 1ac0 subs r0, r0, r3 + 8000312: 4152 adcs r2, r2 + 8000314: 1a41 subs r1, r0, r1 + 8000316: d200 bcs.n 800031a <__divsi3+0xfe> + 8000318: 4601 mov r1, r0 + 800031a: 4152 adcs r2, r2 + 800031c: 4610 mov r0, r2 + 800031e: 4770 bx lr + 8000320: e05d b.n 80003de <__divsi3+0x1c2> + 8000322: 0fca lsrs r2, r1, #31 + 8000324: d000 beq.n 8000328 <__divsi3+0x10c> + 8000326: 4249 negs r1, r1 + 8000328: 1003 asrs r3, r0, #32 + 800032a: d300 bcc.n 800032e <__divsi3+0x112> + 800032c: 4240 negs r0, r0 + 800032e: 4053 eors r3, r2 + 8000330: 2200 movs r2, #0 + 8000332: 469c mov ip, r3 + 8000334: 0903 lsrs r3, r0, #4 + 8000336: 428b cmp r3, r1 + 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> + 800033a: 0a03 lsrs r3, r0, #8 + 800033c: 428b cmp r3, r1 + 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> + 8000340: 22fc movs r2, #252 @ 0xfc + 8000342: 0189 lsls r1, r1, #6 + 8000344: ba12 rev r2, r2 + 8000346: 0a03 lsrs r3, r0, #8 + 8000348: 428b cmp r3, r1 + 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> + 800034c: 0189 lsls r1, r1, #6 + 800034e: 1192 asrs r2, r2, #6 + 8000350: 428b cmp r3, r1 + 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> + 8000354: 0189 lsls r1, r1, #6 + 8000356: 1192 asrs r2, r2, #6 + 8000358: 428b cmp r3, r1 + 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> + 800035c: 0189 lsls r1, r1, #6 + 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> + 8000360: 1192 asrs r2, r2, #6 + 8000362: e000 b.n 8000366 <__divsi3+0x14a> + 8000364: 0989 lsrs r1, r1, #6 + 8000366: 09c3 lsrs r3, r0, #7 + 8000368: 428b cmp r3, r1 + 800036a: d301 bcc.n 8000370 <__divsi3+0x154> + 800036c: 01cb lsls r3, r1, #7 + 800036e: 1ac0 subs r0, r0, r3 + 8000370: 4152 adcs r2, r2 + 8000372: 0983 lsrs r3, r0, #6 + 8000374: 428b cmp r3, r1 + 8000376: d301 bcc.n 800037c <__divsi3+0x160> + 8000378: 018b lsls r3, r1, #6 + 800037a: 1ac0 subs r0, r0, r3 + 800037c: 4152 adcs r2, r2 + 800037e: 0943 lsrs r3, r0, #5 + 8000380: 428b cmp r3, r1 + 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> + 8000384: 014b lsls r3, r1, #5 + 8000386: 1ac0 subs r0, r0, r3 + 8000388: 4152 adcs r2, r2 + 800038a: 0903 lsrs r3, r0, #4 + 800038c: 428b cmp r3, r1 + 800038e: d301 bcc.n 8000394 <__divsi3+0x178> + 8000390: 010b lsls r3, r1, #4 + 8000392: 1ac0 subs r0, r0, r3 + 8000394: 4152 adcs r2, r2 + 8000396: 08c3 lsrs r3, r0, #3 + 8000398: 428b cmp r3, r1 + 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> + 800039c: 00cb lsls r3, r1, #3 + 800039e: 1ac0 subs r0, r0, r3 + 80003a0: 4152 adcs r2, r2 + 80003a2: 0883 lsrs r3, r0, #2 + 80003a4: 428b cmp r3, r1 + 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> + 80003a8: 008b lsls r3, r1, #2 + 80003aa: 1ac0 subs r0, r0, r3 + 80003ac: 4152 adcs r2, r2 + 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> + 80003b0: 0843 lsrs r3, r0, #1 + 80003b2: 428b cmp r3, r1 + 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> + 80003b6: 004b lsls r3, r1, #1 + 80003b8: 1ac0 subs r0, r0, r3 + 80003ba: 4152 adcs r2, r2 + 80003bc: 1a41 subs r1, r0, r1 + 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> + 80003c0: 4601 mov r1, r0 + 80003c2: 4663 mov r3, ip + 80003c4: 4152 adcs r2, r2 + 80003c6: 105b asrs r3, r3, #1 + 80003c8: 4610 mov r0, r2 + 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> + 80003cc: 4240 negs r0, r0 + 80003ce: 2b00 cmp r3, #0 + 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> + 80003d2: 4249 negs r1, r1 + 80003d4: 4770 bx lr + 80003d6: 4663 mov r3, ip + 80003d8: 105b asrs r3, r3, #1 + 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> + 80003dc: 4240 negs r0, r0 + 80003de: b501 push {r0, lr} + 80003e0: 2000 movs r0, #0 + 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> + 80003e6: bd02 pop {r1, pc} + +080003e8 <__aeabi_idivmod>: + 80003e8: 2900 cmp r1, #0 + 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> + 80003ec: e716 b.n 800021c <__divsi3> + 80003ee: 4770 bx lr + +080003f0 <__aeabi_idiv0>: + 80003f0: 4770 bx lr + 80003f2: 46c0 nop @ (mov r8, r8) + +080003f4 <__aeabi_cfrcmple>: + 80003f4: 4684 mov ip, r0 + 80003f6: 0008 movs r0, r1 + 80003f8: 4661 mov r1, ip + 80003fa: e7ff b.n 80003fc <__aeabi_cfcmpeq> + +080003fc <__aeabi_cfcmpeq>: + 80003fc: b51f push {r0, r1, r2, r3, r4, lr} + 80003fe: f000 fbfd bl 8000bfc <__lesf2> + 8000402: 2800 cmp r0, #0 + 8000404: d401 bmi.n 800040a <__aeabi_cfcmpeq+0xe> + 8000406: 2100 movs r1, #0 + 8000408: 42c8 cmn r0, r1 + 800040a: bd1f pop {r0, r1, r2, r3, r4, pc} + +0800040c <__aeabi_fcmpeq>: + 800040c: b510 push {r4, lr} + 800040e: f000 fb85 bl 8000b1c <__eqsf2> + 8000412: 4240 negs r0, r0 + 8000414: 3001 adds r0, #1 + 8000416: bd10 pop {r4, pc} + +08000418 <__aeabi_fcmplt>: + 8000418: b510 push {r4, lr} + 800041a: f000 fbef bl 8000bfc <__lesf2> + 800041e: 2800 cmp r0, #0 + 8000420: db01 blt.n 8000426 <__aeabi_fcmplt+0xe> + 8000422: 2000 movs r0, #0 + 8000424: bd10 pop {r4, pc} + 8000426: 2001 movs r0, #1 + 8000428: bd10 pop {r4, pc} + 800042a: 46c0 nop @ (mov r8, r8) + +0800042c <__aeabi_fcmple>: + 800042c: b510 push {r4, lr} + 800042e: f000 fbe5 bl 8000bfc <__lesf2> + 8000432: 2800 cmp r0, #0 + 8000434: dd01 ble.n 800043a <__aeabi_fcmple+0xe> + 8000436: 2000 movs r0, #0 + 8000438: bd10 pop {r4, pc} + 800043a: 2001 movs r0, #1 + 800043c: bd10 pop {r4, pc} + 800043e: 46c0 nop @ (mov r8, r8) + +08000440 <__aeabi_fcmpgt>: + 8000440: b510 push {r4, lr} + 8000442: f000 fb93 bl 8000b6c <__gesf2> + 8000446: 2800 cmp r0, #0 + 8000448: dc01 bgt.n 800044e <__aeabi_fcmpgt+0xe> + 800044a: 2000 movs r0, #0 + 800044c: bd10 pop {r4, pc} + 800044e: 2001 movs r0, #1 + 8000450: bd10 pop {r4, pc} + 8000452: 46c0 nop @ (mov r8, r8) + +08000454 <__aeabi_fcmpge>: + 8000454: b510 push {r4, lr} + 8000456: f000 fb89 bl 8000b6c <__gesf2> + 800045a: 2800 cmp r0, #0 + 800045c: da01 bge.n 8000462 <__aeabi_fcmpge+0xe> + 800045e: 2000 movs r0, #0 + 8000460: bd10 pop {r4, pc} + 8000462: 2001 movs r0, #1 + 8000464: bd10 pop {r4, pc} + 8000466: 46c0 nop @ (mov r8, r8) + +08000468 <__aeabi_f2uiz>: + 8000468: 219e movs r1, #158 @ 0x9e + 800046a: b510 push {r4, lr} + 800046c: 05c9 lsls r1, r1, #23 + 800046e: 1c04 adds r4, r0, #0 + 8000470: f7ff fff0 bl 8000454 <__aeabi_fcmpge> + 8000474: 2800 cmp r0, #0 + 8000476: d103 bne.n 8000480 <__aeabi_f2uiz+0x18> + 8000478: 1c20 adds r0, r4, #0 + 800047a: f000 ff9b bl 80013b4 <__aeabi_f2iz> + 800047e: bd10 pop {r4, pc} + 8000480: 219e movs r1, #158 @ 0x9e + 8000482: 1c20 adds r0, r4, #0 + 8000484: 05c9 lsls r1, r1, #23 + 8000486: f000 fd53 bl 8000f30 <__aeabi_fsub> + 800048a: f000 ff93 bl 80013b4 <__aeabi_f2iz> + 800048e: 2380 movs r3, #128 @ 0x80 + 8000490: 061b lsls r3, r3, #24 + 8000492: 469c mov ip, r3 + 8000494: 4460 add r0, ip + 8000496: e7f2 b.n 800047e <__aeabi_f2uiz+0x16> + +08000498 <__aeabi_d2uiz>: + 8000498: b570 push {r4, r5, r6, lr} + 800049a: 2200 movs r2, #0 + 800049c: 4b0c ldr r3, [pc, #48] @ (80004d0 <__aeabi_d2uiz+0x38>) + 800049e: 0004 movs r4, r0 + 80004a0: 000d movs r5, r1 + 80004a2: f001 ffdb bl 800245c <__aeabi_dcmpge> + 80004a6: 2800 cmp r0, #0 + 80004a8: d104 bne.n 80004b4 <__aeabi_d2uiz+0x1c> + 80004aa: 0020 movs r0, r4 + 80004ac: 0029 movs r1, r5 + 80004ae: f001 ff37 bl 8002320 <__aeabi_d2iz> + 80004b2: bd70 pop {r4, r5, r6, pc} + 80004b4: 4b06 ldr r3, [pc, #24] @ (80004d0 <__aeabi_d2uiz+0x38>) + 80004b6: 2200 movs r2, #0 + 80004b8: 0020 movs r0, r4 + 80004ba: 0029 movs r1, r5 + 80004bc: f001 faf8 bl 8001ab0 <__aeabi_dsub> + 80004c0: f001 ff2e bl 8002320 <__aeabi_d2iz> + 80004c4: 2380 movs r3, #128 @ 0x80 + 80004c6: 061b lsls r3, r3, #24 + 80004c8: 469c mov ip, r3 + 80004ca: 4460 add r0, ip + 80004cc: e7f1 b.n 80004b2 <__aeabi_d2uiz+0x1a> + 80004ce: 46c0 nop @ (mov r8, r8) + 80004d0: 41e00000 .word 0x41e00000 + +080004d4 <__aeabi_fadd>: + 80004d4: 024a lsls r2, r1, #9 + 80004d6: b5f8 push {r3, r4, r5, r6, r7, lr} + 80004d8: 0a53 lsrs r3, r2, #9 + 80004da: 46ce mov lr, r9 + 80004dc: 4699 mov r9, r3 + 80004de: 004b lsls r3, r1, #1 + 80004e0: 0fc9 lsrs r1, r1, #31 + 80004e2: 4647 mov r7, r8 + 80004e4: 4688 mov r8, r1 + 80004e6: 0046 lsls r6, r0, #1 + 80004e8: 0245 lsls r5, r0, #9 + 80004ea: 0e36 lsrs r6, r6, #24 + 80004ec: 0e1b lsrs r3, r3, #24 + 80004ee: b580 push {r7, lr} + 80004f0: 0fc4 lsrs r4, r0, #31 + 80004f2: 0a6f lsrs r7, r5, #9 + 80004f4: 0992 lsrs r2, r2, #6 + 80004f6: 09ad lsrs r5, r5, #6 + 80004f8: 1af1 subs r1, r6, r3 + 80004fa: 4544 cmp r4, r8 + 80004fc: d04b beq.n 8000596 <__aeabi_fadd+0xc2> + 80004fe: 2900 cmp r1, #0 + 8000500: dd38 ble.n 8000574 <__aeabi_fadd+0xa0> + 8000502: 2b00 cmp r3, #0 + 8000504: d100 bne.n 8000508 <__aeabi_fadd+0x34> + 8000506: e074 b.n 80005f2 <__aeabi_fadd+0x11e> + 8000508: 2eff cmp r6, #255 @ 0xff + 800050a: d100 bne.n 800050e <__aeabi_fadd+0x3a> + 800050c: e0be b.n 800068c <__aeabi_fadd+0x1b8> + 800050e: 2380 movs r3, #128 @ 0x80 + 8000510: 04db lsls r3, r3, #19 + 8000512: 431a orrs r2, r3 + 8000514: 291b cmp r1, #27 + 8000516: dc00 bgt.n 800051a <__aeabi_fadd+0x46> + 8000518: e0fd b.n 8000716 <__aeabi_fadd+0x242> + 800051a: 3d01 subs r5, #1 + 800051c: 016b lsls r3, r5, #5 + 800051e: d400 bmi.n 8000522 <__aeabi_fadd+0x4e> + 8000520: e0af b.n 8000682 <__aeabi_fadd+0x1ae> + 8000522: 2501 movs r5, #1 + 8000524: 426d negs r5, r5 + 8000526: 01ad lsls r5, r5, #6 + 8000528: 09af lsrs r7, r5, #6 + 800052a: 0038 movs r0, r7 + 800052c: f001 ffa0 bl 8002470 <__clzsi2> + 8000530: 003b movs r3, r7 + 8000532: 3805 subs r0, #5 + 8000534: 4083 lsls r3, r0 + 8000536: 4286 cmp r6, r0 + 8000538: dc00 bgt.n 800053c <__aeabi_fadd+0x68> + 800053a: e0d3 b.n 80006e4 <__aeabi_fadd+0x210> + 800053c: 4db9 ldr r5, [pc, #740] @ (8000824 <__aeabi_fadd+0x350>) + 800053e: 1a31 subs r1, r6, r0 + 8000540: 401d ands r5, r3 + 8000542: 075a lsls r2, r3, #29 + 8000544: d100 bne.n 8000548 <__aeabi_fadd+0x74> + 8000546: e09e b.n 8000686 <__aeabi_fadd+0x1b2> + 8000548: 220f movs r2, #15 + 800054a: 4013 ands r3, r2 + 800054c: 2b04 cmp r3, #4 + 800054e: d100 bne.n 8000552 <__aeabi_fadd+0x7e> + 8000550: e099 b.n 8000686 <__aeabi_fadd+0x1b2> + 8000552: 3504 adds r5, #4 + 8000554: 016b lsls r3, r5, #5 + 8000556: d400 bmi.n 800055a <__aeabi_fadd+0x86> + 8000558: e095 b.n 8000686 <__aeabi_fadd+0x1b2> + 800055a: 1c48 adds r0, r1, #1 + 800055c: 29fe cmp r1, #254 @ 0xfe + 800055e: d151 bne.n 8000604 <__aeabi_fadd+0x130> + 8000560: 20ff movs r0, #255 @ 0xff + 8000562: 2300 movs r3, #0 + 8000564: 05c0 lsls r0, r0, #23 + 8000566: 4318 orrs r0, r3 + 8000568: 07e4 lsls r4, r4, #31 + 800056a: 4320 orrs r0, r4 + 800056c: bcc0 pop {r6, r7} + 800056e: 46b9 mov r9, r7 + 8000570: 46b0 mov r8, r6 + 8000572: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8000574: 2900 cmp r1, #0 + 8000576: d049 beq.n 800060c <__aeabi_fadd+0x138> + 8000578: 1b99 subs r1, r3, r6 + 800057a: 2e00 cmp r6, #0 + 800057c: d172 bne.n 8000664 <__aeabi_fadd+0x190> + 800057e: 2d00 cmp r5, #0 + 8000580: d100 bne.n 8000584 <__aeabi_fadd+0xb0> + 8000582: e133 b.n 80007ec <__aeabi_fadd+0x318> + 8000584: 1e4c subs r4, r1, #1 + 8000586: 2901 cmp r1, #1 + 8000588: d100 bne.n 800058c <__aeabi_fadd+0xb8> + 800058a: e159 b.n 8000840 <__aeabi_fadd+0x36c> + 800058c: 29ff cmp r1, #255 @ 0xff + 800058e: d100 bne.n 8000592 <__aeabi_fadd+0xbe> + 8000590: e14c b.n 800082c <__aeabi_fadd+0x358> + 8000592: 0021 movs r1, r4 + 8000594: e06c b.n 8000670 <__aeabi_fadd+0x19c> + 8000596: 2900 cmp r1, #0 + 8000598: dc00 bgt.n 800059c <__aeabi_fadd+0xc8> + 800059a: e081 b.n 80006a0 <__aeabi_fadd+0x1cc> + 800059c: 2b00 cmp r3, #0 + 800059e: d155 bne.n 800064c <__aeabi_fadd+0x178> + 80005a0: 2a00 cmp r2, #0 + 80005a2: d070 beq.n 8000686 <__aeabi_fadd+0x1b2> + 80005a4: 1e4b subs r3, r1, #1 + 80005a6: 2901 cmp r1, #1 + 80005a8: d100 bne.n 80005ac <__aeabi_fadd+0xd8> + 80005aa: e12b b.n 8000804 <__aeabi_fadd+0x330> + 80005ac: 29ff cmp r1, #255 @ 0xff + 80005ae: d06d beq.n 800068c <__aeabi_fadd+0x1b8> + 80005b0: 2b1b cmp r3, #27 + 80005b2: dc50 bgt.n 8000656 <__aeabi_fadd+0x182> + 80005b4: 0019 movs r1, r3 + 80005b6: 2320 movs r3, #32 + 80005b8: 1a5b subs r3, r3, r1 + 80005ba: 0010 movs r0, r2 + 80005bc: 409a lsls r2, r3 + 80005be: 40c8 lsrs r0, r1 + 80005c0: 1e53 subs r3, r2, #1 + 80005c2: 419a sbcs r2, r3 + 80005c4: 4302 orrs r2, r0 + 80005c6: 18ad adds r5, r5, r2 + 80005c8: 2380 movs r3, #128 @ 0x80 + 80005ca: 04db lsls r3, r3, #19 + 80005cc: 421d tst r5, r3 + 80005ce: d100 bne.n 80005d2 <__aeabi_fadd+0xfe> + 80005d0: e0ad b.n 800072e <__aeabi_fadd+0x25a> + 80005d2: 1c71 adds r1, r6, #1 + 80005d4: 2efe cmp r6, #254 @ 0xfe + 80005d6: d0c3 beq.n 8000560 <__aeabi_fadd+0x8c> + 80005d8: 2001 movs r0, #1 + 80005da: 086a lsrs r2, r5, #1 + 80005dc: 4028 ands r0, r5 + 80005de: 4d92 ldr r5, [pc, #584] @ (8000828 <__aeabi_fadd+0x354>) + 80005e0: 4015 ands r5, r2 + 80005e2: 4305 orrs r5, r0 + 80005e4: 076a lsls r2, r5, #29 + 80005e6: d000 beq.n 80005ea <__aeabi_fadd+0x116> + 80005e8: e08b b.n 8000702 <__aeabi_fadd+0x22e> + 80005ea: 421d tst r5, r3 + 80005ec: d1b5 bne.n 800055a <__aeabi_fadd+0x86> + 80005ee: 08ef lsrs r7, r5, #3 + 80005f0: e034 b.n 800065c <__aeabi_fadd+0x188> + 80005f2: 2a00 cmp r2, #0 + 80005f4: d047 beq.n 8000686 <__aeabi_fadd+0x1b2> + 80005f6: 1e4b subs r3, r1, #1 + 80005f8: 2901 cmp r1, #1 + 80005fa: d066 beq.n 80006ca <__aeabi_fadd+0x1f6> + 80005fc: 29ff cmp r1, #255 @ 0xff + 80005fe: d045 beq.n 800068c <__aeabi_fadd+0x1b8> + 8000600: 0019 movs r1, r3 + 8000602: e787 b.n 8000514 <__aeabi_fadd+0x40> + 8000604: b2c0 uxtb r0, r0 + 8000606: 01ab lsls r3, r5, #6 + 8000608: 0a5b lsrs r3, r3, #9 + 800060a: e7ab b.n 8000564 <__aeabi_fadd+0x90> + 800060c: 23fe movs r3, #254 @ 0xfe + 800060e: 469c mov ip, r3 + 8000610: 1c70 adds r0, r6, #1 + 8000612: 0003 movs r3, r0 + 8000614: 4660 mov r0, ip + 8000616: 4218 tst r0, r3 + 8000618: d000 beq.n 800061c <__aeabi_fadd+0x148> + 800061a: e092 b.n 8000742 <__aeabi_fadd+0x26e> + 800061c: 2e00 cmp r6, #0 + 800061e: d000 beq.n 8000622 <__aeabi_fadd+0x14e> + 8000620: e0e7 b.n 80007f2 <__aeabi_fadd+0x31e> + 8000622: 2d00 cmp r5, #0 + 8000624: d100 bne.n 8000628 <__aeabi_fadd+0x154> + 8000626: e119 b.n 800085c <__aeabi_fadd+0x388> + 8000628: 2a00 cmp r2, #0 + 800062a: d017 beq.n 800065c <__aeabi_fadd+0x188> + 800062c: 2380 movs r3, #128 @ 0x80 + 800062e: 1aaf subs r7, r5, r2 + 8000630: 04db lsls r3, r3, #19 + 8000632: 421f tst r7, r3 + 8000634: d100 bne.n 8000638 <__aeabi_fadd+0x164> + 8000636: e142 b.n 80008be <__aeabi_fadd+0x3ea> + 8000638: 4644 mov r4, r8 + 800063a: 1b55 subs r5, r2, r5 + 800063c: d100 bne.n 8000640 <__aeabi_fadd+0x16c> + 800063e: e087 b.n 8000750 <__aeabi_fadd+0x27c> + 8000640: 2001 movs r0, #1 + 8000642: 421d tst r5, r3 + 8000644: d1df bne.n 8000606 <__aeabi_fadd+0x132> + 8000646: 2100 movs r1, #0 + 8000648: 08ef lsrs r7, r5, #3 + 800064a: e007 b.n 800065c <__aeabi_fadd+0x188> + 800064c: 2eff cmp r6, #255 @ 0xff + 800064e: d01d beq.n 800068c <__aeabi_fadd+0x1b8> + 8000650: 291b cmp r1, #27 + 8000652: dc00 bgt.n 8000656 <__aeabi_fadd+0x182> + 8000654: e094 b.n 8000780 <__aeabi_fadd+0x2ac> + 8000656: 0031 movs r1, r6 + 8000658: 3505 adds r5, #5 + 800065a: 08ef lsrs r7, r5, #3 + 800065c: 027b lsls r3, r7, #9 + 800065e: 0a5b lsrs r3, r3, #9 + 8000660: b2c8 uxtb r0, r1 + 8000662: e77f b.n 8000564 <__aeabi_fadd+0x90> + 8000664: 2bff cmp r3, #255 @ 0xff + 8000666: d100 bne.n 800066a <__aeabi_fadd+0x196> + 8000668: e0e0 b.n 800082c <__aeabi_fadd+0x358> + 800066a: 2080 movs r0, #128 @ 0x80 + 800066c: 04c0 lsls r0, r0, #19 + 800066e: 4305 orrs r5, r0 + 8000670: 291b cmp r1, #27 + 8000672: dc00 bgt.n 8000676 <__aeabi_fadd+0x1a2> + 8000674: e088 b.n 8000788 <__aeabi_fadd+0x2b4> + 8000676: 1e55 subs r5, r2, #1 + 8000678: 4644 mov r4, r8 + 800067a: 001e movs r6, r3 + 800067c: 0169 lsls r1, r5, #5 + 800067e: d500 bpl.n 8000682 <__aeabi_fadd+0x1ae> + 8000680: e74f b.n 8000522 <__aeabi_fadd+0x4e> + 8000682: 0031 movs r1, r6 + 8000684: 3504 adds r5, #4 + 8000686: 08ef lsrs r7, r5, #3 + 8000688: 29ff cmp r1, #255 @ 0xff + 800068a: d1e7 bne.n 800065c <__aeabi_fadd+0x188> + 800068c: 2f00 cmp r7, #0 + 800068e: d100 bne.n 8000692 <__aeabi_fadd+0x1be> + 8000690: e766 b.n 8000560 <__aeabi_fadd+0x8c> + 8000692: 2380 movs r3, #128 @ 0x80 + 8000694: 03db lsls r3, r3, #15 + 8000696: 433b orrs r3, r7 + 8000698: 025b lsls r3, r3, #9 + 800069a: 20ff movs r0, #255 @ 0xff + 800069c: 0a5b lsrs r3, r3, #9 + 800069e: e761 b.n 8000564 <__aeabi_fadd+0x90> + 80006a0: 2900 cmp r1, #0 + 80006a2: d058 beq.n 8000756 <__aeabi_fadd+0x282> + 80006a4: 1b99 subs r1, r3, r6 + 80006a6: 2e00 cmp r6, #0 + 80006a8: d000 beq.n 80006ac <__aeabi_fadd+0x1d8> + 80006aa: e089 b.n 80007c0 <__aeabi_fadd+0x2ec> + 80006ac: 2d00 cmp r5, #0 + 80006ae: d100 bne.n 80006b2 <__aeabi_fadd+0x1de> + 80006b0: e09d b.n 80007ee <__aeabi_fadd+0x31a> + 80006b2: 1e4e subs r6, r1, #1 + 80006b4: 2901 cmp r1, #1 + 80006b6: d100 bne.n 80006ba <__aeabi_fadd+0x1e6> + 80006b8: e0a4 b.n 8000804 <__aeabi_fadd+0x330> + 80006ba: 29ff cmp r1, #255 @ 0xff + 80006bc: d100 bne.n 80006c0 <__aeabi_fadd+0x1ec> + 80006be: e0b6 b.n 800082e <__aeabi_fadd+0x35a> + 80006c0: 2e1b cmp r6, #27 + 80006c2: dd00 ble.n 80006c6 <__aeabi_fadd+0x1f2> + 80006c4: e0b8 b.n 8000838 <__aeabi_fadd+0x364> + 80006c6: 0031 movs r1, r6 + 80006c8: e081 b.n 80007ce <__aeabi_fadd+0x2fa> + 80006ca: 1aaa subs r2, r5, r2 + 80006cc: 0153 lsls r3, r2, #5 + 80006ce: d400 bmi.n 80006d2 <__aeabi_fadd+0x1fe> + 80006d0: e0af b.n 8000832 <__aeabi_fadd+0x35e> + 80006d2: 0197 lsls r7, r2, #6 + 80006d4: 09bf lsrs r7, r7, #6 + 80006d6: 0038 movs r0, r7 + 80006d8: f001 feca bl 8002470 <__clzsi2> + 80006dc: 003b movs r3, r7 + 80006de: 3805 subs r0, #5 + 80006e0: 4083 lsls r3, r0 + 80006e2: 2601 movs r6, #1 + 80006e4: 001d movs r5, r3 + 80006e6: 1b81 subs r1, r0, r6 + 80006e8: 2020 movs r0, #32 + 80006ea: 3101 adds r1, #1 + 80006ec: 40cd lsrs r5, r1 + 80006ee: 1a41 subs r1, r0, r1 + 80006f0: 408b lsls r3, r1 + 80006f2: 1e59 subs r1, r3, #1 + 80006f4: 418b sbcs r3, r1 + 80006f6: 431d orrs r5, r3 + 80006f8: d02a beq.n 8000750 <__aeabi_fadd+0x27c> + 80006fa: 2100 movs r1, #0 + 80006fc: 076b lsls r3, r5, #29 + 80006fe: d100 bne.n 8000702 <__aeabi_fadd+0x22e> + 8000700: e0f0 b.n 80008e4 <__aeabi_fadd+0x410> + 8000702: 230f movs r3, #15 + 8000704: 402b ands r3, r5 + 8000706: 2b04 cmp r3, #4 + 8000708: d000 beq.n 800070c <__aeabi_fadd+0x238> + 800070a: e722 b.n 8000552 <__aeabi_fadd+0x7e> + 800070c: 016b lsls r3, r5, #5 + 800070e: d500 bpl.n 8000712 <__aeabi_fadd+0x23e> + 8000710: e723 b.n 800055a <__aeabi_fadd+0x86> + 8000712: 08ef lsrs r7, r5, #3 + 8000714: e7a2 b.n 800065c <__aeabi_fadd+0x188> + 8000716: 2320 movs r3, #32 + 8000718: 1a5b subs r3, r3, r1 + 800071a: 0010 movs r0, r2 + 800071c: 409a lsls r2, r3 + 800071e: 40c8 lsrs r0, r1 + 8000720: 1e53 subs r3, r2, #1 + 8000722: 419a sbcs r2, r3 + 8000724: 4302 orrs r2, r0 + 8000726: 1aad subs r5, r5, r2 + 8000728: 016b lsls r3, r5, #5 + 800072a: d500 bpl.n 800072e <__aeabi_fadd+0x25a> + 800072c: e6fb b.n 8000526 <__aeabi_fadd+0x52> + 800072e: 076b lsls r3, r5, #29 + 8000730: d100 bne.n 8000734 <__aeabi_fadd+0x260> + 8000732: e0d5 b.n 80008e0 <__aeabi_fadd+0x40c> + 8000734: 230f movs r3, #15 + 8000736: 0031 movs r1, r6 + 8000738: 402b ands r3, r5 + 800073a: 2b04 cmp r3, #4 + 800073c: d000 beq.n 8000740 <__aeabi_fadd+0x26c> + 800073e: e708 b.n 8000552 <__aeabi_fadd+0x7e> + 8000740: e7a1 b.n 8000686 <__aeabi_fadd+0x1b2> + 8000742: 1aaf subs r7, r5, r2 + 8000744: 017b lsls r3, r7, #5 + 8000746: d44e bmi.n 80007e6 <__aeabi_fadd+0x312> + 8000748: 2f00 cmp r7, #0 + 800074a: d000 beq.n 800074e <__aeabi_fadd+0x27a> + 800074c: e6ed b.n 800052a <__aeabi_fadd+0x56> + 800074e: 2400 movs r4, #0 + 8000750: 2000 movs r0, #0 + 8000752: 2300 movs r3, #0 + 8000754: e706 b.n 8000564 <__aeabi_fadd+0x90> + 8000756: 23fe movs r3, #254 @ 0xfe + 8000758: 1c71 adds r1, r6, #1 + 800075a: 420b tst r3, r1 + 800075c: d121 bne.n 80007a2 <__aeabi_fadd+0x2ce> + 800075e: 2e00 cmp r6, #0 + 8000760: d000 beq.n 8000764 <__aeabi_fadd+0x290> + 8000762: e081 b.n 8000868 <__aeabi_fadd+0x394> + 8000764: 2d00 cmp r5, #0 + 8000766: d100 bne.n 800076a <__aeabi_fadd+0x296> + 8000768: e09f b.n 80008aa <__aeabi_fadd+0x3d6> + 800076a: 2a00 cmp r2, #0 + 800076c: d100 bne.n 8000770 <__aeabi_fadd+0x29c> + 800076e: e0b2 b.n 80008d6 <__aeabi_fadd+0x402> + 8000770: 18ab adds r3, r5, r2 + 8000772: 015a lsls r2, r3, #5 + 8000774: d400 bmi.n 8000778 <__aeabi_fadd+0x2a4> + 8000776: e0b0 b.n 80008da <__aeabi_fadd+0x406> + 8000778: 019b lsls r3, r3, #6 + 800077a: 2001 movs r0, #1 + 800077c: 0a5b lsrs r3, r3, #9 + 800077e: e6f1 b.n 8000564 <__aeabi_fadd+0x90> + 8000780: 2380 movs r3, #128 @ 0x80 + 8000782: 04db lsls r3, r3, #19 + 8000784: 431a orrs r2, r3 + 8000786: e716 b.n 80005b6 <__aeabi_fadd+0xe2> + 8000788: 2420 movs r4, #32 + 800078a: 0028 movs r0, r5 + 800078c: 40c8 lsrs r0, r1 + 800078e: 1a61 subs r1, r4, r1 + 8000790: 408d lsls r5, r1 + 8000792: 0029 movs r1, r5 + 8000794: 1e4c subs r4, r1, #1 + 8000796: 41a1 sbcs r1, r4 + 8000798: 4301 orrs r1, r0 + 800079a: 4644 mov r4, r8 + 800079c: 001e movs r6, r3 + 800079e: 1a55 subs r5, r2, r1 + 80007a0: e7c2 b.n 8000728 <__aeabi_fadd+0x254> + 80007a2: 29ff cmp r1, #255 @ 0xff + 80007a4: d100 bne.n 80007a8 <__aeabi_fadd+0x2d4> + 80007a6: e6db b.n 8000560 <__aeabi_fadd+0x8c> + 80007a8: 18af adds r7, r5, r2 + 80007aa: 087f lsrs r7, r7, #1 + 80007ac: 077b lsls r3, r7, #29 + 80007ae: d005 beq.n 80007bc <__aeabi_fadd+0x2e8> + 80007b0: 230f movs r3, #15 + 80007b2: 1d3d adds r5, r7, #4 + 80007b4: 403b ands r3, r7 + 80007b6: 2b04 cmp r3, #4 + 80007b8: d000 beq.n 80007bc <__aeabi_fadd+0x2e8> + 80007ba: e764 b.n 8000686 <__aeabi_fadd+0x1b2> + 80007bc: 08ff lsrs r7, r7, #3 + 80007be: e74d b.n 800065c <__aeabi_fadd+0x188> + 80007c0: 2bff cmp r3, #255 @ 0xff + 80007c2: d034 beq.n 800082e <__aeabi_fadd+0x35a> + 80007c4: 291b cmp r1, #27 + 80007c6: dc37 bgt.n 8000838 <__aeabi_fadd+0x364> + 80007c8: 2080 movs r0, #128 @ 0x80 + 80007ca: 04c0 lsls r0, r0, #19 + 80007cc: 4305 orrs r5, r0 + 80007ce: 0028 movs r0, r5 + 80007d0: 2620 movs r6, #32 + 80007d2: 40c8 lsrs r0, r1 + 80007d4: 1a71 subs r1, r6, r1 + 80007d6: 408d lsls r5, r1 + 80007d8: 0029 movs r1, r5 + 80007da: 1e4d subs r5, r1, #1 + 80007dc: 41a9 sbcs r1, r5 + 80007de: 4301 orrs r1, r0 + 80007e0: 001e movs r6, r3 + 80007e2: 188d adds r5, r1, r2 + 80007e4: e6f0 b.n 80005c8 <__aeabi_fadd+0xf4> + 80007e6: 4644 mov r4, r8 + 80007e8: 1b57 subs r7, r2, r5 + 80007ea: e69e b.n 800052a <__aeabi_fadd+0x56> + 80007ec: 4644 mov r4, r8 + 80007ee: 0015 movs r5, r2 + 80007f0: e749 b.n 8000686 <__aeabi_fadd+0x1b2> + 80007f2: 2d00 cmp r5, #0 + 80007f4: d146 bne.n 8000884 <__aeabi_fadd+0x3b0> + 80007f6: 2a00 cmp r2, #0 + 80007f8: d166 bne.n 80008c8 <__aeabi_fadd+0x3f4> + 80007fa: 2380 movs r3, #128 @ 0x80 + 80007fc: 2400 movs r4, #0 + 80007fe: 20ff movs r0, #255 @ 0xff + 8000800: 03db lsls r3, r3, #15 + 8000802: e6af b.n 8000564 <__aeabi_fadd+0x90> + 8000804: 18aa adds r2, r5, r2 + 8000806: 0153 lsls r3, r2, #5 + 8000808: d513 bpl.n 8000832 <__aeabi_fadd+0x35e> + 800080a: 4f07 ldr r7, [pc, #28] @ (8000828 <__aeabi_fadd+0x354>) + 800080c: 0852 lsrs r2, r2, #1 + 800080e: 4017 ands r7, r2 + 8000810: 0753 lsls r3, r2, #29 + 8000812: d044 beq.n 800089e <__aeabi_fadd+0x3ca> + 8000814: 230f movs r3, #15 + 8000816: 4013 ands r3, r2 + 8000818: 2b04 cmp r3, #4 + 800081a: d040 beq.n 800089e <__aeabi_fadd+0x3ca> + 800081c: 2102 movs r1, #2 + 800081e: 1d3d adds r5, r7, #4 + 8000820: e731 b.n 8000686 <__aeabi_fadd+0x1b2> + 8000822: 46c0 nop @ (mov r8, r8) + 8000824: fbffffff .word 0xfbffffff + 8000828: 7dffffff .word 0x7dffffff + 800082c: 4644 mov r4, r8 + 800082e: 464f mov r7, r9 + 8000830: e72c b.n 800068c <__aeabi_fadd+0x1b8> + 8000832: 2101 movs r1, #1 + 8000834: 08d7 lsrs r7, r2, #3 + 8000836: e711 b.n 800065c <__aeabi_fadd+0x188> + 8000838: 3205 adds r2, #5 + 800083a: 0019 movs r1, r3 + 800083c: 08d7 lsrs r7, r2, #3 + 800083e: e70d b.n 800065c <__aeabi_fadd+0x188> + 8000840: 1b57 subs r7, r2, r5 + 8000842: 017b lsls r3, r7, #5 + 8000844: d537 bpl.n 80008b6 <__aeabi_fadd+0x3e2> + 8000846: 01bf lsls r7, r7, #6 + 8000848: 09bf lsrs r7, r7, #6 + 800084a: 0038 movs r0, r7 + 800084c: f001 fe10 bl 8002470 <__clzsi2> + 8000850: 003b movs r3, r7 + 8000852: 3805 subs r0, #5 + 8000854: 4083 lsls r3, r0 + 8000856: 4644 mov r4, r8 + 8000858: 3601 adds r6, #1 + 800085a: e743 b.n 80006e4 <__aeabi_fadd+0x210> + 800085c: 2a00 cmp r2, #0 + 800085e: d100 bne.n 8000862 <__aeabi_fadd+0x38e> + 8000860: e775 b.n 800074e <__aeabi_fadd+0x27a> + 8000862: 4644 mov r4, r8 + 8000864: 464f mov r7, r9 + 8000866: e6f9 b.n 800065c <__aeabi_fadd+0x188> + 8000868: 2d00 cmp r5, #0 + 800086a: d0e0 beq.n 800082e <__aeabi_fadd+0x35a> + 800086c: 2380 movs r3, #128 @ 0x80 + 800086e: 03db lsls r3, r3, #15 + 8000870: 2a00 cmp r2, #0 + 8000872: d017 beq.n 80008a4 <__aeabi_fadd+0x3d0> + 8000874: 429f cmp r7, r3 + 8000876: d200 bcs.n 800087a <__aeabi_fadd+0x3a6> + 8000878: e70b b.n 8000692 <__aeabi_fadd+0x1be> + 800087a: 4599 cmp r9, r3 + 800087c: d300 bcc.n 8000880 <__aeabi_fadd+0x3ac> + 800087e: e708 b.n 8000692 <__aeabi_fadd+0x1be> + 8000880: 464f mov r7, r9 + 8000882: e706 b.n 8000692 <__aeabi_fadd+0x1be> + 8000884: 2380 movs r3, #128 @ 0x80 + 8000886: 03db lsls r3, r3, #15 + 8000888: 2a00 cmp r2, #0 + 800088a: d00b beq.n 80008a4 <__aeabi_fadd+0x3d0> + 800088c: 429f cmp r7, r3 + 800088e: d200 bcs.n 8000892 <__aeabi_fadd+0x3be> + 8000890: e6ff b.n 8000692 <__aeabi_fadd+0x1be> + 8000892: 4599 cmp r9, r3 + 8000894: d300 bcc.n 8000898 <__aeabi_fadd+0x3c4> + 8000896: e6fc b.n 8000692 <__aeabi_fadd+0x1be> + 8000898: 4644 mov r4, r8 + 800089a: 464f mov r7, r9 + 800089c: e6f9 b.n 8000692 <__aeabi_fadd+0x1be> + 800089e: 2102 movs r1, #2 + 80008a0: 08ff lsrs r7, r7, #3 + 80008a2: e6db b.n 800065c <__aeabi_fadd+0x188> + 80008a4: 20ff movs r0, #255 @ 0xff + 80008a6: 433b orrs r3, r7 + 80008a8: e65c b.n 8000564 <__aeabi_fadd+0x90> + 80008aa: 2a00 cmp r2, #0 + 80008ac: d100 bne.n 80008b0 <__aeabi_fadd+0x3dc> + 80008ae: e74f b.n 8000750 <__aeabi_fadd+0x27c> + 80008b0: 2100 movs r1, #0 + 80008b2: 08d7 lsrs r7, r2, #3 + 80008b4: e6d2 b.n 800065c <__aeabi_fadd+0x188> + 80008b6: 4644 mov r4, r8 + 80008b8: 2101 movs r1, #1 + 80008ba: 08ff lsrs r7, r7, #3 + 80008bc: e6ce b.n 800065c <__aeabi_fadd+0x188> + 80008be: 2f00 cmp r7, #0 + 80008c0: d000 beq.n 80008c4 <__aeabi_fadd+0x3f0> + 80008c2: e77b b.n 80007bc <__aeabi_fadd+0x2e8> + 80008c4: 2400 movs r4, #0 + 80008c6: e743 b.n 8000750 <__aeabi_fadd+0x27c> + 80008c8: 2380 movs r3, #128 @ 0x80 + 80008ca: 464a mov r2, r9 + 80008cc: 03db lsls r3, r3, #15 + 80008ce: 4644 mov r4, r8 + 80008d0: 20ff movs r0, #255 @ 0xff + 80008d2: 4313 orrs r3, r2 + 80008d4: e646 b.n 8000564 <__aeabi_fadd+0x90> + 80008d6: 2100 movs r1, #0 + 80008d8: e6c0 b.n 800065c <__aeabi_fadd+0x188> + 80008da: 2100 movs r1, #0 + 80008dc: 08df lsrs r7, r3, #3 + 80008de: e6bd b.n 800065c <__aeabi_fadd+0x188> + 80008e0: 0031 movs r1, r6 + 80008e2: e6d0 b.n 8000686 <__aeabi_fadd+0x1b2> + 80008e4: 2001 movs r0, #1 + 80008e6: 016a lsls r2, r5, #5 + 80008e8: d500 bpl.n 80008ec <__aeabi_fadd+0x418> + 80008ea: e68b b.n 8000604 <__aeabi_fadd+0x130> + 80008ec: 002a movs r2, r5 + 80008ee: e7df b.n 80008b0 <__aeabi_fadd+0x3dc> + +080008f0 <__aeabi_fdiv>: + 80008f0: b5f0 push {r4, r5, r6, r7, lr} + 80008f2: 4646 mov r6, r8 + 80008f4: 464f mov r7, r9 + 80008f6: 46d6 mov lr, sl + 80008f8: 0245 lsls r5, r0, #9 + 80008fa: b5c0 push {r6, r7, lr} + 80008fc: 0fc3 lsrs r3, r0, #31 + 80008fe: 0047 lsls r7, r0, #1 + 8000900: 4698 mov r8, r3 + 8000902: 1c0e adds r6, r1, #0 + 8000904: 0a6d lsrs r5, r5, #9 + 8000906: 0e3f lsrs r7, r7, #24 + 8000908: d05b beq.n 80009c2 <__aeabi_fdiv+0xd2> + 800090a: 2fff cmp r7, #255 @ 0xff + 800090c: d021 beq.n 8000952 <__aeabi_fdiv+0x62> + 800090e: 2380 movs r3, #128 @ 0x80 + 8000910: 00ed lsls r5, r5, #3 + 8000912: 04db lsls r3, r3, #19 + 8000914: 431d orrs r5, r3 + 8000916: 2300 movs r3, #0 + 8000918: 4699 mov r9, r3 + 800091a: 469a mov sl, r3 + 800091c: 3f7f subs r7, #127 @ 0x7f + 800091e: 0274 lsls r4, r6, #9 + 8000920: 0073 lsls r3, r6, #1 + 8000922: 0a64 lsrs r4, r4, #9 + 8000924: 0e1b lsrs r3, r3, #24 + 8000926: 0ff6 lsrs r6, r6, #31 + 8000928: 2b00 cmp r3, #0 + 800092a: d020 beq.n 800096e <__aeabi_fdiv+0x7e> + 800092c: 2bff cmp r3, #255 @ 0xff + 800092e: d043 beq.n 80009b8 <__aeabi_fdiv+0xc8> + 8000930: 2280 movs r2, #128 @ 0x80 + 8000932: 2000 movs r0, #0 + 8000934: 00e4 lsls r4, r4, #3 + 8000936: 04d2 lsls r2, r2, #19 + 8000938: 4314 orrs r4, r2 + 800093a: 3b7f subs r3, #127 @ 0x7f + 800093c: 4642 mov r2, r8 + 800093e: 1aff subs r7, r7, r3 + 8000940: 464b mov r3, r9 + 8000942: 4072 eors r2, r6 + 8000944: 2b0f cmp r3, #15 + 8000946: d900 bls.n 800094a <__aeabi_fdiv+0x5a> + 8000948: e09d b.n 8000a86 <__aeabi_fdiv+0x196> + 800094a: 4971 ldr r1, [pc, #452] @ (8000b10 <__aeabi_fdiv+0x220>) + 800094c: 009b lsls r3, r3, #2 + 800094e: 58cb ldr r3, [r1, r3] + 8000950: 469f mov pc, r3 + 8000952: 2d00 cmp r5, #0 + 8000954: d15a bne.n 8000a0c <__aeabi_fdiv+0x11c> + 8000956: 2308 movs r3, #8 + 8000958: 4699 mov r9, r3 + 800095a: 3b06 subs r3, #6 + 800095c: 0274 lsls r4, r6, #9 + 800095e: 469a mov sl, r3 + 8000960: 0073 lsls r3, r6, #1 + 8000962: 27ff movs r7, #255 @ 0xff + 8000964: 0a64 lsrs r4, r4, #9 + 8000966: 0e1b lsrs r3, r3, #24 + 8000968: 0ff6 lsrs r6, r6, #31 + 800096a: 2b00 cmp r3, #0 + 800096c: d1de bne.n 800092c <__aeabi_fdiv+0x3c> + 800096e: 2c00 cmp r4, #0 + 8000970: d13b bne.n 80009ea <__aeabi_fdiv+0xfa> + 8000972: 2301 movs r3, #1 + 8000974: 4642 mov r2, r8 + 8000976: 4649 mov r1, r9 + 8000978: 4072 eors r2, r6 + 800097a: 4319 orrs r1, r3 + 800097c: 290e cmp r1, #14 + 800097e: d818 bhi.n 80009b2 <__aeabi_fdiv+0xc2> + 8000980: 4864 ldr r0, [pc, #400] @ (8000b14 <__aeabi_fdiv+0x224>) + 8000982: 0089 lsls r1, r1, #2 + 8000984: 5841 ldr r1, [r0, r1] + 8000986: 468f mov pc, r1 + 8000988: 4653 mov r3, sl + 800098a: 2b02 cmp r3, #2 + 800098c: d100 bne.n 8000990 <__aeabi_fdiv+0xa0> + 800098e: e0b8 b.n 8000b02 <__aeabi_fdiv+0x212> + 8000990: 2b03 cmp r3, #3 + 8000992: d06e beq.n 8000a72 <__aeabi_fdiv+0x182> + 8000994: 4642 mov r2, r8 + 8000996: 002c movs r4, r5 + 8000998: 2b01 cmp r3, #1 + 800099a: d140 bne.n 8000a1e <__aeabi_fdiv+0x12e> + 800099c: 2000 movs r0, #0 + 800099e: 2400 movs r4, #0 + 80009a0: 05c0 lsls r0, r0, #23 + 80009a2: 4320 orrs r0, r4 + 80009a4: 07d2 lsls r2, r2, #31 + 80009a6: 4310 orrs r0, r2 + 80009a8: bce0 pop {r5, r6, r7} + 80009aa: 46ba mov sl, r7 + 80009ac: 46b1 mov r9, r6 + 80009ae: 46a8 mov r8, r5 + 80009b0: bdf0 pop {r4, r5, r6, r7, pc} + 80009b2: 20ff movs r0, #255 @ 0xff + 80009b4: 2400 movs r4, #0 + 80009b6: e7f3 b.n 80009a0 <__aeabi_fdiv+0xb0> + 80009b8: 2c00 cmp r4, #0 + 80009ba: d120 bne.n 80009fe <__aeabi_fdiv+0x10e> + 80009bc: 2302 movs r3, #2 + 80009be: 3fff subs r7, #255 @ 0xff + 80009c0: e7d8 b.n 8000974 <__aeabi_fdiv+0x84> + 80009c2: 2d00 cmp r5, #0 + 80009c4: d105 bne.n 80009d2 <__aeabi_fdiv+0xe2> + 80009c6: 2304 movs r3, #4 + 80009c8: 4699 mov r9, r3 + 80009ca: 3b03 subs r3, #3 + 80009cc: 2700 movs r7, #0 + 80009ce: 469a mov sl, r3 + 80009d0: e7a5 b.n 800091e <__aeabi_fdiv+0x2e> + 80009d2: 0028 movs r0, r5 + 80009d4: f001 fd4c bl 8002470 <__clzsi2> + 80009d8: 2776 movs r7, #118 @ 0x76 + 80009da: 1f43 subs r3, r0, #5 + 80009dc: 409d lsls r5, r3 + 80009de: 2300 movs r3, #0 + 80009e0: 427f negs r7, r7 + 80009e2: 4699 mov r9, r3 + 80009e4: 469a mov sl, r3 + 80009e6: 1a3f subs r7, r7, r0 + 80009e8: e799 b.n 800091e <__aeabi_fdiv+0x2e> + 80009ea: 0020 movs r0, r4 + 80009ec: f001 fd40 bl 8002470 <__clzsi2> + 80009f0: 1f43 subs r3, r0, #5 + 80009f2: 409c lsls r4, r3 + 80009f4: 2376 movs r3, #118 @ 0x76 + 80009f6: 425b negs r3, r3 + 80009f8: 1a1b subs r3, r3, r0 + 80009fa: 2000 movs r0, #0 + 80009fc: e79e b.n 800093c <__aeabi_fdiv+0x4c> + 80009fe: 2303 movs r3, #3 + 8000a00: 464a mov r2, r9 + 8000a02: 431a orrs r2, r3 + 8000a04: 4691 mov r9, r2 + 8000a06: 2003 movs r0, #3 + 8000a08: 33fc adds r3, #252 @ 0xfc + 8000a0a: e797 b.n 800093c <__aeabi_fdiv+0x4c> + 8000a0c: 230c movs r3, #12 + 8000a0e: 4699 mov r9, r3 + 8000a10: 3b09 subs r3, #9 + 8000a12: 27ff movs r7, #255 @ 0xff + 8000a14: 469a mov sl, r3 + 8000a16: e782 b.n 800091e <__aeabi_fdiv+0x2e> + 8000a18: 2803 cmp r0, #3 + 8000a1a: d02c beq.n 8000a76 <__aeabi_fdiv+0x186> + 8000a1c: 0032 movs r2, r6 + 8000a1e: 0038 movs r0, r7 + 8000a20: 307f adds r0, #127 @ 0x7f + 8000a22: 2800 cmp r0, #0 + 8000a24: dd47 ble.n 8000ab6 <__aeabi_fdiv+0x1c6> + 8000a26: 0763 lsls r3, r4, #29 + 8000a28: d004 beq.n 8000a34 <__aeabi_fdiv+0x144> + 8000a2a: 230f movs r3, #15 + 8000a2c: 4023 ands r3, r4 + 8000a2e: 2b04 cmp r3, #4 + 8000a30: d000 beq.n 8000a34 <__aeabi_fdiv+0x144> + 8000a32: 3404 adds r4, #4 + 8000a34: 0123 lsls r3, r4, #4 + 8000a36: d503 bpl.n 8000a40 <__aeabi_fdiv+0x150> + 8000a38: 0038 movs r0, r7 + 8000a3a: 4b37 ldr r3, [pc, #220] @ (8000b18 <__aeabi_fdiv+0x228>) + 8000a3c: 3080 adds r0, #128 @ 0x80 + 8000a3e: 401c ands r4, r3 + 8000a40: 28fe cmp r0, #254 @ 0xfe + 8000a42: dcb6 bgt.n 80009b2 <__aeabi_fdiv+0xc2> + 8000a44: 01a4 lsls r4, r4, #6 + 8000a46: 0a64 lsrs r4, r4, #9 + 8000a48: b2c0 uxtb r0, r0 + 8000a4a: e7a9 b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000a4c: 2480 movs r4, #128 @ 0x80 + 8000a4e: 2200 movs r2, #0 + 8000a50: 20ff movs r0, #255 @ 0xff + 8000a52: 03e4 lsls r4, r4, #15 + 8000a54: e7a4 b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000a56: 2380 movs r3, #128 @ 0x80 + 8000a58: 03db lsls r3, r3, #15 + 8000a5a: 421d tst r5, r3 + 8000a5c: d001 beq.n 8000a62 <__aeabi_fdiv+0x172> + 8000a5e: 421c tst r4, r3 + 8000a60: d00b beq.n 8000a7a <__aeabi_fdiv+0x18a> + 8000a62: 2480 movs r4, #128 @ 0x80 + 8000a64: 03e4 lsls r4, r4, #15 + 8000a66: 432c orrs r4, r5 + 8000a68: 0264 lsls r4, r4, #9 + 8000a6a: 4642 mov r2, r8 + 8000a6c: 20ff movs r0, #255 @ 0xff + 8000a6e: 0a64 lsrs r4, r4, #9 + 8000a70: e796 b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000a72: 4646 mov r6, r8 + 8000a74: 002c movs r4, r5 + 8000a76: 2380 movs r3, #128 @ 0x80 + 8000a78: 03db lsls r3, r3, #15 + 8000a7a: 431c orrs r4, r3 + 8000a7c: 0264 lsls r4, r4, #9 + 8000a7e: 0032 movs r2, r6 + 8000a80: 20ff movs r0, #255 @ 0xff + 8000a82: 0a64 lsrs r4, r4, #9 + 8000a84: e78c b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000a86: 016d lsls r5, r5, #5 + 8000a88: 0160 lsls r0, r4, #5 + 8000a8a: 4285 cmp r5, r0 + 8000a8c: d22d bcs.n 8000aea <__aeabi_fdiv+0x1fa> + 8000a8e: 231b movs r3, #27 + 8000a90: 2400 movs r4, #0 + 8000a92: 3f01 subs r7, #1 + 8000a94: 2601 movs r6, #1 + 8000a96: 0029 movs r1, r5 + 8000a98: 0064 lsls r4, r4, #1 + 8000a9a: 006d lsls r5, r5, #1 + 8000a9c: 2900 cmp r1, #0 + 8000a9e: db01 blt.n 8000aa4 <__aeabi_fdiv+0x1b4> + 8000aa0: 4285 cmp r5, r0 + 8000aa2: d301 bcc.n 8000aa8 <__aeabi_fdiv+0x1b8> + 8000aa4: 1a2d subs r5, r5, r0 + 8000aa6: 4334 orrs r4, r6 + 8000aa8: 3b01 subs r3, #1 + 8000aaa: 2b00 cmp r3, #0 + 8000aac: d1f3 bne.n 8000a96 <__aeabi_fdiv+0x1a6> + 8000aae: 1e6b subs r3, r5, #1 + 8000ab0: 419d sbcs r5, r3 + 8000ab2: 432c orrs r4, r5 + 8000ab4: e7b3 b.n 8000a1e <__aeabi_fdiv+0x12e> + 8000ab6: 2301 movs r3, #1 + 8000ab8: 1a1b subs r3, r3, r0 + 8000aba: 2b1b cmp r3, #27 + 8000abc: dd00 ble.n 8000ac0 <__aeabi_fdiv+0x1d0> + 8000abe: e76d b.n 800099c <__aeabi_fdiv+0xac> + 8000ac0: 0021 movs r1, r4 + 8000ac2: 379e adds r7, #158 @ 0x9e + 8000ac4: 40d9 lsrs r1, r3 + 8000ac6: 40bc lsls r4, r7 + 8000ac8: 000b movs r3, r1 + 8000aca: 1e61 subs r1, r4, #1 + 8000acc: 418c sbcs r4, r1 + 8000ace: 4323 orrs r3, r4 + 8000ad0: 0759 lsls r1, r3, #29 + 8000ad2: d004 beq.n 8000ade <__aeabi_fdiv+0x1ee> + 8000ad4: 210f movs r1, #15 + 8000ad6: 4019 ands r1, r3 + 8000ad8: 2904 cmp r1, #4 + 8000ada: d000 beq.n 8000ade <__aeabi_fdiv+0x1ee> + 8000adc: 3304 adds r3, #4 + 8000ade: 0159 lsls r1, r3, #5 + 8000ae0: d413 bmi.n 8000b0a <__aeabi_fdiv+0x21a> + 8000ae2: 019b lsls r3, r3, #6 + 8000ae4: 2000 movs r0, #0 + 8000ae6: 0a5c lsrs r4, r3, #9 + 8000ae8: e75a b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000aea: 231a movs r3, #26 + 8000aec: 2401 movs r4, #1 + 8000aee: 1a2d subs r5, r5, r0 + 8000af0: e7d0 b.n 8000a94 <__aeabi_fdiv+0x1a4> + 8000af2: 1e98 subs r0, r3, #2 + 8000af4: 4243 negs r3, r0 + 8000af6: 4158 adcs r0, r3 + 8000af8: 4240 negs r0, r0 + 8000afa: 0032 movs r2, r6 + 8000afc: 2400 movs r4, #0 + 8000afe: b2c0 uxtb r0, r0 + 8000b00: e74e b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000b02: 4642 mov r2, r8 + 8000b04: 20ff movs r0, #255 @ 0xff + 8000b06: 2400 movs r4, #0 + 8000b08: e74a b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000b0a: 2001 movs r0, #1 + 8000b0c: 2400 movs r4, #0 + 8000b0e: e747 b.n 80009a0 <__aeabi_fdiv+0xb0> + 8000b10: 080089b4 .word 0x080089b4 + 8000b14: 080089f4 .word 0x080089f4 + 8000b18: f7ffffff .word 0xf7ffffff + +08000b1c <__eqsf2>: + 8000b1c: b570 push {r4, r5, r6, lr} + 8000b1e: 0042 lsls r2, r0, #1 + 8000b20: 024e lsls r6, r1, #9 + 8000b22: 004c lsls r4, r1, #1 + 8000b24: 0245 lsls r5, r0, #9 + 8000b26: 0a6d lsrs r5, r5, #9 + 8000b28: 0e12 lsrs r2, r2, #24 + 8000b2a: 0fc3 lsrs r3, r0, #31 + 8000b2c: 0a76 lsrs r6, r6, #9 + 8000b2e: 0e24 lsrs r4, r4, #24 + 8000b30: 0fc9 lsrs r1, r1, #31 + 8000b32: 2aff cmp r2, #255 @ 0xff + 8000b34: d010 beq.n 8000b58 <__eqsf2+0x3c> + 8000b36: 2cff cmp r4, #255 @ 0xff + 8000b38: d00c beq.n 8000b54 <__eqsf2+0x38> + 8000b3a: 2001 movs r0, #1 + 8000b3c: 42a2 cmp r2, r4 + 8000b3e: d10a bne.n 8000b56 <__eqsf2+0x3a> + 8000b40: 42b5 cmp r5, r6 + 8000b42: d108 bne.n 8000b56 <__eqsf2+0x3a> + 8000b44: 428b cmp r3, r1 + 8000b46: d00f beq.n 8000b68 <__eqsf2+0x4c> + 8000b48: 2a00 cmp r2, #0 + 8000b4a: d104 bne.n 8000b56 <__eqsf2+0x3a> + 8000b4c: 0028 movs r0, r5 + 8000b4e: 1e43 subs r3, r0, #1 + 8000b50: 4198 sbcs r0, r3 + 8000b52: e000 b.n 8000b56 <__eqsf2+0x3a> + 8000b54: 2001 movs r0, #1 + 8000b56: bd70 pop {r4, r5, r6, pc} + 8000b58: 2001 movs r0, #1 + 8000b5a: 2cff cmp r4, #255 @ 0xff + 8000b5c: d1fb bne.n 8000b56 <__eqsf2+0x3a> + 8000b5e: 4335 orrs r5, r6 + 8000b60: d1f9 bne.n 8000b56 <__eqsf2+0x3a> + 8000b62: 404b eors r3, r1 + 8000b64: 0018 movs r0, r3 + 8000b66: e7f6 b.n 8000b56 <__eqsf2+0x3a> + 8000b68: 2000 movs r0, #0 + 8000b6a: e7f4 b.n 8000b56 <__eqsf2+0x3a> + +08000b6c <__gesf2>: + 8000b6c: b530 push {r4, r5, lr} + 8000b6e: 0042 lsls r2, r0, #1 + 8000b70: 0244 lsls r4, r0, #9 + 8000b72: 024d lsls r5, r1, #9 + 8000b74: 0fc3 lsrs r3, r0, #31 + 8000b76: 0048 lsls r0, r1, #1 + 8000b78: 0a64 lsrs r4, r4, #9 + 8000b7a: 0e12 lsrs r2, r2, #24 + 8000b7c: 0a6d lsrs r5, r5, #9 + 8000b7e: 0e00 lsrs r0, r0, #24 + 8000b80: 0fc9 lsrs r1, r1, #31 + 8000b82: 2aff cmp r2, #255 @ 0xff + 8000b84: d018 beq.n 8000bb8 <__gesf2+0x4c> + 8000b86: 28ff cmp r0, #255 @ 0xff + 8000b88: d00a beq.n 8000ba0 <__gesf2+0x34> + 8000b8a: 2a00 cmp r2, #0 + 8000b8c: d11e bne.n 8000bcc <__gesf2+0x60> + 8000b8e: 2800 cmp r0, #0 + 8000b90: d10a bne.n 8000ba8 <__gesf2+0x3c> + 8000b92: 2d00 cmp r5, #0 + 8000b94: d029 beq.n 8000bea <__gesf2+0x7e> + 8000b96: 2c00 cmp r4, #0 + 8000b98: d12d bne.n 8000bf6 <__gesf2+0x8a> + 8000b9a: 0048 lsls r0, r1, #1 + 8000b9c: 3801 subs r0, #1 + 8000b9e: bd30 pop {r4, r5, pc} + 8000ba0: 2d00 cmp r5, #0 + 8000ba2: d125 bne.n 8000bf0 <__gesf2+0x84> + 8000ba4: 2a00 cmp r2, #0 + 8000ba6: d101 bne.n 8000bac <__gesf2+0x40> + 8000ba8: 2c00 cmp r4, #0 + 8000baa: d0f6 beq.n 8000b9a <__gesf2+0x2e> + 8000bac: 428b cmp r3, r1 + 8000bae: d019 beq.n 8000be4 <__gesf2+0x78> + 8000bb0: 2001 movs r0, #1 + 8000bb2: 425b negs r3, r3 + 8000bb4: 4318 orrs r0, r3 + 8000bb6: e7f2 b.n 8000b9e <__gesf2+0x32> + 8000bb8: 2c00 cmp r4, #0 + 8000bba: d119 bne.n 8000bf0 <__gesf2+0x84> + 8000bbc: 28ff cmp r0, #255 @ 0xff + 8000bbe: d1f7 bne.n 8000bb0 <__gesf2+0x44> + 8000bc0: 2d00 cmp r5, #0 + 8000bc2: d115 bne.n 8000bf0 <__gesf2+0x84> + 8000bc4: 2000 movs r0, #0 + 8000bc6: 428b cmp r3, r1 + 8000bc8: d1f2 bne.n 8000bb0 <__gesf2+0x44> + 8000bca: e7e8 b.n 8000b9e <__gesf2+0x32> + 8000bcc: 2800 cmp r0, #0 + 8000bce: d0ef beq.n 8000bb0 <__gesf2+0x44> + 8000bd0: 428b cmp r3, r1 + 8000bd2: d1ed bne.n 8000bb0 <__gesf2+0x44> + 8000bd4: 4282 cmp r2, r0 + 8000bd6: dceb bgt.n 8000bb0 <__gesf2+0x44> + 8000bd8: db04 blt.n 8000be4 <__gesf2+0x78> + 8000bda: 42ac cmp r4, r5 + 8000bdc: d8e8 bhi.n 8000bb0 <__gesf2+0x44> + 8000bde: 2000 movs r0, #0 + 8000be0: 42ac cmp r4, r5 + 8000be2: d2dc bcs.n 8000b9e <__gesf2+0x32> + 8000be4: 0058 lsls r0, r3, #1 + 8000be6: 3801 subs r0, #1 + 8000be8: e7d9 b.n 8000b9e <__gesf2+0x32> + 8000bea: 2c00 cmp r4, #0 + 8000bec: d0d7 beq.n 8000b9e <__gesf2+0x32> + 8000bee: e7df b.n 8000bb0 <__gesf2+0x44> + 8000bf0: 2002 movs r0, #2 + 8000bf2: 4240 negs r0, r0 + 8000bf4: e7d3 b.n 8000b9e <__gesf2+0x32> + 8000bf6: 428b cmp r3, r1 + 8000bf8: d1da bne.n 8000bb0 <__gesf2+0x44> + 8000bfa: e7ee b.n 8000bda <__gesf2+0x6e> + +08000bfc <__lesf2>: + 8000bfc: b530 push {r4, r5, lr} + 8000bfe: 0042 lsls r2, r0, #1 + 8000c00: 0244 lsls r4, r0, #9 + 8000c02: 024d lsls r5, r1, #9 + 8000c04: 0fc3 lsrs r3, r0, #31 + 8000c06: 0048 lsls r0, r1, #1 + 8000c08: 0a64 lsrs r4, r4, #9 + 8000c0a: 0e12 lsrs r2, r2, #24 + 8000c0c: 0a6d lsrs r5, r5, #9 + 8000c0e: 0e00 lsrs r0, r0, #24 + 8000c10: 0fc9 lsrs r1, r1, #31 + 8000c12: 2aff cmp r2, #255 @ 0xff + 8000c14: d017 beq.n 8000c46 <__lesf2+0x4a> + 8000c16: 28ff cmp r0, #255 @ 0xff + 8000c18: d00a beq.n 8000c30 <__lesf2+0x34> + 8000c1a: 2a00 cmp r2, #0 + 8000c1c: d11b bne.n 8000c56 <__lesf2+0x5a> + 8000c1e: 2800 cmp r0, #0 + 8000c20: d10a bne.n 8000c38 <__lesf2+0x3c> + 8000c22: 2d00 cmp r5, #0 + 8000c24: d01d beq.n 8000c62 <__lesf2+0x66> + 8000c26: 2c00 cmp r4, #0 + 8000c28: d12d bne.n 8000c86 <__lesf2+0x8a> + 8000c2a: 0048 lsls r0, r1, #1 + 8000c2c: 3801 subs r0, #1 + 8000c2e: e011 b.n 8000c54 <__lesf2+0x58> + 8000c30: 2d00 cmp r5, #0 + 8000c32: d10e bne.n 8000c52 <__lesf2+0x56> + 8000c34: 2a00 cmp r2, #0 + 8000c36: d101 bne.n 8000c3c <__lesf2+0x40> + 8000c38: 2c00 cmp r4, #0 + 8000c3a: d0f6 beq.n 8000c2a <__lesf2+0x2e> + 8000c3c: 428b cmp r3, r1 + 8000c3e: d10c bne.n 8000c5a <__lesf2+0x5e> + 8000c40: 0058 lsls r0, r3, #1 + 8000c42: 3801 subs r0, #1 + 8000c44: e006 b.n 8000c54 <__lesf2+0x58> + 8000c46: 2c00 cmp r4, #0 + 8000c48: d103 bne.n 8000c52 <__lesf2+0x56> + 8000c4a: 28ff cmp r0, #255 @ 0xff + 8000c4c: d105 bne.n 8000c5a <__lesf2+0x5e> + 8000c4e: 2d00 cmp r5, #0 + 8000c50: d015 beq.n 8000c7e <__lesf2+0x82> + 8000c52: 2002 movs r0, #2 + 8000c54: bd30 pop {r4, r5, pc} + 8000c56: 2800 cmp r0, #0 + 8000c58: d106 bne.n 8000c68 <__lesf2+0x6c> + 8000c5a: 2001 movs r0, #1 + 8000c5c: 425b negs r3, r3 + 8000c5e: 4318 orrs r0, r3 + 8000c60: e7f8 b.n 8000c54 <__lesf2+0x58> + 8000c62: 2c00 cmp r4, #0 + 8000c64: d0f6 beq.n 8000c54 <__lesf2+0x58> + 8000c66: e7f8 b.n 8000c5a <__lesf2+0x5e> + 8000c68: 428b cmp r3, r1 + 8000c6a: d1f6 bne.n 8000c5a <__lesf2+0x5e> + 8000c6c: 4282 cmp r2, r0 + 8000c6e: dcf4 bgt.n 8000c5a <__lesf2+0x5e> + 8000c70: dbe6 blt.n 8000c40 <__lesf2+0x44> + 8000c72: 42ac cmp r4, r5 + 8000c74: d8f1 bhi.n 8000c5a <__lesf2+0x5e> + 8000c76: 2000 movs r0, #0 + 8000c78: 42ac cmp r4, r5 + 8000c7a: d2eb bcs.n 8000c54 <__lesf2+0x58> + 8000c7c: e7e0 b.n 8000c40 <__lesf2+0x44> + 8000c7e: 2000 movs r0, #0 + 8000c80: 428b cmp r3, r1 + 8000c82: d1ea bne.n 8000c5a <__lesf2+0x5e> + 8000c84: e7e6 b.n 8000c54 <__lesf2+0x58> + 8000c86: 428b cmp r3, r1 + 8000c88: d1e7 bne.n 8000c5a <__lesf2+0x5e> + 8000c8a: e7f2 b.n 8000c72 <__lesf2+0x76> + +08000c8c <__aeabi_fmul>: + 8000c8c: b5f0 push {r4, r5, r6, r7, lr} + 8000c8e: 464f mov r7, r9 + 8000c90: 4646 mov r6, r8 + 8000c92: 46d6 mov lr, sl + 8000c94: 0245 lsls r5, r0, #9 + 8000c96: b5c0 push {r6, r7, lr} + 8000c98: 0046 lsls r6, r0, #1 + 8000c9a: 1c0f adds r7, r1, #0 + 8000c9c: 0a6d lsrs r5, r5, #9 + 8000c9e: 0e36 lsrs r6, r6, #24 + 8000ca0: 0fc4 lsrs r4, r0, #31 + 8000ca2: 2e00 cmp r6, #0 + 8000ca4: d100 bne.n 8000ca8 <__aeabi_fmul+0x1c> + 8000ca6: e0cd b.n 8000e44 <__aeabi_fmul+0x1b8> + 8000ca8: 2eff cmp r6, #255 @ 0xff + 8000caa: d072 beq.n 8000d92 <__aeabi_fmul+0x106> + 8000cac: 2380 movs r3, #128 @ 0x80 + 8000cae: 00ed lsls r5, r5, #3 + 8000cb0: 04db lsls r3, r3, #19 + 8000cb2: 431d orrs r5, r3 + 8000cb4: 2300 movs r3, #0 + 8000cb6: 4699 mov r9, r3 + 8000cb8: 469a mov sl, r3 + 8000cba: 3e7f subs r6, #127 @ 0x7f + 8000cbc: 027b lsls r3, r7, #9 + 8000cbe: 0a5b lsrs r3, r3, #9 + 8000cc0: 4698 mov r8, r3 + 8000cc2: 007b lsls r3, r7, #1 + 8000cc4: 0e1b lsrs r3, r3, #24 + 8000cc6: 0fff lsrs r7, r7, #31 + 8000cc8: 2b00 cmp r3, #0 + 8000cca: d072 beq.n 8000db2 <__aeabi_fmul+0x126> + 8000ccc: 2bff cmp r3, #255 @ 0xff + 8000cce: d100 bne.n 8000cd2 <__aeabi_fmul+0x46> + 8000cd0: e0a9 b.n 8000e26 <__aeabi_fmul+0x19a> + 8000cd2: 3b7f subs r3, #127 @ 0x7f + 8000cd4: 18f6 adds r6, r6, r3 + 8000cd6: 464b mov r3, r9 + 8000cd8: 2b0a cmp r3, #10 + 8000cda: dd00 ble.n 8000cde <__aeabi_fmul+0x52> + 8000cdc: e085 b.n 8000dea <__aeabi_fmul+0x15e> + 8000cde: 4643 mov r3, r8 + 8000ce0: 2280 movs r2, #128 @ 0x80 + 8000ce2: 00db lsls r3, r3, #3 + 8000ce4: 04d2 lsls r2, r2, #19 + 8000ce6: 431a orrs r2, r3 + 8000ce8: 464b mov r3, r9 + 8000cea: 4690 mov r8, r2 + 8000cec: 407c eors r4, r7 + 8000cee: 2200 movs r2, #0 + 8000cf0: 2b02 cmp r3, #2 + 8000cf2: dd0f ble.n 8000d14 <__aeabi_fmul+0x88> + 8000cf4: 4649 mov r1, r9 + 8000cf6: 2301 movs r3, #1 + 8000cf8: 408b lsls r3, r1 + 8000cfa: 21a6 movs r1, #166 @ 0xa6 + 8000cfc: 00c9 lsls r1, r1, #3 + 8000cfe: 420b tst r3, r1 + 8000d00: d000 beq.n 8000d04 <__aeabi_fmul+0x78> + 8000d02: e072 b.n 8000dea <__aeabi_fmul+0x15e> + 8000d04: 2190 movs r1, #144 @ 0x90 + 8000d06: 0089 lsls r1, r1, #2 + 8000d08: 420b tst r3, r1 + 8000d0a: d000 beq.n 8000d0e <__aeabi_fmul+0x82> + 8000d0c: e0da b.n 8000ec4 <__aeabi_fmul+0x238> + 8000d0e: 2188 movs r1, #136 @ 0x88 + 8000d10: 4219 tst r1, r3 + 8000d12: d167 bne.n 8000de4 <__aeabi_fmul+0x158> + 8000d14: 0c28 lsrs r0, r5, #16 + 8000d16: 4642 mov r2, r8 + 8000d18: 042d lsls r5, r5, #16 + 8000d1a: 0c2d lsrs r5, r5, #16 + 8000d1c: 4643 mov r3, r8 + 8000d1e: 0029 movs r1, r5 + 8000d20: 0412 lsls r2, r2, #16 + 8000d22: 0c1b lsrs r3, r3, #16 + 8000d24: 0c12 lsrs r2, r2, #16 + 8000d26: 4351 muls r1, r2 + 8000d28: 435d muls r5, r3 + 8000d2a: 4342 muls r2, r0 + 8000d2c: 4358 muls r0, r3 + 8000d2e: 18ad adds r5, r5, r2 + 8000d30: 0c0b lsrs r3, r1, #16 + 8000d32: 195b adds r3, r3, r5 + 8000d34: 429a cmp r2, r3 + 8000d36: d903 bls.n 8000d40 <__aeabi_fmul+0xb4> + 8000d38: 2280 movs r2, #128 @ 0x80 + 8000d3a: 0252 lsls r2, r2, #9 + 8000d3c: 4694 mov ip, r2 + 8000d3e: 4460 add r0, ip + 8000d40: 0409 lsls r1, r1, #16 + 8000d42: 041a lsls r2, r3, #16 + 8000d44: 0c09 lsrs r1, r1, #16 + 8000d46: 1852 adds r2, r2, r1 + 8000d48: 0195 lsls r5, r2, #6 + 8000d4a: 1e69 subs r1, r5, #1 + 8000d4c: 418d sbcs r5, r1 + 8000d4e: 0c1b lsrs r3, r3, #16 + 8000d50: 0e92 lsrs r2, r2, #26 + 8000d52: 181b adds r3, r3, r0 + 8000d54: 4315 orrs r5, r2 + 8000d56: 019b lsls r3, r3, #6 + 8000d58: 431d orrs r5, r3 + 8000d5a: 011b lsls r3, r3, #4 + 8000d5c: d500 bpl.n 8000d60 <__aeabi_fmul+0xd4> + 8000d5e: e0cf b.n 8000f00 <__aeabi_fmul+0x274> + 8000d60: 0030 movs r0, r6 + 8000d62: 307f adds r0, #127 @ 0x7f + 8000d64: 2800 cmp r0, #0 + 8000d66: dc00 bgt.n 8000d6a <__aeabi_fmul+0xde> + 8000d68: e0b1 b.n 8000ece <__aeabi_fmul+0x242> + 8000d6a: 076b lsls r3, r5, #29 + 8000d6c: d00b beq.n 8000d86 <__aeabi_fmul+0xfa> + 8000d6e: 230f movs r3, #15 + 8000d70: 0032 movs r2, r6 + 8000d72: 402b ands r3, r5 + 8000d74: 2b04 cmp r3, #4 + 8000d76: d006 beq.n 8000d86 <__aeabi_fmul+0xfa> + 8000d78: 3504 adds r5, #4 + 8000d7a: 012b lsls r3, r5, #4 + 8000d7c: d503 bpl.n 8000d86 <__aeabi_fmul+0xfa> + 8000d7e: 3280 adds r2, #128 @ 0x80 + 8000d80: 0010 movs r0, r2 + 8000d82: 4b6a ldr r3, [pc, #424] @ (8000f2c <__aeabi_fmul+0x2a0>) + 8000d84: 401d ands r5, r3 + 8000d86: 28fe cmp r0, #254 @ 0xfe + 8000d88: dc64 bgt.n 8000e54 <__aeabi_fmul+0x1c8> + 8000d8a: 01ab lsls r3, r5, #6 + 8000d8c: 0a5b lsrs r3, r3, #9 + 8000d8e: b2c0 uxtb r0, r0 + 8000d90: e01f b.n 8000dd2 <__aeabi_fmul+0x146> + 8000d92: 2d00 cmp r5, #0 + 8000d94: d000 beq.n 8000d98 <__aeabi_fmul+0x10c> + 8000d96: e08f b.n 8000eb8 <__aeabi_fmul+0x22c> + 8000d98: 2308 movs r3, #8 + 8000d9a: 4699 mov r9, r3 + 8000d9c: 3b06 subs r3, #6 + 8000d9e: 469a mov sl, r3 + 8000da0: 027b lsls r3, r7, #9 + 8000da2: 0a5b lsrs r3, r3, #9 + 8000da4: 4698 mov r8, r3 + 8000da6: 007b lsls r3, r7, #1 + 8000da8: 26ff movs r6, #255 @ 0xff + 8000daa: 0e1b lsrs r3, r3, #24 + 8000dac: 0fff lsrs r7, r7, #31 + 8000dae: 2b00 cmp r3, #0 + 8000db0: d18c bne.n 8000ccc <__aeabi_fmul+0x40> + 8000db2: 4643 mov r3, r8 + 8000db4: 2b00 cmp r3, #0 + 8000db6: d15c bne.n 8000e72 <__aeabi_fmul+0x1e6> + 8000db8: 464a mov r2, r9 + 8000dba: 3301 adds r3, #1 + 8000dbc: 431a orrs r2, r3 + 8000dbe: 4691 mov r9, r2 + 8000dc0: 0013 movs r3, r2 + 8000dc2: 2a0a cmp r2, #10 + 8000dc4: dc11 bgt.n 8000dea <__aeabi_fmul+0x15e> + 8000dc6: 2201 movs r2, #1 + 8000dc8: 407c eors r4, r7 + 8000dca: 2b02 cmp r3, #2 + 8000dcc: dc92 bgt.n 8000cf4 <__aeabi_fmul+0x68> + 8000dce: 2000 movs r0, #0 + 8000dd0: 2300 movs r3, #0 + 8000dd2: 05c0 lsls r0, r0, #23 + 8000dd4: 4318 orrs r0, r3 + 8000dd6: 07e4 lsls r4, r4, #31 + 8000dd8: 4320 orrs r0, r4 + 8000dda: bce0 pop {r5, r6, r7} + 8000ddc: 46ba mov sl, r7 + 8000dde: 46b1 mov r9, r6 + 8000de0: 46a8 mov r8, r5 + 8000de2: bdf0 pop {r4, r5, r6, r7, pc} + 8000de4: 003c movs r4, r7 + 8000de6: 4645 mov r5, r8 + 8000de8: 4692 mov sl, r2 + 8000dea: 4653 mov r3, sl + 8000dec: 2b02 cmp r3, #2 + 8000dee: d031 beq.n 8000e54 <__aeabi_fmul+0x1c8> + 8000df0: 2b03 cmp r3, #3 + 8000df2: d011 beq.n 8000e18 <__aeabi_fmul+0x18c> + 8000df4: 2b01 cmp r3, #1 + 8000df6: d0ea beq.n 8000dce <__aeabi_fmul+0x142> + 8000df8: 0030 movs r0, r6 + 8000dfa: 3080 adds r0, #128 @ 0x80 + 8000dfc: 1c72 adds r2, r6, #1 + 8000dfe: 2800 cmp r0, #0 + 8000e00: dd66 ble.n 8000ed0 <__aeabi_fmul+0x244> + 8000e02: 076b lsls r3, r5, #29 + 8000e04: d0b9 beq.n 8000d7a <__aeabi_fmul+0xee> + 8000e06: 230f movs r3, #15 + 8000e08: 402b ands r3, r5 + 8000e0a: 2b04 cmp r3, #4 + 8000e0c: d1b4 bne.n 8000d78 <__aeabi_fmul+0xec> + 8000e0e: e7b4 b.n 8000d7a <__aeabi_fmul+0xee> + 8000e10: 2a0f cmp r2, #15 + 8000e12: d07a beq.n 8000f0a <__aeabi_fmul+0x27e> + 8000e14: 003c movs r4, r7 + 8000e16: 4645 mov r5, r8 + 8000e18: 2380 movs r3, #128 @ 0x80 + 8000e1a: 03db lsls r3, r3, #15 + 8000e1c: 432b orrs r3, r5 + 8000e1e: 025b lsls r3, r3, #9 + 8000e20: 20ff movs r0, #255 @ 0xff + 8000e22: 0a5b lsrs r3, r3, #9 + 8000e24: e7d5 b.n 8000dd2 <__aeabi_fmul+0x146> + 8000e26: 4643 mov r3, r8 + 8000e28: 36ff adds r6, #255 @ 0xff + 8000e2a: 2b00 cmp r3, #0 + 8000e2c: d134 bne.n 8000e98 <__aeabi_fmul+0x20c> + 8000e2e: 464a mov r2, r9 + 8000e30: 3302 adds r3, #2 + 8000e32: 4313 orrs r3, r2 + 8000e34: 2b0a cmp r3, #10 + 8000e36: dcd8 bgt.n 8000dea <__aeabi_fmul+0x15e> + 8000e38: 407c eors r4, r7 + 8000e3a: 2a00 cmp r2, #0 + 8000e3c: d00a beq.n 8000e54 <__aeabi_fmul+0x1c8> + 8000e3e: 4699 mov r9, r3 + 8000e40: 2202 movs r2, #2 + 8000e42: e757 b.n 8000cf4 <__aeabi_fmul+0x68> + 8000e44: 2d00 cmp r5, #0 + 8000e46: d108 bne.n 8000e5a <__aeabi_fmul+0x1ce> + 8000e48: 2304 movs r3, #4 + 8000e4a: 4699 mov r9, r3 + 8000e4c: 3b03 subs r3, #3 + 8000e4e: 2600 movs r6, #0 + 8000e50: 469a mov sl, r3 + 8000e52: e733 b.n 8000cbc <__aeabi_fmul+0x30> + 8000e54: 20ff movs r0, #255 @ 0xff + 8000e56: 2300 movs r3, #0 + 8000e58: e7bb b.n 8000dd2 <__aeabi_fmul+0x146> + 8000e5a: 0028 movs r0, r5 + 8000e5c: f001 fb08 bl 8002470 <__clzsi2> + 8000e60: 2676 movs r6, #118 @ 0x76 + 8000e62: 1f43 subs r3, r0, #5 + 8000e64: 409d lsls r5, r3 + 8000e66: 2300 movs r3, #0 + 8000e68: 4276 negs r6, r6 + 8000e6a: 4699 mov r9, r3 + 8000e6c: 469a mov sl, r3 + 8000e6e: 1a36 subs r6, r6, r0 + 8000e70: e724 b.n 8000cbc <__aeabi_fmul+0x30> + 8000e72: 4640 mov r0, r8 + 8000e74: f001 fafc bl 8002470 <__clzsi2> + 8000e78: 464b mov r3, r9 + 8000e7a: 1a36 subs r6, r6, r0 + 8000e7c: 3e76 subs r6, #118 @ 0x76 + 8000e7e: 2b0a cmp r3, #10 + 8000e80: dcb3 bgt.n 8000dea <__aeabi_fmul+0x15e> + 8000e82: 4643 mov r3, r8 + 8000e84: 3805 subs r0, #5 + 8000e86: 4083 lsls r3, r0 + 8000e88: 4698 mov r8, r3 + 8000e8a: 464b mov r3, r9 + 8000e8c: 2200 movs r2, #0 + 8000e8e: 407c eors r4, r7 + 8000e90: 2b02 cmp r3, #2 + 8000e92: dd00 ble.n 8000e96 <__aeabi_fmul+0x20a> + 8000e94: e72e b.n 8000cf4 <__aeabi_fmul+0x68> + 8000e96: e73d b.n 8000d14 <__aeabi_fmul+0x88> + 8000e98: 2303 movs r3, #3 + 8000e9a: 464a mov r2, r9 + 8000e9c: 431a orrs r2, r3 + 8000e9e: 0013 movs r3, r2 + 8000ea0: 2a0a cmp r2, #10 + 8000ea2: dcb5 bgt.n 8000e10 <__aeabi_fmul+0x184> + 8000ea4: 2201 movs r2, #1 + 8000ea6: 409a lsls r2, r3 + 8000ea8: 2188 movs r1, #136 @ 0x88 + 8000eaa: 0013 movs r3, r2 + 8000eac: 407c eors r4, r7 + 8000eae: 2203 movs r2, #3 + 8000eb0: 4219 tst r1, r3 + 8000eb2: d100 bne.n 8000eb6 <__aeabi_fmul+0x22a> + 8000eb4: e72e b.n 8000d14 <__aeabi_fmul+0x88> + 8000eb6: e795 b.n 8000de4 <__aeabi_fmul+0x158> + 8000eb8: 230c movs r3, #12 + 8000eba: 4699 mov r9, r3 + 8000ebc: 3b09 subs r3, #9 + 8000ebe: 26ff movs r6, #255 @ 0xff + 8000ec0: 469a mov sl, r3 + 8000ec2: e6fb b.n 8000cbc <__aeabi_fmul+0x30> + 8000ec4: 2380 movs r3, #128 @ 0x80 + 8000ec6: 2400 movs r4, #0 + 8000ec8: 20ff movs r0, #255 @ 0xff + 8000eca: 03db lsls r3, r3, #15 + 8000ecc: e781 b.n 8000dd2 <__aeabi_fmul+0x146> + 8000ece: 0032 movs r2, r6 + 8000ed0: 2301 movs r3, #1 + 8000ed2: 1a1b subs r3, r3, r0 + 8000ed4: 2b1b cmp r3, #27 + 8000ed6: dd00 ble.n 8000eda <__aeabi_fmul+0x24e> + 8000ed8: e779 b.n 8000dce <__aeabi_fmul+0x142> + 8000eda: 329e adds r2, #158 @ 0x9e + 8000edc: 0029 movs r1, r5 + 8000ede: 4095 lsls r5, r2 + 8000ee0: 40d9 lsrs r1, r3 + 8000ee2: 1e6a subs r2, r5, #1 + 8000ee4: 4195 sbcs r5, r2 + 8000ee6: 430d orrs r5, r1 + 8000ee8: 076b lsls r3, r5, #29 + 8000eea: d004 beq.n 8000ef6 <__aeabi_fmul+0x26a> + 8000eec: 230f movs r3, #15 + 8000eee: 402b ands r3, r5 + 8000ef0: 2b04 cmp r3, #4 + 8000ef2: d000 beq.n 8000ef6 <__aeabi_fmul+0x26a> + 8000ef4: 3504 adds r5, #4 + 8000ef6: 016b lsls r3, r5, #5 + 8000ef8: d513 bpl.n 8000f22 <__aeabi_fmul+0x296> + 8000efa: 2001 movs r0, #1 + 8000efc: 2300 movs r3, #0 + 8000efe: e768 b.n 8000dd2 <__aeabi_fmul+0x146> + 8000f00: 2301 movs r3, #1 + 8000f02: 086a lsrs r2, r5, #1 + 8000f04: 401d ands r5, r3 + 8000f06: 4315 orrs r5, r2 + 8000f08: e776 b.n 8000df8 <__aeabi_fmul+0x16c> + 8000f0a: 2380 movs r3, #128 @ 0x80 + 8000f0c: 03db lsls r3, r3, #15 + 8000f0e: 421d tst r5, r3 + 8000f10: d082 beq.n 8000e18 <__aeabi_fmul+0x18c> + 8000f12: 4642 mov r2, r8 + 8000f14: 421a tst r2, r3 + 8000f16: d000 beq.n 8000f1a <__aeabi_fmul+0x28e> + 8000f18: e77e b.n 8000e18 <__aeabi_fmul+0x18c> + 8000f1a: 003c movs r4, r7 + 8000f1c: 20ff movs r0, #255 @ 0xff + 8000f1e: 4313 orrs r3, r2 + 8000f20: e757 b.n 8000dd2 <__aeabi_fmul+0x146> + 8000f22: 01ab lsls r3, r5, #6 + 8000f24: 2000 movs r0, #0 + 8000f26: 0a5b lsrs r3, r3, #9 + 8000f28: e753 b.n 8000dd2 <__aeabi_fmul+0x146> + 8000f2a: 46c0 nop @ (mov r8, r8) + 8000f2c: f7ffffff .word 0xf7ffffff + +08000f30 <__aeabi_fsub>: + 8000f30: b5f8 push {r3, r4, r5, r6, r7, lr} + 8000f32: 4647 mov r7, r8 + 8000f34: 46ce mov lr, r9 + 8000f36: 024b lsls r3, r1, #9 + 8000f38: 0046 lsls r6, r0, #1 + 8000f3a: b580 push {r7, lr} + 8000f3c: 0fc4 lsrs r4, r0, #31 + 8000f3e: 0247 lsls r7, r0, #9 + 8000f40: 0a58 lsrs r0, r3, #9 + 8000f42: 4684 mov ip, r0 + 8000f44: 0048 lsls r0, r1, #1 + 8000f46: 0a7a lsrs r2, r7, #9 + 8000f48: 0e36 lsrs r6, r6, #24 + 8000f4a: 09bf lsrs r7, r7, #6 + 8000f4c: 0e00 lsrs r0, r0, #24 + 8000f4e: 0fcd lsrs r5, r1, #31 + 8000f50: 099b lsrs r3, r3, #6 + 8000f52: 28ff cmp r0, #255 @ 0xff + 8000f54: d06d beq.n 8001032 <__aeabi_fsub+0x102> + 8000f56: 2101 movs r1, #1 + 8000f58: 404d eors r5, r1 + 8000f5a: 1a31 subs r1, r6, r0 + 8000f5c: 42ac cmp r4, r5 + 8000f5e: d03a beq.n 8000fd6 <__aeabi_fsub+0xa6> + 8000f60: 2900 cmp r1, #0 + 8000f62: dc00 bgt.n 8000f66 <__aeabi_fsub+0x36> + 8000f64: e19c b.n 80012a0 <__aeabi_fsub+0x370> + 8000f66: 2800 cmp r0, #0 + 8000f68: d100 bne.n 8000f6c <__aeabi_fsub+0x3c> + 8000f6a: e09e b.n 80010aa <__aeabi_fsub+0x17a> + 8000f6c: 2eff cmp r6, #255 @ 0xff + 8000f6e: d100 bne.n 8000f72 <__aeabi_fsub+0x42> + 8000f70: e088 b.n 8001084 <__aeabi_fsub+0x154> + 8000f72: 2280 movs r2, #128 @ 0x80 + 8000f74: 04d2 lsls r2, r2, #19 + 8000f76: 4313 orrs r3, r2 + 8000f78: 291b cmp r1, #27 + 8000f7a: dc00 bgt.n 8000f7e <__aeabi_fsub+0x4e> + 8000f7c: e0f6 b.n 800116c <__aeabi_fsub+0x23c> + 8000f7e: 3f01 subs r7, #1 + 8000f80: 017a lsls r2, r7, #5 + 8000f82: d400 bmi.n 8000f86 <__aeabi_fsub+0x56> + 8000f84: e079 b.n 800107a <__aeabi_fsub+0x14a> + 8000f86: 2701 movs r7, #1 + 8000f88: 427f negs r7, r7 + 8000f8a: 01bf lsls r7, r7, #6 + 8000f8c: 09bb lsrs r3, r7, #6 + 8000f8e: 4698 mov r8, r3 + 8000f90: 4640 mov r0, r8 + 8000f92: f001 fa6d bl 8002470 <__clzsi2> + 8000f96: 4643 mov r3, r8 + 8000f98: 3805 subs r0, #5 + 8000f9a: 4083 lsls r3, r0 + 8000f9c: 4286 cmp r6, r0 + 8000f9e: dc00 bgt.n 8000fa2 <__aeabi_fsub+0x72> + 8000fa0: e0cc b.n 800113c <__aeabi_fsub+0x20c> + 8000fa2: 4fb4 ldr r7, [pc, #720] @ (8001274 <__aeabi_fsub+0x344>) + 8000fa4: 1a31 subs r1, r6, r0 + 8000fa6: 401f ands r7, r3 + 8000fa8: 075a lsls r2, r3, #29 + 8000faa: d068 beq.n 800107e <__aeabi_fsub+0x14e> + 8000fac: 220f movs r2, #15 + 8000fae: 4013 ands r3, r2 + 8000fb0: 2b04 cmp r3, #4 + 8000fb2: d064 beq.n 800107e <__aeabi_fsub+0x14e> + 8000fb4: 3704 adds r7, #4 + 8000fb6: 017b lsls r3, r7, #5 + 8000fb8: d561 bpl.n 800107e <__aeabi_fsub+0x14e> + 8000fba: 1c48 adds r0, r1, #1 + 8000fbc: 29fe cmp r1, #254 @ 0xfe + 8000fbe: d000 beq.n 8000fc2 <__aeabi_fsub+0x92> + 8000fc0: e081 b.n 80010c6 <__aeabi_fsub+0x196> + 8000fc2: 20ff movs r0, #255 @ 0xff + 8000fc4: 2300 movs r3, #0 + 8000fc6: 05c0 lsls r0, r0, #23 + 8000fc8: 4318 orrs r0, r3 + 8000fca: 07e4 lsls r4, r4, #31 + 8000fcc: 4320 orrs r0, r4 + 8000fce: bcc0 pop {r6, r7} + 8000fd0: 46b9 mov r9, r7 + 8000fd2: 46b0 mov r8, r6 + 8000fd4: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8000fd6: 2900 cmp r1, #0 + 8000fd8: dc00 bgt.n 8000fdc <__aeabi_fsub+0xac> + 8000fda: e179 b.n 80012d0 <__aeabi_fsub+0x3a0> + 8000fdc: 2800 cmp r0, #0 + 8000fde: d176 bne.n 80010ce <__aeabi_fsub+0x19e> + 8000fe0: 2b00 cmp r3, #0 + 8000fe2: d04c beq.n 800107e <__aeabi_fsub+0x14e> + 8000fe4: 1e48 subs r0, r1, #1 + 8000fe6: 2901 cmp r1, #1 + 8000fe8: d100 bne.n 8000fec <__aeabi_fsub+0xbc> + 8000fea: e147 b.n 800127c <__aeabi_fsub+0x34c> + 8000fec: 29ff cmp r1, #255 @ 0xff + 8000fee: d049 beq.n 8001084 <__aeabi_fsub+0x154> + 8000ff0: 281b cmp r0, #27 + 8000ff2: dc71 bgt.n 80010d8 <__aeabi_fsub+0x1a8> + 8000ff4: 0001 movs r1, r0 + 8000ff6: 001a movs r2, r3 + 8000ff8: 2020 movs r0, #32 + 8000ffa: 40ca lsrs r2, r1 + 8000ffc: 1a41 subs r1, r0, r1 + 8000ffe: 408b lsls r3, r1 + 8001000: 1e59 subs r1, r3, #1 + 8001002: 418b sbcs r3, r1 + 8001004: 4313 orrs r3, r2 + 8001006: 18ff adds r7, r7, r3 + 8001008: 2380 movs r3, #128 @ 0x80 + 800100a: 04db lsls r3, r3, #19 + 800100c: 421f tst r7, r3 + 800100e: d100 bne.n 8001012 <__aeabi_fsub+0xe2> + 8001010: e0b8 b.n 8001184 <__aeabi_fsub+0x254> + 8001012: 1c71 adds r1, r6, #1 + 8001014: 2efe cmp r6, #254 @ 0xfe + 8001016: d0d4 beq.n 8000fc2 <__aeabi_fsub+0x92> + 8001018: 2201 movs r2, #1 + 800101a: 4897 ldr r0, [pc, #604] @ (8001278 <__aeabi_fsub+0x348>) + 800101c: 403a ands r2, r7 + 800101e: 087f lsrs r7, r7, #1 + 8001020: 4007 ands r7, r0 + 8001022: 4317 orrs r7, r2 + 8001024: 077a lsls r2, r7, #29 + 8001026: d000 beq.n 800102a <__aeabi_fsub+0xfa> + 8001028: e096 b.n 8001158 <__aeabi_fsub+0x228> + 800102a: 421f tst r7, r3 + 800102c: d1c5 bne.n 8000fba <__aeabi_fsub+0x8a> + 800102e: 08fa lsrs r2, r7, #3 + 8001030: e055 b.n 80010de <__aeabi_fsub+0x1ae> + 8001032: 0031 movs r1, r6 + 8001034: 39ff subs r1, #255 @ 0xff + 8001036: 4689 mov r9, r1 + 8001038: 2b00 cmp r3, #0 + 800103a: d12c bne.n 8001096 <__aeabi_fsub+0x166> + 800103c: 2101 movs r1, #1 + 800103e: 404d eors r5, r1 + 8001040: 42ac cmp r4, r5 + 8001042: d100 bne.n 8001046 <__aeabi_fsub+0x116> + 8001044: e0b4 b.n 80011b0 <__aeabi_fsub+0x280> + 8001046: 4649 mov r1, r9 + 8001048: 2900 cmp r1, #0 + 800104a: d04c beq.n 80010e6 <__aeabi_fsub+0x1b6> + 800104c: 2e00 cmp r6, #0 + 800104e: d000 beq.n 8001052 <__aeabi_fsub+0x122> + 8001050: e0f9 b.n 8001246 <__aeabi_fsub+0x316> + 8001052: 21ff movs r1, #255 @ 0xff + 8001054: 2f00 cmp r7, #0 + 8001056: d100 bne.n 800105a <__aeabi_fsub+0x12a> + 8001058: e108 b.n 800126c <__aeabi_fsub+0x33c> + 800105a: 1e4a subs r2, r1, #1 + 800105c: 2901 cmp r1, #1 + 800105e: d100 bne.n 8001062 <__aeabi_fsub+0x132> + 8001060: e156 b.n 8001310 <__aeabi_fsub+0x3e0> + 8001062: 29ff cmp r1, #255 @ 0xff + 8001064: d100 bne.n 8001068 <__aeabi_fsub+0x138> + 8001066: e142 b.n 80012ee <__aeabi_fsub+0x3be> + 8001068: 2a1b cmp r2, #27 + 800106a: dc00 bgt.n 800106e <__aeabi_fsub+0x13e> + 800106c: e124 b.n 80012b8 <__aeabi_fsub+0x388> + 800106e: 1e5f subs r7, r3, #1 + 8001070: 002c movs r4, r5 + 8001072: 0006 movs r6, r0 + 8001074: 017a lsls r2, r7, #5 + 8001076: d500 bpl.n 800107a <__aeabi_fsub+0x14a> + 8001078: e785 b.n 8000f86 <__aeabi_fsub+0x56> + 800107a: 0031 movs r1, r6 + 800107c: 3704 adds r7, #4 + 800107e: 08fa lsrs r2, r7, #3 + 8001080: 29ff cmp r1, #255 @ 0xff + 8001082: d12c bne.n 80010de <__aeabi_fsub+0x1ae> + 8001084: 2a00 cmp r2, #0 + 8001086: d09c beq.n 8000fc2 <__aeabi_fsub+0x92> + 8001088: 2380 movs r3, #128 @ 0x80 + 800108a: 03db lsls r3, r3, #15 + 800108c: 4313 orrs r3, r2 + 800108e: 025b lsls r3, r3, #9 + 8001090: 20ff movs r0, #255 @ 0xff + 8001092: 0a5b lsrs r3, r3, #9 + 8001094: e797 b.n 8000fc6 <__aeabi_fsub+0x96> + 8001096: 42ac cmp r4, r5 + 8001098: d100 bne.n 800109c <__aeabi_fsub+0x16c> + 800109a: e0a7 b.n 80011ec <__aeabi_fsub+0x2bc> + 800109c: 2900 cmp r1, #0 + 800109e: d022 beq.n 80010e6 <__aeabi_fsub+0x1b6> + 80010a0: 2e00 cmp r6, #0 + 80010a2: d0d6 beq.n 8001052 <__aeabi_fsub+0x122> + 80010a4: 4662 mov r2, ip + 80010a6: 002c movs r4, r5 + 80010a8: e7ee b.n 8001088 <__aeabi_fsub+0x158> + 80010aa: 2b00 cmp r3, #0 + 80010ac: d0e7 beq.n 800107e <__aeabi_fsub+0x14e> + 80010ae: 1e48 subs r0, r1, #1 + 80010b0: 2901 cmp r1, #1 + 80010b2: d036 beq.n 8001122 <__aeabi_fsub+0x1f2> + 80010b4: 29ff cmp r1, #255 @ 0xff + 80010b6: d0e5 beq.n 8001084 <__aeabi_fsub+0x154> + 80010b8: 0001 movs r1, r0 + 80010ba: e75d b.n 8000f78 <__aeabi_fsub+0x48> + 80010bc: 2001 movs r0, #1 + 80010be: 003b movs r3, r7 + 80010c0: 017a lsls r2, r7, #5 + 80010c2: d400 bmi.n 80010c6 <__aeabi_fsub+0x196> + 80010c4: e157 b.n 8001376 <__aeabi_fsub+0x446> + 80010c6: b2c0 uxtb r0, r0 + 80010c8: 01bb lsls r3, r7, #6 + 80010ca: 0a5b lsrs r3, r3, #9 + 80010cc: e77b b.n 8000fc6 <__aeabi_fsub+0x96> + 80010ce: 2eff cmp r6, #255 @ 0xff + 80010d0: d0d8 beq.n 8001084 <__aeabi_fsub+0x154> + 80010d2: 291b cmp r1, #27 + 80010d4: dc00 bgt.n 80010d8 <__aeabi_fsub+0x1a8> + 80010d6: e09f b.n 8001218 <__aeabi_fsub+0x2e8> + 80010d8: 0031 movs r1, r6 + 80010da: 3705 adds r7, #5 + 80010dc: 08fa lsrs r2, r7, #3 + 80010de: 0253 lsls r3, r2, #9 + 80010e0: 0a5b lsrs r3, r3, #9 + 80010e2: b2c8 uxtb r0, r1 + 80010e4: e76f b.n 8000fc6 <__aeabi_fsub+0x96> + 80010e6: 20fe movs r0, #254 @ 0xfe + 80010e8: 1c71 adds r1, r6, #1 + 80010ea: 4208 tst r0, r1 + 80010ec: d154 bne.n 8001198 <__aeabi_fsub+0x268> + 80010ee: 2e00 cmp r6, #0 + 80010f0: d000 beq.n 80010f4 <__aeabi_fsub+0x1c4> + 80010f2: e0b1 b.n 8001258 <__aeabi_fsub+0x328> + 80010f4: 2f00 cmp r7, #0 + 80010f6: d100 bne.n 80010fa <__aeabi_fsub+0x1ca> + 80010f8: e102 b.n 8001300 <__aeabi_fsub+0x3d0> + 80010fa: 2b00 cmp r3, #0 + 80010fc: d100 bne.n 8001100 <__aeabi_fsub+0x1d0> + 80010fe: e0f9 b.n 80012f4 <__aeabi_fsub+0x3c4> + 8001100: 2180 movs r1, #128 @ 0x80 + 8001102: 1afa subs r2, r7, r3 + 8001104: 04c9 lsls r1, r1, #19 + 8001106: 420a tst r2, r1 + 8001108: d100 bne.n 800110c <__aeabi_fsub+0x1dc> + 800110a: e13b b.n 8001384 <__aeabi_fsub+0x454> + 800110c: 2401 movs r4, #1 + 800110e: 1bdf subs r7, r3, r7 + 8001110: 402c ands r4, r5 + 8001112: 2f00 cmp r7, #0 + 8001114: d049 beq.n 80011aa <__aeabi_fsub+0x27a> + 8001116: 2001 movs r0, #1 + 8001118: 420f tst r7, r1 + 800111a: d1d5 bne.n 80010c8 <__aeabi_fsub+0x198> + 800111c: 2100 movs r1, #0 + 800111e: 08fa lsrs r2, r7, #3 + 8001120: e7dd b.n 80010de <__aeabi_fsub+0x1ae> + 8001122: 1aff subs r7, r7, r3 + 8001124: 017b lsls r3, r7, #5 + 8001126: d400 bmi.n 800112a <__aeabi_fsub+0x1fa> + 8001128: e0de b.n 80012e8 <__aeabi_fsub+0x3b8> + 800112a: 01bd lsls r5, r7, #6 + 800112c: 09ad lsrs r5, r5, #6 + 800112e: 0028 movs r0, r5 + 8001130: f001 f99e bl 8002470 <__clzsi2> + 8001134: 002b movs r3, r5 + 8001136: 3805 subs r0, #5 + 8001138: 4083 lsls r3, r0 + 800113a: 2601 movs r6, #1 + 800113c: 2220 movs r2, #32 + 800113e: 1b81 subs r1, r0, r6 + 8001140: 3101 adds r1, #1 + 8001142: 1a52 subs r2, r2, r1 + 8001144: 001f movs r7, r3 + 8001146: 4093 lsls r3, r2 + 8001148: 40cf lsrs r7, r1 + 800114a: 1e5a subs r2, r3, #1 + 800114c: 4193 sbcs r3, r2 + 800114e: 431f orrs r7, r3 + 8001150: d02b beq.n 80011aa <__aeabi_fsub+0x27a> + 8001152: 2100 movs r1, #0 + 8001154: 077b lsls r3, r7, #29 + 8001156: d0b1 beq.n 80010bc <__aeabi_fsub+0x18c> + 8001158: 230f movs r3, #15 + 800115a: 403b ands r3, r7 + 800115c: 2b04 cmp r3, #4 + 800115e: d000 beq.n 8001162 <__aeabi_fsub+0x232> + 8001160: e728 b.n 8000fb4 <__aeabi_fsub+0x84> + 8001162: 017b lsls r3, r7, #5 + 8001164: d500 bpl.n 8001168 <__aeabi_fsub+0x238> + 8001166: e728 b.n 8000fba <__aeabi_fsub+0x8a> + 8001168: 08fa lsrs r2, r7, #3 + 800116a: e7b8 b.n 80010de <__aeabi_fsub+0x1ae> + 800116c: 001a movs r2, r3 + 800116e: 2020 movs r0, #32 + 8001170: 40ca lsrs r2, r1 + 8001172: 1a41 subs r1, r0, r1 + 8001174: 408b lsls r3, r1 + 8001176: 1e59 subs r1, r3, #1 + 8001178: 418b sbcs r3, r1 + 800117a: 4313 orrs r3, r2 + 800117c: 1aff subs r7, r7, r3 + 800117e: 017b lsls r3, r7, #5 + 8001180: d500 bpl.n 8001184 <__aeabi_fsub+0x254> + 8001182: e702 b.n 8000f8a <__aeabi_fsub+0x5a> + 8001184: 077b lsls r3, r7, #29 + 8001186: d100 bne.n 800118a <__aeabi_fsub+0x25a> + 8001188: e10d b.n 80013a6 <__aeabi_fsub+0x476> + 800118a: 230f movs r3, #15 + 800118c: 0031 movs r1, r6 + 800118e: 403b ands r3, r7 + 8001190: 2b04 cmp r3, #4 + 8001192: d000 beq.n 8001196 <__aeabi_fsub+0x266> + 8001194: e70e b.n 8000fb4 <__aeabi_fsub+0x84> + 8001196: e772 b.n 800107e <__aeabi_fsub+0x14e> + 8001198: 1afa subs r2, r7, r3 + 800119a: 4690 mov r8, r2 + 800119c: 0152 lsls r2, r2, #5 + 800119e: d456 bmi.n 800124e <__aeabi_fsub+0x31e> + 80011a0: 4643 mov r3, r8 + 80011a2: 2b00 cmp r3, #0 + 80011a4: d000 beq.n 80011a8 <__aeabi_fsub+0x278> + 80011a6: e6f3 b.n 8000f90 <__aeabi_fsub+0x60> + 80011a8: 2400 movs r4, #0 + 80011aa: 2000 movs r0, #0 + 80011ac: 2300 movs r3, #0 + 80011ae: e70a b.n 8000fc6 <__aeabi_fsub+0x96> + 80011b0: 4649 mov r1, r9 + 80011b2: 2900 cmp r1, #0 + 80011b4: d01c beq.n 80011f0 <__aeabi_fsub+0x2c0> + 80011b6: 2e00 cmp r6, #0 + 80011b8: d000 beq.n 80011bc <__aeabi_fsub+0x28c> + 80011ba: e702 b.n 8000fc2 <__aeabi_fsub+0x92> + 80011bc: 21ff movs r1, #255 @ 0xff + 80011be: 2f00 cmp r7, #0 + 80011c0: d055 beq.n 800126e <__aeabi_fsub+0x33e> + 80011c2: 1e4a subs r2, r1, #1 + 80011c4: 2901 cmp r1, #1 + 80011c6: d059 beq.n 800127c <__aeabi_fsub+0x34c> + 80011c8: 29ff cmp r1, #255 @ 0xff + 80011ca: d100 bne.n 80011ce <__aeabi_fsub+0x29e> + 80011cc: e090 b.n 80012f0 <__aeabi_fsub+0x3c0> + 80011ce: 2a1b cmp r2, #27 + 80011d0: dd00 ble.n 80011d4 <__aeabi_fsub+0x2a4> + 80011d2: e091 b.n 80012f8 <__aeabi_fsub+0x3c8> + 80011d4: 0011 movs r1, r2 + 80011d6: 003a movs r2, r7 + 80011d8: 2520 movs r5, #32 + 80011da: 40ca lsrs r2, r1 + 80011dc: 1a69 subs r1, r5, r1 + 80011de: 408f lsls r7, r1 + 80011e0: 1e79 subs r1, r7, #1 + 80011e2: 418f sbcs r7, r1 + 80011e4: 4317 orrs r7, r2 + 80011e6: 0006 movs r6, r0 + 80011e8: 18ff adds r7, r7, r3 + 80011ea: e70d b.n 8001008 <__aeabi_fsub+0xd8> + 80011ec: 2900 cmp r1, #0 + 80011ee: d126 bne.n 800123e <__aeabi_fsub+0x30e> + 80011f0: 20fe movs r0, #254 @ 0xfe + 80011f2: 1c71 adds r1, r6, #1 + 80011f4: 4208 tst r0, r1 + 80011f6: d113 bne.n 8001220 <__aeabi_fsub+0x2f0> + 80011f8: 2e00 cmp r6, #0 + 80011fa: d000 beq.n 80011fe <__aeabi_fsub+0x2ce> + 80011fc: e096 b.n 800132c <__aeabi_fsub+0x3fc> + 80011fe: 2f00 cmp r7, #0 + 8001200: d100 bne.n 8001204 <__aeabi_fsub+0x2d4> + 8001202: e0b4 b.n 800136e <__aeabi_fsub+0x43e> + 8001204: 2b00 cmp r3, #0 + 8001206: d075 beq.n 80012f4 <__aeabi_fsub+0x3c4> + 8001208: 18fb adds r3, r7, r3 + 800120a: 015a lsls r2, r3, #5 + 800120c: d400 bmi.n 8001210 <__aeabi_fsub+0x2e0> + 800120e: e0b2 b.n 8001376 <__aeabi_fsub+0x446> + 8001210: 019b lsls r3, r3, #6 + 8001212: 0a5b lsrs r3, r3, #9 + 8001214: 38fd subs r0, #253 @ 0xfd + 8001216: e6d6 b.n 8000fc6 <__aeabi_fsub+0x96> + 8001218: 2280 movs r2, #128 @ 0x80 + 800121a: 04d2 lsls r2, r2, #19 + 800121c: 4313 orrs r3, r2 + 800121e: e6ea b.n 8000ff6 <__aeabi_fsub+0xc6> + 8001220: 29ff cmp r1, #255 @ 0xff + 8001222: d100 bne.n 8001226 <__aeabi_fsub+0x2f6> + 8001224: e6cd b.n 8000fc2 <__aeabi_fsub+0x92> + 8001226: 18fa adds r2, r7, r3 + 8001228: 0852 lsrs r2, r2, #1 + 800122a: 0753 lsls r3, r2, #29 + 800122c: d005 beq.n 800123a <__aeabi_fsub+0x30a> + 800122e: 230f movs r3, #15 + 8001230: 1d17 adds r7, r2, #4 + 8001232: 4013 ands r3, r2 + 8001234: 2b04 cmp r3, #4 + 8001236: d000 beq.n 800123a <__aeabi_fsub+0x30a> + 8001238: e721 b.n 800107e <__aeabi_fsub+0x14e> + 800123a: 08d2 lsrs r2, r2, #3 + 800123c: e74f b.n 80010de <__aeabi_fsub+0x1ae> + 800123e: 2e00 cmp r6, #0 + 8001240: d0bc beq.n 80011bc <__aeabi_fsub+0x28c> + 8001242: 4662 mov r2, ip + 8001244: e720 b.n 8001088 <__aeabi_fsub+0x158> + 8001246: 002c movs r4, r5 + 8001248: 20ff movs r0, #255 @ 0xff + 800124a: 2300 movs r3, #0 + 800124c: e6bb b.n 8000fc6 <__aeabi_fsub+0x96> + 800124e: 2401 movs r4, #1 + 8001250: 1bdb subs r3, r3, r7 + 8001252: 4698 mov r8, r3 + 8001254: 402c ands r4, r5 + 8001256: e69b b.n 8000f90 <__aeabi_fsub+0x60> + 8001258: 2f00 cmp r7, #0 + 800125a: d175 bne.n 8001348 <__aeabi_fsub+0x418> + 800125c: 2b00 cmp r3, #0 + 800125e: d000 beq.n 8001262 <__aeabi_fsub+0x332> + 8001260: e096 b.n 8001390 <__aeabi_fsub+0x460> + 8001262: 2380 movs r3, #128 @ 0x80 + 8001264: 2400 movs r4, #0 + 8001266: 20ff movs r0, #255 @ 0xff + 8001268: 03db lsls r3, r3, #15 + 800126a: e6ac b.n 8000fc6 <__aeabi_fsub+0x96> + 800126c: 002c movs r4, r5 + 800126e: 001f movs r7, r3 + 8001270: e705 b.n 800107e <__aeabi_fsub+0x14e> + 8001272: 46c0 nop @ (mov r8, r8) + 8001274: fbffffff .word 0xfbffffff + 8001278: 7dffffff .word 0x7dffffff + 800127c: 18fb adds r3, r7, r3 + 800127e: 015a lsls r2, r3, #5 + 8001280: d400 bmi.n 8001284 <__aeabi_fsub+0x354> + 8001282: e08d b.n 80013a0 <__aeabi_fsub+0x470> + 8001284: 4a4a ldr r2, [pc, #296] @ (80013b0 <__aeabi_fsub+0x480>) + 8001286: 085b lsrs r3, r3, #1 + 8001288: 401a ands r2, r3 + 800128a: 0759 lsls r1, r3, #29 + 800128c: d100 bne.n 8001290 <__aeabi_fsub+0x360> + 800128e: e08c b.n 80013aa <__aeabi_fsub+0x47a> + 8001290: 210f movs r1, #15 + 8001292: 400b ands r3, r1 + 8001294: 390d subs r1, #13 + 8001296: 2b04 cmp r3, #4 + 8001298: d0cf beq.n 800123a <__aeabi_fsub+0x30a> + 800129a: 2102 movs r1, #2 + 800129c: 1d17 adds r7, r2, #4 + 800129e: e6ee b.n 800107e <__aeabi_fsub+0x14e> + 80012a0: 2900 cmp r1, #0 + 80012a2: d100 bne.n 80012a6 <__aeabi_fsub+0x376> + 80012a4: e71f b.n 80010e6 <__aeabi_fsub+0x1b6> + 80012a6: 1b82 subs r2, r0, r6 + 80012a8: 0011 movs r1, r2 + 80012aa: 2e00 cmp r6, #0 + 80012ac: d100 bne.n 80012b0 <__aeabi_fsub+0x380> + 80012ae: e6d1 b.n 8001054 <__aeabi_fsub+0x124> + 80012b0: 2180 movs r1, #128 @ 0x80 + 80012b2: 04c9 lsls r1, r1, #19 + 80012b4: 430f orrs r7, r1 + 80012b6: e6d7 b.n 8001068 <__aeabi_fsub+0x138> + 80012b8: 0039 movs r1, r7 + 80012ba: 2420 movs r4, #32 + 80012bc: 40d1 lsrs r1, r2 + 80012be: 1aa2 subs r2, r4, r2 + 80012c0: 4097 lsls r7, r2 + 80012c2: 1e7a subs r2, r7, #1 + 80012c4: 4197 sbcs r7, r2 + 80012c6: 430f orrs r7, r1 + 80012c8: 002c movs r4, r5 + 80012ca: 0006 movs r6, r0 + 80012cc: 1bdf subs r7, r3, r7 + 80012ce: e756 b.n 800117e <__aeabi_fsub+0x24e> + 80012d0: 2900 cmp r1, #0 + 80012d2: d08d beq.n 80011f0 <__aeabi_fsub+0x2c0> + 80012d4: 1b81 subs r1, r0, r6 + 80012d6: 2e00 cmp r6, #0 + 80012d8: d100 bne.n 80012dc <__aeabi_fsub+0x3ac> + 80012da: e770 b.n 80011be <__aeabi_fsub+0x28e> + 80012dc: 291b cmp r1, #27 + 80012de: dc0b bgt.n 80012f8 <__aeabi_fsub+0x3c8> + 80012e0: 2280 movs r2, #128 @ 0x80 + 80012e2: 04d2 lsls r2, r2, #19 + 80012e4: 4317 orrs r7, r2 + 80012e6: e776 b.n 80011d6 <__aeabi_fsub+0x2a6> + 80012e8: 2101 movs r1, #1 + 80012ea: 08fa lsrs r2, r7, #3 + 80012ec: e6f7 b.n 80010de <__aeabi_fsub+0x1ae> + 80012ee: 002c movs r4, r5 + 80012f0: 4662 mov r2, ip + 80012f2: e6c7 b.n 8001084 <__aeabi_fsub+0x154> + 80012f4: 2100 movs r1, #0 + 80012f6: e6f2 b.n 80010de <__aeabi_fsub+0x1ae> + 80012f8: 3305 adds r3, #5 + 80012fa: 0001 movs r1, r0 + 80012fc: 08da lsrs r2, r3, #3 + 80012fe: e6ee b.n 80010de <__aeabi_fsub+0x1ae> + 8001300: 2b00 cmp r3, #0 + 8001302: d100 bne.n 8001306 <__aeabi_fsub+0x3d6> + 8001304: e750 b.n 80011a8 <__aeabi_fsub+0x278> + 8001306: 2401 movs r4, #1 + 8001308: 2100 movs r1, #0 + 800130a: 4662 mov r2, ip + 800130c: 402c ands r4, r5 + 800130e: e6e6 b.n 80010de <__aeabi_fsub+0x1ae> + 8001310: 1bda subs r2, r3, r7 + 8001312: 0153 lsls r3, r2, #5 + 8001314: d532 bpl.n 800137c <__aeabi_fsub+0x44c> + 8001316: 0192 lsls r2, r2, #6 + 8001318: 0994 lsrs r4, r2, #6 + 800131a: 0020 movs r0, r4 + 800131c: f001 f8a8 bl 8002470 <__clzsi2> + 8001320: 0023 movs r3, r4 + 8001322: 3805 subs r0, #5 + 8001324: 4083 lsls r3, r0 + 8001326: 002c movs r4, r5 + 8001328: 2601 movs r6, #1 + 800132a: e707 b.n 800113c <__aeabi_fsub+0x20c> + 800132c: 2f00 cmp r7, #0 + 800132e: d0df beq.n 80012f0 <__aeabi_fsub+0x3c0> + 8001330: 2b00 cmp r3, #0 + 8001332: d017 beq.n 8001364 <__aeabi_fsub+0x434> + 8001334: 2380 movs r3, #128 @ 0x80 + 8001336: 03db lsls r3, r3, #15 + 8001338: 429a cmp r2, r3 + 800133a: d200 bcs.n 800133e <__aeabi_fsub+0x40e> + 800133c: e6a4 b.n 8001088 <__aeabi_fsub+0x158> + 800133e: 459c cmp ip, r3 + 8001340: d300 bcc.n 8001344 <__aeabi_fsub+0x414> + 8001342: e6a1 b.n 8001088 <__aeabi_fsub+0x158> + 8001344: 4662 mov r2, ip + 8001346: e69f b.n 8001088 <__aeabi_fsub+0x158> + 8001348: 2b00 cmp r3, #0 + 800134a: d00b beq.n 8001364 <__aeabi_fsub+0x434> + 800134c: 2380 movs r3, #128 @ 0x80 + 800134e: 03db lsls r3, r3, #15 + 8001350: 429a cmp r2, r3 + 8001352: d200 bcs.n 8001356 <__aeabi_fsub+0x426> + 8001354: e698 b.n 8001088 <__aeabi_fsub+0x158> + 8001356: 459c cmp ip, r3 + 8001358: d300 bcc.n 800135c <__aeabi_fsub+0x42c> + 800135a: e695 b.n 8001088 <__aeabi_fsub+0x158> + 800135c: 2401 movs r4, #1 + 800135e: 4662 mov r2, ip + 8001360: 402c ands r4, r5 + 8001362: e691 b.n 8001088 <__aeabi_fsub+0x158> + 8001364: 2380 movs r3, #128 @ 0x80 + 8001366: 03db lsls r3, r3, #15 + 8001368: 20ff movs r0, #255 @ 0xff + 800136a: 4313 orrs r3, r2 + 800136c: e62b b.n 8000fc6 <__aeabi_fsub+0x96> + 800136e: 2000 movs r0, #0 + 8001370: 2b00 cmp r3, #0 + 8001372: d100 bne.n 8001376 <__aeabi_fsub+0x446> + 8001374: e627 b.n 8000fc6 <__aeabi_fsub+0x96> + 8001376: 2100 movs r1, #0 + 8001378: 08da lsrs r2, r3, #3 + 800137a: e6b0 b.n 80010de <__aeabi_fsub+0x1ae> + 800137c: 002c movs r4, r5 + 800137e: 2101 movs r1, #1 + 8001380: 08d2 lsrs r2, r2, #3 + 8001382: e6ac b.n 80010de <__aeabi_fsub+0x1ae> + 8001384: 2a00 cmp r2, #0 + 8001386: d100 bne.n 800138a <__aeabi_fsub+0x45a> + 8001388: e70e b.n 80011a8 <__aeabi_fsub+0x278> + 800138a: 2100 movs r1, #0 + 800138c: 08d2 lsrs r2, r2, #3 + 800138e: e6a6 b.n 80010de <__aeabi_fsub+0x1ae> + 8001390: 2380 movs r3, #128 @ 0x80 + 8001392: 4662 mov r2, ip + 8001394: 2401 movs r4, #1 + 8001396: 03db lsls r3, r3, #15 + 8001398: 20ff movs r0, #255 @ 0xff + 800139a: 4313 orrs r3, r2 + 800139c: 402c ands r4, r5 + 800139e: e612 b.n 8000fc6 <__aeabi_fsub+0x96> + 80013a0: 2101 movs r1, #1 + 80013a2: 08da lsrs r2, r3, #3 + 80013a4: e69b b.n 80010de <__aeabi_fsub+0x1ae> + 80013a6: 0031 movs r1, r6 + 80013a8: e669 b.n 800107e <__aeabi_fsub+0x14e> + 80013aa: 2102 movs r1, #2 + 80013ac: 08d2 lsrs r2, r2, #3 + 80013ae: e696 b.n 80010de <__aeabi_fsub+0x1ae> + 80013b0: 7dffffff .word 0x7dffffff + +080013b4 <__aeabi_f2iz>: + 80013b4: 0241 lsls r1, r0, #9 + 80013b6: 0042 lsls r2, r0, #1 + 80013b8: 0fc3 lsrs r3, r0, #31 + 80013ba: 0a49 lsrs r1, r1, #9 + 80013bc: 2000 movs r0, #0 + 80013be: 0e12 lsrs r2, r2, #24 + 80013c0: 2a7e cmp r2, #126 @ 0x7e + 80013c2: dd03 ble.n 80013cc <__aeabi_f2iz+0x18> + 80013c4: 2a9d cmp r2, #157 @ 0x9d + 80013c6: dd02 ble.n 80013ce <__aeabi_f2iz+0x1a> + 80013c8: 4a09 ldr r2, [pc, #36] @ (80013f0 <__aeabi_f2iz+0x3c>) + 80013ca: 1898 adds r0, r3, r2 + 80013cc: 4770 bx lr + 80013ce: 2080 movs r0, #128 @ 0x80 + 80013d0: 0400 lsls r0, r0, #16 + 80013d2: 4301 orrs r1, r0 + 80013d4: 2a95 cmp r2, #149 @ 0x95 + 80013d6: dc07 bgt.n 80013e8 <__aeabi_f2iz+0x34> + 80013d8: 2096 movs r0, #150 @ 0x96 + 80013da: 1a82 subs r2, r0, r2 + 80013dc: 40d1 lsrs r1, r2 + 80013de: 4248 negs r0, r1 + 80013e0: 2b00 cmp r3, #0 + 80013e2: d1f3 bne.n 80013cc <__aeabi_f2iz+0x18> + 80013e4: 0008 movs r0, r1 + 80013e6: e7f1 b.n 80013cc <__aeabi_f2iz+0x18> + 80013e8: 3a96 subs r2, #150 @ 0x96 + 80013ea: 4091 lsls r1, r2 + 80013ec: e7f7 b.n 80013de <__aeabi_f2iz+0x2a> + 80013ee: 46c0 nop @ (mov r8, r8) + 80013f0: 7fffffff .word 0x7fffffff + +080013f4 <__aeabi_i2f>: + 80013f4: b570 push {r4, r5, r6, lr} + 80013f6: 2800 cmp r0, #0 + 80013f8: d012 beq.n 8001420 <__aeabi_i2f+0x2c> + 80013fa: 17c3 asrs r3, r0, #31 + 80013fc: 18c5 adds r5, r0, r3 + 80013fe: 405d eors r5, r3 + 8001400: 0fc4 lsrs r4, r0, #31 + 8001402: 0028 movs r0, r5 + 8001404: f001 f834 bl 8002470 <__clzsi2> + 8001408: 239e movs r3, #158 @ 0x9e + 800140a: 1a1b subs r3, r3, r0 + 800140c: 2b96 cmp r3, #150 @ 0x96 + 800140e: dc0f bgt.n 8001430 <__aeabi_i2f+0x3c> + 8001410: 2808 cmp r0, #8 + 8001412: d038 beq.n 8001486 <__aeabi_i2f+0x92> + 8001414: 3808 subs r0, #8 + 8001416: 4085 lsls r5, r0 + 8001418: 026d lsls r5, r5, #9 + 800141a: 0a6d lsrs r5, r5, #9 + 800141c: b2d8 uxtb r0, r3 + 800141e: e002 b.n 8001426 <__aeabi_i2f+0x32> + 8001420: 2400 movs r4, #0 + 8001422: 2000 movs r0, #0 + 8001424: 2500 movs r5, #0 + 8001426: 05c0 lsls r0, r0, #23 + 8001428: 4328 orrs r0, r5 + 800142a: 07e4 lsls r4, r4, #31 + 800142c: 4320 orrs r0, r4 + 800142e: bd70 pop {r4, r5, r6, pc} + 8001430: 2b99 cmp r3, #153 @ 0x99 + 8001432: dc14 bgt.n 800145e <__aeabi_i2f+0x6a> + 8001434: 1f42 subs r2, r0, #5 + 8001436: 4095 lsls r5, r2 + 8001438: 002a movs r2, r5 + 800143a: 4915 ldr r1, [pc, #84] @ (8001490 <__aeabi_i2f+0x9c>) + 800143c: 4011 ands r1, r2 + 800143e: 0755 lsls r5, r2, #29 + 8001440: d01c beq.n 800147c <__aeabi_i2f+0x88> + 8001442: 250f movs r5, #15 + 8001444: 402a ands r2, r5 + 8001446: 2a04 cmp r2, #4 + 8001448: d018 beq.n 800147c <__aeabi_i2f+0x88> + 800144a: 3104 adds r1, #4 + 800144c: 08ca lsrs r2, r1, #3 + 800144e: 0149 lsls r1, r1, #5 + 8001450: d515 bpl.n 800147e <__aeabi_i2f+0x8a> + 8001452: 239f movs r3, #159 @ 0x9f + 8001454: 0252 lsls r2, r2, #9 + 8001456: 1a18 subs r0, r3, r0 + 8001458: 0a55 lsrs r5, r2, #9 + 800145a: b2c0 uxtb r0, r0 + 800145c: e7e3 b.n 8001426 <__aeabi_i2f+0x32> + 800145e: 0002 movs r2, r0 + 8001460: 0029 movs r1, r5 + 8001462: 321b adds r2, #27 + 8001464: 4091 lsls r1, r2 + 8001466: 1e4a subs r2, r1, #1 + 8001468: 4191 sbcs r1, r2 + 800146a: 2205 movs r2, #5 + 800146c: 1a12 subs r2, r2, r0 + 800146e: 40d5 lsrs r5, r2 + 8001470: 002a movs r2, r5 + 8001472: 430a orrs r2, r1 + 8001474: 4906 ldr r1, [pc, #24] @ (8001490 <__aeabi_i2f+0x9c>) + 8001476: 4011 ands r1, r2 + 8001478: 0755 lsls r5, r2, #29 + 800147a: d1e2 bne.n 8001442 <__aeabi_i2f+0x4e> + 800147c: 08ca lsrs r2, r1, #3 + 800147e: 0252 lsls r2, r2, #9 + 8001480: 0a55 lsrs r5, r2, #9 + 8001482: b2d8 uxtb r0, r3 + 8001484: e7cf b.n 8001426 <__aeabi_i2f+0x32> + 8001486: 026d lsls r5, r5, #9 + 8001488: 0a6d lsrs r5, r5, #9 + 800148a: 308e adds r0, #142 @ 0x8e + 800148c: e7cb b.n 8001426 <__aeabi_i2f+0x32> + 800148e: 46c0 nop @ (mov r8, r8) + 8001490: fbffffff .word 0xfbffffff + +08001494 <__aeabi_ui2f>: + 8001494: b510 push {r4, lr} + 8001496: 1e04 subs r4, r0, #0 + 8001498: d00d beq.n 80014b6 <__aeabi_ui2f+0x22> + 800149a: f000 ffe9 bl 8002470 <__clzsi2> + 800149e: 239e movs r3, #158 @ 0x9e + 80014a0: 1a1b subs r3, r3, r0 + 80014a2: 2b96 cmp r3, #150 @ 0x96 + 80014a4: dc0c bgt.n 80014c0 <__aeabi_ui2f+0x2c> + 80014a6: 2808 cmp r0, #8 + 80014a8: d034 beq.n 8001514 <__aeabi_ui2f+0x80> + 80014aa: 3808 subs r0, #8 + 80014ac: 4084 lsls r4, r0 + 80014ae: 0264 lsls r4, r4, #9 + 80014b0: 0a64 lsrs r4, r4, #9 + 80014b2: b2d8 uxtb r0, r3 + 80014b4: e001 b.n 80014ba <__aeabi_ui2f+0x26> + 80014b6: 2000 movs r0, #0 + 80014b8: 2400 movs r4, #0 + 80014ba: 05c0 lsls r0, r0, #23 + 80014bc: 4320 orrs r0, r4 + 80014be: bd10 pop {r4, pc} + 80014c0: 2b99 cmp r3, #153 @ 0x99 + 80014c2: dc13 bgt.n 80014ec <__aeabi_ui2f+0x58> + 80014c4: 1f42 subs r2, r0, #5 + 80014c6: 4094 lsls r4, r2 + 80014c8: 4a14 ldr r2, [pc, #80] @ (800151c <__aeabi_ui2f+0x88>) + 80014ca: 4022 ands r2, r4 + 80014cc: 0761 lsls r1, r4, #29 + 80014ce: d01c beq.n 800150a <__aeabi_ui2f+0x76> + 80014d0: 210f movs r1, #15 + 80014d2: 4021 ands r1, r4 + 80014d4: 2904 cmp r1, #4 + 80014d6: d018 beq.n 800150a <__aeabi_ui2f+0x76> + 80014d8: 3204 adds r2, #4 + 80014da: 08d4 lsrs r4, r2, #3 + 80014dc: 0152 lsls r2, r2, #5 + 80014de: d515 bpl.n 800150c <__aeabi_ui2f+0x78> + 80014e0: 239f movs r3, #159 @ 0x9f + 80014e2: 0264 lsls r4, r4, #9 + 80014e4: 1a18 subs r0, r3, r0 + 80014e6: 0a64 lsrs r4, r4, #9 + 80014e8: b2c0 uxtb r0, r0 + 80014ea: e7e6 b.n 80014ba <__aeabi_ui2f+0x26> + 80014ec: 0002 movs r2, r0 + 80014ee: 0021 movs r1, r4 + 80014f0: 321b adds r2, #27 + 80014f2: 4091 lsls r1, r2 + 80014f4: 000a movs r2, r1 + 80014f6: 1e51 subs r1, r2, #1 + 80014f8: 418a sbcs r2, r1 + 80014fa: 2105 movs r1, #5 + 80014fc: 1a09 subs r1, r1, r0 + 80014fe: 40cc lsrs r4, r1 + 8001500: 4314 orrs r4, r2 + 8001502: 4a06 ldr r2, [pc, #24] @ (800151c <__aeabi_ui2f+0x88>) + 8001504: 4022 ands r2, r4 + 8001506: 0761 lsls r1, r4, #29 + 8001508: d1e2 bne.n 80014d0 <__aeabi_ui2f+0x3c> + 800150a: 08d4 lsrs r4, r2, #3 + 800150c: 0264 lsls r4, r4, #9 + 800150e: 0a64 lsrs r4, r4, #9 + 8001510: b2d8 uxtb r0, r3 + 8001512: e7d2 b.n 80014ba <__aeabi_ui2f+0x26> + 8001514: 0264 lsls r4, r4, #9 + 8001516: 0a64 lsrs r4, r4, #9 + 8001518: 308e adds r0, #142 @ 0x8e + 800151a: e7ce b.n 80014ba <__aeabi_ui2f+0x26> + 800151c: fbffffff .word 0xfbffffff + +08001520 <__aeabi_dmul>: + 8001520: b5f0 push {r4, r5, r6, r7, lr} + 8001522: 4657 mov r7, sl + 8001524: 464e mov r6, r9 + 8001526: 4645 mov r5, r8 + 8001528: 46de mov lr, fp + 800152a: b5e0 push {r5, r6, r7, lr} + 800152c: 001f movs r7, r3 + 800152e: 030b lsls r3, r1, #12 + 8001530: 0b1b lsrs r3, r3, #12 + 8001532: 0016 movs r6, r2 + 8001534: 4698 mov r8, r3 + 8001536: 0fca lsrs r2, r1, #31 + 8001538: 004b lsls r3, r1, #1 + 800153a: 0004 movs r4, r0 + 800153c: 4692 mov sl, r2 + 800153e: b085 sub sp, #20 + 8001540: 0d5b lsrs r3, r3, #21 + 8001542: d100 bne.n 8001546 <__aeabi_dmul+0x26> + 8001544: e1c2 b.n 80018cc <__aeabi_dmul+0x3ac> + 8001546: 4acc ldr r2, [pc, #816] @ (8001878 <__aeabi_dmul+0x358>) + 8001548: 4293 cmp r3, r2 + 800154a: d100 bne.n 800154e <__aeabi_dmul+0x2e> + 800154c: e128 b.n 80017a0 <__aeabi_dmul+0x280> + 800154e: 4641 mov r1, r8 + 8001550: 0f42 lsrs r2, r0, #29 + 8001552: 00c9 lsls r1, r1, #3 + 8001554: 430a orrs r2, r1 + 8001556: 2180 movs r1, #128 @ 0x80 + 8001558: 0409 lsls r1, r1, #16 + 800155a: 4311 orrs r1, r2 + 800155c: 00c2 lsls r2, r0, #3 + 800155e: 4691 mov r9, r2 + 8001560: 4ac6 ldr r2, [pc, #792] @ (800187c <__aeabi_dmul+0x35c>) + 8001562: 4688 mov r8, r1 + 8001564: 4693 mov fp, r2 + 8001566: 449b add fp, r3 + 8001568: 2300 movs r3, #0 + 800156a: 2500 movs r5, #0 + 800156c: 9301 str r3, [sp, #4] + 800156e: 033c lsls r4, r7, #12 + 8001570: 007a lsls r2, r7, #1 + 8001572: 0ffb lsrs r3, r7, #31 + 8001574: 0030 movs r0, r6 + 8001576: 0b24 lsrs r4, r4, #12 + 8001578: 0d52 lsrs r2, r2, #21 + 800157a: 9300 str r3, [sp, #0] + 800157c: d100 bne.n 8001580 <__aeabi_dmul+0x60> + 800157e: e185 b.n 800188c <__aeabi_dmul+0x36c> + 8001580: 4bbd ldr r3, [pc, #756] @ (8001878 <__aeabi_dmul+0x358>) + 8001582: 429a cmp r2, r3 + 8001584: d100 bne.n 8001588 <__aeabi_dmul+0x68> + 8001586: e160 b.n 800184a <__aeabi_dmul+0x32a> + 8001588: 4bbc ldr r3, [pc, #752] @ (800187c <__aeabi_dmul+0x35c>) + 800158a: 469c mov ip, r3 + 800158c: 4462 add r2, ip + 800158e: 4493 add fp, r2 + 8001590: 2d0a cmp r5, #10 + 8001592: dd00 ble.n 8001596 <__aeabi_dmul+0x76> + 8001594: e114 b.n 80017c0 <__aeabi_dmul+0x2a0> + 8001596: 0f73 lsrs r3, r6, #29 + 8001598: 00e4 lsls r4, r4, #3 + 800159a: 431c orrs r4, r3 + 800159c: 2380 movs r3, #128 @ 0x80 + 800159e: 041b lsls r3, r3, #16 + 80015a0: 4323 orrs r3, r4 + 80015a2: 00f0 lsls r0, r6, #3 + 80015a4: 4652 mov r2, sl + 80015a6: 9900 ldr r1, [sp, #0] + 80015a8: 2600 movs r6, #0 + 80015aa: 404a eors r2, r1 + 80015ac: 4692 mov sl, r2 + 80015ae: 2d02 cmp r5, #2 + 80015b0: dd11 ble.n 80015d6 <__aeabi_dmul+0xb6> + 80015b2: 2201 movs r2, #1 + 80015b4: 40aa lsls r2, r5 + 80015b6: 21a6 movs r1, #166 @ 0xa6 + 80015b8: 0014 movs r4, r2 + 80015ba: 00c9 lsls r1, r1, #3 + 80015bc: 400c ands r4, r1 + 80015be: 420a tst r2, r1 + 80015c0: d000 beq.n 80015c4 <__aeabi_dmul+0xa4> + 80015c2: e0fd b.n 80017c0 <__aeabi_dmul+0x2a0> + 80015c4: 2190 movs r1, #144 @ 0x90 + 80015c6: 0089 lsls r1, r1, #2 + 80015c8: 420a tst r2, r1 + 80015ca: d000 beq.n 80015ce <__aeabi_dmul+0xae> + 80015cc: e1d4 b.n 8001978 <__aeabi_dmul+0x458> + 80015ce: 2188 movs r1, #136 @ 0x88 + 80015d0: 4211 tst r1, r2 + 80015d2: d000 beq.n 80015d6 <__aeabi_dmul+0xb6> + 80015d4: e0ef b.n 80017b6 <__aeabi_dmul+0x296> + 80015d6: 4649 mov r1, r9 + 80015d8: 464a mov r2, r9 + 80015da: 0409 lsls r1, r1, #16 + 80015dc: 0c14 lsrs r4, r2, #16 + 80015de: 0c09 lsrs r1, r1, #16 + 80015e0: 0c02 lsrs r2, r0, #16 + 80015e2: 000f movs r7, r1 + 80015e4: 0015 movs r5, r2 + 80015e6: 0400 lsls r0, r0, #16 + 80015e8: 0c00 lsrs r0, r0, #16 + 80015ea: 4365 muls r5, r4 + 80015ec: 4347 muls r7, r0 + 80015ee: 9501 str r5, [sp, #4] + 80015f0: 46b9 mov r9, r7 + 80015f2: 002f movs r7, r5 + 80015f4: 000d movs r5, r1 + 80015f6: 0006 movs r6, r0 + 80015f8: 4355 muls r5, r2 + 80015fa: 46ac mov ip, r5 + 80015fc: 464d mov r5, r9 + 80015fe: 4366 muls r6, r4 + 8001600: 0c2d lsrs r5, r5, #16 + 8001602: 44b4 add ip, r6 + 8001604: 4465 add r5, ip + 8001606: 42ae cmp r6, r5 + 8001608: d905 bls.n 8001616 <__aeabi_dmul+0xf6> + 800160a: 003e movs r6, r7 + 800160c: 2780 movs r7, #128 @ 0x80 + 800160e: 027f lsls r7, r7, #9 + 8001610: 46bc mov ip, r7 + 8001612: 4466 add r6, ip + 8001614: 9601 str r6, [sp, #4] + 8001616: 464f mov r7, r9 + 8001618: 043f lsls r7, r7, #16 + 800161a: 0c3f lsrs r7, r7, #16 + 800161c: 0c2e lsrs r6, r5, #16 + 800161e: 042d lsls r5, r5, #16 + 8001620: 19ed adds r5, r5, r7 + 8001622: 9502 str r5, [sp, #8] + 8001624: 0c1d lsrs r5, r3, #16 + 8001626: 041b lsls r3, r3, #16 + 8001628: 0c1b lsrs r3, r3, #16 + 800162a: 9500 str r5, [sp, #0] + 800162c: 001d movs r5, r3 + 800162e: 001f movs r7, r3 + 8001630: 4365 muls r5, r4 + 8001632: 434f muls r7, r1 + 8001634: 46ac mov ip, r5 + 8001636: 9d00 ldr r5, [sp, #0] + 8001638: 4369 muls r1, r5 + 800163a: 436c muls r4, r5 + 800163c: 0c3d lsrs r5, r7, #16 + 800163e: 46a9 mov r9, r5 + 8001640: 4461 add r1, ip + 8001642: 4449 add r1, r9 + 8001644: 458c cmp ip, r1 + 8001646: d903 bls.n 8001650 <__aeabi_dmul+0x130> + 8001648: 2580 movs r5, #128 @ 0x80 + 800164a: 026d lsls r5, r5, #9 + 800164c: 46ac mov ip, r5 + 800164e: 4464 add r4, ip + 8001650: 043f lsls r7, r7, #16 + 8001652: 0c0d lsrs r5, r1, #16 + 8001654: 0c3f lsrs r7, r7, #16 + 8001656: 0409 lsls r1, r1, #16 + 8001658: 19c9 adds r1, r1, r7 + 800165a: 46ac mov ip, r5 + 800165c: 1875 adds r5, r6, r1 + 800165e: 9503 str r5, [sp, #12] + 8001660: 4645 mov r5, r8 + 8001662: 042e lsls r6, r5, #16 + 8001664: 0c36 lsrs r6, r6, #16 + 8001666: 0c2f lsrs r7, r5, #16 + 8001668: 0035 movs r5, r6 + 800166a: 4345 muls r5, r0 + 800166c: 4378 muls r0, r7 + 800166e: 4680 mov r8, r0 + 8001670: 0038 movs r0, r7 + 8001672: 4464 add r4, ip + 8001674: 46ac mov ip, r5 + 8001676: 0c2d lsrs r5, r5, #16 + 8001678: 46a9 mov r9, r5 + 800167a: 4350 muls r0, r2 + 800167c: 4372 muls r2, r6 + 800167e: 4442 add r2, r8 + 8001680: 444a add r2, r9 + 8001682: 4590 cmp r8, r2 + 8001684: d903 bls.n 800168e <__aeabi_dmul+0x16e> + 8001686: 2580 movs r5, #128 @ 0x80 + 8001688: 026d lsls r5, r5, #9 + 800168a: 46a8 mov r8, r5 + 800168c: 4440 add r0, r8 + 800168e: 0c15 lsrs r5, r2, #16 + 8001690: 46a8 mov r8, r5 + 8001692: 4665 mov r5, ip + 8001694: 042d lsls r5, r5, #16 + 8001696: 0c2d lsrs r5, r5, #16 + 8001698: 46ac mov ip, r5 + 800169a: 0035 movs r5, r6 + 800169c: 435d muls r5, r3 + 800169e: 0412 lsls r2, r2, #16 + 80016a0: 4462 add r2, ip + 80016a2: 46ac mov ip, r5 + 80016a4: 437b muls r3, r7 + 80016a6: 9d00 ldr r5, [sp, #0] + 80016a8: 4440 add r0, r8 + 80016aa: 4698 mov r8, r3 + 80016ac: 002b movs r3, r5 + 80016ae: 436e muls r6, r5 + 80016b0: 4665 mov r5, ip + 80016b2: 437b muls r3, r7 + 80016b4: 4446 add r6, r8 + 80016b6: 0c2d lsrs r5, r5, #16 + 80016b8: 19ad adds r5, r5, r6 + 80016ba: 001f movs r7, r3 + 80016bc: 9300 str r3, [sp, #0] + 80016be: 45a8 cmp r8, r5 + 80016c0: d904 bls.n 80016cc <__aeabi_dmul+0x1ac> + 80016c2: 2380 movs r3, #128 @ 0x80 + 80016c4: 025b lsls r3, r3, #9 + 80016c6: 4698 mov r8, r3 + 80016c8: 4447 add r7, r8 + 80016ca: 9700 str r7, [sp, #0] + 80016cc: 9b03 ldr r3, [sp, #12] + 80016ce: 9e01 ldr r6, [sp, #4] + 80016d0: 4698 mov r8, r3 + 80016d2: 042b lsls r3, r5, #16 + 80016d4: 4446 add r6, r8 + 80016d6: 4698 mov r8, r3 + 80016d8: 4663 mov r3, ip + 80016da: 428e cmp r6, r1 + 80016dc: 4189 sbcs r1, r1 + 80016de: 041b lsls r3, r3, #16 + 80016e0: 0c1b lsrs r3, r3, #16 + 80016e2: 4443 add r3, r8 + 80016e4: 18b6 adds r6, r6, r2 + 80016e6: 4249 negs r1, r1 + 80016e8: 191b adds r3, r3, r4 + 80016ea: 185f adds r7, r3, r1 + 80016ec: 4296 cmp r6, r2 + 80016ee: 4192 sbcs r2, r2 + 80016f0: 46bc mov ip, r7 + 80016f2: 4252 negs r2, r2 + 80016f4: 4680 mov r8, r0 + 80016f6: 4691 mov r9, r2 + 80016f8: 458c cmp ip, r1 + 80016fa: 4189 sbcs r1, r1 + 80016fc: 42a3 cmp r3, r4 + 80016fe: 419b sbcs r3, r3 + 8001700: 44e0 add r8, ip + 8001702: 44c1 add r9, r8 + 8001704: 4249 negs r1, r1 + 8001706: 425b negs r3, r3 + 8001708: 4591 cmp r9, r2 + 800170a: 4192 sbcs r2, r2 + 800170c: 430b orrs r3, r1 + 800170e: 4580 cmp r8, r0 + 8001710: 4189 sbcs r1, r1 + 8001712: 0c2d lsrs r5, r5, #16 + 8001714: 4249 negs r1, r1 + 8001716: 4252 negs r2, r2 + 8001718: 430a orrs r2, r1 + 800171a: 195b adds r3, r3, r5 + 800171c: 189b adds r3, r3, r2 + 800171e: 9a00 ldr r2, [sp, #0] + 8001720: 9902 ldr r1, [sp, #8] + 8001722: 4694 mov ip, r2 + 8001724: 464a mov r2, r9 + 8001726: 4463 add r3, ip + 8001728: 025b lsls r3, r3, #9 + 800172a: 0dd2 lsrs r2, r2, #23 + 800172c: 431a orrs r2, r3 + 800172e: 4690 mov r8, r2 + 8001730: 0272 lsls r2, r6, #9 + 8001732: 430a orrs r2, r1 + 8001734: 1e51 subs r1, r2, #1 + 8001736: 418a sbcs r2, r1 + 8001738: 0df6 lsrs r6, r6, #23 + 800173a: 4316 orrs r6, r2 + 800173c: 464a mov r2, r9 + 800173e: 0252 lsls r2, r2, #9 + 8001740: 4316 orrs r6, r2 + 8001742: 46b1 mov r9, r6 + 8001744: 01db lsls r3, r3, #7 + 8001746: d454 bmi.n 80017f2 <__aeabi_dmul+0x2d2> + 8001748: 4a4d ldr r2, [pc, #308] @ (8001880 <__aeabi_dmul+0x360>) + 800174a: 445a add r2, fp + 800174c: 2a00 cmp r2, #0 + 800174e: dc00 bgt.n 8001752 <__aeabi_dmul+0x232> + 8001750: e118 b.n 8001984 <__aeabi_dmul+0x464> + 8001752: 0033 movs r3, r6 + 8001754: 075b lsls r3, r3, #29 + 8001756: d015 beq.n 8001784 <__aeabi_dmul+0x264> + 8001758: 210f movs r1, #15 + 800175a: 465b mov r3, fp + 800175c: 4031 ands r1, r6 + 800175e: 2904 cmp r1, #4 + 8001760: d010 beq.n 8001784 <__aeabi_dmul+0x264> + 8001762: 4649 mov r1, r9 + 8001764: 1d08 adds r0, r1, #4 + 8001766: 4548 cmp r0, r9 + 8001768: 4189 sbcs r1, r1 + 800176a: 4681 mov r9, r0 + 800176c: 4249 negs r1, r1 + 800176e: 4488 add r8, r1 + 8001770: 4641 mov r1, r8 + 8001772: 01c9 lsls r1, r1, #7 + 8001774: d506 bpl.n 8001784 <__aeabi_dmul+0x264> + 8001776: 4641 mov r1, r8 + 8001778: 4a42 ldr r2, [pc, #264] @ (8001884 <__aeabi_dmul+0x364>) + 800177a: 4011 ands r1, r2 + 800177c: 2280 movs r2, #128 @ 0x80 + 800177e: 4688 mov r8, r1 + 8001780: 00d2 lsls r2, r2, #3 + 8001782: 189a adds r2, r3, r2 + 8001784: 4b40 ldr r3, [pc, #256] @ (8001888 <__aeabi_dmul+0x368>) + 8001786: 429a cmp r2, r3 + 8001788: dd00 ble.n 800178c <__aeabi_dmul+0x26c> + 800178a: e12b b.n 80019e4 <__aeabi_dmul+0x4c4> + 800178c: 4641 mov r1, r8 + 800178e: 464b mov r3, r9 + 8001790: 074c lsls r4, r1, #29 + 8001792: 08db lsrs r3, r3, #3 + 8001794: 431c orrs r4, r3 + 8001796: 0552 lsls r2, r2, #21 + 8001798: 024b lsls r3, r1, #9 + 800179a: 0b1b lsrs r3, r3, #12 + 800179c: 0d52 lsrs r2, r2, #21 + 800179e: e01a b.n 80017d6 <__aeabi_dmul+0x2b6> + 80017a0: 4642 mov r2, r8 + 80017a2: 4302 orrs r2, r0 + 80017a4: 4691 mov r9, r2 + 80017a6: d000 beq.n 80017aa <__aeabi_dmul+0x28a> + 80017a8: e0e0 b.n 800196c <__aeabi_dmul+0x44c> + 80017aa: 469b mov fp, r3 + 80017ac: 2302 movs r3, #2 + 80017ae: 4690 mov r8, r2 + 80017b0: 2508 movs r5, #8 + 80017b2: 9301 str r3, [sp, #4] + 80017b4: e6db b.n 800156e <__aeabi_dmul+0x4e> + 80017b6: 9a00 ldr r2, [sp, #0] + 80017b8: 4698 mov r8, r3 + 80017ba: 4692 mov sl, r2 + 80017bc: 4681 mov r9, r0 + 80017be: 9601 str r6, [sp, #4] + 80017c0: 9b01 ldr r3, [sp, #4] + 80017c2: 2b02 cmp r3, #2 + 80017c4: d100 bne.n 80017c8 <__aeabi_dmul+0x2a8> + 80017c6: e10d b.n 80019e4 <__aeabi_dmul+0x4c4> + 80017c8: 2b03 cmp r3, #3 + 80017ca: d035 beq.n 8001838 <__aeabi_dmul+0x318> + 80017cc: 2b01 cmp r3, #1 + 80017ce: d11b bne.n 8001808 <__aeabi_dmul+0x2e8> + 80017d0: 2200 movs r2, #0 + 80017d2: 2300 movs r3, #0 + 80017d4: 2400 movs r4, #0 + 80017d6: 0512 lsls r2, r2, #20 + 80017d8: 431a orrs r2, r3 + 80017da: 4653 mov r3, sl + 80017dc: 07db lsls r3, r3, #31 + 80017de: 431a orrs r2, r3 + 80017e0: 0020 movs r0, r4 + 80017e2: 0011 movs r1, r2 + 80017e4: b005 add sp, #20 + 80017e6: bcf0 pop {r4, r5, r6, r7} + 80017e8: 46bb mov fp, r7 + 80017ea: 46b2 mov sl, r6 + 80017ec: 46a9 mov r9, r5 + 80017ee: 46a0 mov r8, r4 + 80017f0: bdf0 pop {r4, r5, r6, r7, pc} + 80017f2: 2201 movs r2, #1 + 80017f4: 0873 lsrs r3, r6, #1 + 80017f6: 4032 ands r2, r6 + 80017f8: 4313 orrs r3, r2 + 80017fa: 4642 mov r2, r8 + 80017fc: 07d2 lsls r2, r2, #31 + 80017fe: 4313 orrs r3, r2 + 8001800: 4699 mov r9, r3 + 8001802: 4643 mov r3, r8 + 8001804: 085b lsrs r3, r3, #1 + 8001806: 4698 mov r8, r3 + 8001808: 2280 movs r2, #128 @ 0x80 + 800180a: 465b mov r3, fp + 800180c: 00d2 lsls r2, r2, #3 + 800180e: 445a add r2, fp + 8001810: 3301 adds r3, #1 + 8001812: 2a00 cmp r2, #0 + 8001814: dc00 bgt.n 8001818 <__aeabi_dmul+0x2f8> + 8001816: e0b6 b.n 8001986 <__aeabi_dmul+0x466> + 8001818: 4649 mov r1, r9 + 800181a: 0749 lsls r1, r1, #29 + 800181c: d0a8 beq.n 8001770 <__aeabi_dmul+0x250> + 800181e: 210f movs r1, #15 + 8001820: 4648 mov r0, r9 + 8001822: 4001 ands r1, r0 + 8001824: 2904 cmp r1, #4 + 8001826: d19c bne.n 8001762 <__aeabi_dmul+0x242> + 8001828: e7a2 b.n 8001770 <__aeabi_dmul+0x250> + 800182a: 2d0f cmp r5, #15 + 800182c: d100 bne.n 8001830 <__aeabi_dmul+0x310> + 800182e: e0fd b.n 8001a2c <__aeabi_dmul+0x50c> + 8001830: 9b00 ldr r3, [sp, #0] + 8001832: 46a0 mov r8, r4 + 8001834: 469a mov sl, r3 + 8001836: 46b1 mov r9, r6 + 8001838: 2380 movs r3, #128 @ 0x80 + 800183a: 4642 mov r2, r8 + 800183c: 031b lsls r3, r3, #12 + 800183e: 4313 orrs r3, r2 + 8001840: 031b lsls r3, r3, #12 + 8001842: 464c mov r4, r9 + 8001844: 4a0c ldr r2, [pc, #48] @ (8001878 <__aeabi_dmul+0x358>) + 8001846: 0b1b lsrs r3, r3, #12 + 8001848: e7c5 b.n 80017d6 <__aeabi_dmul+0x2b6> + 800184a: 490b ldr r1, [pc, #44] @ (8001878 <__aeabi_dmul+0x358>) + 800184c: 0033 movs r3, r6 + 800184e: 468c mov ip, r1 + 8001850: 4323 orrs r3, r4 + 8001852: 44e3 add fp, ip + 8001854: 2b00 cmp r3, #0 + 8001856: d177 bne.n 8001948 <__aeabi_dmul+0x428> + 8001858: 2102 movs r1, #2 + 800185a: 4329 orrs r1, r5 + 800185c: 290a cmp r1, #10 + 800185e: dcaf bgt.n 80017c0 <__aeabi_dmul+0x2a0> + 8001860: 4650 mov r0, sl + 8001862: 9c00 ldr r4, [sp, #0] + 8001864: 4060 eors r0, r4 + 8001866: 4682 mov sl, r0 + 8001868: 2d00 cmp r5, #0 + 800186a: d100 bne.n 800186e <__aeabi_dmul+0x34e> + 800186c: e10e b.n 8001a8c <__aeabi_dmul+0x56c> + 800186e: 000d movs r5, r1 + 8001870: 2000 movs r0, #0 + 8001872: 2602 movs r6, #2 + 8001874: e69d b.n 80015b2 <__aeabi_dmul+0x92> + 8001876: 46c0 nop @ (mov r8, r8) + 8001878: 000007ff .word 0x000007ff + 800187c: fffffc01 .word 0xfffffc01 + 8001880: 000003ff .word 0x000003ff + 8001884: feffffff .word 0xfeffffff + 8001888: 000007fe .word 0x000007fe + 800188c: 0023 movs r3, r4 + 800188e: 4333 orrs r3, r6 + 8001890: d04b beq.n 800192a <__aeabi_dmul+0x40a> + 8001892: 2c00 cmp r4, #0 + 8001894: d100 bne.n 8001898 <__aeabi_dmul+0x378> + 8001896: e0bb b.n 8001a10 <__aeabi_dmul+0x4f0> + 8001898: 0020 movs r0, r4 + 800189a: f000 fde9 bl 8002470 <__clzsi2> + 800189e: 0003 movs r3, r0 + 80018a0: 0002 movs r2, r0 + 80018a2: 3b0b subs r3, #11 + 80018a4: 201d movs r0, #29 + 80018a6: 1ac3 subs r3, r0, r3 + 80018a8: 0030 movs r0, r6 + 80018aa: 40d8 lsrs r0, r3 + 80018ac: 0011 movs r1, r2 + 80018ae: 0003 movs r3, r0 + 80018b0: 0030 movs r0, r6 + 80018b2: 3908 subs r1, #8 + 80018b4: 408c lsls r4, r1 + 80018b6: 4088 lsls r0, r1 + 80018b8: 4323 orrs r3, r4 + 80018ba: 4659 mov r1, fp + 80018bc: 1a8a subs r2, r1, r2 + 80018be: 4978 ldr r1, [pc, #480] @ (8001aa0 <__aeabi_dmul+0x580>) + 80018c0: 468b mov fp, r1 + 80018c2: 4493 add fp, r2 + 80018c4: 2d0a cmp r5, #10 + 80018c6: dc00 bgt.n 80018ca <__aeabi_dmul+0x3aa> + 80018c8: e66c b.n 80015a4 <__aeabi_dmul+0x84> + 80018ca: e779 b.n 80017c0 <__aeabi_dmul+0x2a0> + 80018cc: 4643 mov r3, r8 + 80018ce: 4303 orrs r3, r0 + 80018d0: 4699 mov r9, r3 + 80018d2: d023 beq.n 800191c <__aeabi_dmul+0x3fc> + 80018d4: 4643 mov r3, r8 + 80018d6: 2b00 cmp r3, #0 + 80018d8: d100 bne.n 80018dc <__aeabi_dmul+0x3bc> + 80018da: e087 b.n 80019ec <__aeabi_dmul+0x4cc> + 80018dc: 4640 mov r0, r8 + 80018de: f000 fdc7 bl 8002470 <__clzsi2> + 80018e2: 230b movs r3, #11 + 80018e4: 425b negs r3, r3 + 80018e6: 469c mov ip, r3 + 80018e8: 0002 movs r2, r0 + 80018ea: 4484 add ip, r0 + 80018ec: 0011 movs r1, r2 + 80018ee: 4640 mov r0, r8 + 80018f0: 3908 subs r1, #8 + 80018f2: 4088 lsls r0, r1 + 80018f4: 231d movs r3, #29 + 80018f6: 4680 mov r8, r0 + 80018f8: 4660 mov r0, ip + 80018fa: 1a1b subs r3, r3, r0 + 80018fc: 0020 movs r0, r4 + 80018fe: 40d8 lsrs r0, r3 + 8001900: 0003 movs r3, r0 + 8001902: 4640 mov r0, r8 + 8001904: 4303 orrs r3, r0 + 8001906: 4698 mov r8, r3 + 8001908: 0023 movs r3, r4 + 800190a: 408b lsls r3, r1 + 800190c: 4699 mov r9, r3 + 800190e: 4b64 ldr r3, [pc, #400] @ (8001aa0 <__aeabi_dmul+0x580>) + 8001910: 2500 movs r5, #0 + 8001912: 1a9b subs r3, r3, r2 + 8001914: 469b mov fp, r3 + 8001916: 2300 movs r3, #0 + 8001918: 9301 str r3, [sp, #4] + 800191a: e628 b.n 800156e <__aeabi_dmul+0x4e> + 800191c: 2300 movs r3, #0 + 800191e: 4698 mov r8, r3 + 8001920: 469b mov fp, r3 + 8001922: 3301 adds r3, #1 + 8001924: 2504 movs r5, #4 + 8001926: 9301 str r3, [sp, #4] + 8001928: e621 b.n 800156e <__aeabi_dmul+0x4e> + 800192a: 2201 movs r2, #1 + 800192c: 4315 orrs r5, r2 + 800192e: 2d0a cmp r5, #10 + 8001930: dd00 ble.n 8001934 <__aeabi_dmul+0x414> + 8001932: e745 b.n 80017c0 <__aeabi_dmul+0x2a0> + 8001934: 4652 mov r2, sl + 8001936: 9900 ldr r1, [sp, #0] + 8001938: 404a eors r2, r1 + 800193a: 4692 mov sl, r2 + 800193c: 2d02 cmp r5, #2 + 800193e: dc00 bgt.n 8001942 <__aeabi_dmul+0x422> + 8001940: e746 b.n 80017d0 <__aeabi_dmul+0x2b0> + 8001942: 2000 movs r0, #0 + 8001944: 2601 movs r6, #1 + 8001946: e634 b.n 80015b2 <__aeabi_dmul+0x92> + 8001948: 2303 movs r3, #3 + 800194a: 431d orrs r5, r3 + 800194c: 2d0a cmp r5, #10 + 800194e: dd00 ble.n 8001952 <__aeabi_dmul+0x432> + 8001950: e76b b.n 800182a <__aeabi_dmul+0x30a> + 8001952: 4653 mov r3, sl + 8001954: 9a00 ldr r2, [sp, #0] + 8001956: 2188 movs r1, #136 @ 0x88 + 8001958: 4053 eors r3, r2 + 800195a: 2201 movs r2, #1 + 800195c: 40aa lsls r2, r5 + 800195e: 469a mov sl, r3 + 8001960: 2603 movs r6, #3 + 8001962: 0023 movs r3, r4 + 8001964: 4211 tst r1, r2 + 8001966: d100 bne.n 800196a <__aeabi_dmul+0x44a> + 8001968: e635 b.n 80015d6 <__aeabi_dmul+0xb6> + 800196a: e724 b.n 80017b6 <__aeabi_dmul+0x296> + 800196c: 469b mov fp, r3 + 800196e: 2303 movs r3, #3 + 8001970: 4681 mov r9, r0 + 8001972: 250c movs r5, #12 + 8001974: 9301 str r3, [sp, #4] + 8001976: e5fa b.n 800156e <__aeabi_dmul+0x4e> + 8001978: 2300 movs r3, #0 + 800197a: 469a mov sl, r3 + 800197c: 2380 movs r3, #128 @ 0x80 + 800197e: 4a49 ldr r2, [pc, #292] @ (8001aa4 <__aeabi_dmul+0x584>) + 8001980: 031b lsls r3, r3, #12 + 8001982: e728 b.n 80017d6 <__aeabi_dmul+0x2b6> + 8001984: 465b mov r3, fp + 8001986: 2101 movs r1, #1 + 8001988: 1a89 subs r1, r1, r2 + 800198a: 2938 cmp r1, #56 @ 0x38 + 800198c: dd00 ble.n 8001990 <__aeabi_dmul+0x470> + 800198e: e71f b.n 80017d0 <__aeabi_dmul+0x2b0> + 8001990: 291f cmp r1, #31 + 8001992: dd5a ble.n 8001a4a <__aeabi_dmul+0x52a> + 8001994: 201f movs r0, #31 + 8001996: 4240 negs r0, r0 + 8001998: 1a82 subs r2, r0, r2 + 800199a: 4640 mov r0, r8 + 800199c: 40d0 lsrs r0, r2 + 800199e: 2920 cmp r1, #32 + 80019a0: d008 beq.n 80019b4 <__aeabi_dmul+0x494> + 80019a2: 4a41 ldr r2, [pc, #260] @ (8001aa8 <__aeabi_dmul+0x588>) + 80019a4: 4694 mov ip, r2 + 80019a6: 4642 mov r2, r8 + 80019a8: 4463 add r3, ip + 80019aa: 409a lsls r2, r3 + 80019ac: 0013 movs r3, r2 + 80019ae: 464a mov r2, r9 + 80019b0: 431a orrs r2, r3 + 80019b2: 4691 mov r9, r2 + 80019b4: 464a mov r2, r9 + 80019b6: 2107 movs r1, #7 + 80019b8: 1e53 subs r3, r2, #1 + 80019ba: 419a sbcs r2, r3 + 80019bc: 000c movs r4, r1 + 80019be: 4302 orrs r2, r0 + 80019c0: 2300 movs r3, #0 + 80019c2: 4014 ands r4, r2 + 80019c4: 4211 tst r1, r2 + 80019c6: d009 beq.n 80019dc <__aeabi_dmul+0x4bc> + 80019c8: 3108 adds r1, #8 + 80019ca: 4011 ands r1, r2 + 80019cc: 2904 cmp r1, #4 + 80019ce: d060 beq.n 8001a92 <__aeabi_dmul+0x572> + 80019d0: 1d11 adds r1, r2, #4 + 80019d2: 4291 cmp r1, r2 + 80019d4: 41a4 sbcs r4, r4 + 80019d6: 000a movs r2, r1 + 80019d8: 4264 negs r4, r4 + 80019da: 0764 lsls r4, r4, #29 + 80019dc: 08d2 lsrs r2, r2, #3 + 80019de: 4314 orrs r4, r2 + 80019e0: 2200 movs r2, #0 + 80019e2: e6f8 b.n 80017d6 <__aeabi_dmul+0x2b6> + 80019e4: 2300 movs r3, #0 + 80019e6: 2400 movs r4, #0 + 80019e8: 4a2e ldr r2, [pc, #184] @ (8001aa4 <__aeabi_dmul+0x584>) + 80019ea: e6f4 b.n 80017d6 <__aeabi_dmul+0x2b6> + 80019ec: f000 fd40 bl 8002470 <__clzsi2> + 80019f0: 2315 movs r3, #21 + 80019f2: 469c mov ip, r3 + 80019f4: 4484 add ip, r0 + 80019f6: 0002 movs r2, r0 + 80019f8: 4663 mov r3, ip + 80019fa: 3220 adds r2, #32 + 80019fc: 2b1c cmp r3, #28 + 80019fe: dc00 bgt.n 8001a02 <__aeabi_dmul+0x4e2> + 8001a00: e774 b.n 80018ec <__aeabi_dmul+0x3cc> + 8001a02: 2300 movs r3, #0 + 8001a04: 4699 mov r9, r3 + 8001a06: 0023 movs r3, r4 + 8001a08: 3808 subs r0, #8 + 8001a0a: 4083 lsls r3, r0 + 8001a0c: 4698 mov r8, r3 + 8001a0e: e77e b.n 800190e <__aeabi_dmul+0x3ee> + 8001a10: f000 fd2e bl 8002470 <__clzsi2> + 8001a14: 0003 movs r3, r0 + 8001a16: 0002 movs r2, r0 + 8001a18: 3315 adds r3, #21 + 8001a1a: 3220 adds r2, #32 + 8001a1c: 2b1c cmp r3, #28 + 8001a1e: dc00 bgt.n 8001a22 <__aeabi_dmul+0x502> + 8001a20: e740 b.n 80018a4 <__aeabi_dmul+0x384> + 8001a22: 0033 movs r3, r6 + 8001a24: 3808 subs r0, #8 + 8001a26: 4083 lsls r3, r0 + 8001a28: 2000 movs r0, #0 + 8001a2a: e746 b.n 80018ba <__aeabi_dmul+0x39a> + 8001a2c: 2380 movs r3, #128 @ 0x80 + 8001a2e: 4642 mov r2, r8 + 8001a30: 031b lsls r3, r3, #12 + 8001a32: 421a tst r2, r3 + 8001a34: d100 bne.n 8001a38 <__aeabi_dmul+0x518> + 8001a36: e6ff b.n 8001838 <__aeabi_dmul+0x318> + 8001a38: 421c tst r4, r3 + 8001a3a: d000 beq.n 8001a3e <__aeabi_dmul+0x51e> + 8001a3c: e6fc b.n 8001838 <__aeabi_dmul+0x318> + 8001a3e: 9a00 ldr r2, [sp, #0] + 8001a40: 4323 orrs r3, r4 + 8001a42: 4692 mov sl, r2 + 8001a44: 0034 movs r4, r6 + 8001a46: 4a17 ldr r2, [pc, #92] @ (8001aa4 <__aeabi_dmul+0x584>) + 8001a48: e6c5 b.n 80017d6 <__aeabi_dmul+0x2b6> + 8001a4a: 4a18 ldr r2, [pc, #96] @ (8001aac <__aeabi_dmul+0x58c>) + 8001a4c: 4640 mov r0, r8 + 8001a4e: 4694 mov ip, r2 + 8001a50: 464a mov r2, r9 + 8001a52: 4463 add r3, ip + 8001a54: 4098 lsls r0, r3 + 8001a56: 40ca lsrs r2, r1 + 8001a58: 4310 orrs r0, r2 + 8001a5a: 464a mov r2, r9 + 8001a5c: 409a lsls r2, r3 + 8001a5e: 1e53 subs r3, r2, #1 + 8001a60: 419a sbcs r2, r3 + 8001a62: 4643 mov r3, r8 + 8001a64: 4302 orrs r2, r0 + 8001a66: 40cb lsrs r3, r1 + 8001a68: 0751 lsls r1, r2, #29 + 8001a6a: d009 beq.n 8001a80 <__aeabi_dmul+0x560> + 8001a6c: 210f movs r1, #15 + 8001a6e: 4011 ands r1, r2 + 8001a70: 2904 cmp r1, #4 + 8001a72: d005 beq.n 8001a80 <__aeabi_dmul+0x560> + 8001a74: 1d11 adds r1, r2, #4 + 8001a76: 4291 cmp r1, r2 + 8001a78: 4192 sbcs r2, r2 + 8001a7a: 4252 negs r2, r2 + 8001a7c: 189b adds r3, r3, r2 + 8001a7e: 000a movs r2, r1 + 8001a80: 0219 lsls r1, r3, #8 + 8001a82: d508 bpl.n 8001a96 <__aeabi_dmul+0x576> + 8001a84: 2201 movs r2, #1 + 8001a86: 2300 movs r3, #0 + 8001a88: 2400 movs r4, #0 + 8001a8a: e6a4 b.n 80017d6 <__aeabi_dmul+0x2b6> + 8001a8c: 2300 movs r3, #0 + 8001a8e: 2400 movs r4, #0 + 8001a90: e6a1 b.n 80017d6 <__aeabi_dmul+0x2b6> + 8001a92: 2400 movs r4, #0 + 8001a94: e7a2 b.n 80019dc <__aeabi_dmul+0x4bc> + 8001a96: 075c lsls r4, r3, #29 + 8001a98: 025b lsls r3, r3, #9 + 8001a9a: 0b1b lsrs r3, r3, #12 + 8001a9c: e79e b.n 80019dc <__aeabi_dmul+0x4bc> + 8001a9e: 46c0 nop @ (mov r8, r8) + 8001aa0: fffffc0d .word 0xfffffc0d + 8001aa4: 000007ff .word 0x000007ff + 8001aa8: 0000043e .word 0x0000043e + 8001aac: 0000041e .word 0x0000041e + +08001ab0 <__aeabi_dsub>: + 8001ab0: b5f0 push {r4, r5, r6, r7, lr} + 8001ab2: 464e mov r6, r9 + 8001ab4: 4645 mov r5, r8 + 8001ab6: 46de mov lr, fp + 8001ab8: 4657 mov r7, sl + 8001aba: b5e0 push {r5, r6, r7, lr} + 8001abc: b083 sub sp, #12 + 8001abe: 9000 str r0, [sp, #0] + 8001ac0: 9101 str r1, [sp, #4] + 8001ac2: 030d lsls r5, r1, #12 + 8001ac4: 004e lsls r6, r1, #1 + 8001ac6: 9901 ldr r1, [sp, #4] + 8001ac8: 0d76 lsrs r6, r6, #21 + 8001aca: 0fcc lsrs r4, r1, #31 + 8001acc: 0a69 lsrs r1, r5, #9 + 8001ace: 9d00 ldr r5, [sp, #0] + 8001ad0: 0f6d lsrs r5, r5, #29 + 8001ad2: 430d orrs r5, r1 + 8001ad4: 9900 ldr r1, [sp, #0] + 8001ad6: 9200 str r2, [sp, #0] + 8001ad8: 9301 str r3, [sp, #4] + 8001ada: 00c8 lsls r0, r1, #3 + 8001adc: 0319 lsls r1, r3, #12 + 8001ade: 9b01 ldr r3, [sp, #4] + 8001ae0: 4acb ldr r2, [pc, #812] @ (8001e10 <__aeabi_dsub+0x360>) + 8001ae2: 005b lsls r3, r3, #1 + 8001ae4: 0d5b lsrs r3, r3, #21 + 8001ae6: 4699 mov r9, r3 + 8001ae8: 9b01 ldr r3, [sp, #4] + 8001aea: 4683 mov fp, r0 + 8001aec: 0fdb lsrs r3, r3, #31 + 8001aee: 4698 mov r8, r3 + 8001af0: 0a4b lsrs r3, r1, #9 + 8001af2: 9900 ldr r1, [sp, #0] + 8001af4: 0f49 lsrs r1, r1, #29 + 8001af6: 4319 orrs r1, r3 + 8001af8: 9b00 ldr r3, [sp, #0] + 8001afa: 00db lsls r3, r3, #3 + 8001afc: 469c mov ip, r3 + 8001afe: 469a mov sl, r3 + 8001b00: 4591 cmp r9, r2 + 8001b02: d100 bne.n 8001b06 <__aeabi_dsub+0x56> + 8001b04: e073 b.n 8001bee <__aeabi_dsub+0x13e> + 8001b06: 2301 movs r3, #1 + 8001b08: 4647 mov r7, r8 + 8001b0a: 405f eors r7, r3 + 8001b0c: 464b mov r3, r9 + 8001b0e: 46b8 mov r8, r7 + 8001b10: 1af3 subs r3, r6, r3 + 8001b12: 42bc cmp r4, r7 + 8001b14: d016 beq.n 8001b44 <__aeabi_dsub+0x94> + 8001b16: 2b00 cmp r3, #0 + 8001b18: dc00 bgt.n 8001b1c <__aeabi_dsub+0x6c> + 8001b1a: e29a b.n 8002052 <__aeabi_dsub+0x5a2> + 8001b1c: 464f mov r7, r9 + 8001b1e: 2f00 cmp r7, #0 + 8001b20: d000 beq.n 8001b24 <__aeabi_dsub+0x74> + 8001b22: e082 b.n 8001c2a <__aeabi_dsub+0x17a> + 8001b24: 4667 mov r7, ip + 8001b26: 430f orrs r7, r1 + 8001b28: d100 bne.n 8001b2c <__aeabi_dsub+0x7c> + 8001b2a: e13a b.n 8001da2 <__aeabi_dsub+0x2f2> + 8001b2c: 1e5f subs r7, r3, #1 + 8001b2e: 2b01 cmp r3, #1 + 8001b30: d100 bne.n 8001b34 <__aeabi_dsub+0x84> + 8001b32: e2a4 b.n 800207e <__aeabi_dsub+0x5ce> + 8001b34: 4293 cmp r3, r2 + 8001b36: d100 bne.n 8001b3a <__aeabi_dsub+0x8a> + 8001b38: e12e b.n 8001d98 <__aeabi_dsub+0x2e8> + 8001b3a: 2f38 cmp r7, #56 @ 0x38 + 8001b3c: dd00 ble.n 8001b40 <__aeabi_dsub+0x90> + 8001b3e: e243 b.n 8001fc8 <__aeabi_dsub+0x518> + 8001b40: 003b movs r3, r7 + 8001b42: e13e b.n 8001dc2 <__aeabi_dsub+0x312> + 8001b44: 2b00 cmp r3, #0 + 8001b46: dc00 bgt.n 8001b4a <__aeabi_dsub+0x9a> + 8001b48: e2d7 b.n 80020fa <__aeabi_dsub+0x64a> + 8001b4a: 464f mov r7, r9 + 8001b4c: 2f00 cmp r7, #0 + 8001b4e: d000 beq.n 8001b52 <__aeabi_dsub+0xa2> + 8001b50: e0f8 b.n 8001d44 <__aeabi_dsub+0x294> + 8001b52: 4667 mov r7, ip + 8001b54: 430f orrs r7, r1 + 8001b56: d100 bne.n 8001b5a <__aeabi_dsub+0xaa> + 8001b58: e123 b.n 8001da2 <__aeabi_dsub+0x2f2> + 8001b5a: 1e5f subs r7, r3, #1 + 8001b5c: 2b01 cmp r3, #1 + 8001b5e: d100 bne.n 8001b62 <__aeabi_dsub+0xb2> + 8001b60: e257 b.n 8002012 <__aeabi_dsub+0x562> + 8001b62: 4293 cmp r3, r2 + 8001b64: d100 bne.n 8001b68 <__aeabi_dsub+0xb8> + 8001b66: e117 b.n 8001d98 <__aeabi_dsub+0x2e8> + 8001b68: 2f38 cmp r7, #56 @ 0x38 + 8001b6a: dc00 bgt.n 8001b6e <__aeabi_dsub+0xbe> + 8001b6c: e304 b.n 8002178 <__aeabi_dsub+0x6c8> + 8001b6e: 2280 movs r2, #128 @ 0x80 + 8001b70: 0412 lsls r2, r2, #16 + 8001b72: 4215 tst r5, r2 + 8001b74: d100 bne.n 8001b78 <__aeabi_dsub+0xc8> + 8001b76: e3aa b.n 80022ce <__aeabi_dsub+0x81e> + 8001b78: 001e movs r6, r3 + 8001b7a: 0015 movs r5, r2 + 8001b7c: 2700 movs r7, #0 + 8001b7e: 4ba4 ldr r3, [pc, #656] @ (8001e10 <__aeabi_dsub+0x360>) + 8001b80: 3601 adds r6, #1 + 8001b82: 429e cmp r6, r3 + 8001b84: d100 bne.n 8001b88 <__aeabi_dsub+0xd8> + 8001b86: e103 b.n 8001d90 <__aeabi_dsub+0x2e0> + 8001b88: 2201 movs r2, #1 + 8001b8a: 4ba2 ldr r3, [pc, #648] @ (8001e14 <__aeabi_dsub+0x364>) + 8001b8c: 403a ands r2, r7 + 8001b8e: 401d ands r5, r3 + 8001b90: 0879 lsrs r1, r7, #1 + 8001b92: 4311 orrs r1, r2 + 8001b94: 07ea lsls r2, r5, #31 + 8001b96: 430a orrs r2, r1 + 8001b98: 086d lsrs r5, r5, #1 + 8001b9a: 0753 lsls r3, r2, #29 + 8001b9c: d009 beq.n 8001bb2 <__aeabi_dsub+0x102> + 8001b9e: 230f movs r3, #15 + 8001ba0: 4013 ands r3, r2 + 8001ba2: 2b04 cmp r3, #4 + 8001ba4: d005 beq.n 8001bb2 <__aeabi_dsub+0x102> + 8001ba6: 0017 movs r7, r2 + 8001ba8: 1d3a adds r2, r7, #4 + 8001baa: 42ba cmp r2, r7 + 8001bac: 41bf sbcs r7, r7 + 8001bae: 427f negs r7, r7 + 8001bb0: 19ed adds r5, r5, r7 + 8001bb2: 022b lsls r3, r5, #8 + 8001bb4: d400 bmi.n 8001bb8 <__aeabi_dsub+0x108> + 8001bb6: e377 b.n 80022a8 <__aeabi_dsub+0x7f8> + 8001bb8: 4995 ldr r1, [pc, #596] @ (8001e10 <__aeabi_dsub+0x360>) + 8001bba: 3601 adds r6, #1 + 8001bbc: 428e cmp r6, r1 + 8001bbe: d100 bne.n 8001bc2 <__aeabi_dsub+0x112> + 8001bc0: e0e6 b.n 8001d90 <__aeabi_dsub+0x2e0> + 8001bc2: 4994 ldr r1, [pc, #592] @ (8001e14 <__aeabi_dsub+0x364>) + 8001bc4: 0573 lsls r3, r6, #21 + 8001bc6: 400d ands r5, r1 + 8001bc8: 0d5b lsrs r3, r3, #21 + 8001bca: 0769 lsls r1, r5, #29 + 8001bcc: 08d2 lsrs r2, r2, #3 + 8001bce: 026d lsls r5, r5, #9 + 8001bd0: 430a orrs r2, r1 + 8001bd2: 0b2d lsrs r5, r5, #12 + 8001bd4: 051b lsls r3, r3, #20 + 8001bd6: 432b orrs r3, r5 + 8001bd8: 07e4 lsls r4, r4, #31 + 8001bda: 4323 orrs r3, r4 + 8001bdc: 0010 movs r0, r2 + 8001bde: 0019 movs r1, r3 + 8001be0: b003 add sp, #12 + 8001be2: bcf0 pop {r4, r5, r6, r7} + 8001be4: 46bb mov fp, r7 + 8001be6: 46b2 mov sl, r6 + 8001be8: 46a9 mov r9, r5 + 8001bea: 46a0 mov r8, r4 + 8001bec: bdf0 pop {r4, r5, r6, r7, pc} + 8001bee: 4b8a ldr r3, [pc, #552] @ (8001e18 <__aeabi_dsub+0x368>) + 8001bf0: 18f2 adds r2, r6, r3 + 8001bf2: 4663 mov r3, ip + 8001bf4: 430b orrs r3, r1 + 8001bf6: d04c beq.n 8001c92 <__aeabi_dsub+0x1e2> + 8001bf8: 4544 cmp r4, r8 + 8001bfa: d050 beq.n 8001c9e <__aeabi_dsub+0x1ee> + 8001bfc: 2a00 cmp r2, #0 + 8001bfe: d06c beq.n 8001cda <__aeabi_dsub+0x22a> + 8001c00: 2e00 cmp r6, #0 + 8001c02: d100 bne.n 8001c06 <__aeabi_dsub+0x156> + 8001c04: e17d b.n 8001f02 <__aeabi_dsub+0x452> + 8001c06: 4663 mov r3, ip + 8001c08: 4644 mov r4, r8 + 8001c0a: 074f lsls r7, r1, #29 + 8001c0c: 08da lsrs r2, r3, #3 + 8001c0e: 4317 orrs r7, r2 + 8001c10: 08c8 lsrs r0, r1, #3 + 8001c12: 003a movs r2, r7 + 8001c14: 4302 orrs r2, r0 + 8001c16: d100 bne.n 8001c1a <__aeabi_dsub+0x16a> + 8001c18: e0cd b.n 8001db6 <__aeabi_dsub+0x306> + 8001c1a: 2580 movs r5, #128 @ 0x80 + 8001c1c: 032d lsls r5, r5, #12 + 8001c1e: 4305 orrs r5, r0 + 8001c20: 032d lsls r5, r5, #12 + 8001c22: 003a movs r2, r7 + 8001c24: 4b7a ldr r3, [pc, #488] @ (8001e10 <__aeabi_dsub+0x360>) + 8001c26: 0b2d lsrs r5, r5, #12 + 8001c28: e7d4 b.n 8001bd4 <__aeabi_dsub+0x124> + 8001c2a: 4296 cmp r6, r2 + 8001c2c: d100 bne.n 8001c30 <__aeabi_dsub+0x180> + 8001c2e: e0b3 b.n 8001d98 <__aeabi_dsub+0x2e8> + 8001c30: 2b38 cmp r3, #56 @ 0x38 + 8001c32: dc00 bgt.n 8001c36 <__aeabi_dsub+0x186> + 8001c34: e0c2 b.n 8001dbc <__aeabi_dsub+0x30c> + 8001c36: 1e47 subs r7, r0, #1 + 8001c38: 42b8 cmp r0, r7 + 8001c3a: 4180 sbcs r0, r0 + 8001c3c: 4240 negs r0, r0 + 8001c3e: 1a2d subs r5, r5, r0 + 8001c40: 022b lsls r3, r5, #8 + 8001c42: d5b1 bpl.n 8001ba8 <__aeabi_dsub+0xf8> + 8001c44: 2701 movs r7, #1 + 8001c46: 4d75 ldr r5, [pc, #468] @ (8001e1c <__aeabi_dsub+0x36c>) + 8001c48: 427f negs r7, r7 + 8001c4a: 0028 movs r0, r5 + 8001c4c: f000 fc10 bl 8002470 <__clzsi2> + 8001c50: 3808 subs r0, #8 + 8001c52: 2320 movs r3, #32 + 8001c54: 0039 movs r1, r7 + 8001c56: 1a1a subs r2, r3, r0 + 8001c58: 4085 lsls r5, r0 + 8001c5a: 40d1 lsrs r1, r2 + 8001c5c: 4087 lsls r7, r0 + 8001c5e: 4329 orrs r1, r5 + 8001c60: 42b0 cmp r0, r6 + 8001c62: da00 bge.n 8001c66 <__aeabi_dsub+0x1b6> + 8001c64: e145 b.n 8001ef2 <__aeabi_dsub+0x442> + 8001c66: 1b80 subs r0, r0, r6 + 8001c68: 3001 adds r0, #1 + 8001c6a: 1a1b subs r3, r3, r0 + 8001c6c: 003d movs r5, r7 + 8001c6e: 409f lsls r7, r3 + 8001c70: 40c5 lsrs r5, r0 + 8001c72: 1e7a subs r2, r7, #1 + 8001c74: 4197 sbcs r7, r2 + 8001c76: 000a movs r2, r1 + 8001c78: 409a lsls r2, r3 + 8001c7a: 432f orrs r7, r5 + 8001c7c: 433a orrs r2, r7 + 8001c7e: 40c1 lsrs r1, r0 + 8001c80: 0013 movs r3, r2 + 8001c82: 000d movs r5, r1 + 8001c84: 2600 movs r6, #0 + 8001c86: 430b orrs r3, r1 + 8001c88: d000 beq.n 8001c8c <__aeabi_dsub+0x1dc> + 8001c8a: e786 b.n 8001b9a <__aeabi_dsub+0xea> + 8001c8c: 2200 movs r2, #0 + 8001c8e: 2500 movs r5, #0 + 8001c90: e7a0 b.n 8001bd4 <__aeabi_dsub+0x124> + 8001c92: 4647 mov r7, r8 + 8001c94: 2301 movs r3, #1 + 8001c96: 405f eors r7, r3 + 8001c98: 46b8 mov r8, r7 + 8001c9a: 4544 cmp r4, r8 + 8001c9c: d1ae bne.n 8001bfc <__aeabi_dsub+0x14c> + 8001c9e: 2a00 cmp r2, #0 + 8001ca0: d100 bne.n 8001ca4 <__aeabi_dsub+0x1f4> + 8001ca2: e0ef b.n 8001e84 <__aeabi_dsub+0x3d4> + 8001ca4: 2e00 cmp r6, #0 + 8001ca6: d000 beq.n 8001caa <__aeabi_dsub+0x1fa> + 8001ca8: e188 b.n 8001fbc <__aeabi_dsub+0x50c> + 8001caa: 464b mov r3, r9 + 8001cac: 002a movs r2, r5 + 8001cae: 4302 orrs r2, r0 + 8001cb0: d100 bne.n 8001cb4 <__aeabi_dsub+0x204> + 8001cb2: e2a0 b.n 80021f6 <__aeabi_dsub+0x746> + 8001cb4: 1e5a subs r2, r3, #1 + 8001cb6: 2b01 cmp r3, #1 + 8001cb8: d100 bne.n 8001cbc <__aeabi_dsub+0x20c> + 8001cba: e2b7 b.n 800222c <__aeabi_dsub+0x77c> + 8001cbc: 4e54 ldr r6, [pc, #336] @ (8001e10 <__aeabi_dsub+0x360>) + 8001cbe: 42b3 cmp r3, r6 + 8001cc0: d100 bne.n 8001cc4 <__aeabi_dsub+0x214> + 8001cc2: e17b b.n 8001fbc <__aeabi_dsub+0x50c> + 8001cc4: 2a38 cmp r2, #56 @ 0x38 + 8001cc6: dc00 bgt.n 8001cca <__aeabi_dsub+0x21a> + 8001cc8: e312 b.n 80022f0 <__aeabi_dsub+0x840> + 8001cca: 2580 movs r5, #128 @ 0x80 + 8001ccc: 042d lsls r5, r5, #16 + 8001cce: 4229 tst r1, r5 + 8001cd0: d100 bne.n 8001cd4 <__aeabi_dsub+0x224> + 8001cd2: e312 b.n 80022fa <__aeabi_dsub+0x84a> + 8001cd4: 001e movs r6, r3 + 8001cd6: 2700 movs r7, #0 + 8001cd8: e751 b.n 8001b7e <__aeabi_dsub+0xce> + 8001cda: 4a51 ldr r2, [pc, #324] @ (8001e20 <__aeabi_dsub+0x370>) + 8001cdc: 1c73 adds r3, r6, #1 + 8001cde: 4213 tst r3, r2 + 8001ce0: d000 beq.n 8001ce4 <__aeabi_dsub+0x234> + 8001ce2: e0f4 b.n 8001ece <__aeabi_dsub+0x41e> + 8001ce4: 4662 mov r2, ip + 8001ce6: 002b movs r3, r5 + 8001ce8: 430a orrs r2, r1 + 8001cea: 4303 orrs r3, r0 + 8001cec: 2e00 cmp r6, #0 + 8001cee: d000 beq.n 8001cf2 <__aeabi_dsub+0x242> + 8001cf0: e174 b.n 8001fdc <__aeabi_dsub+0x52c> + 8001cf2: 2b00 cmp r3, #0 + 8001cf4: d100 bne.n 8001cf8 <__aeabi_dsub+0x248> + 8001cf6: e223 b.n 8002140 <__aeabi_dsub+0x690> + 8001cf8: 2a00 cmp r2, #0 + 8001cfa: d100 bne.n 8001cfe <__aeabi_dsub+0x24e> + 8001cfc: e0e0 b.n 8001ec0 <__aeabi_dsub+0x410> + 8001cfe: 4663 mov r3, ip + 8001d00: 1ac7 subs r7, r0, r3 + 8001d02: 42b8 cmp r0, r7 + 8001d04: 4192 sbcs r2, r2 + 8001d06: 2680 movs r6, #128 @ 0x80 + 8001d08: 1a6b subs r3, r5, r1 + 8001d0a: 4252 negs r2, r2 + 8001d0c: 1a9b subs r3, r3, r2 + 8001d0e: 0436 lsls r6, r6, #16 + 8001d10: 4233 tst r3, r6 + 8001d12: d100 bne.n 8001d16 <__aeabi_dsub+0x266> + 8001d14: e2c1 b.n 800229a <__aeabi_dsub+0x7ea> + 8001d16: 4663 mov r3, ip + 8001d18: 1a18 subs r0, r3, r0 + 8001d1a: 4584 cmp ip, r0 + 8001d1c: 4192 sbcs r2, r2 + 8001d1e: 1b4d subs r5, r1, r5 + 8001d20: 4252 negs r2, r2 + 8001d22: 1aad subs r5, r5, r2 + 8001d24: 2401 movs r4, #1 + 8001d26: 0002 movs r2, r0 + 8001d28: 4643 mov r3, r8 + 8001d2a: 432a orrs r2, r5 + 8001d2c: 401c ands r4, r3 + 8001d2e: 2a00 cmp r2, #0 + 8001d30: d100 bne.n 8001d34 <__aeabi_dsub+0x284> + 8001d32: e0db b.n 8001eec <__aeabi_dsub+0x43c> + 8001d34: 4235 tst r5, r6 + 8001d36: d100 bne.n 8001d3a <__aeabi_dsub+0x28a> + 8001d38: e2e9 b.n 800230e <__aeabi_dsub+0x85e> + 8001d3a: 4b36 ldr r3, [pc, #216] @ (8001e14 <__aeabi_dsub+0x364>) + 8001d3c: 0002 movs r2, r0 + 8001d3e: 401d ands r5, r3 + 8001d40: 2301 movs r3, #1 + 8001d42: e742 b.n 8001bca <__aeabi_dsub+0x11a> + 8001d44: 4296 cmp r6, r2 + 8001d46: d027 beq.n 8001d98 <__aeabi_dsub+0x2e8> + 8001d48: 2b38 cmp r3, #56 @ 0x38 + 8001d4a: dd00 ble.n 8001d4e <__aeabi_dsub+0x29e> + 8001d4c: e111 b.n 8001f72 <__aeabi_dsub+0x4c2> + 8001d4e: 2280 movs r2, #128 @ 0x80 + 8001d50: 0412 lsls r2, r2, #16 + 8001d52: 4311 orrs r1, r2 + 8001d54: 2b1f cmp r3, #31 + 8001d56: dd00 ble.n 8001d5a <__aeabi_dsub+0x2aa> + 8001d58: e1a1 b.n 800209e <__aeabi_dsub+0x5ee> + 8001d5a: 2220 movs r2, #32 + 8001d5c: 000f movs r7, r1 + 8001d5e: 1ad2 subs r2, r2, r3 + 8001d60: 4691 mov r9, r2 + 8001d62: 4097 lsls r7, r2 + 8001d64: 4662 mov r2, ip + 8001d66: 40da lsrs r2, r3 + 8001d68: 4317 orrs r7, r2 + 8001d6a: 46b8 mov r8, r7 + 8001d6c: 4662 mov r2, ip + 8001d6e: 464f mov r7, r9 + 8001d70: 40ba lsls r2, r7 + 8001d72: 40d9 lsrs r1, r3 + 8001d74: 1e57 subs r7, r2, #1 + 8001d76: 41ba sbcs r2, r7 + 8001d78: 4647 mov r7, r8 + 8001d7a: 186d adds r5, r5, r1 + 8001d7c: 4317 orrs r7, r2 + 8001d7e: 183f adds r7, r7, r0 + 8001d80: 4287 cmp r7, r0 + 8001d82: 4180 sbcs r0, r0 + 8001d84: 4240 negs r0, r0 + 8001d86: 182d adds r5, r5, r0 + 8001d88: 022b lsls r3, r5, #8 + 8001d8a: d500 bpl.n 8001d8e <__aeabi_dsub+0x2de> + 8001d8c: e6f7 b.n 8001b7e <__aeabi_dsub+0xce> + 8001d8e: e034 b.n 8001dfa <__aeabi_dsub+0x34a> + 8001d90: 0033 movs r3, r6 + 8001d92: 2500 movs r5, #0 + 8001d94: 2200 movs r2, #0 + 8001d96: e71d b.n 8001bd4 <__aeabi_dsub+0x124> + 8001d98: 08c0 lsrs r0, r0, #3 + 8001d9a: 076f lsls r7, r5, #29 + 8001d9c: 4307 orrs r7, r0 + 8001d9e: 08e8 lsrs r0, r5, #3 + 8001da0: e737 b.n 8001c12 <__aeabi_dsub+0x162> + 8001da2: 08c7 lsrs r7, r0, #3 + 8001da4: 076a lsls r2, r5, #29 + 8001da6: 4317 orrs r7, r2 + 8001da8: 4a19 ldr r2, [pc, #100] @ (8001e10 <__aeabi_dsub+0x360>) + 8001daa: 08e8 lsrs r0, r5, #3 + 8001dac: 4293 cmp r3, r2 + 8001dae: d100 bne.n 8001db2 <__aeabi_dsub+0x302> + 8001db0: e72f b.n 8001c12 <__aeabi_dsub+0x162> + 8001db2: 003a movs r2, r7 + 8001db4: e0d8 b.n 8001f68 <__aeabi_dsub+0x4b8> + 8001db6: 4b16 ldr r3, [pc, #88] @ (8001e10 <__aeabi_dsub+0x360>) + 8001db8: 2500 movs r5, #0 + 8001dba: e70b b.n 8001bd4 <__aeabi_dsub+0x124> + 8001dbc: 2280 movs r2, #128 @ 0x80 + 8001dbe: 0412 lsls r2, r2, #16 + 8001dc0: 4311 orrs r1, r2 + 8001dc2: 2b1f cmp r3, #31 + 8001dc4: dd00 ble.n 8001dc8 <__aeabi_dsub+0x318> + 8001dc6: e0b7 b.n 8001f38 <__aeabi_dsub+0x488> + 8001dc8: 2220 movs r2, #32 + 8001dca: 000f movs r7, r1 + 8001dcc: 1ad2 subs r2, r2, r3 + 8001dce: 4691 mov r9, r2 + 8001dd0: 4097 lsls r7, r2 + 8001dd2: 4662 mov r2, ip + 8001dd4: 40da lsrs r2, r3 + 8001dd6: 4317 orrs r7, r2 + 8001dd8: 46b8 mov r8, r7 + 8001dda: 4662 mov r2, ip + 8001ddc: 464f mov r7, r9 + 8001dde: 40ba lsls r2, r7 + 8001de0: 40d9 lsrs r1, r3 + 8001de2: 1e57 subs r7, r2, #1 + 8001de4: 41ba sbcs r2, r7 + 8001de6: 4647 mov r7, r8 + 8001de8: 1a6d subs r5, r5, r1 + 8001dea: 4317 orrs r7, r2 + 8001dec: 1bc7 subs r7, r0, r7 + 8001dee: 42b8 cmp r0, r7 + 8001df0: 4180 sbcs r0, r0 + 8001df2: 4240 negs r0, r0 + 8001df4: 1a2d subs r5, r5, r0 + 8001df6: 022b lsls r3, r5, #8 + 8001df8: d416 bmi.n 8001e28 <__aeabi_dsub+0x378> + 8001dfa: 077b lsls r3, r7, #29 + 8001dfc: d100 bne.n 8001e00 <__aeabi_dsub+0x350> + 8001dfe: e279 b.n 80022f4 <__aeabi_dsub+0x844> + 8001e00: 230f movs r3, #15 + 8001e02: 403b ands r3, r7 + 8001e04: 2b04 cmp r3, #4 + 8001e06: d000 beq.n 8001e0a <__aeabi_dsub+0x35a> + 8001e08: e6ce b.n 8001ba8 <__aeabi_dsub+0xf8> + 8001e0a: 0033 movs r3, r6 + 8001e0c: 08ff lsrs r7, r7, #3 + 8001e0e: e7c9 b.n 8001da4 <__aeabi_dsub+0x2f4> + 8001e10: 000007ff .word 0x000007ff + 8001e14: ff7fffff .word 0xff7fffff + 8001e18: fffff801 .word 0xfffff801 + 8001e1c: 007fffff .word 0x007fffff + 8001e20: 000007fe .word 0x000007fe + 8001e24: 4644 mov r4, r8 + 8001e26: 2601 movs r6, #1 + 8001e28: 026d lsls r5, r5, #9 + 8001e2a: 0a6d lsrs r5, r5, #9 + 8001e2c: 2d00 cmp r5, #0 + 8001e2e: d000 beq.n 8001e32 <__aeabi_dsub+0x382> + 8001e30: e70b b.n 8001c4a <__aeabi_dsub+0x19a> + 8001e32: 0038 movs r0, r7 + 8001e34: f000 fb1c bl 8002470 <__clzsi2> + 8001e38: 0003 movs r3, r0 + 8001e3a: 3018 adds r0, #24 + 8001e3c: 281f cmp r0, #31 + 8001e3e: dc00 bgt.n 8001e42 <__aeabi_dsub+0x392> + 8001e40: e707 b.n 8001c52 <__aeabi_dsub+0x1a2> + 8001e42: 0039 movs r1, r7 + 8001e44: 3b08 subs r3, #8 + 8001e46: 4099 lsls r1, r3 + 8001e48: 4286 cmp r6, r0 + 8001e4a: dd00 ble.n 8001e4e <__aeabi_dsub+0x39e> + 8001e4c: e087 b.n 8001f5e <__aeabi_dsub+0x4ae> + 8001e4e: 1b83 subs r3, r0, r6 + 8001e50: 1c58 adds r0, r3, #1 + 8001e52: 281f cmp r0, #31 + 8001e54: dc00 bgt.n 8001e58 <__aeabi_dsub+0x3a8> + 8001e56: e214 b.n 8002282 <__aeabi_dsub+0x7d2> + 8001e58: 000a movs r2, r1 + 8001e5a: 3b1f subs r3, #31 + 8001e5c: 40da lsrs r2, r3 + 8001e5e: 2820 cmp r0, #32 + 8001e60: d005 beq.n 8001e6e <__aeabi_dsub+0x3be> + 8001e62: 2340 movs r3, #64 @ 0x40 + 8001e64: 1a1b subs r3, r3, r0 + 8001e66: 4099 lsls r1, r3 + 8001e68: 1e4b subs r3, r1, #1 + 8001e6a: 4199 sbcs r1, r3 + 8001e6c: 430a orrs r2, r1 + 8001e6e: 2a00 cmp r2, #0 + 8001e70: d03c beq.n 8001eec <__aeabi_dsub+0x43c> + 8001e72: 2600 movs r6, #0 + 8001e74: 0753 lsls r3, r2, #29 + 8001e76: d000 beq.n 8001e7a <__aeabi_dsub+0x3ca> + 8001e78: e691 b.n 8001b9e <__aeabi_dsub+0xee> + 8001e7a: 0017 movs r7, r2 + 8001e7c: 0035 movs r5, r6 + 8001e7e: 0033 movs r3, r6 + 8001e80: 08ff lsrs r7, r7, #3 + 8001e82: e78f b.n 8001da4 <__aeabi_dsub+0x2f4> + 8001e84: 4aca ldr r2, [pc, #808] @ (80021b0 <__aeabi_dsub+0x700>) + 8001e86: 1c73 adds r3, r6, #1 + 8001e88: 4213 tst r3, r2 + 8001e8a: d17a bne.n 8001f82 <__aeabi_dsub+0x4d2> + 8001e8c: 002b movs r3, r5 + 8001e8e: 4303 orrs r3, r0 + 8001e90: 2e00 cmp r6, #0 + 8001e92: d000 beq.n 8001e96 <__aeabi_dsub+0x3e6> + 8001e94: e192 b.n 80021bc <__aeabi_dsub+0x70c> + 8001e96: 4662 mov r2, ip + 8001e98: 430a orrs r2, r1 + 8001e9a: 2b00 cmp r3, #0 + 8001e9c: d100 bne.n 8001ea0 <__aeabi_dsub+0x3f0> + 8001e9e: e1f4 b.n 800228a <__aeabi_dsub+0x7da> + 8001ea0: 2a00 cmp r2, #0 + 8001ea2: d00d beq.n 8001ec0 <__aeabi_dsub+0x410> + 8001ea4: 4663 mov r3, ip + 8001ea6: 18c7 adds r7, r0, r3 + 8001ea8: 4287 cmp r7, r0 + 8001eaa: 4180 sbcs r0, r0 + 8001eac: 186d adds r5, r5, r1 + 8001eae: 4240 negs r0, r0 + 8001eb0: 182d adds r5, r5, r0 + 8001eb2: 022b lsls r3, r5, #8 + 8001eb4: d500 bpl.n 8001eb8 <__aeabi_dsub+0x408> + 8001eb6: e212 b.n 80022de <__aeabi_dsub+0x82e> + 8001eb8: 003a movs r2, r7 + 8001eba: 46bb mov fp, r7 + 8001ebc: 432a orrs r2, r5 + 8001ebe: d015 beq.n 8001eec <__aeabi_dsub+0x43c> + 8001ec0: 465b mov r3, fp + 8001ec2: 076a lsls r2, r5, #29 + 8001ec4: 08df lsrs r7, r3, #3 + 8001ec6: 433a orrs r2, r7 + 8001ec8: 2300 movs r3, #0 + 8001eca: 08e8 lsrs r0, r5, #3 + 8001ecc: e04c b.n 8001f68 <__aeabi_dsub+0x4b8> + 8001ece: 4663 mov r3, ip + 8001ed0: 1ac7 subs r7, r0, r3 + 8001ed2: 42b8 cmp r0, r7 + 8001ed4: 4192 sbcs r2, r2 + 8001ed6: 1a6b subs r3, r5, r1 + 8001ed8: 4252 negs r2, r2 + 8001eda: 1a9b subs r3, r3, r2 + 8001edc: 021a lsls r2, r3, #8 + 8001ede: d500 bpl.n 8001ee2 <__aeabi_dsub+0x432> + 8001ee0: e087 b.n 8001ff2 <__aeabi_dsub+0x542> + 8001ee2: 003a movs r2, r7 + 8001ee4: 001d movs r5, r3 + 8001ee6: 431a orrs r2, r3 + 8001ee8: d1a0 bne.n 8001e2c <__aeabi_dsub+0x37c> + 8001eea: 2400 movs r4, #0 + 8001eec: 2300 movs r3, #0 + 8001eee: 2500 movs r5, #0 + 8001ef0: e670 b.n 8001bd4 <__aeabi_dsub+0x124> + 8001ef2: 4db0 ldr r5, [pc, #704] @ (80021b4 <__aeabi_dsub+0x704>) + 8001ef4: 1a36 subs r6, r6, r0 + 8001ef6: 400d ands r5, r1 + 8001ef8: 077b lsls r3, r7, #29 + 8001efa: d000 beq.n 8001efe <__aeabi_dsub+0x44e> + 8001efc: e780 b.n 8001e00 <__aeabi_dsub+0x350> + 8001efe: 0033 movs r3, r6 + 8001f00: e784 b.n 8001e0c <__aeabi_dsub+0x35c> + 8001f02: 464b mov r3, r9 + 8001f04: 002a movs r2, r5 + 8001f06: 4302 orrs r2, r0 + 8001f08: d07e beq.n 8002008 <__aeabi_dsub+0x558> + 8001f0a: 1e5a subs r2, r3, #1 + 8001f0c: 2b01 cmp r3, #1 + 8001f0e: d100 bne.n 8001f12 <__aeabi_dsub+0x462> + 8001f10: e11f b.n 8002152 <__aeabi_dsub+0x6a2> + 8001f12: 4ca9 ldr r4, [pc, #676] @ (80021b8 <__aeabi_dsub+0x708>) + 8001f14: 42a3 cmp r3, r4 + 8001f16: d100 bne.n 8001f1a <__aeabi_dsub+0x46a> + 8001f18: e198 b.n 800224c <__aeabi_dsub+0x79c> + 8001f1a: 2a38 cmp r2, #56 @ 0x38 + 8001f1c: dc00 bgt.n 8001f20 <__aeabi_dsub+0x470> + 8001f1e: e19c b.n 800225a <__aeabi_dsub+0x7aa> + 8001f20: 4662 mov r2, ip + 8001f22: 1e57 subs r7, r2, #1 + 8001f24: 45bc cmp ip, r7 + 8001f26: 4192 sbcs r2, r2 + 8001f28: 4252 negs r2, r2 + 8001f2a: 1a8d subs r5, r1, r2 + 8001f2c: 4644 mov r4, r8 + 8001f2e: 001e movs r6, r3 + 8001f30: 022a lsls r2, r5, #8 + 8001f32: d500 bpl.n 8001f36 <__aeabi_dsub+0x486> + 8001f34: e686 b.n 8001c44 <__aeabi_dsub+0x194> + 8001f36: e637 b.n 8001ba8 <__aeabi_dsub+0xf8> + 8001f38: 001a movs r2, r3 + 8001f3a: 000f movs r7, r1 + 8001f3c: 3a20 subs r2, #32 + 8001f3e: 40d7 lsrs r7, r2 + 8001f40: 46b8 mov r8, r7 + 8001f42: 2b20 cmp r3, #32 + 8001f44: d005 beq.n 8001f52 <__aeabi_dsub+0x4a2> + 8001f46: 2240 movs r2, #64 @ 0x40 + 8001f48: 1ad3 subs r3, r2, r3 + 8001f4a: 4099 lsls r1, r3 + 8001f4c: 4663 mov r3, ip + 8001f4e: 430b orrs r3, r1 + 8001f50: 469a mov sl, r3 + 8001f52: 4657 mov r7, sl + 8001f54: 1e7b subs r3, r7, #1 + 8001f56: 419f sbcs r7, r3 + 8001f58: 4643 mov r3, r8 + 8001f5a: 431f orrs r7, r3 + 8001f5c: e746 b.n 8001dec <__aeabi_dsub+0x33c> + 8001f5e: 4a95 ldr r2, [pc, #596] @ (80021b4 <__aeabi_dsub+0x704>) + 8001f60: 1a33 subs r3, r6, r0 + 8001f62: 4011 ands r1, r2 + 8001f64: 074a lsls r2, r1, #29 + 8001f66: 08c8 lsrs r0, r1, #3 + 8001f68: 0305 lsls r5, r0, #12 + 8001f6a: 055b lsls r3, r3, #21 + 8001f6c: 0b2d lsrs r5, r5, #12 + 8001f6e: 0d5b lsrs r3, r3, #21 + 8001f70: e630 b.n 8001bd4 <__aeabi_dsub+0x124> + 8001f72: 2380 movs r3, #128 @ 0x80 + 8001f74: 041b lsls r3, r3, #16 + 8001f76: 421d tst r5, r3 + 8001f78: d100 bne.n 8001f7c <__aeabi_dsub+0x4cc> + 8001f7a: e0fb b.n 8002174 <__aeabi_dsub+0x6c4> + 8001f7c: 001d movs r5, r3 + 8001f7e: 2700 movs r7, #0 + 8001f80: e5fd b.n 8001b7e <__aeabi_dsub+0xce> + 8001f82: 4a8d ldr r2, [pc, #564] @ (80021b8 <__aeabi_dsub+0x708>) + 8001f84: 4293 cmp r3, r2 + 8001f86: d100 bne.n 8001f8a <__aeabi_dsub+0x4da> + 8001f88: e703 b.n 8001d92 <__aeabi_dsub+0x2e2> + 8001f8a: 4662 mov r2, ip + 8001f8c: 1882 adds r2, r0, r2 + 8001f8e: 4282 cmp r2, r0 + 8001f90: 4180 sbcs r0, r0 + 8001f92: 1869 adds r1, r5, r1 + 8001f94: 4240 negs r0, r0 + 8001f96: 1808 adds r0, r1, r0 + 8001f98: 07c7 lsls r7, r0, #31 + 8001f9a: 0852 lsrs r2, r2, #1 + 8001f9c: 4317 orrs r7, r2 + 8001f9e: 0845 lsrs r5, r0, #1 + 8001fa0: 0752 lsls r2, r2, #29 + 8001fa2: d400 bmi.n 8001fa6 <__aeabi_dsub+0x4f6> + 8001fa4: e1ae b.n 8002304 <__aeabi_dsub+0x854> + 8001fa6: 220f movs r2, #15 + 8001fa8: 001e movs r6, r3 + 8001faa: 403a ands r2, r7 + 8001fac: 2a04 cmp r2, #4 + 8001fae: d000 beq.n 8001fb2 <__aeabi_dsub+0x502> + 8001fb0: e5fa b.n 8001ba8 <__aeabi_dsub+0xf8> + 8001fb2: 08ff lsrs r7, r7, #3 + 8001fb4: 076a lsls r2, r5, #29 + 8001fb6: 433a orrs r2, r7 + 8001fb8: 0900 lsrs r0, r0, #4 + 8001fba: e7d5 b.n 8001f68 <__aeabi_dsub+0x4b8> + 8001fbc: 4663 mov r3, ip + 8001fbe: 074f lsls r7, r1, #29 + 8001fc0: 08da lsrs r2, r3, #3 + 8001fc2: 4317 orrs r7, r2 + 8001fc4: 08c8 lsrs r0, r1, #3 + 8001fc6: e624 b.n 8001c12 <__aeabi_dsub+0x162> + 8001fc8: 1e47 subs r7, r0, #1 + 8001fca: 42b8 cmp r0, r7 + 8001fcc: 4180 sbcs r0, r0 + 8001fce: 4240 negs r0, r0 + 8001fd0: 1a2d subs r5, r5, r0 + 8001fd2: 001e movs r6, r3 + 8001fd4: 022a lsls r2, r5, #8 + 8001fd6: d500 bpl.n 8001fda <__aeabi_dsub+0x52a> + 8001fd8: e634 b.n 8001c44 <__aeabi_dsub+0x194> + 8001fda: e5e5 b.n 8001ba8 <__aeabi_dsub+0xf8> + 8001fdc: 2b00 cmp r3, #0 + 8001fde: d000 beq.n 8001fe2 <__aeabi_dsub+0x532> + 8001fe0: e10d b.n 80021fe <__aeabi_dsub+0x74e> + 8001fe2: 2a00 cmp r2, #0 + 8001fe4: d000 beq.n 8001fe8 <__aeabi_dsub+0x538> + 8001fe6: e169 b.n 80022bc <__aeabi_dsub+0x80c> + 8001fe8: 2580 movs r5, #128 @ 0x80 + 8001fea: 2400 movs r4, #0 + 8001fec: 4b72 ldr r3, [pc, #456] @ (80021b8 <__aeabi_dsub+0x708>) + 8001fee: 032d lsls r5, r5, #12 + 8001ff0: e5f0 b.n 8001bd4 <__aeabi_dsub+0x124> + 8001ff2: 4663 mov r3, ip + 8001ff4: 1a1f subs r7, r3, r0 + 8001ff6: 45bc cmp ip, r7 + 8001ff8: 4192 sbcs r2, r2 + 8001ffa: 2401 movs r4, #1 + 8001ffc: 4643 mov r3, r8 + 8001ffe: 1b4d subs r5, r1, r5 + 8002000: 4252 negs r2, r2 + 8002002: 1aad subs r5, r5, r2 + 8002004: 401c ands r4, r3 + 8002006: e711 b.n 8001e2c <__aeabi_dsub+0x37c> + 8002008: 4662 mov r2, ip + 800200a: 4644 mov r4, r8 + 800200c: 000d movs r5, r1 + 800200e: 08d7 lsrs r7, r2, #3 + 8002010: e6c8 b.n 8001da4 <__aeabi_dsub+0x2f4> + 8002012: 4663 mov r3, ip + 8002014: 18c6 adds r6, r0, r3 + 8002016: 4286 cmp r6, r0 + 8002018: 4180 sbcs r0, r0 + 800201a: 1869 adds r1, r5, r1 + 800201c: 4240 negs r0, r0 + 800201e: 1809 adds r1, r1, r0 + 8002020: 020b lsls r3, r1, #8 + 8002022: d400 bmi.n 8002026 <__aeabi_dsub+0x576> + 8002024: e10c b.n 8002240 <__aeabi_dsub+0x790> + 8002026: 4b63 ldr r3, [pc, #396] @ (80021b4 <__aeabi_dsub+0x704>) + 8002028: 0870 lsrs r0, r6, #1 + 800202a: 4019 ands r1, r3 + 800202c: 07cb lsls r3, r1, #31 + 800202e: 4303 orrs r3, r0 + 8002030: 084a lsrs r2, r1, #1 + 8002032: 0740 lsls r0, r0, #29 + 8002034: d400 bmi.n 8002038 <__aeabi_dsub+0x588> + 8002036: e13b b.n 80022b0 <__aeabi_dsub+0x800> + 8002038: 200f movs r0, #15 + 800203a: 4018 ands r0, r3 + 800203c: 2804 cmp r0, #4 + 800203e: d100 bne.n 8002042 <__aeabi_dsub+0x592> + 8002040: e136 b.n 80022b0 <__aeabi_dsub+0x800> + 8002042: 1d1f adds r7, r3, #4 + 8002044: 429f cmp r7, r3 + 8002046: 41ad sbcs r5, r5 + 8002048: 426d negs r5, r5 + 800204a: 2302 movs r3, #2 + 800204c: 18ad adds r5, r5, r2 + 800204e: 08ff lsrs r7, r7, #3 + 8002050: e6a8 b.n 8001da4 <__aeabi_dsub+0x2f4> + 8002052: 2b00 cmp r3, #0 + 8002054: d100 bne.n 8002058 <__aeabi_dsub+0x5a8> + 8002056: e640 b.n 8001cda <__aeabi_dsub+0x22a> + 8002058: 464b mov r3, r9 + 800205a: 1b9b subs r3, r3, r6 + 800205c: 2e00 cmp r6, #0 + 800205e: d100 bne.n 8002062 <__aeabi_dsub+0x5b2> + 8002060: e750 b.n 8001f04 <__aeabi_dsub+0x454> + 8002062: 2b38 cmp r3, #56 @ 0x38 + 8002064: dd2e ble.n 80020c4 <__aeabi_dsub+0x614> + 8002066: 4663 mov r3, ip + 8002068: 1e5f subs r7, r3, #1 + 800206a: 45bc cmp ip, r7 + 800206c: 4192 sbcs r2, r2 + 800206e: 4252 negs r2, r2 + 8002070: 1a8d subs r5, r1, r2 + 8002072: 4644 mov r4, r8 + 8002074: 464e mov r6, r9 + 8002076: 022b lsls r3, r5, #8 + 8002078: d500 bpl.n 800207c <__aeabi_dsub+0x5cc> + 800207a: e5e3 b.n 8001c44 <__aeabi_dsub+0x194> + 800207c: e594 b.n 8001ba8 <__aeabi_dsub+0xf8> + 800207e: 4663 mov r3, ip + 8002080: 1ac7 subs r7, r0, r3 + 8002082: 42b8 cmp r0, r7 + 8002084: 4180 sbcs r0, r0 + 8002086: 1a6d subs r5, r5, r1 + 8002088: 4240 negs r0, r0 + 800208a: 1a2d subs r5, r5, r0 + 800208c: 022b lsls r3, r5, #8 + 800208e: d500 bpl.n 8002092 <__aeabi_dsub+0x5e2> + 8002090: e6c9 b.n 8001e26 <__aeabi_dsub+0x376> + 8002092: 076a lsls r2, r5, #29 + 8002094: 08ff lsrs r7, r7, #3 + 8002096: 2301 movs r3, #1 + 8002098: 433a orrs r2, r7 + 800209a: 08e8 lsrs r0, r5, #3 + 800209c: e764 b.n 8001f68 <__aeabi_dsub+0x4b8> + 800209e: 001a movs r2, r3 + 80020a0: 000f movs r7, r1 + 80020a2: 3a20 subs r2, #32 + 80020a4: 40d7 lsrs r7, r2 + 80020a6: 46b8 mov r8, r7 + 80020a8: 2b20 cmp r3, #32 + 80020aa: d005 beq.n 80020b8 <__aeabi_dsub+0x608> + 80020ac: 2240 movs r2, #64 @ 0x40 + 80020ae: 1ad3 subs r3, r2, r3 + 80020b0: 4099 lsls r1, r3 + 80020b2: 4663 mov r3, ip + 80020b4: 430b orrs r3, r1 + 80020b6: 469a mov sl, r3 + 80020b8: 4657 mov r7, sl + 80020ba: 1e7b subs r3, r7, #1 + 80020bc: 419f sbcs r7, r3 + 80020be: 4643 mov r3, r8 + 80020c0: 431f orrs r7, r3 + 80020c2: e65c b.n 8001d7e <__aeabi_dsub+0x2ce> + 80020c4: 2280 movs r2, #128 @ 0x80 + 80020c6: 003c movs r4, r7 + 80020c8: 0412 lsls r2, r2, #16 + 80020ca: 4315 orrs r5, r2 + 80020cc: 2b1f cmp r3, #31 + 80020ce: dc26 bgt.n 800211e <__aeabi_dsub+0x66e> + 80020d0: 2220 movs r2, #32 + 80020d2: 002f movs r7, r5 + 80020d4: 1ad2 subs r2, r2, r3 + 80020d6: 0006 movs r6, r0 + 80020d8: 4090 lsls r0, r2 + 80020da: 4097 lsls r7, r2 + 80020dc: 40de lsrs r6, r3 + 80020de: 1e42 subs r2, r0, #1 + 80020e0: 4190 sbcs r0, r2 + 80020e2: 40dd lsrs r5, r3 + 80020e4: 4337 orrs r7, r6 + 80020e6: 4307 orrs r7, r0 + 80020e8: 1b49 subs r1, r1, r5 + 80020ea: 4663 mov r3, ip + 80020ec: 1bdf subs r7, r3, r7 + 80020ee: 45bc cmp ip, r7 + 80020f0: 4192 sbcs r2, r2 + 80020f2: 4252 negs r2, r2 + 80020f4: 464e mov r6, r9 + 80020f6: 1a8d subs r5, r1, r2 + 80020f8: e67d b.n 8001df6 <__aeabi_dsub+0x346> + 80020fa: 2b00 cmp r3, #0 + 80020fc: d100 bne.n 8002100 <__aeabi_dsub+0x650> + 80020fe: e6c1 b.n 8001e84 <__aeabi_dsub+0x3d4> + 8002100: 464b mov r3, r9 + 8002102: 1b9b subs r3, r3, r6 + 8002104: 2e00 cmp r6, #0 + 8002106: d100 bne.n 800210a <__aeabi_dsub+0x65a> + 8002108: e5d0 b.n 8001cac <__aeabi_dsub+0x1fc> + 800210a: 2b38 cmp r3, #56 @ 0x38 + 800210c: dd36 ble.n 800217c <__aeabi_dsub+0x6cc> + 800210e: 2580 movs r5, #128 @ 0x80 + 8002110: 042d lsls r5, r5, #16 + 8002112: 4229 tst r1, r5 + 8002114: d100 bne.n 8002118 <__aeabi_dsub+0x668> + 8002116: e0dd b.n 80022d4 <__aeabi_dsub+0x824> + 8002118: 464e mov r6, r9 + 800211a: 2700 movs r7, #0 + 800211c: e52f b.n 8001b7e <__aeabi_dsub+0xce> + 800211e: 001a movs r2, r3 + 8002120: 002e movs r6, r5 + 8002122: 3a20 subs r2, #32 + 8002124: 40d6 lsrs r6, r2 + 8002126: 2b20 cmp r3, #32 + 8002128: d005 beq.n 8002136 <__aeabi_dsub+0x686> + 800212a: 2240 movs r2, #64 @ 0x40 + 800212c: 1ad3 subs r3, r2, r3 + 800212e: 409d lsls r5, r3 + 8002130: 002f movs r7, r5 + 8002132: 4307 orrs r7, r0 + 8002134: 46bb mov fp, r7 + 8002136: 465f mov r7, fp + 8002138: 1e7b subs r3, r7, #1 + 800213a: 419f sbcs r7, r3 + 800213c: 4337 orrs r7, r6 + 800213e: e7d4 b.n 80020ea <__aeabi_dsub+0x63a> + 8002140: 2a00 cmp r2, #0 + 8002142: d100 bne.n 8002146 <__aeabi_dsub+0x696> + 8002144: e6d1 b.n 8001eea <__aeabi_dsub+0x43a> + 8002146: 2401 movs r4, #1 + 8002148: 4643 mov r3, r8 + 800214a: 000d movs r5, r1 + 800214c: 46e3 mov fp, ip + 800214e: 401c ands r4, r3 + 8002150: e6b6 b.n 8001ec0 <__aeabi_dsub+0x410> + 8002152: 4663 mov r3, ip + 8002154: 1a1f subs r7, r3, r0 + 8002156: 45bc cmp ip, r7 + 8002158: 4192 sbcs r2, r2 + 800215a: 1b4d subs r5, r1, r5 + 800215c: 4252 negs r2, r2 + 800215e: 1aad subs r5, r5, r2 + 8002160: 022b lsls r3, r5, #8 + 8002162: d500 bpl.n 8002166 <__aeabi_dsub+0x6b6> + 8002164: e65e b.n 8001e24 <__aeabi_dsub+0x374> + 8002166: 076a lsls r2, r5, #29 + 8002168: 08ff lsrs r7, r7, #3 + 800216a: 4644 mov r4, r8 + 800216c: 2301 movs r3, #1 + 800216e: 433a orrs r2, r7 + 8002170: 08e8 lsrs r0, r5, #3 + 8002172: e6f9 b.n 8001f68 <__aeabi_dsub+0x4b8> + 8002174: 1c47 adds r7, r0, #1 + 8002176: e517 b.n 8001ba8 <__aeabi_dsub+0xf8> + 8002178: 003b movs r3, r7 + 800217a: e5eb b.n 8001d54 <__aeabi_dsub+0x2a4> + 800217c: 2280 movs r2, #128 @ 0x80 + 800217e: 0412 lsls r2, r2, #16 + 8002180: 4315 orrs r5, r2 + 8002182: 2b1f cmp r3, #31 + 8002184: dc6c bgt.n 8002260 <__aeabi_dsub+0x7b0> + 8002186: 2220 movs r2, #32 + 8002188: 002f movs r7, r5 + 800218a: 1ad2 subs r2, r2, r3 + 800218c: 0006 movs r6, r0 + 800218e: 4090 lsls r0, r2 + 8002190: 4097 lsls r7, r2 + 8002192: 40de lsrs r6, r3 + 8002194: 1e42 subs r2, r0, #1 + 8002196: 4190 sbcs r0, r2 + 8002198: 40dd lsrs r5, r3 + 800219a: 4337 orrs r7, r6 + 800219c: 4307 orrs r7, r0 + 800219e: 1949 adds r1, r1, r5 + 80021a0: 4467 add r7, ip + 80021a2: 4567 cmp r7, ip + 80021a4: 4192 sbcs r2, r2 + 80021a6: 4252 negs r2, r2 + 80021a8: 464e mov r6, r9 + 80021aa: 1855 adds r5, r2, r1 + 80021ac: e5ec b.n 8001d88 <__aeabi_dsub+0x2d8> + 80021ae: 46c0 nop @ (mov r8, r8) + 80021b0: 000007fe .word 0x000007fe + 80021b4: ff7fffff .word 0xff7fffff + 80021b8: 000007ff .word 0x000007ff + 80021bc: 2b00 cmp r3, #0 + 80021be: d100 bne.n 80021c2 <__aeabi_dsub+0x712> + 80021c0: e6fc b.n 8001fbc <__aeabi_dsub+0x50c> + 80021c2: 08c7 lsrs r7, r0, #3 + 80021c4: 076b lsls r3, r5, #29 + 80021c6: 431f orrs r7, r3 + 80021c8: 4663 mov r3, ip + 80021ca: 08e8 lsrs r0, r5, #3 + 80021cc: 430b orrs r3, r1 + 80021ce: d100 bne.n 80021d2 <__aeabi_dsub+0x722> + 80021d0: e51f b.n 8001c12 <__aeabi_dsub+0x162> + 80021d2: 2380 movs r3, #128 @ 0x80 + 80021d4: 031b lsls r3, r3, #12 + 80021d6: 4218 tst r0, r3 + 80021d8: d007 beq.n 80021ea <__aeabi_dsub+0x73a> + 80021da: 08ca lsrs r2, r1, #3 + 80021dc: 421a tst r2, r3 + 80021de: d104 bne.n 80021ea <__aeabi_dsub+0x73a> + 80021e0: 4663 mov r3, ip + 80021e2: 0010 movs r0, r2 + 80021e4: 08df lsrs r7, r3, #3 + 80021e6: 0749 lsls r1, r1, #29 + 80021e8: 430f orrs r7, r1 + 80021ea: 0f7b lsrs r3, r7, #29 + 80021ec: 00ff lsls r7, r7, #3 + 80021ee: 08ff lsrs r7, r7, #3 + 80021f0: 075b lsls r3, r3, #29 + 80021f2: 431f orrs r7, r3 + 80021f4: e50d b.n 8001c12 <__aeabi_dsub+0x162> + 80021f6: 4662 mov r2, ip + 80021f8: 000d movs r5, r1 + 80021fa: 08d7 lsrs r7, r2, #3 + 80021fc: e5d2 b.n 8001da4 <__aeabi_dsub+0x2f4> + 80021fe: 08c7 lsrs r7, r0, #3 + 8002200: 076b lsls r3, r5, #29 + 8002202: 431f orrs r7, r3 + 8002204: 08e8 lsrs r0, r5, #3 + 8002206: 2a00 cmp r2, #0 + 8002208: d100 bne.n 800220c <__aeabi_dsub+0x75c> + 800220a: e502 b.n 8001c12 <__aeabi_dsub+0x162> + 800220c: 2380 movs r3, #128 @ 0x80 + 800220e: 031b lsls r3, r3, #12 + 8002210: 4218 tst r0, r3 + 8002212: d0ea beq.n 80021ea <__aeabi_dsub+0x73a> + 8002214: 08ca lsrs r2, r1, #3 + 8002216: 421a tst r2, r3 + 8002218: d1e7 bne.n 80021ea <__aeabi_dsub+0x73a> + 800221a: 4663 mov r3, ip + 800221c: 2401 movs r4, #1 + 800221e: 08df lsrs r7, r3, #3 + 8002220: 4643 mov r3, r8 + 8002222: 0749 lsls r1, r1, #29 + 8002224: 0010 movs r0, r2 + 8002226: 430f orrs r7, r1 + 8002228: 401c ands r4, r3 + 800222a: e7de b.n 80021ea <__aeabi_dsub+0x73a> + 800222c: 4460 add r0, ip + 800222e: 4560 cmp r0, ip + 8002230: 4192 sbcs r2, r2 + 8002232: 1869 adds r1, r5, r1 + 8002234: 4252 negs r2, r2 + 8002236: 1889 adds r1, r1, r2 + 8002238: 0006 movs r6, r0 + 800223a: 020b lsls r3, r1, #8 + 800223c: d500 bpl.n 8002240 <__aeabi_dsub+0x790> + 800223e: e6f2 b.n 8002026 <__aeabi_dsub+0x576> + 8002240: 074a lsls r2, r1, #29 + 8002242: 08f6 lsrs r6, r6, #3 + 8002244: 2301 movs r3, #1 + 8002246: 4332 orrs r2, r6 + 8002248: 08c8 lsrs r0, r1, #3 + 800224a: e68d b.n 8001f68 <__aeabi_dsub+0x4b8> + 800224c: 4663 mov r3, ip + 800224e: 08df lsrs r7, r3, #3 + 8002250: 074b lsls r3, r1, #29 + 8002252: 4644 mov r4, r8 + 8002254: 431f orrs r7, r3 + 8002256: 08c8 lsrs r0, r1, #3 + 8002258: e4db b.n 8001c12 <__aeabi_dsub+0x162> + 800225a: 4644 mov r4, r8 + 800225c: 0013 movs r3, r2 + 800225e: e735 b.n 80020cc <__aeabi_dsub+0x61c> + 8002260: 001a movs r2, r3 + 8002262: 002e movs r6, r5 + 8002264: 3a20 subs r2, #32 + 8002266: 40d6 lsrs r6, r2 + 8002268: 2b20 cmp r3, #32 + 800226a: d005 beq.n 8002278 <__aeabi_dsub+0x7c8> + 800226c: 2240 movs r2, #64 @ 0x40 + 800226e: 1ad3 subs r3, r2, r3 + 8002270: 409d lsls r5, r3 + 8002272: 002f movs r7, r5 + 8002274: 4307 orrs r7, r0 + 8002276: 46bb mov fp, r7 + 8002278: 465f mov r7, fp + 800227a: 1e7b subs r3, r7, #1 + 800227c: 419f sbcs r7, r3 + 800227e: 4337 orrs r7, r6 + 8002280: e78e b.n 80021a0 <__aeabi_dsub+0x6f0> + 8002282: 2320 movs r3, #32 + 8002284: 2700 movs r7, #0 + 8002286: 1a1b subs r3, r3, r0 + 8002288: e4f5 b.n 8001c76 <__aeabi_dsub+0x1c6> + 800228a: 2300 movs r3, #0 + 800228c: 2a00 cmp r2, #0 + 800228e: d100 bne.n 8002292 <__aeabi_dsub+0x7e2> + 8002290: e592 b.n 8001db8 <__aeabi_dsub+0x308> + 8002292: 4667 mov r7, ip + 8002294: 000d movs r5, r1 + 8002296: 08ff lsrs r7, r7, #3 + 8002298: e584 b.n 8001da4 <__aeabi_dsub+0x2f4> + 800229a: 003a movs r2, r7 + 800229c: 431a orrs r2, r3 + 800229e: d100 bne.n 80022a2 <__aeabi_dsub+0x7f2> + 80022a0: e623 b.n 8001eea <__aeabi_dsub+0x43a> + 80022a2: 001d movs r5, r3 + 80022a4: 46bb mov fp, r7 + 80022a6: e60b b.n 8001ec0 <__aeabi_dsub+0x410> + 80022a8: 0017 movs r7, r2 + 80022aa: 0033 movs r3, r6 + 80022ac: 08ff lsrs r7, r7, #3 + 80022ae: e579 b.n 8001da4 <__aeabi_dsub+0x2f4> + 80022b0: 08db lsrs r3, r3, #3 + 80022b2: 0752 lsls r2, r2, #29 + 80022b4: 431a orrs r2, r3 + 80022b6: 0908 lsrs r0, r1, #4 + 80022b8: 2302 movs r3, #2 + 80022ba: e655 b.n 8001f68 <__aeabi_dsub+0x4b8> + 80022bc: 4663 mov r3, ip + 80022be: 2401 movs r4, #1 + 80022c0: 08da lsrs r2, r3, #3 + 80022c2: 4643 mov r3, r8 + 80022c4: 074f lsls r7, r1, #29 + 80022c6: 4317 orrs r7, r2 + 80022c8: 08c8 lsrs r0, r1, #3 + 80022ca: 401c ands r4, r3 + 80022cc: e4a1 b.n 8001c12 <__aeabi_dsub+0x162> + 80022ce: 001e movs r6, r3 + 80022d0: 1c47 adds r7, r0, #1 + 80022d2: e469 b.n 8001ba8 <__aeabi_dsub+0xf8> + 80022d4: 4667 mov r7, ip + 80022d6: 000d movs r5, r1 + 80022d8: 464e mov r6, r9 + 80022da: 3701 adds r7, #1 + 80022dc: e464 b.n 8001ba8 <__aeabi_dsub+0xf8> + 80022de: 4b0f ldr r3, [pc, #60] @ (800231c <__aeabi_dsub+0x86c>) + 80022e0: 08ff lsrs r7, r7, #3 + 80022e2: 401d ands r5, r3 + 80022e4: 076a lsls r2, r5, #29 + 80022e6: 026d lsls r5, r5, #9 + 80022e8: 2301 movs r3, #1 + 80022ea: 433a orrs r2, r7 + 80022ec: 0b2d lsrs r5, r5, #12 + 80022ee: e471 b.n 8001bd4 <__aeabi_dsub+0x124> + 80022f0: 0013 movs r3, r2 + 80022f2: e746 b.n 8002182 <__aeabi_dsub+0x6d2> + 80022f4: 0033 movs r3, r6 + 80022f6: 08ff lsrs r7, r7, #3 + 80022f8: e554 b.n 8001da4 <__aeabi_dsub+0x2f4> + 80022fa: 4667 mov r7, ip + 80022fc: 000d movs r5, r1 + 80022fe: 001e movs r6, r3 + 8002300: 3701 adds r7, #1 + 8002302: e451 b.n 8001ba8 <__aeabi_dsub+0xf8> + 8002304: 076a lsls r2, r5, #29 + 8002306: 08ff lsrs r7, r7, #3 + 8002308: 433a orrs r2, r7 + 800230a: 0900 lsrs r0, r0, #4 + 800230c: e62c b.n 8001f68 <__aeabi_dsub+0x4b8> + 800230e: 08c0 lsrs r0, r0, #3 + 8002310: 076a lsls r2, r5, #29 + 8002312: 4302 orrs r2, r0 + 8002314: 2300 movs r3, #0 + 8002316: 08e8 lsrs r0, r5, #3 + 8002318: e626 b.n 8001f68 <__aeabi_dsub+0x4b8> + 800231a: 46c0 nop @ (mov r8, r8) + 800231c: ff7fffff .word 0xff7fffff + +08002320 <__aeabi_d2iz>: + 8002320: 000b movs r3, r1 + 8002322: 0002 movs r2, r0 + 8002324: b570 push {r4, r5, r6, lr} + 8002326: 4d16 ldr r5, [pc, #88] @ (8002380 <__aeabi_d2iz+0x60>) + 8002328: 030c lsls r4, r1, #12 + 800232a: b082 sub sp, #8 + 800232c: 0049 lsls r1, r1, #1 + 800232e: 2000 movs r0, #0 + 8002330: 9200 str r2, [sp, #0] + 8002332: 9301 str r3, [sp, #4] + 8002334: 0b24 lsrs r4, r4, #12 + 8002336: 0d49 lsrs r1, r1, #21 + 8002338: 0fde lsrs r6, r3, #31 + 800233a: 42a9 cmp r1, r5 + 800233c: dd04 ble.n 8002348 <__aeabi_d2iz+0x28> + 800233e: 4811 ldr r0, [pc, #68] @ (8002384 <__aeabi_d2iz+0x64>) + 8002340: 4281 cmp r1, r0 + 8002342: dd03 ble.n 800234c <__aeabi_d2iz+0x2c> + 8002344: 4b10 ldr r3, [pc, #64] @ (8002388 <__aeabi_d2iz+0x68>) + 8002346: 18f0 adds r0, r6, r3 + 8002348: b002 add sp, #8 + 800234a: bd70 pop {r4, r5, r6, pc} + 800234c: 2080 movs r0, #128 @ 0x80 + 800234e: 0340 lsls r0, r0, #13 + 8002350: 4320 orrs r0, r4 + 8002352: 4c0e ldr r4, [pc, #56] @ (800238c <__aeabi_d2iz+0x6c>) + 8002354: 1a64 subs r4, r4, r1 + 8002356: 2c1f cmp r4, #31 + 8002358: dd08 ble.n 800236c <__aeabi_d2iz+0x4c> + 800235a: 4b0d ldr r3, [pc, #52] @ (8002390 <__aeabi_d2iz+0x70>) + 800235c: 1a5b subs r3, r3, r1 + 800235e: 40d8 lsrs r0, r3 + 8002360: 0003 movs r3, r0 + 8002362: 4258 negs r0, r3 + 8002364: 2e00 cmp r6, #0 + 8002366: d1ef bne.n 8002348 <__aeabi_d2iz+0x28> + 8002368: 0018 movs r0, r3 + 800236a: e7ed b.n 8002348 <__aeabi_d2iz+0x28> + 800236c: 4b09 ldr r3, [pc, #36] @ (8002394 <__aeabi_d2iz+0x74>) + 800236e: 9a00 ldr r2, [sp, #0] + 8002370: 469c mov ip, r3 + 8002372: 0003 movs r3, r0 + 8002374: 4461 add r1, ip + 8002376: 408b lsls r3, r1 + 8002378: 40e2 lsrs r2, r4 + 800237a: 4313 orrs r3, r2 + 800237c: e7f1 b.n 8002362 <__aeabi_d2iz+0x42> + 800237e: 46c0 nop @ (mov r8, r8) + 8002380: 000003fe .word 0x000003fe + 8002384: 0000041d .word 0x0000041d + 8002388: 7fffffff .word 0x7fffffff + 800238c: 00000433 .word 0x00000433 + 8002390: 00000413 .word 0x00000413 + 8002394: fffffbed .word 0xfffffbed + +08002398 <__aeabi_i2d>: + 8002398: b570 push {r4, r5, r6, lr} + 800239a: 2800 cmp r0, #0 + 800239c: d016 beq.n 80023cc <__aeabi_i2d+0x34> + 800239e: 17c3 asrs r3, r0, #31 + 80023a0: 18c5 adds r5, r0, r3 + 80023a2: 405d eors r5, r3 + 80023a4: 0fc4 lsrs r4, r0, #31 + 80023a6: 0028 movs r0, r5 + 80023a8: f000 f862 bl 8002470 <__clzsi2> + 80023ac: 4b10 ldr r3, [pc, #64] @ (80023f0 <__aeabi_i2d+0x58>) + 80023ae: 1a1b subs r3, r3, r0 + 80023b0: 055b lsls r3, r3, #21 + 80023b2: 0d5b lsrs r3, r3, #21 + 80023b4: 280a cmp r0, #10 + 80023b6: dc14 bgt.n 80023e2 <__aeabi_i2d+0x4a> + 80023b8: 0002 movs r2, r0 + 80023ba: 002e movs r6, r5 + 80023bc: 3215 adds r2, #21 + 80023be: 4096 lsls r6, r2 + 80023c0: 220b movs r2, #11 + 80023c2: 1a12 subs r2, r2, r0 + 80023c4: 40d5 lsrs r5, r2 + 80023c6: 032d lsls r5, r5, #12 + 80023c8: 0b2d lsrs r5, r5, #12 + 80023ca: e003 b.n 80023d4 <__aeabi_i2d+0x3c> + 80023cc: 2400 movs r4, #0 + 80023ce: 2300 movs r3, #0 + 80023d0: 2500 movs r5, #0 + 80023d2: 2600 movs r6, #0 + 80023d4: 051b lsls r3, r3, #20 + 80023d6: 432b orrs r3, r5 + 80023d8: 07e4 lsls r4, r4, #31 + 80023da: 4323 orrs r3, r4 + 80023dc: 0030 movs r0, r6 + 80023de: 0019 movs r1, r3 + 80023e0: bd70 pop {r4, r5, r6, pc} + 80023e2: 380b subs r0, #11 + 80023e4: 4085 lsls r5, r0 + 80023e6: 032d lsls r5, r5, #12 + 80023e8: 2600 movs r6, #0 + 80023ea: 0b2d lsrs r5, r5, #12 + 80023ec: e7f2 b.n 80023d4 <__aeabi_i2d+0x3c> + 80023ee: 46c0 nop @ (mov r8, r8) + 80023f0: 0000041e .word 0x0000041e + +080023f4 <__aeabi_cdrcmple>: + 80023f4: 4684 mov ip, r0 + 80023f6: 0010 movs r0, r2 + 80023f8: 4662 mov r2, ip + 80023fa: 468c mov ip, r1 + 80023fc: 0019 movs r1, r3 + 80023fe: 4663 mov r3, ip + 8002400: e000 b.n 8002404 <__aeabi_cdcmpeq> + 8002402: 46c0 nop @ (mov r8, r8) + +08002404 <__aeabi_cdcmpeq>: + 8002404: b51f push {r0, r1, r2, r3, r4, lr} + 8002406: f000 f907 bl 8002618 <__ledf2> + 800240a: 2800 cmp r0, #0 + 800240c: d401 bmi.n 8002412 <__aeabi_cdcmpeq+0xe> + 800240e: 2100 movs r1, #0 + 8002410: 42c8 cmn r0, r1 + 8002412: bd1f pop {r0, r1, r2, r3, r4, pc} + +08002414 <__aeabi_dcmpeq>: + 8002414: b510 push {r4, lr} + 8002416: f000 f849 bl 80024ac <__eqdf2> + 800241a: 4240 negs r0, r0 + 800241c: 3001 adds r0, #1 + 800241e: bd10 pop {r4, pc} + +08002420 <__aeabi_dcmplt>: + 8002420: b510 push {r4, lr} + 8002422: f000 f8f9 bl 8002618 <__ledf2> + 8002426: 2800 cmp r0, #0 + 8002428: db01 blt.n 800242e <__aeabi_dcmplt+0xe> + 800242a: 2000 movs r0, #0 + 800242c: bd10 pop {r4, pc} + 800242e: 2001 movs r0, #1 + 8002430: bd10 pop {r4, pc} + 8002432: 46c0 nop @ (mov r8, r8) + +08002434 <__aeabi_dcmple>: + 8002434: b510 push {r4, lr} + 8002436: f000 f8ef bl 8002618 <__ledf2> + 800243a: 2800 cmp r0, #0 + 800243c: dd01 ble.n 8002442 <__aeabi_dcmple+0xe> + 800243e: 2000 movs r0, #0 + 8002440: bd10 pop {r4, pc} + 8002442: 2001 movs r0, #1 + 8002444: bd10 pop {r4, pc} + 8002446: 46c0 nop @ (mov r8, r8) + +08002448 <__aeabi_dcmpgt>: + 8002448: b510 push {r4, lr} + 800244a: f000 f875 bl 8002538 <__gedf2> + 800244e: 2800 cmp r0, #0 + 8002450: dc01 bgt.n 8002456 <__aeabi_dcmpgt+0xe> + 8002452: 2000 movs r0, #0 + 8002454: bd10 pop {r4, pc} + 8002456: 2001 movs r0, #1 + 8002458: bd10 pop {r4, pc} + 800245a: 46c0 nop @ (mov r8, r8) + +0800245c <__aeabi_dcmpge>: + 800245c: b510 push {r4, lr} + 800245e: f000 f86b bl 8002538 <__gedf2> + 8002462: 2800 cmp r0, #0 + 8002464: da01 bge.n 800246a <__aeabi_dcmpge+0xe> + 8002466: 2000 movs r0, #0 + 8002468: bd10 pop {r4, pc} + 800246a: 2001 movs r0, #1 + 800246c: bd10 pop {r4, pc} + 800246e: 46c0 nop @ (mov r8, r8) + +08002470 <__clzsi2>: + 8002470: 211c movs r1, #28 + 8002472: 2301 movs r3, #1 + 8002474: 041b lsls r3, r3, #16 + 8002476: 4298 cmp r0, r3 + 8002478: d301 bcc.n 800247e <__clzsi2+0xe> + 800247a: 0c00 lsrs r0, r0, #16 + 800247c: 3910 subs r1, #16 + 800247e: 0a1b lsrs r3, r3, #8 + 8002480: 4298 cmp r0, r3 + 8002482: d301 bcc.n 8002488 <__clzsi2+0x18> + 8002484: 0a00 lsrs r0, r0, #8 + 8002486: 3908 subs r1, #8 + 8002488: 091b lsrs r3, r3, #4 + 800248a: 4298 cmp r0, r3 + 800248c: d301 bcc.n 8002492 <__clzsi2+0x22> + 800248e: 0900 lsrs r0, r0, #4 + 8002490: 3904 subs r1, #4 + 8002492: a202 add r2, pc, #8 @ (adr r2, 800249c <__clzsi2+0x2c>) + 8002494: 5c10 ldrb r0, [r2, r0] + 8002496: 1840 adds r0, r0, r1 + 8002498: 4770 bx lr + 800249a: 46c0 nop @ (mov r8, r8) + 800249c: 02020304 .word 0x02020304 + 80024a0: 01010101 .word 0x01010101 + ... + +080024ac <__eqdf2>: + 80024ac: b5f0 push {r4, r5, r6, r7, lr} + 80024ae: 4657 mov r7, sl + 80024b0: 46de mov lr, fp + 80024b2: 464e mov r6, r9 + 80024b4: 4645 mov r5, r8 + 80024b6: b5e0 push {r5, r6, r7, lr} + 80024b8: 000d movs r5, r1 + 80024ba: 0004 movs r4, r0 + 80024bc: 0fe8 lsrs r0, r5, #31 + 80024be: 4683 mov fp, r0 + 80024c0: 0309 lsls r1, r1, #12 + 80024c2: 0fd8 lsrs r0, r3, #31 + 80024c4: 0b09 lsrs r1, r1, #12 + 80024c6: 4682 mov sl, r0 + 80024c8: 481a ldr r0, [pc, #104] @ (8002534 <__eqdf2+0x88>) + 80024ca: 468c mov ip, r1 + 80024cc: 031f lsls r7, r3, #12 + 80024ce: 0069 lsls r1, r5, #1 + 80024d0: 005e lsls r6, r3, #1 + 80024d2: 0d49 lsrs r1, r1, #21 + 80024d4: 0b3f lsrs r7, r7, #12 + 80024d6: 0d76 lsrs r6, r6, #21 + 80024d8: 4281 cmp r1, r0 + 80024da: d01a beq.n 8002512 <__eqdf2+0x66> + 80024dc: 4286 cmp r6, r0 + 80024de: d011 beq.n 8002504 <__eqdf2+0x58> + 80024e0: 2001 movs r0, #1 + 80024e2: 42b1 cmp r1, r6 + 80024e4: d10f bne.n 8002506 <__eqdf2+0x5a> + 80024e6: 45bc cmp ip, r7 + 80024e8: d10d bne.n 8002506 <__eqdf2+0x5a> + 80024ea: 42a2 cmp r2, r4 + 80024ec: d10b bne.n 8002506 <__eqdf2+0x5a> + 80024ee: 45d3 cmp fp, sl + 80024f0: d01e beq.n 8002530 <__eqdf2+0x84> + 80024f2: 2900 cmp r1, #0 + 80024f4: d107 bne.n 8002506 <__eqdf2+0x5a> + 80024f6: 4661 mov r1, ip + 80024f8: 4311 orrs r1, r2 + 80024fa: 000a movs r2, r1 + 80024fc: 1e53 subs r3, r2, #1 + 80024fe: 419a sbcs r2, r3 + 8002500: 0010 movs r0, r2 + 8002502: e000 b.n 8002506 <__eqdf2+0x5a> + 8002504: 2001 movs r0, #1 + 8002506: bcf0 pop {r4, r5, r6, r7} + 8002508: 46bb mov fp, r7 + 800250a: 46b2 mov sl, r6 + 800250c: 46a9 mov r9, r5 + 800250e: 46a0 mov r8, r4 + 8002510: bdf0 pop {r4, r5, r6, r7, pc} + 8002512: 2001 movs r0, #1 + 8002514: 428e cmp r6, r1 + 8002516: d1f6 bne.n 8002506 <__eqdf2+0x5a> + 8002518: 4661 mov r1, ip + 800251a: 4339 orrs r1, r7 + 800251c: 000f movs r7, r1 + 800251e: 4317 orrs r7, r2 + 8002520: 4327 orrs r7, r4 + 8002522: d1f0 bne.n 8002506 <__eqdf2+0x5a> + 8002524: 465b mov r3, fp + 8002526: 4652 mov r2, sl + 8002528: 1a98 subs r0, r3, r2 + 800252a: 1e43 subs r3, r0, #1 + 800252c: 4198 sbcs r0, r3 + 800252e: e7ea b.n 8002506 <__eqdf2+0x5a> + 8002530: 2000 movs r0, #0 + 8002532: e7e8 b.n 8002506 <__eqdf2+0x5a> + 8002534: 000007ff .word 0x000007ff + +08002538 <__gedf2>: + 8002538: b5f0 push {r4, r5, r6, r7, lr} + 800253a: 4657 mov r7, sl + 800253c: 464e mov r6, r9 + 800253e: 4645 mov r5, r8 + 8002540: 46de mov lr, fp + 8002542: b5e0 push {r5, r6, r7, lr} + 8002544: 000d movs r5, r1 + 8002546: 030e lsls r6, r1, #12 + 8002548: 0049 lsls r1, r1, #1 + 800254a: 0d49 lsrs r1, r1, #21 + 800254c: 468a mov sl, r1 + 800254e: 0fdf lsrs r7, r3, #31 + 8002550: 0fe9 lsrs r1, r5, #31 + 8002552: 46bc mov ip, r7 + 8002554: b083 sub sp, #12 + 8002556: 4f2f ldr r7, [pc, #188] @ (8002614 <__gedf2+0xdc>) + 8002558: 0004 movs r4, r0 + 800255a: 4680 mov r8, r0 + 800255c: 9101 str r1, [sp, #4] + 800255e: 0058 lsls r0, r3, #1 + 8002560: 0319 lsls r1, r3, #12 + 8002562: 4691 mov r9, r2 + 8002564: 0b36 lsrs r6, r6, #12 + 8002566: 0b09 lsrs r1, r1, #12 + 8002568: 0d40 lsrs r0, r0, #21 + 800256a: 45ba cmp sl, r7 + 800256c: d01d beq.n 80025aa <__gedf2+0x72> + 800256e: 42b8 cmp r0, r7 + 8002570: d00d beq.n 800258e <__gedf2+0x56> + 8002572: 4657 mov r7, sl + 8002574: 2f00 cmp r7, #0 + 8002576: d12a bne.n 80025ce <__gedf2+0x96> + 8002578: 4334 orrs r4, r6 + 800257a: 2800 cmp r0, #0 + 800257c: d124 bne.n 80025c8 <__gedf2+0x90> + 800257e: 430a orrs r2, r1 + 8002580: d036 beq.n 80025f0 <__gedf2+0xb8> + 8002582: 2c00 cmp r4, #0 + 8002584: d141 bne.n 800260a <__gedf2+0xd2> + 8002586: 4663 mov r3, ip + 8002588: 0058 lsls r0, r3, #1 + 800258a: 3801 subs r0, #1 + 800258c: e015 b.n 80025ba <__gedf2+0x82> + 800258e: 4311 orrs r1, r2 + 8002590: d138 bne.n 8002604 <__gedf2+0xcc> + 8002592: 4653 mov r3, sl + 8002594: 2b00 cmp r3, #0 + 8002596: d101 bne.n 800259c <__gedf2+0x64> + 8002598: 4326 orrs r6, r4 + 800259a: d0f4 beq.n 8002586 <__gedf2+0x4e> + 800259c: 9b01 ldr r3, [sp, #4] + 800259e: 4563 cmp r3, ip + 80025a0: d107 bne.n 80025b2 <__gedf2+0x7a> + 80025a2: 9b01 ldr r3, [sp, #4] + 80025a4: 0058 lsls r0, r3, #1 + 80025a6: 3801 subs r0, #1 + 80025a8: e007 b.n 80025ba <__gedf2+0x82> + 80025aa: 4326 orrs r6, r4 + 80025ac: d12a bne.n 8002604 <__gedf2+0xcc> + 80025ae: 4550 cmp r0, sl + 80025b0: d021 beq.n 80025f6 <__gedf2+0xbe> + 80025b2: 2001 movs r0, #1 + 80025b4: 9b01 ldr r3, [sp, #4] + 80025b6: 425f negs r7, r3 + 80025b8: 4338 orrs r0, r7 + 80025ba: b003 add sp, #12 + 80025bc: bcf0 pop {r4, r5, r6, r7} + 80025be: 46bb mov fp, r7 + 80025c0: 46b2 mov sl, r6 + 80025c2: 46a9 mov r9, r5 + 80025c4: 46a0 mov r8, r4 + 80025c6: bdf0 pop {r4, r5, r6, r7, pc} + 80025c8: 2c00 cmp r4, #0 + 80025ca: d0dc beq.n 8002586 <__gedf2+0x4e> + 80025cc: e7e6 b.n 800259c <__gedf2+0x64> + 80025ce: 2800 cmp r0, #0 + 80025d0: d0ef beq.n 80025b2 <__gedf2+0x7a> + 80025d2: 9b01 ldr r3, [sp, #4] + 80025d4: 4563 cmp r3, ip + 80025d6: d1ec bne.n 80025b2 <__gedf2+0x7a> + 80025d8: 4582 cmp sl, r0 + 80025da: dcea bgt.n 80025b2 <__gedf2+0x7a> + 80025dc: dbe1 blt.n 80025a2 <__gedf2+0x6a> + 80025de: 428e cmp r6, r1 + 80025e0: d8e7 bhi.n 80025b2 <__gedf2+0x7a> + 80025e2: d1de bne.n 80025a2 <__gedf2+0x6a> + 80025e4: 45c8 cmp r8, r9 + 80025e6: d8e4 bhi.n 80025b2 <__gedf2+0x7a> + 80025e8: 2000 movs r0, #0 + 80025ea: 45c8 cmp r8, r9 + 80025ec: d2e5 bcs.n 80025ba <__gedf2+0x82> + 80025ee: e7d8 b.n 80025a2 <__gedf2+0x6a> + 80025f0: 2c00 cmp r4, #0 + 80025f2: d0e2 beq.n 80025ba <__gedf2+0x82> + 80025f4: e7dd b.n 80025b2 <__gedf2+0x7a> + 80025f6: 4311 orrs r1, r2 + 80025f8: d104 bne.n 8002604 <__gedf2+0xcc> + 80025fa: 9b01 ldr r3, [sp, #4] + 80025fc: 4563 cmp r3, ip + 80025fe: d1d8 bne.n 80025b2 <__gedf2+0x7a> + 8002600: 2000 movs r0, #0 + 8002602: e7da b.n 80025ba <__gedf2+0x82> + 8002604: 2002 movs r0, #2 + 8002606: 4240 negs r0, r0 + 8002608: e7d7 b.n 80025ba <__gedf2+0x82> + 800260a: 9b01 ldr r3, [sp, #4] + 800260c: 4563 cmp r3, ip + 800260e: d0e6 beq.n 80025de <__gedf2+0xa6> + 8002610: e7cf b.n 80025b2 <__gedf2+0x7a> + 8002612: 46c0 nop @ (mov r8, r8) + 8002614: 000007ff .word 0x000007ff + +08002618 <__ledf2>: + 8002618: b5f0 push {r4, r5, r6, r7, lr} + 800261a: 4657 mov r7, sl + 800261c: 464e mov r6, r9 + 800261e: 4645 mov r5, r8 + 8002620: 46de mov lr, fp + 8002622: b5e0 push {r5, r6, r7, lr} + 8002624: 000d movs r5, r1 + 8002626: 030e lsls r6, r1, #12 + 8002628: 0049 lsls r1, r1, #1 + 800262a: 0d49 lsrs r1, r1, #21 + 800262c: 468a mov sl, r1 + 800262e: 0fdf lsrs r7, r3, #31 + 8002630: 0fe9 lsrs r1, r5, #31 + 8002632: 46bc mov ip, r7 + 8002634: b083 sub sp, #12 + 8002636: 4f2e ldr r7, [pc, #184] @ (80026f0 <__ledf2+0xd8>) + 8002638: 0004 movs r4, r0 + 800263a: 4680 mov r8, r0 + 800263c: 9101 str r1, [sp, #4] + 800263e: 0058 lsls r0, r3, #1 + 8002640: 0319 lsls r1, r3, #12 + 8002642: 4691 mov r9, r2 + 8002644: 0b36 lsrs r6, r6, #12 + 8002646: 0b09 lsrs r1, r1, #12 + 8002648: 0d40 lsrs r0, r0, #21 + 800264a: 45ba cmp sl, r7 + 800264c: d01e beq.n 800268c <__ledf2+0x74> + 800264e: 42b8 cmp r0, r7 + 8002650: d00d beq.n 800266e <__ledf2+0x56> + 8002652: 4657 mov r7, sl + 8002654: 2f00 cmp r7, #0 + 8002656: d127 bne.n 80026a8 <__ledf2+0x90> + 8002658: 4334 orrs r4, r6 + 800265a: 2800 cmp r0, #0 + 800265c: d133 bne.n 80026c6 <__ledf2+0xae> + 800265e: 430a orrs r2, r1 + 8002660: d034 beq.n 80026cc <__ledf2+0xb4> + 8002662: 2c00 cmp r4, #0 + 8002664: d140 bne.n 80026e8 <__ledf2+0xd0> + 8002666: 4663 mov r3, ip + 8002668: 0058 lsls r0, r3, #1 + 800266a: 3801 subs r0, #1 + 800266c: e015 b.n 800269a <__ledf2+0x82> + 800266e: 4311 orrs r1, r2 + 8002670: d112 bne.n 8002698 <__ledf2+0x80> + 8002672: 4653 mov r3, sl + 8002674: 2b00 cmp r3, #0 + 8002676: d101 bne.n 800267c <__ledf2+0x64> + 8002678: 4326 orrs r6, r4 + 800267a: d0f4 beq.n 8002666 <__ledf2+0x4e> + 800267c: 9b01 ldr r3, [sp, #4] + 800267e: 4563 cmp r3, ip + 8002680: d01d beq.n 80026be <__ledf2+0xa6> + 8002682: 2001 movs r0, #1 + 8002684: 9b01 ldr r3, [sp, #4] + 8002686: 425f negs r7, r3 + 8002688: 4338 orrs r0, r7 + 800268a: e006 b.n 800269a <__ledf2+0x82> + 800268c: 4326 orrs r6, r4 + 800268e: d103 bne.n 8002698 <__ledf2+0x80> + 8002690: 4550 cmp r0, sl + 8002692: d1f6 bne.n 8002682 <__ledf2+0x6a> + 8002694: 4311 orrs r1, r2 + 8002696: d01c beq.n 80026d2 <__ledf2+0xba> + 8002698: 2002 movs r0, #2 + 800269a: b003 add sp, #12 + 800269c: bcf0 pop {r4, r5, r6, r7} + 800269e: 46bb mov fp, r7 + 80026a0: 46b2 mov sl, r6 + 80026a2: 46a9 mov r9, r5 + 80026a4: 46a0 mov r8, r4 + 80026a6: bdf0 pop {r4, r5, r6, r7, pc} + 80026a8: 2800 cmp r0, #0 + 80026aa: d0ea beq.n 8002682 <__ledf2+0x6a> + 80026ac: 9b01 ldr r3, [sp, #4] + 80026ae: 4563 cmp r3, ip + 80026b0: d1e7 bne.n 8002682 <__ledf2+0x6a> + 80026b2: 4582 cmp sl, r0 + 80026b4: dce5 bgt.n 8002682 <__ledf2+0x6a> + 80026b6: db02 blt.n 80026be <__ledf2+0xa6> + 80026b8: 428e cmp r6, r1 + 80026ba: d8e2 bhi.n 8002682 <__ledf2+0x6a> + 80026bc: d00e beq.n 80026dc <__ledf2+0xc4> + 80026be: 9b01 ldr r3, [sp, #4] + 80026c0: 0058 lsls r0, r3, #1 + 80026c2: 3801 subs r0, #1 + 80026c4: e7e9 b.n 800269a <__ledf2+0x82> + 80026c6: 2c00 cmp r4, #0 + 80026c8: d0cd beq.n 8002666 <__ledf2+0x4e> + 80026ca: e7d7 b.n 800267c <__ledf2+0x64> + 80026cc: 2c00 cmp r4, #0 + 80026ce: d0e4 beq.n 800269a <__ledf2+0x82> + 80026d0: e7d7 b.n 8002682 <__ledf2+0x6a> + 80026d2: 9b01 ldr r3, [sp, #4] + 80026d4: 2000 movs r0, #0 + 80026d6: 4563 cmp r3, ip + 80026d8: d0df beq.n 800269a <__ledf2+0x82> + 80026da: e7d2 b.n 8002682 <__ledf2+0x6a> + 80026dc: 45c8 cmp r8, r9 + 80026de: d8d0 bhi.n 8002682 <__ledf2+0x6a> + 80026e0: 2000 movs r0, #0 + 80026e2: 45c8 cmp r8, r9 + 80026e4: d2d9 bcs.n 800269a <__ledf2+0x82> + 80026e6: e7ea b.n 80026be <__ledf2+0xa6> + 80026e8: 9b01 ldr r3, [sp, #4] + 80026ea: 4563 cmp r3, ip + 80026ec: d0e4 beq.n 80026b8 <__ledf2+0xa0> + 80026ee: e7c8 b.n 8002682 <__ledf2+0x6a> + 80026f0: 000007ff .word 0x000007ff + +080026f4 : + * Author: dmitrijs + */ + +#include "main.h" + +void Adc_Init(void) { + 80026f4: b580 push {r7, lr} + 80026f6: af00 add r7, sp, #0 + + RCC->APB2ENR |= RCC_APB2ENR_ADCEN; + 80026f8: 4b28 ldr r3, [pc, #160] @ (800279c ) + 80026fa: 699a ldr r2, [r3, #24] + 80026fc: 4b27 ldr r3, [pc, #156] @ (800279c ) + 80026fe: 2180 movs r1, #128 @ 0x80 + 8002700: 0089 lsls r1, r1, #2 + 8002702: 430a orrs r2, r1 + 8002704: 619a str r2, [r3, #24] + ADC1->CFGR2 = (0x00000002 << 30); // pclk/4 -> 12Mhz + 8002706: 4b26 ldr r3, [pc, #152] @ (80027a0 ) + 8002708: 2280 movs r2, #128 @ 0x80 + 800270a: 0612 lsls r2, r2, #24 + 800270c: 611a str r2, [r3, #16] + ADC1->SMPR = 0x00000001; // Sample 7.5 adc cycles + 800270e: 4b24 ldr r3, [pc, #144] @ (80027a0 ) + 8002710: 2201 movs r2, #1 + 8002712: 615a str r2, [r3, #20] + ADC1->CFGR1 = 0; + 8002714: 4b22 ldr r3, [pc, #136] @ (80027a0 ) + 8002716: 2200 movs r2, #0 + 8002718: 60da str r2, [r3, #12] + /* (1) Ensure that ADEN = 0 */ + /* (2) Clear ADEN by setting ADDIS*/ + /* (3) Clear DMAEN */ + /* (4) Launch the calibration by setting ADCAL */ + /* (5) Wait until ADCAL=0 */ + if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */ + 800271a: 4b21 ldr r3, [pc, #132] @ (80027a0 ) + 800271c: 689b ldr r3, [r3, #8] + 800271e: 2201 movs r2, #1 + 8002720: 4013 ands r3, r2 + 8002722: d005 beq.n 8002730 + { + ADC1->CR |= ADC_CR_ADDIS; /* (2) */ + 8002724: 4b1e ldr r3, [pc, #120] @ (80027a0 ) + 8002726: 689a ldr r2, [r3, #8] + 8002728: 4b1d ldr r3, [pc, #116] @ (80027a0 ) + 800272a: 2102 movs r1, #2 + 800272c: 430a orrs r2, r1 + 800272e: 609a str r2, [r3, #8] + } + while ((ADC1->CR & ADC_CR_ADEN) != 0) { + 8002730: 46c0 nop @ (mov r8, r8) + 8002732: 4b1b ldr r3, [pc, #108] @ (80027a0 ) + 8002734: 689b ldr r3, [r3, #8] + 8002736: 2201 movs r2, #1 + 8002738: 4013 ands r3, r2 + 800273a: d1fa bne.n 8002732 + /* For robust implementation, add here time-out management */ + } + ADC1->CFGR1 &= ~ADC_CFGR1_DMAEN; /* (3) */ + 800273c: 4b18 ldr r3, [pc, #96] @ (80027a0 ) + 800273e: 68da ldr r2, [r3, #12] + 8002740: 4b17 ldr r3, [pc, #92] @ (80027a0 ) + 8002742: 2101 movs r1, #1 + 8002744: 438a bics r2, r1 + 8002746: 60da str r2, [r3, #12] + ADC1->CR |= ADC_CR_ADCAL; /* (4) */ + 8002748: 4b15 ldr r3, [pc, #84] @ (80027a0 ) + 800274a: 689a ldr r2, [r3, #8] + 800274c: 4b14 ldr r3, [pc, #80] @ (80027a0 ) + 800274e: 2180 movs r1, #128 @ 0x80 + 8002750: 0609 lsls r1, r1, #24 + 8002752: 430a orrs r2, r1 + 8002754: 609a str r2, [r3, #8] + while ((ADC1->CR & ADC_CR_ADCAL) != 0) /* (5) */ + 8002756: 46c0 nop @ (mov r8, r8) + 8002758: 4b11 ldr r3, [pc, #68] @ (80027a0 ) + 800275a: 689b ldr r3, [r3, #8] + 800275c: 2b00 cmp r3, #0 + 800275e: dbfb blt.n 8002758 + } + /* (1) Ensure that ADRDY = 0 */ + /* (2) Clear ADRDY */ + /* (3) Enable the ADC */ + /* (4) Wait until ADC ready */ + if ((ADC1->ISR & ADC_ISR_ADRDY) != 0) /* (1) */ + 8002760: 4b0f ldr r3, [pc, #60] @ (80027a0 ) + 8002762: 681b ldr r3, [r3, #0] + 8002764: 2201 movs r2, #1 + 8002766: 4013 ands r3, r2 + 8002768: d005 beq.n 8002776 + { + ADC1->ISR |= ADC_ISR_ADRDY; /* (2) */ + 800276a: 4b0d ldr r3, [pc, #52] @ (80027a0 ) + 800276c: 681a ldr r2, [r3, #0] + 800276e: 4b0c ldr r3, [pc, #48] @ (80027a0 ) + 8002770: 2101 movs r1, #1 + 8002772: 430a orrs r2, r1 + 8002774: 601a str r2, [r3, #0] + } + ADC1->CR |= ADC_CR_ADEN; /* (3) */ + 8002776: 4b0a ldr r3, [pc, #40] @ (80027a0 ) + 8002778: 689a ldr r2, [r3, #8] + 800277a: 4b09 ldr r3, [pc, #36] @ (80027a0 ) + 800277c: 2101 movs r1, #1 + 800277e: 430a orrs r2, r1 + 8002780: 609a str r2, [r3, #8] + while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (4) */ + 8002782: 46c0 nop @ (mov r8, r8) + 8002784: 4b06 ldr r3, [pc, #24] @ (80027a0 ) + 8002786: 681b ldr r3, [r3, #0] + 8002788: 2201 movs r2, #1 + 800278a: 4013 ands r3, r2 + 800278c: d0fa beq.n 8002784 + { + /*TODO For robust implementation, add here time-out management */ + } + + ADC1->IER = 0; + 800278e: 4b04 ldr r3, [pc, #16] @ (80027a0 ) + 8002790: 2200 movs r2, #0 + 8002792: 605a str r2, [r3, #4] +//NVIC_EnableIRQ(ADC1_IRQn); +} + 8002794: 46c0 nop @ (mov r8, r8) + 8002796: 46bd mov sp, r7 + 8002798: bd80 pop {r7, pc} + 800279a: 46c0 nop @ (mov r8, r8) + 800279c: 40021000 .word 0x40021000 + 80027a0: 40012400 .word 0x40012400 + +080027a4 : + +unsigned short LPF(unsigned short lpf_c, unsigned short value, + unsigned short old_value) { + 80027a4: b590 push {r4, r7, lr} + 80027a6: b085 sub sp, #20 + 80027a8: af00 add r7, sp, #0 + 80027aa: 0004 movs r4, r0 + 80027ac: 0008 movs r0, r1 + 80027ae: 0011 movs r1, r2 + 80027b0: 1dbb adds r3, r7, #6 + 80027b2: 1c22 adds r2, r4, #0 + 80027b4: 801a strh r2, [r3, #0] + 80027b6: 1d3b adds r3, r7, #4 + 80027b8: 1c02 adds r2, r0, #0 + 80027ba: 801a strh r2, [r3, #0] + 80027bc: 1cbb adds r3, r7, #2 + 80027be: 1c0a adds r2, r1, #0 + 80027c0: 801a strh r2, [r3, #0] + // Averageing filtering + + float tmp; + + tmp = ((float) (value - old_value) * ((float) (lpf_c) / (float) 1000.0)); // filter + 80027c2: 1d3b adds r3, r7, #4 + 80027c4: 881a ldrh r2, [r3, #0] + 80027c6: 1cbb adds r3, r7, #2 + 80027c8: 881b ldrh r3, [r3, #0] + 80027ca: 1ad3 subs r3, r2, r3 + 80027cc: 0018 movs r0, r3 + 80027ce: f7fe fe11 bl 80013f4 <__aeabi_i2f> + 80027d2: 1c04 adds r4, r0, #0 + 80027d4: 1dbb adds r3, r7, #6 + 80027d6: 881b ldrh r3, [r3, #0] + 80027d8: 0018 movs r0, r3 + 80027da: f7fe fe5b bl 8001494 <__aeabi_ui2f> + 80027de: 1c03 adds r3, r0, #0 + 80027e0: 4916 ldr r1, [pc, #88] @ (800283c ) + 80027e2: 1c18 adds r0, r3, #0 + 80027e4: f7fe f884 bl 80008f0 <__aeabi_fdiv> + 80027e8: 1c03 adds r3, r0, #0 + 80027ea: 1c19 adds r1, r3, #0 + 80027ec: 1c20 adds r0, r4, #0 + 80027ee: f7fe fa4d bl 8000c8c <__aeabi_fmul> + 80027f2: 1c03 adds r3, r0, #0 + 80027f4: 60fb str r3, [r7, #12] + if (tmp > 0) + 80027f6: 2100 movs r1, #0 + 80027f8: 68f8 ldr r0, [r7, #12] + 80027fa: f7fd fe21 bl 8000440 <__aeabi_fcmpgt> + 80027fe: 1e03 subs r3, r0, #0 + 8002800: d007 beq.n 8002812 + tmp += (float) 0.5; // roundup + 8002802: 21fc movs r1, #252 @ 0xfc + 8002804: 0589 lsls r1, r1, #22 + 8002806: 68f8 ldr r0, [r7, #12] + 8002808: f7fd fe64 bl 80004d4 <__aeabi_fadd> + 800280c: 1c03 adds r3, r0, #0 + 800280e: 60fb str r3, [r7, #12] + 8002810: e006 b.n 8002820 + else + tmp -= (float) 0.5; + 8002812: 21fc movs r1, #252 @ 0xfc + 8002814: 0589 lsls r1, r1, #22 + 8002816: 68f8 ldr r0, [r7, #12] + 8002818: f7fe fb8a bl 8000f30 <__aeabi_fsub> + 800281c: 1c03 adds r3, r0, #0 + 800281e: 60fb str r3, [r7, #12] + + return (unsigned short) ((signed int) old_value + (signed int) tmp); + 8002820: 68f8 ldr r0, [r7, #12] + 8002822: f7fe fdc7 bl 80013b4 <__aeabi_f2iz> + 8002826: 0003 movs r3, r0 + 8002828: b29a uxth r2, r3 + 800282a: 1cbb adds r3, r7, #2 + 800282c: 881b ldrh r3, [r3, #0] + 800282e: 18d3 adds r3, r2, r3 + 8002830: b29b uxth r3, r3 + +} + 8002832: 0018 movs r0, r3 + 8002834: 46bd mov sp, r7 + 8002836: b005 add sp, #20 + 8002838: bd90 pop {r4, r7, pc} + 800283a: 46c0 nop @ (mov r8, r8) + 800283c: 447a0000 .word 0x447a0000 + +08002840 : + +unsigned short Adc_Read(unsigned char ch) { + 8002840: b580 push {r7, lr} + 8002842: b084 sub sp, #16 + 8002844: af00 add r7, sp, #0 + 8002846: 0002 movs r2, r0 + 8002848: 1dfb adds r3, r7, #7 + 800284a: 701a strb r2, [r3, #0] + unsigned short tmp; + if (ADC1->ISR & ADC_ISR_EOC) + 800284c: 4b16 ldr r3, [pc, #88] @ (80028a8 ) + 800284e: 681b ldr r3, [r3, #0] + 8002850: 2204 movs r2, #4 + 8002852: 4013 ands r3, r2 + 8002854: d004 beq.n 8002860 + tmp = ADC1->DR; //ADC1->ISR |= ADC_ISR_EOC; // clear EOC flag + 8002856: 4b14 ldr r3, [pc, #80] @ (80028a8 ) + 8002858: 6c1a ldr r2, [r3, #64] @ 0x40 + 800285a: 230e movs r3, #14 + 800285c: 18fb adds r3, r7, r3 + 800285e: 801a strh r2, [r3, #0] + ADC1->CHSELR = (1 << ch); // select channel + 8002860: 1dfb adds r3, r7, #7 + 8002862: 781b ldrb r3, [r3, #0] + 8002864: 2201 movs r2, #1 + 8002866: 409a lsls r2, r3 + 8002868: 4b0f ldr r3, [pc, #60] @ (80028a8 ) + 800286a: 629a str r2, [r3, #40] @ 0x28 + ADC1->CR |= ADC_CR_ADSTART; + 800286c: 4b0e ldr r3, [pc, #56] @ (80028a8 ) + 800286e: 689a ldr r2, [r3, #8] + 8002870: 4b0d ldr r3, [pc, #52] @ (80028a8 ) + 8002872: 2104 movs r1, #4 + 8002874: 430a orrs r2, r1 + 8002876: 609a str r2, [r3, #8] + while ((~ADC1->ISR) & ADC_ISR_EOC) + 8002878: 46c0 nop @ (mov r8, r8) + 800287a: 4b0b ldr r3, [pc, #44] @ (80028a8 ) + 800287c: 681b ldr r3, [r3, #0] + 800287e: 2204 movs r2, #4 + 8002880: 4013 ands r3, r2 + 8002882: d0fa beq.n 800287a + ; + ADC1->ISR |= ADC_ISR_EOC; + 8002884: 4b08 ldr r3, [pc, #32] @ (80028a8 ) + 8002886: 681a ldr r2, [r3, #0] + 8002888: 4b07 ldr r3, [pc, #28] @ (80028a8 ) + 800288a: 2104 movs r1, #4 + 800288c: 430a orrs r2, r1 + 800288e: 601a str r2, [r3, #0] + tmp = ADC1->DR; + 8002890: 4b05 ldr r3, [pc, #20] @ (80028a8 ) + 8002892: 6c1a ldr r2, [r3, #64] @ 0x40 + 8002894: 210e movs r1, #14 + 8002896: 187b adds r3, r7, r1 + 8002898: 801a strh r2, [r3, #0] + return tmp; + 800289a: 187b adds r3, r7, r1 + 800289c: 881b ldrh r3, [r3, #0] +} + 800289e: 0018 movs r0, r3 + 80028a0: 46bd mov sp, r7 + 80028a2: b004 add sp, #16 + 80028a4: bd80 pop {r7, pc} + 80028a6: 46c0 nop @ (mov r8, r8) + 80028a8: 40012400 .word 0x40012400 + +080028ac : + } + CAN_TX_Rdy = 1; +} + +// CAN send data +void CAN_Send_Msg(can_msg_typedef *msg) { + 80028ac: b580 push {r7, lr} + 80028ae: b082 sub sp, #8 + 80028b0: af00 add r7, sp, #0 + 80028b2: 6078 str r0, [r7, #4] + CAN_TX_Rdy = 0; + 80028b4: 4b47 ldr r3, [pc, #284] @ (80029d4 ) + 80028b6: 2200 movs r2, #0 + 80028b8: 701a strb r2, [r3, #0] + CAN->sTxMailBox[0].TIR = (uint32_t) 0; + 80028ba: 4a47 ldr r2, [pc, #284] @ (80029d8 ) + 80028bc: 23c0 movs r3, #192 @ 0xc0 + 80028be: 005b lsls r3, r3, #1 + 80028c0: 2100 movs r1, #0 + 80028c2: 50d1 str r1, [r2, r3] + if (msg->format == STD_FORMAT) { + 80028c4: 687b ldr r3, [r7, #4] + 80028c6: 7b5b ldrb r3, [r3, #13] + 80028c8: 2b00 cmp r3, #0 + 80028ca: d10c bne.n 80028e6 + CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 21) | CAN_ID_STD; + 80028cc: 4a42 ldr r2, [pc, #264] @ (80029d8 ) + 80028ce: 23c0 movs r3, #192 @ 0xc0 + 80028d0: 005b lsls r3, r3, #1 + 80028d2: 58d2 ldr r2, [r2, r3] + 80028d4: 687b ldr r3, [r7, #4] + 80028d6: 681b ldr r3, [r3, #0] + 80028d8: 055b lsls r3, r3, #21 + 80028da: 493f ldr r1, [pc, #252] @ (80029d8 ) + 80028dc: 431a orrs r2, r3 + 80028de: 23c0 movs r3, #192 @ 0xc0 + 80028e0: 005b lsls r3, r3, #1 + 80028e2: 50ca str r2, [r1, r3] + 80028e4: e00d b.n 8002902 + } else { + CAN->sTxMailBox[0].TIR |= (uint32_t) (msg->id << 3) | CAN_ID_EXT; + 80028e6: 4a3c ldr r2, [pc, #240] @ (80029d8 ) + 80028e8: 23c0 movs r3, #192 @ 0xc0 + 80028ea: 005b lsls r3, r3, #1 + 80028ec: 58d2 ldr r2, [r2, r3] + 80028ee: 687b ldr r3, [r7, #4] + 80028f0: 681b ldr r3, [r3, #0] + 80028f2: 00db lsls r3, r3, #3 + 80028f4: 4313 orrs r3, r2 + 80028f6: 4938 ldr r1, [pc, #224] @ (80029d8 ) + 80028f8: 2204 movs r2, #4 + 80028fa: 431a orrs r2, r3 + 80028fc: 23c0 movs r3, #192 @ 0xc0 + 80028fe: 005b lsls r3, r3, #1 + 8002900: 50ca str r2, [r1, r3] + } + if (msg->frame == DATA_FRAME) { + 8002902: 687b ldr r3, [r7, #4] + 8002904: 7b9b ldrb r3, [r3, #14] + 8002906: 2b00 cmp r3, #0 + 8002908: d108 bne.n 800291c + CAN->sTxMailBox[0].TIR |= CAN_RTR_DATA; + 800290a: 4a33 ldr r2, [pc, #204] @ (80029d8 ) + 800290c: 4932 ldr r1, [pc, #200] @ (80029d8 ) + 800290e: 23c0 movs r3, #192 @ 0xc0 + 8002910: 005b lsls r3, r3, #1 + 8002912: 58d2 ldr r2, [r2, r3] + 8002914: 23c0 movs r3, #192 @ 0xc0 + 8002916: 005b lsls r3, r3, #1 + 8002918: 50ca str r2, [r1, r3] + 800291a: e009 b.n 8002930 + } else { + CAN->sTxMailBox[0].TIR |= CAN_RTR_REMOTE; + 800291c: 4a2e ldr r2, [pc, #184] @ (80029d8 ) + 800291e: 23c0 movs r3, #192 @ 0xc0 + 8002920: 005b lsls r3, r3, #1 + 8002922: 58d3 ldr r3, [r2, r3] + 8002924: 492c ldr r1, [pc, #176] @ (80029d8 ) + 8002926: 2202 movs r2, #2 + 8002928: 431a orrs r2, r3 + 800292a: 23c0 movs r3, #192 @ 0xc0 + 800292c: 005b lsls r3, r3, #1 + 800292e: 50ca str r2, [r1, r3] + } + CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24) + 8002930: 687b ldr r3, [r7, #4] + 8002932: 79db ldrb r3, [r3, #7] + 8002934: 061a lsls r2, r3, #24 + | ((uint32_t) msg->data[2] << 16) | ((uint32_t) msg->data[1] << 8) + 8002936: 687b ldr r3, [r7, #4] + 8002938: 799b ldrb r3, [r3, #6] + 800293a: 041b lsls r3, r3, #16 + 800293c: 431a orrs r2, r3 + 800293e: 687b ldr r3, [r7, #4] + 8002940: 795b ldrb r3, [r3, #5] + 8002942: 021b lsls r3, r3, #8 + 8002944: 4313 orrs r3, r2 + | ((uint32_t) msg->data[0])); + 8002946: 687a ldr r2, [r7, #4] + 8002948: 7912 ldrb r2, [r2, #4] + CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24) + 800294a: 4923 ldr r1, [pc, #140] @ (80029d8 ) + | ((uint32_t) msg->data[0])); + 800294c: 431a orrs r2, r3 + CAN->sTxMailBox[0].TDLR = (((uint32_t) msg->data[3] << 24) + 800294e: 23c4 movs r3, #196 @ 0xc4 + 8002950: 005b lsls r3, r3, #1 + 8002952: 50ca str r2, [r1, r3] + CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24) + 8002954: 687b ldr r3, [r7, #4] + 8002956: 7adb ldrb r3, [r3, #11] + 8002958: 061a lsls r2, r3, #24 + | ((uint32_t) msg->data[6] << 16) | ((uint32_t) msg->data[5] << 8) + 800295a: 687b ldr r3, [r7, #4] + 800295c: 7a9b ldrb r3, [r3, #10] + 800295e: 041b lsls r3, r3, #16 + 8002960: 431a orrs r2, r3 + 8002962: 687b ldr r3, [r7, #4] + 8002964: 7a5b ldrb r3, [r3, #9] + 8002966: 021b lsls r3, r3, #8 + 8002968: 4313 orrs r3, r2 + | ((uint32_t) msg->data[4])); + 800296a: 687a ldr r2, [r7, #4] + 800296c: 7a12 ldrb r2, [r2, #8] + CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24) + 800296e: 491a ldr r1, [pc, #104] @ (80029d8 ) + | ((uint32_t) msg->data[4])); + 8002970: 431a orrs r2, r3 + CAN->sTxMailBox[0].TDHR = (((uint32_t) msg->data[7] << 24) + 8002972: 23c6 movs r3, #198 @ 0xc6 + 8002974: 005b lsls r3, r3, #1 + 8002976: 50ca str r2, [r1, r3] + CAN->sTxMailBox[0].TDTR &= ~CAN_TDT0R_DLC; + 8002978: 4a17 ldr r2, [pc, #92] @ (80029d8 ) + 800297a: 23c2 movs r3, #194 @ 0xc2 + 800297c: 005b lsls r3, r3, #1 + 800297e: 58d3 ldr r3, [r2, r3] + 8002980: 4915 ldr r1, [pc, #84] @ (80029d8 ) + 8002982: 220f movs r2, #15 + 8002984: 4393 bics r3, r2 + 8002986: 001a movs r2, r3 + 8002988: 23c2 movs r3, #194 @ 0xc2 + 800298a: 005b lsls r3, r3, #1 + 800298c: 50ca str r2, [r1, r3] + CAN->sTxMailBox[0].TDTR |= (msg->lenght & CAN_TDT0R_DLC); + 800298e: 4a12 ldr r2, [pc, #72] @ (80029d8 ) + 8002990: 23c2 movs r3, #194 @ 0xc2 + 8002992: 005b lsls r3, r3, #1 + 8002994: 58d2 ldr r2, [r2, r3] + 8002996: 687b ldr r3, [r7, #4] + 8002998: 7b1b ldrb r3, [r3, #12] + 800299a: 0019 movs r1, r3 + 800299c: 230f movs r3, #15 + 800299e: 400b ands r3, r1 + 80029a0: 490d ldr r1, [pc, #52] @ (80029d8 ) + 80029a2: 431a orrs r2, r3 + 80029a4: 23c2 movs r3, #194 @ 0xc2 + 80029a6: 005b lsls r3, r3, #1 + 80029a8: 50ca str r2, [r1, r3] + CAN->IER |= CAN_IER_TMEIE; + 80029aa: 4b0b ldr r3, [pc, #44] @ (80029d8 ) + 80029ac: 695a ldr r2, [r3, #20] + 80029ae: 4b0a ldr r3, [pc, #40] @ (80029d8 ) + 80029b0: 2101 movs r1, #1 + 80029b2: 430a orrs r2, r1 + 80029b4: 615a str r2, [r3, #20] + CAN->sTxMailBox[0].TIR |= CAN_TI0R_TXRQ; + 80029b6: 4a08 ldr r2, [pc, #32] @ (80029d8 ) + 80029b8: 23c0 movs r3, #192 @ 0xc0 + 80029ba: 005b lsls r3, r3, #1 + 80029bc: 58d3 ldr r3, [r2, r3] + 80029be: 4906 ldr r1, [pc, #24] @ (80029d8 ) + 80029c0: 2201 movs r2, #1 + 80029c2: 431a orrs r2, r3 + 80029c4: 23c0 movs r3, #192 @ 0xc0 + 80029c6: 005b lsls r3, r3, #1 + 80029c8: 50ca str r2, [r1, r3] +} + 80029ca: 46c0 nop @ (mov r8, r8) + 80029cc: 46bd mov sp, r7 + 80029ce: b002 add sp, #8 + 80029d0: bd80 pop {r7, pc} + 80029d2: 46c0 nop @ (mov r8, r8) + 80029d4: 20000434 .word 0x20000434 + 80029d8: 40006400 .word 0x40006400 + +080029dc : + CAN->FA1R |= (uint32_t) (1 << CAN_Filter_Idx); + CAN->FMR &= ~CAN_FMR_FINIT; + CAN_Filter_Idx++; +} +//CAN recive/transmit irq handler +void CEC_CAN_IRQHandler(void) { + 80029dc: b580 push {r7, lr} + 80029de: af00 add r7, sp, #0 + if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) { + 80029e0: 4b15 ldr r3, [pc, #84] @ (8002a38 ) + 80029e2: 689a ldr r2, [r3, #8] + 80029e4: 2380 movs r3, #128 @ 0x80 + 80029e6: 04db lsls r3, r3, #19 + 80029e8: 401a ands r2, r3 + 80029ea: 2380 movs r3, #128 @ 0x80 + 80029ec: 04db lsls r3, r3, #19 + 80029ee: 429a cmp r2, r3 + 80029f0: d10e bne.n 8002a10 + CAN->TSR |= CAN_TSR_RQCP0; + 80029f2: 4b11 ldr r3, [pc, #68] @ (8002a38 ) + 80029f4: 689a ldr r2, [r3, #8] + 80029f6: 4b10 ldr r3, [pc, #64] @ (8002a38 ) + 80029f8: 2101 movs r1, #1 + 80029fa: 430a orrs r2, r1 + 80029fc: 609a str r2, [r3, #8] + CAN->IER &= ~CAN_IER_TMEIE; + 80029fe: 4b0e ldr r3, [pc, #56] @ (8002a38 ) + 8002a00: 695a ldr r2, [r3, #20] + 8002a02: 4b0d ldr r3, [pc, #52] @ (8002a38 ) + 8002a04: 2101 movs r1, #1 + 8002a06: 438a bics r2, r1 + 8002a08: 615a str r2, [r3, #20] + CAN_TX_Rdy = 1; + 8002a0a: 4b0c ldr r3, [pc, #48] @ (8002a3c ) + 8002a0c: 2201 movs r2, #1 + 8002a0e: 701a strb r2, [r3, #0] + } + if ((CAN->RF0R & CAN_RF0R_FMP0) != 0) { + 8002a10: 4b09 ldr r3, [pc, #36] @ (8002a38 ) + 8002a12: 68db ldr r3, [r3, #12] + 8002a14: 2203 movs r2, #3 + 8002a16: 4013 ands r3, r2 + 8002a18: d00a beq.n 8002a30 + CAN_Add_RX_Buffer(); + 8002a1a: f000 f90d bl 8002c38 + // TO DO + CAN->RF0R |= CAN_RF0R_RFOM0; + 8002a1e: 4b06 ldr r3, [pc, #24] @ (8002a38 ) + 8002a20: 68da ldr r2, [r3, #12] + 8002a22: 4b05 ldr r3, [pc, #20] @ (8002a38 ) + 8002a24: 2120 movs r1, #32 + 8002a26: 430a orrs r2, r1 + 8002a28: 60da str r2, [r3, #12] + CAN_RX_Rdy = 1; + 8002a2a: 4b05 ldr r3, [pc, #20] @ (8002a40 ) + 8002a2c: 2201 movs r2, #1 + 8002a2e: 701a strb r2, [r3, #0] + } +} + 8002a30: 46c0 nop @ (mov r8, r8) + 8002a32: 46bd mov sp, r7 + 8002a34: bd80 pop {r7, pc} + 8002a36: 46c0 nop @ (mov r8, r8) + 8002a38: 40006400 .word 0x40006400 + 8002a3c: 20000434 .word 0x20000434 + 8002a40: 20000435 .word 0x20000435 + +08002a44 : +void CAN_Send_TX_Buffer(void) { + 8002a44: b580 push {r7, lr} + 8002a46: af00 add r7, sp, #0 + + if (CAN_TX_Rdy) { + 8002a48: 4b18 ldr r3, [pc, #96] @ (8002aac ) + 8002a4a: 781b ldrb r3, [r3, #0] + 8002a4c: 2b00 cmp r3, #0 + 8002a4e: d02a beq.n 8002aa6 + //HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1); + if (CAN_TX_Buffer.todo > 0) { + 8002a50: 4a17 ldr r2, [pc, #92] @ (8002ab0 ) + 8002a52: 2380 movs r3, #128 @ 0x80 + 8002a54: 005b lsls r3, r3, #1 + 8002a56: 5cd3 ldrb r3, [r2, r3] + 8002a58: 2b00 cmp r3, #0 + 8002a5a: d024 beq.n 8002aa6 + CAN_TX_Buffer.todo--; + 8002a5c: 4a14 ldr r2, [pc, #80] @ (8002ab0 ) + 8002a5e: 2380 movs r3, #128 @ 0x80 + 8002a60: 005b lsls r3, r3, #1 + 8002a62: 5cd3 ldrb r3, [r2, r3] + 8002a64: 3b01 subs r3, #1 + 8002a66: b2d9 uxtb r1, r3 + 8002a68: 4a11 ldr r2, [pc, #68] @ (8002ab0 ) + 8002a6a: 2380 movs r3, #128 @ 0x80 + 8002a6c: 005b lsls r3, r3, #1 + 8002a6e: 54d1 strb r1, [r2, r3] + //HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_1); + CAN_Send_Msg(&CAN_TX_Buffer.data[CAN_TX_Buffer.done]); + 8002a70: 4a0f ldr r2, [pc, #60] @ (8002ab0 ) + 8002a72: 2381 movs r3, #129 @ 0x81 + 8002a74: 005b lsls r3, r3, #1 + 8002a76: 5cd3 ldrb r3, [r2, r3] + 8002a78: 011a lsls r2, r3, #4 + 8002a7a: 4b0d ldr r3, [pc, #52] @ (8002ab0 ) + 8002a7c: 18d3 adds r3, r2, r3 + 8002a7e: 0018 movs r0, r3 + 8002a80: f7ff ff14 bl 80028ac + if ((CAN_TX_Buffer.done++) > 14) { + 8002a84: 4a0a ldr r2, [pc, #40] @ (8002ab0 ) + 8002a86: 2381 movs r3, #129 @ 0x81 + 8002a88: 005b lsls r3, r3, #1 + 8002a8a: 5cd3 ldrb r3, [r2, r3] + 8002a8c: 1c5a adds r2, r3, #1 + 8002a8e: b2d0 uxtb r0, r2 + 8002a90: 4907 ldr r1, [pc, #28] @ (8002ab0 ) + 8002a92: 2281 movs r2, #129 @ 0x81 + 8002a94: 0052 lsls r2, r2, #1 + 8002a96: 5488 strb r0, [r1, r2] + 8002a98: 2b0e cmp r3, #14 + 8002a9a: d904 bls.n 8002aa6 + CAN_TX_Buffer.done = 0; + 8002a9c: 4a04 ldr r2, [pc, #16] @ (8002ab0 ) + 8002a9e: 2381 movs r3, #129 @ 0x81 + 8002aa0: 005b lsls r3, r3, #1 + 8002aa2: 2100 movs r1, #0 + 8002aa4: 54d1 strb r1, [r2, r3] + } + } + } +} + 8002aa6: 46c0 nop @ (mov r8, r8) + 8002aa8: 46bd mov sp, r7 + 8002aaa: bd80 pop {r7, pc} + 8002aac: 20000434 .word 0x20000434 + 8002ab0: 20000438 .word 0x20000438 + +08002ab4 : +void CAN_Add_TX_Buffer(can_msg_typedef *data) { + 8002ab4: b580 push {r7, lr} + 8002ab6: b082 sub sp, #8 + 8002ab8: af00 add r7, sp, #0 + 8002aba: 6078 str r0, [r7, #4] + if ((CAN_TX_Buffer.todo++) < 15) { + 8002abc: 4a5d ldr r2, [pc, #372] @ (8002c34 ) + 8002abe: 2380 movs r3, #128 @ 0x80 + 8002ac0: 005b lsls r3, r3, #1 + 8002ac2: 5cd3 ldrb r3, [r2, r3] + 8002ac4: 1c5a adds r2, r3, #1 + 8002ac6: b2d0 uxtb r0, r2 + 8002ac8: 495a ldr r1, [pc, #360] @ (8002c34 ) + 8002aca: 2280 movs r2, #128 @ 0x80 + 8002acc: 0052 lsls r2, r2, #1 + 8002ace: 5488 strb r0, [r1, r2] + 8002ad0: 2b0e cmp r3, #14 + 8002ad2: d900 bls.n 8002ad6 + 8002ad4: e0a9 b.n 8002c2a + if ((CAN_TX_Buffer.corent++) > 14) { + 8002ad6: 4a57 ldr r2, [pc, #348] @ (8002c34 ) + 8002ad8: 2302 movs r3, #2 + 8002ada: 33ff adds r3, #255 @ 0xff + 8002adc: 5cd3 ldrb r3, [r2, r3] + 8002ade: 1c5a adds r2, r3, #1 + 8002ae0: b2d0 uxtb r0, r2 + 8002ae2: 4954 ldr r1, [pc, #336] @ (8002c34 ) + 8002ae4: 2202 movs r2, #2 + 8002ae6: 32ff adds r2, #255 @ 0xff + 8002ae8: 5488 strb r0, [r1, r2] + 8002aea: 2b0e cmp r3, #14 + 8002aec: d904 bls.n 8002af8 + CAN_TX_Buffer.corent = 0; + 8002aee: 4a51 ldr r2, [pc, #324] @ (8002c34 ) + 8002af0: 2302 movs r3, #2 + 8002af2: 33ff adds r3, #255 @ 0xff + 8002af4: 2100 movs r1, #0 + 8002af6: 54d1 strb r1, [r2, r3] + } + //memcpy((void*) &canTX_buffer.data[canTX_buffer.corent], (void*) &data, sizeof(CAN_msg_typedef)); + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].id = data->id; + 8002af8: 4a4e ldr r2, [pc, #312] @ (8002c34 ) + 8002afa: 2302 movs r3, #2 + 8002afc: 33ff adds r3, #255 @ 0xff + 8002afe: 5cd3 ldrb r3, [r2, r3] + 8002b00: 001a movs r2, r3 + 8002b02: 687b ldr r3, [r7, #4] + 8002b04: 6819 ldr r1, [r3, #0] + 8002b06: 4b4b ldr r3, [pc, #300] @ (8002c34 ) + 8002b08: 0112 lsls r2, r2, #4 + 8002b0a: 50d1 str r1, [r2, r3] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].format = data->format; + 8002b0c: 4a49 ldr r2, [pc, #292] @ (8002c34 ) + 8002b0e: 2302 movs r3, #2 + 8002b10: 33ff adds r3, #255 @ 0xff + 8002b12: 5cd3 ldrb r3, [r2, r3] + 8002b14: 0018 movs r0, r3 + 8002b16: 687b ldr r3, [r7, #4] + 8002b18: 7b59 ldrb r1, [r3, #13] + 8002b1a: 4a46 ldr r2, [pc, #280] @ (8002c34 ) + 8002b1c: 0103 lsls r3, r0, #4 + 8002b1e: 18d3 adds r3, r2, r3 + 8002b20: 330d adds r3, #13 + 8002b22: 1c0a adds r2, r1, #0 + 8002b24: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].frame = data->frame; + 8002b26: 4a43 ldr r2, [pc, #268] @ (8002c34 ) + 8002b28: 2302 movs r3, #2 + 8002b2a: 33ff adds r3, #255 @ 0xff + 8002b2c: 5cd3 ldrb r3, [r2, r3] + 8002b2e: 0018 movs r0, r3 + 8002b30: 687b ldr r3, [r7, #4] + 8002b32: 7b99 ldrb r1, [r3, #14] + 8002b34: 4a3f ldr r2, [pc, #252] @ (8002c34 ) + 8002b36: 0103 lsls r3, r0, #4 + 8002b38: 18d3 adds r3, r2, r3 + 8002b3a: 330e adds r3, #14 + 8002b3c: 1c0a adds r2, r1, #0 + 8002b3e: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].lenght = data->lenght; + 8002b40: 4a3c ldr r2, [pc, #240] @ (8002c34 ) + 8002b42: 2302 movs r3, #2 + 8002b44: 33ff adds r3, #255 @ 0xff + 8002b46: 5cd3 ldrb r3, [r2, r3] + 8002b48: 0018 movs r0, r3 + 8002b4a: 687b ldr r3, [r7, #4] + 8002b4c: 7b19 ldrb r1, [r3, #12] + 8002b4e: 4a39 ldr r2, [pc, #228] @ (8002c34 ) + 8002b50: 0103 lsls r3, r0, #4 + 8002b52: 18d3 adds r3, r2, r3 + 8002b54: 330c adds r3, #12 + 8002b56: 1c0a adds r2, r1, #0 + 8002b58: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[0] = data->data[0]; + 8002b5a: 4a36 ldr r2, [pc, #216] @ (8002c34 ) + 8002b5c: 2302 movs r3, #2 + 8002b5e: 33ff adds r3, #255 @ 0xff + 8002b60: 5cd3 ldrb r3, [r2, r3] + 8002b62: 0018 movs r0, r3 + 8002b64: 687b ldr r3, [r7, #4] + 8002b66: 7919 ldrb r1, [r3, #4] + 8002b68: 4a32 ldr r2, [pc, #200] @ (8002c34 ) + 8002b6a: 0103 lsls r3, r0, #4 + 8002b6c: 18d3 adds r3, r2, r3 + 8002b6e: 3304 adds r3, #4 + 8002b70: 1c0a adds r2, r1, #0 + 8002b72: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[1] = data->data[1]; + 8002b74: 4a2f ldr r2, [pc, #188] @ (8002c34 ) + 8002b76: 2302 movs r3, #2 + 8002b78: 33ff adds r3, #255 @ 0xff + 8002b7a: 5cd3 ldrb r3, [r2, r3] + 8002b7c: 0018 movs r0, r3 + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 7959 ldrb r1, [r3, #5] + 8002b82: 4a2c ldr r2, [pc, #176] @ (8002c34 ) + 8002b84: 0103 lsls r3, r0, #4 + 8002b86: 18d3 adds r3, r2, r3 + 8002b88: 3305 adds r3, #5 + 8002b8a: 1c0a adds r2, r1, #0 + 8002b8c: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[2] = data->data[2]; + 8002b8e: 4a29 ldr r2, [pc, #164] @ (8002c34 ) + 8002b90: 2302 movs r3, #2 + 8002b92: 33ff adds r3, #255 @ 0xff + 8002b94: 5cd3 ldrb r3, [r2, r3] + 8002b96: 0018 movs r0, r3 + 8002b98: 687b ldr r3, [r7, #4] + 8002b9a: 7999 ldrb r1, [r3, #6] + 8002b9c: 4a25 ldr r2, [pc, #148] @ (8002c34 ) + 8002b9e: 0103 lsls r3, r0, #4 + 8002ba0: 18d3 adds r3, r2, r3 + 8002ba2: 3306 adds r3, #6 + 8002ba4: 1c0a adds r2, r1, #0 + 8002ba6: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[3] = data->data[3]; + 8002ba8: 4a22 ldr r2, [pc, #136] @ (8002c34 ) + 8002baa: 2302 movs r3, #2 + 8002bac: 33ff adds r3, #255 @ 0xff + 8002bae: 5cd3 ldrb r3, [r2, r3] + 8002bb0: 0018 movs r0, r3 + 8002bb2: 687b ldr r3, [r7, #4] + 8002bb4: 79d9 ldrb r1, [r3, #7] + 8002bb6: 4a1f ldr r2, [pc, #124] @ (8002c34 ) + 8002bb8: 0103 lsls r3, r0, #4 + 8002bba: 18d3 adds r3, r2, r3 + 8002bbc: 3307 adds r3, #7 + 8002bbe: 1c0a adds r2, r1, #0 + 8002bc0: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[4] = data->data[4]; + 8002bc2: 4a1c ldr r2, [pc, #112] @ (8002c34 ) + 8002bc4: 2302 movs r3, #2 + 8002bc6: 33ff adds r3, #255 @ 0xff + 8002bc8: 5cd3 ldrb r3, [r2, r3] + 8002bca: 0018 movs r0, r3 + 8002bcc: 687b ldr r3, [r7, #4] + 8002bce: 7a19 ldrb r1, [r3, #8] + 8002bd0: 4a18 ldr r2, [pc, #96] @ (8002c34 ) + 8002bd2: 0103 lsls r3, r0, #4 + 8002bd4: 18d3 adds r3, r2, r3 + 8002bd6: 3308 adds r3, #8 + 8002bd8: 1c0a adds r2, r1, #0 + 8002bda: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[5] = data->data[5]; + 8002bdc: 4a15 ldr r2, [pc, #84] @ (8002c34 ) + 8002bde: 2302 movs r3, #2 + 8002be0: 33ff adds r3, #255 @ 0xff + 8002be2: 5cd3 ldrb r3, [r2, r3] + 8002be4: 0018 movs r0, r3 + 8002be6: 687b ldr r3, [r7, #4] + 8002be8: 7a59 ldrb r1, [r3, #9] + 8002bea: 4a12 ldr r2, [pc, #72] @ (8002c34 ) + 8002bec: 0103 lsls r3, r0, #4 + 8002bee: 18d3 adds r3, r2, r3 + 8002bf0: 3309 adds r3, #9 + 8002bf2: 1c0a adds r2, r1, #0 + 8002bf4: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[6] = data->data[6]; + 8002bf6: 4a0f ldr r2, [pc, #60] @ (8002c34 ) + 8002bf8: 2302 movs r3, #2 + 8002bfa: 33ff adds r3, #255 @ 0xff + 8002bfc: 5cd3 ldrb r3, [r2, r3] + 8002bfe: 0018 movs r0, r3 + 8002c00: 687b ldr r3, [r7, #4] + 8002c02: 7a99 ldrb r1, [r3, #10] + 8002c04: 4a0b ldr r2, [pc, #44] @ (8002c34 ) + 8002c06: 0103 lsls r3, r0, #4 + 8002c08: 18d3 adds r3, r2, r3 + 8002c0a: 330a adds r3, #10 + 8002c0c: 1c0a adds r2, r1, #0 + 8002c0e: 701a strb r2, [r3, #0] + CAN_TX_Buffer.data[CAN_TX_Buffer.corent].data[7] = data->data[7]; + 8002c10: 4a08 ldr r2, [pc, #32] @ (8002c34 ) + 8002c12: 2302 movs r3, #2 + 8002c14: 33ff adds r3, #255 @ 0xff + 8002c16: 5cd3 ldrb r3, [r2, r3] + 8002c18: 0018 movs r0, r3 + 8002c1a: 687b ldr r3, [r7, #4] + 8002c1c: 7ad9 ldrb r1, [r3, #11] + 8002c1e: 4a05 ldr r2, [pc, #20] @ (8002c34 ) + 8002c20: 0103 lsls r3, r0, #4 + 8002c22: 18d3 adds r3, r2, r3 + 8002c24: 330b adds r3, #11 + 8002c26: 1c0a adds r2, r1, #0 + 8002c28: 701a strb r2, [r3, #0] + } +} + 8002c2a: 46c0 nop @ (mov r8, r8) + 8002c2c: 46bd mov sp, r7 + 8002c2e: b002 add sp, #8 + 8002c30: bd80 pop {r7, pc} + 8002c32: 46c0 nop @ (mov r8, r8) + 8002c34: 20000438 .word 0x20000438 + +08002c38 : +void CAN_Add_RX_Buffer(void) { + 8002c38: b580 push {r7, lr} + 8002c3a: af00 add r7, sp, #0 + if ((CAN_RX_Buffer.todo) < 16) { + 8002c3c: 4a87 ldr r2, [pc, #540] @ (8002e5c ) + 8002c3e: 2380 movs r3, #128 @ 0x80 + 8002c40: 005b lsls r3, r3, #1 + 8002c42: 5cd3 ldrb r3, [r2, r3] + 8002c44: 2b0f cmp r3, #15 + 8002c46: d900 bls.n 8002c4a + 8002c48: e0ff b.n 8002e4a + CAN_RX_Buffer.todo++; + 8002c4a: 4a84 ldr r2, [pc, #528] @ (8002e5c ) + 8002c4c: 2380 movs r3, #128 @ 0x80 + 8002c4e: 005b lsls r3, r3, #1 + 8002c50: 5cd3 ldrb r3, [r2, r3] + 8002c52: 3301 adds r3, #1 + 8002c54: b2d9 uxtb r1, r3 + 8002c56: 4a81 ldr r2, [pc, #516] @ (8002e5c ) + 8002c58: 2380 movs r3, #128 @ 0x80 + 8002c5a: 005b lsls r3, r3, #1 + 8002c5c: 54d1 strb r1, [r2, r3] + if ((CAN->sFIFOMailBox[0].RIR & CAN_ID_EXT) == 0) { + 8002c5e: 4a80 ldr r2, [pc, #512] @ (8002e60 ) + 8002c60: 23d8 movs r3, #216 @ 0xd8 + 8002c62: 005b lsls r3, r3, #1 + 8002c64: 58d3 ldr r3, [r2, r3] + 8002c66: 2204 movs r2, #4 + 8002c68: 4013 ands r3, r2 + 8002c6a: d118 bne.n 8002c9e + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = STD_FORMAT; + 8002c6c: 4a7b ldr r2, [pc, #492] @ (8002e5c ) + 8002c6e: 2302 movs r3, #2 + 8002c70: 33ff adds r3, #255 @ 0xff + 8002c72: 5cd3 ldrb r3, [r2, r3] + 8002c74: 4a79 ldr r2, [pc, #484] @ (8002e5c ) + 8002c76: 011b lsls r3, r3, #4 + 8002c78: 18d3 adds r3, r2, r3 + 8002c7a: 330d adds r3, #13 + 8002c7c: 2200 movs r2, #0 + 8002c7e: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF + & (CAN->sFIFOMailBox[0].RIR >> 21); + 8002c80: 4a77 ldr r2, [pc, #476] @ (8002e60 ) + 8002c82: 23d8 movs r3, #216 @ 0xd8 + 8002c84: 005b lsls r3, r3, #1 + 8002c86: 58d3 ldr r3, [r2, r3] + 8002c88: 0d5b lsrs r3, r3, #21 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF + 8002c8a: 4974 ldr r1, [pc, #464] @ (8002e5c ) + 8002c8c: 2202 movs r2, #2 + 8002c8e: 32ff adds r2, #255 @ 0xff + 8002c90: 5c8a ldrb r2, [r1, r2] + & (CAN->sFIFOMailBox[0].RIR >> 21); + 8002c92: 055b lsls r3, r3, #21 + 8002c94: 0d59 lsrs r1, r3, #21 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x000007FF + 8002c96: 4b71 ldr r3, [pc, #452] @ (8002e5c ) + 8002c98: 0112 lsls r2, r2, #4 + 8002c9a: 50d1 str r1, [r2, r3] + 8002c9c: e017 b.n 8002cce + } else { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].format = EXTD_FORMAT; + 8002c9e: 4a6f ldr r2, [pc, #444] @ (8002e5c ) + 8002ca0: 2302 movs r3, #2 + 8002ca2: 33ff adds r3, #255 @ 0xff + 8002ca4: 5cd3 ldrb r3, [r2, r3] + 8002ca6: 4a6d ldr r2, [pc, #436] @ (8002e5c ) + 8002ca8: 011b lsls r3, r3, #4 + 8002caa: 18d3 adds r3, r2, r3 + 8002cac: 330d adds r3, #13 + 8002cae: 2201 movs r2, #1 + 8002cb0: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF + & (CAN->sFIFOMailBox[0].RIR >> 3); + 8002cb2: 4a6b ldr r2, [pc, #428] @ (8002e60 ) + 8002cb4: 23d8 movs r3, #216 @ 0xd8 + 8002cb6: 005b lsls r3, r3, #1 + 8002cb8: 58d3 ldr r3, [r2, r3] + 8002cba: 08db lsrs r3, r3, #3 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF + 8002cbc: 4967 ldr r1, [pc, #412] @ (8002e5c ) + 8002cbe: 2202 movs r2, #2 + 8002cc0: 32ff adds r2, #255 @ 0xff + 8002cc2: 5c8a ldrb r2, [r1, r2] + & (CAN->sFIFOMailBox[0].RIR >> 3); + 8002cc4: 039b lsls r3, r3, #14 + 8002cc6: 0b99 lsrs r1, r3, #14 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].id = (uint32_t) 0x0003FFFF + 8002cc8: 4b64 ldr r3, [pc, #400] @ (8002e5c ) + 8002cca: 0112 lsls r2, r2, #4 + 8002ccc: 50d1 str r1, [r2, r3] + } + if ((CAN->sFIFOMailBox[0].RIR & CAN_RTR_REMOTE) == 0) { + 8002cce: 4a64 ldr r2, [pc, #400] @ (8002e60 ) + 8002cd0: 23d8 movs r3, #216 @ 0xd8 + 8002cd2: 005b lsls r3, r3, #1 + 8002cd4: 58d3 ldr r3, [r2, r3] + 8002cd6: 2202 movs r2, #2 + 8002cd8: 4013 ands r3, r2 + 8002cda: d10a bne.n 8002cf2 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = DATA_FRAME; + 8002cdc: 4a5f ldr r2, [pc, #380] @ (8002e5c ) + 8002cde: 2302 movs r3, #2 + 8002ce0: 33ff adds r3, #255 @ 0xff + 8002ce2: 5cd3 ldrb r3, [r2, r3] + 8002ce4: 4a5d ldr r2, [pc, #372] @ (8002e5c ) + 8002ce6: 011b lsls r3, r3, #4 + 8002ce8: 18d3 adds r3, r2, r3 + 8002cea: 330e adds r3, #14 + 8002cec: 2200 movs r2, #0 + 8002cee: 701a strb r2, [r3, #0] + 8002cf0: e009 b.n 8002d06 + } else { + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].frame = REMOTE_FRAME; + 8002cf2: 4a5a ldr r2, [pc, #360] @ (8002e5c ) + 8002cf4: 2302 movs r3, #2 + 8002cf6: 33ff adds r3, #255 @ 0xff + 8002cf8: 5cd3 ldrb r3, [r2, r3] + 8002cfa: 4a58 ldr r2, [pc, #352] @ (8002e5c ) + 8002cfc: 011b lsls r3, r3, #4 + 8002cfe: 18d3 adds r3, r2, r3 + 8002d00: 330e adds r3, #14 + 8002d02: 2201 movs r2, #1 + 8002d04: 701a strb r2, [r3, #0] + } + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F + & CAN->sFIFOMailBox[0].RDTR; + 8002d06: 4a56 ldr r2, [pc, #344] @ (8002e60 ) + 8002d08: 23da movs r3, #218 @ 0xda + 8002d0a: 005b lsls r3, r3, #1 + 8002d0c: 58d3 ldr r3, [r2, r3] + 8002d0e: b2db uxtb r3, r3 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F + 8002d10: 4952 ldr r1, [pc, #328] @ (8002e5c ) + 8002d12: 2202 movs r2, #2 + 8002d14: 32ff adds r2, #255 @ 0xff + 8002d16: 5c8a ldrb r2, [r1, r2] + 8002d18: 0010 movs r0, r2 + & CAN->sFIFOMailBox[0].RDTR; + 8002d1a: 220f movs r2, #15 + 8002d1c: 4013 ands r3, r2 + 8002d1e: b2d9 uxtb r1, r3 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].lenght = (uint8_t) 0x0000000F + 8002d20: 4a4e ldr r2, [pc, #312] @ (8002e5c ) + 8002d22: 0103 lsls r3, r0, #4 + 8002d24: 18d3 adds r3, r2, r3 + 8002d26: 330c adds r3, #12 + 8002d28: 1c0a adds r2, r1, #0 + 8002d2a: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[0] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR); + 8002d2c: 4a4c ldr r2, [pc, #304] @ (8002e60 ) + 8002d2e: 23dc movs r3, #220 @ 0xdc + 8002d30: 005b lsls r3, r3, #1 + 8002d32: 58d1 ldr r1, [r2, r3] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[0] = (uint32_t) 0x000000FF + 8002d34: 4a49 ldr r2, [pc, #292] @ (8002e5c ) + 8002d36: 2302 movs r3, #2 + 8002d38: 33ff adds r3, #255 @ 0xff + 8002d3a: 5cd3 ldrb r3, [r2, r3] + 8002d3c: b2c9 uxtb r1, r1 + 8002d3e: 4a47 ldr r2, [pc, #284] @ (8002e5c ) + 8002d40: 011b lsls r3, r3, #4 + 8002d42: 18d3 adds r3, r2, r3 + 8002d44: 3304 adds r3, #4 + 8002d46: 1c0a adds r2, r1, #0 + 8002d48: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[1] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 8); + 8002d4a: 4a45 ldr r2, [pc, #276] @ (8002e60 ) + 8002d4c: 23dc movs r3, #220 @ 0xdc + 8002d4e: 005b lsls r3, r3, #1 + 8002d50: 58d3 ldr r3, [r2, r3] + 8002d52: 0a19 lsrs r1, r3, #8 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[1] = (uint32_t) 0x000000FF + 8002d54: 4a41 ldr r2, [pc, #260] @ (8002e5c ) + 8002d56: 2302 movs r3, #2 + 8002d58: 33ff adds r3, #255 @ 0xff + 8002d5a: 5cd3 ldrb r3, [r2, r3] + 8002d5c: b2c9 uxtb r1, r1 + 8002d5e: 4a3f ldr r2, [pc, #252] @ (8002e5c ) + 8002d60: 011b lsls r3, r3, #4 + 8002d62: 18d3 adds r3, r2, r3 + 8002d64: 3305 adds r3, #5 + 8002d66: 1c0a adds r2, r1, #0 + 8002d68: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[2] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 16); + 8002d6a: 4a3d ldr r2, [pc, #244] @ (8002e60 ) + 8002d6c: 23dc movs r3, #220 @ 0xdc + 8002d6e: 005b lsls r3, r3, #1 + 8002d70: 58d3 ldr r3, [r2, r3] + 8002d72: 0c19 lsrs r1, r3, #16 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[2] = (uint32_t) 0x000000FF + 8002d74: 4a39 ldr r2, [pc, #228] @ (8002e5c ) + 8002d76: 2302 movs r3, #2 + 8002d78: 33ff adds r3, #255 @ 0xff + 8002d7a: 5cd3 ldrb r3, [r2, r3] + 8002d7c: b2c9 uxtb r1, r1 + 8002d7e: 4a37 ldr r2, [pc, #220] @ (8002e5c ) + 8002d80: 011b lsls r3, r3, #4 + 8002d82: 18d3 adds r3, r2, r3 + 8002d84: 3306 adds r3, #6 + 8002d86: 1c0a adds r2, r1, #0 + 8002d88: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[3] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDLR >> 24); + 8002d8a: 4a35 ldr r2, [pc, #212] @ (8002e60 ) + 8002d8c: 23dc movs r3, #220 @ 0xdc + 8002d8e: 005b lsls r3, r3, #1 + 8002d90: 58d3 ldr r3, [r2, r3] + 8002d92: 0e19 lsrs r1, r3, #24 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[3] = (uint32_t) 0x000000FF + 8002d94: 4a31 ldr r2, [pc, #196] @ (8002e5c ) + 8002d96: 2302 movs r3, #2 + 8002d98: 33ff adds r3, #255 @ 0xff + 8002d9a: 5cd3 ldrb r3, [r2, r3] + 8002d9c: b2c9 uxtb r1, r1 + 8002d9e: 4a2f ldr r2, [pc, #188] @ (8002e5c ) + 8002da0: 011b lsls r3, r3, #4 + 8002da2: 18d3 adds r3, r2, r3 + 8002da4: 3307 adds r3, #7 + 8002da6: 1c0a adds r2, r1, #0 + 8002da8: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[4] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR); + 8002daa: 4a2d ldr r2, [pc, #180] @ (8002e60 ) + 8002dac: 23de movs r3, #222 @ 0xde + 8002dae: 005b lsls r3, r3, #1 + 8002db0: 58d1 ldr r1, [r2, r3] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[4] = (uint32_t) 0x000000FF + 8002db2: 4a2a ldr r2, [pc, #168] @ (8002e5c ) + 8002db4: 2302 movs r3, #2 + 8002db6: 33ff adds r3, #255 @ 0xff + 8002db8: 5cd3 ldrb r3, [r2, r3] + 8002dba: b2c9 uxtb r1, r1 + 8002dbc: 4a27 ldr r2, [pc, #156] @ (8002e5c ) + 8002dbe: 011b lsls r3, r3, #4 + 8002dc0: 18d3 adds r3, r2, r3 + 8002dc2: 3308 adds r3, #8 + 8002dc4: 1c0a adds r2, r1, #0 + 8002dc6: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[5] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 8); + 8002dc8: 4a25 ldr r2, [pc, #148] @ (8002e60 ) + 8002dca: 23de movs r3, #222 @ 0xde + 8002dcc: 005b lsls r3, r3, #1 + 8002dce: 58d3 ldr r3, [r2, r3] + 8002dd0: 0a19 lsrs r1, r3, #8 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[5] = (uint32_t) 0x000000FF + 8002dd2: 4a22 ldr r2, [pc, #136] @ (8002e5c ) + 8002dd4: 2302 movs r3, #2 + 8002dd6: 33ff adds r3, #255 @ 0xff + 8002dd8: 5cd3 ldrb r3, [r2, r3] + 8002dda: b2c9 uxtb r1, r1 + 8002ddc: 4a1f ldr r2, [pc, #124] @ (8002e5c ) + 8002dde: 011b lsls r3, r3, #4 + 8002de0: 18d3 adds r3, r2, r3 + 8002de2: 3309 adds r3, #9 + 8002de4: 1c0a adds r2, r1, #0 + 8002de6: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[6] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 16); + 8002de8: 4a1d ldr r2, [pc, #116] @ (8002e60 ) + 8002dea: 23de movs r3, #222 @ 0xde + 8002dec: 005b lsls r3, r3, #1 + 8002dee: 58d3 ldr r3, [r2, r3] + 8002df0: 0c19 lsrs r1, r3, #16 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[6] = (uint32_t) 0x000000FF + 8002df2: 4a1a ldr r2, [pc, #104] @ (8002e5c ) + 8002df4: 2302 movs r3, #2 + 8002df6: 33ff adds r3, #255 @ 0xff + 8002df8: 5cd3 ldrb r3, [r2, r3] + 8002dfa: b2c9 uxtb r1, r1 + 8002dfc: 4a17 ldr r2, [pc, #92] @ (8002e5c ) + 8002dfe: 011b lsls r3, r3, #4 + 8002e00: 18d3 adds r3, r2, r3 + 8002e02: 330a adds r3, #10 + 8002e04: 1c0a adds r2, r1, #0 + 8002e06: 701a strb r2, [r3, #0] + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[7] = (uint32_t) 0x000000FF + & (CAN->sFIFOMailBox[0].RDHR >> 24); + 8002e08: 4a15 ldr r2, [pc, #84] @ (8002e60 ) + 8002e0a: 23de movs r3, #222 @ 0xde + 8002e0c: 005b lsls r3, r3, #1 + 8002e0e: 58d3 ldr r3, [r2, r3] + 8002e10: 0e19 lsrs r1, r3, #24 + CAN_RX_Buffer.data[CAN_RX_Buffer.corent].data[7] = (uint32_t) 0x000000FF + 8002e12: 4a12 ldr r2, [pc, #72] @ (8002e5c ) + 8002e14: 2302 movs r3, #2 + 8002e16: 33ff adds r3, #255 @ 0xff + 8002e18: 5cd3 ldrb r3, [r2, r3] + 8002e1a: b2c9 uxtb r1, r1 + 8002e1c: 4a0f ldr r2, [pc, #60] @ (8002e5c ) + 8002e1e: 011b lsls r3, r3, #4 + 8002e20: 18d3 adds r3, r2, r3 + 8002e22: 330b adds r3, #11 + 8002e24: 1c0a adds r2, r1, #0 + 8002e26: 701a strb r2, [r3, #0] + if ((CAN_RX_Buffer.corent++) > 15) { + 8002e28: 4a0c ldr r2, [pc, #48] @ (8002e5c ) + 8002e2a: 2302 movs r3, #2 + 8002e2c: 33ff adds r3, #255 @ 0xff + 8002e2e: 5cd3 ldrb r3, [r2, r3] + 8002e30: 1c5a adds r2, r3, #1 + 8002e32: b2d0 uxtb r0, r2 + 8002e34: 4909 ldr r1, [pc, #36] @ (8002e5c ) + 8002e36: 2202 movs r2, #2 + 8002e38: 32ff adds r2, #255 @ 0xff + 8002e3a: 5488 strb r0, [r1, r2] + 8002e3c: 2b0f cmp r3, #15 + 8002e3e: d904 bls.n 8002e4a + CAN_RX_Buffer.corent = 0; + 8002e40: 4a06 ldr r2, [pc, #24] @ (8002e5c ) + 8002e42: 2302 movs r3, #2 + 8002e44: 33ff adds r3, #255 @ 0xff + 8002e46: 2100 movs r1, #0 + 8002e48: 54d1 strb r1, [r2, r3] + } + + //canAddRXBuffer(&canRxMsg); //TO DO not realy working + } + CAN->RF0R |= CAN_RF0R_RFOM0; + 8002e4a: 4b05 ldr r3, [pc, #20] @ (8002e60 ) + 8002e4c: 68da ldr r2, [r3, #12] + 8002e4e: 4b04 ldr r3, [pc, #16] @ (8002e60 ) + 8002e50: 2120 movs r1, #32 + 8002e52: 430a orrs r2, r1 + 8002e54: 60da str r2, [r3, #12] +} + 8002e56: 46c0 nop @ (mov r8, r8) + 8002e58: 46bd mov sp, r7 + 8002e5a: bd80 pop {r7, pc} + 8002e5c: 2000053c .word 0x2000053c + 8002e60: 40006400 .word 0x40006400 + +08002e64 : +void CAN_Read_RX_Buffer(can_msg_typedef *data) { + 8002e64: b580 push {r7, lr} + 8002e66: b082 sub sp, #8 + 8002e68: af00 add r7, sp, #0 + 8002e6a: 6078 str r0, [r7, #4] + if (CAN_RX_Buffer.todo > 0) { + 8002e6c: 4a54 ldr r2, [pc, #336] @ (8002fc0 ) + 8002e6e: 2380 movs r3, #128 @ 0x80 + 8002e70: 005b lsls r3, r3, #1 + 8002e72: 5cd3 ldrb r3, [r2, r3] + 8002e74: 2b00 cmp r3, #0 + 8002e76: d100 bne.n 8002e7a + 8002e78: e09d b.n 8002fb6 + //memcpy((void*) &data, (void*) &canRX_buffer.data[canRX_buffer.done], sizeof(CAN_msg_typedef)); + data->id = CAN_RX_Buffer.data[CAN_RX_Buffer.done].id; + 8002e7a: 4a51 ldr r2, [pc, #324] @ (8002fc0 ) + 8002e7c: 2381 movs r3, #129 @ 0x81 + 8002e7e: 005b lsls r3, r3, #1 + 8002e80: 5cd3 ldrb r3, [r2, r3] + 8002e82: 001a movs r2, r3 + 8002e84: 4b4e ldr r3, [pc, #312] @ (8002fc0 ) + 8002e86: 0112 lsls r2, r2, #4 + 8002e88: 58d2 ldr r2, [r2, r3] + 8002e8a: 687b ldr r3, [r7, #4] + 8002e8c: 601a str r2, [r3, #0] + data->format = CAN_RX_Buffer.data[CAN_RX_Buffer.done].format; + 8002e8e: 4a4c ldr r2, [pc, #304] @ (8002fc0 ) + 8002e90: 2381 movs r3, #129 @ 0x81 + 8002e92: 005b lsls r3, r3, #1 + 8002e94: 5cd3 ldrb r3, [r2, r3] + 8002e96: 4a4a ldr r2, [pc, #296] @ (8002fc0 ) + 8002e98: 011b lsls r3, r3, #4 + 8002e9a: 18d3 adds r3, r2, r3 + 8002e9c: 330d adds r3, #13 + 8002e9e: 781a ldrb r2, [r3, #0] + 8002ea0: 687b ldr r3, [r7, #4] + 8002ea2: 735a strb r2, [r3, #13] + data->frame = CAN_RX_Buffer.data[CAN_RX_Buffer.done].frame; + 8002ea4: 4a46 ldr r2, [pc, #280] @ (8002fc0 ) + 8002ea6: 2381 movs r3, #129 @ 0x81 + 8002ea8: 005b lsls r3, r3, #1 + 8002eaa: 5cd3 ldrb r3, [r2, r3] + 8002eac: 4a44 ldr r2, [pc, #272] @ (8002fc0 ) + 8002eae: 011b lsls r3, r3, #4 + 8002eb0: 18d3 adds r3, r2, r3 + 8002eb2: 330e adds r3, #14 + 8002eb4: 781a ldrb r2, [r3, #0] + 8002eb6: 687b ldr r3, [r7, #4] + 8002eb8: 739a strb r2, [r3, #14] + data->lenght = CAN_RX_Buffer.data[CAN_RX_Buffer.done].lenght; + 8002eba: 4a41 ldr r2, [pc, #260] @ (8002fc0 ) + 8002ebc: 2381 movs r3, #129 @ 0x81 + 8002ebe: 005b lsls r3, r3, #1 + 8002ec0: 5cd3 ldrb r3, [r2, r3] + 8002ec2: 4a3f ldr r2, [pc, #252] @ (8002fc0 ) + 8002ec4: 011b lsls r3, r3, #4 + 8002ec6: 18d3 adds r3, r2, r3 + 8002ec8: 330c adds r3, #12 + 8002eca: 781a ldrb r2, [r3, #0] + 8002ecc: 687b ldr r3, [r7, #4] + 8002ece: 731a strb r2, [r3, #12] + data->data[0] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[0]; + 8002ed0: 4a3b ldr r2, [pc, #236] @ (8002fc0 ) + 8002ed2: 2381 movs r3, #129 @ 0x81 + 8002ed4: 005b lsls r3, r3, #1 + 8002ed6: 5cd3 ldrb r3, [r2, r3] + 8002ed8: 4a39 ldr r2, [pc, #228] @ (8002fc0 ) + 8002eda: 011b lsls r3, r3, #4 + 8002edc: 18d3 adds r3, r2, r3 + 8002ede: 3304 adds r3, #4 + 8002ee0: 781a ldrb r2, [r3, #0] + 8002ee2: 687b ldr r3, [r7, #4] + 8002ee4: 711a strb r2, [r3, #4] + data->data[1] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[1]; + 8002ee6: 4a36 ldr r2, [pc, #216] @ (8002fc0 ) + 8002ee8: 2381 movs r3, #129 @ 0x81 + 8002eea: 005b lsls r3, r3, #1 + 8002eec: 5cd3 ldrb r3, [r2, r3] + 8002eee: 4a34 ldr r2, [pc, #208] @ (8002fc0 ) + 8002ef0: 011b lsls r3, r3, #4 + 8002ef2: 18d3 adds r3, r2, r3 + 8002ef4: 3305 adds r3, #5 + 8002ef6: 781a ldrb r2, [r3, #0] + 8002ef8: 687b ldr r3, [r7, #4] + 8002efa: 715a strb r2, [r3, #5] + data->data[2] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[2]; + 8002efc: 4a30 ldr r2, [pc, #192] @ (8002fc0 ) + 8002efe: 2381 movs r3, #129 @ 0x81 + 8002f00: 005b lsls r3, r3, #1 + 8002f02: 5cd3 ldrb r3, [r2, r3] + 8002f04: 4a2e ldr r2, [pc, #184] @ (8002fc0 ) + 8002f06: 011b lsls r3, r3, #4 + 8002f08: 18d3 adds r3, r2, r3 + 8002f0a: 3306 adds r3, #6 + 8002f0c: 781a ldrb r2, [r3, #0] + 8002f0e: 687b ldr r3, [r7, #4] + 8002f10: 719a strb r2, [r3, #6] + data->data[3] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[3]; + 8002f12: 4a2b ldr r2, [pc, #172] @ (8002fc0 ) + 8002f14: 2381 movs r3, #129 @ 0x81 + 8002f16: 005b lsls r3, r3, #1 + 8002f18: 5cd3 ldrb r3, [r2, r3] + 8002f1a: 4a29 ldr r2, [pc, #164] @ (8002fc0 ) + 8002f1c: 011b lsls r3, r3, #4 + 8002f1e: 18d3 adds r3, r2, r3 + 8002f20: 3307 adds r3, #7 + 8002f22: 781a ldrb r2, [r3, #0] + 8002f24: 687b ldr r3, [r7, #4] + 8002f26: 71da strb r2, [r3, #7] + data->data[4] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[4]; + 8002f28: 4a25 ldr r2, [pc, #148] @ (8002fc0 ) + 8002f2a: 2381 movs r3, #129 @ 0x81 + 8002f2c: 005b lsls r3, r3, #1 + 8002f2e: 5cd3 ldrb r3, [r2, r3] + 8002f30: 4a23 ldr r2, [pc, #140] @ (8002fc0 ) + 8002f32: 011b lsls r3, r3, #4 + 8002f34: 18d3 adds r3, r2, r3 + 8002f36: 3308 adds r3, #8 + 8002f38: 781a ldrb r2, [r3, #0] + 8002f3a: 687b ldr r3, [r7, #4] + 8002f3c: 721a strb r2, [r3, #8] + data->data[5] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[5]; + 8002f3e: 4a20 ldr r2, [pc, #128] @ (8002fc0 ) + 8002f40: 2381 movs r3, #129 @ 0x81 + 8002f42: 005b lsls r3, r3, #1 + 8002f44: 5cd3 ldrb r3, [r2, r3] + 8002f46: 4a1e ldr r2, [pc, #120] @ (8002fc0 ) + 8002f48: 011b lsls r3, r3, #4 + 8002f4a: 18d3 adds r3, r2, r3 + 8002f4c: 3309 adds r3, #9 + 8002f4e: 781a ldrb r2, [r3, #0] + 8002f50: 687b ldr r3, [r7, #4] + 8002f52: 725a strb r2, [r3, #9] + data->data[6] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[6]; + 8002f54: 4a1a ldr r2, [pc, #104] @ (8002fc0 ) + 8002f56: 2381 movs r3, #129 @ 0x81 + 8002f58: 005b lsls r3, r3, #1 + 8002f5a: 5cd3 ldrb r3, [r2, r3] + 8002f5c: 4a18 ldr r2, [pc, #96] @ (8002fc0 ) + 8002f5e: 011b lsls r3, r3, #4 + 8002f60: 18d3 adds r3, r2, r3 + 8002f62: 330a adds r3, #10 + 8002f64: 781a ldrb r2, [r3, #0] + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 729a strb r2, [r3, #10] + data->data[7] = CAN_RX_Buffer.data[CAN_RX_Buffer.done].data[7]; + 8002f6a: 4a15 ldr r2, [pc, #84] @ (8002fc0 ) + 8002f6c: 2381 movs r3, #129 @ 0x81 + 8002f6e: 005b lsls r3, r3, #1 + 8002f70: 5cd3 ldrb r3, [r2, r3] + 8002f72: 4a13 ldr r2, [pc, #76] @ (8002fc0 ) + 8002f74: 011b lsls r3, r3, #4 + 8002f76: 18d3 adds r3, r2, r3 + 8002f78: 330b adds r3, #11 + 8002f7a: 781a ldrb r2, [r3, #0] + 8002f7c: 687b ldr r3, [r7, #4] + 8002f7e: 72da strb r2, [r3, #11] + if ((CAN_RX_Buffer.done++) > 15) { + 8002f80: 4a0f ldr r2, [pc, #60] @ (8002fc0 ) + 8002f82: 2381 movs r3, #129 @ 0x81 + 8002f84: 005b lsls r3, r3, #1 + 8002f86: 5cd3 ldrb r3, [r2, r3] + 8002f88: 1c5a adds r2, r3, #1 + 8002f8a: b2d0 uxtb r0, r2 + 8002f8c: 490c ldr r1, [pc, #48] @ (8002fc0 ) + 8002f8e: 2281 movs r2, #129 @ 0x81 + 8002f90: 0052 lsls r2, r2, #1 + 8002f92: 5488 strb r0, [r1, r2] + 8002f94: 2b0f cmp r3, #15 + 8002f96: d904 bls.n 8002fa2 + CAN_RX_Buffer.done = 0; + 8002f98: 4a09 ldr r2, [pc, #36] @ (8002fc0 ) + 8002f9a: 2381 movs r3, #129 @ 0x81 + 8002f9c: 005b lsls r3, r3, #1 + 8002f9e: 2100 movs r1, #0 + 8002fa0: 54d1 strb r1, [r2, r3] + } + CAN_RX_Buffer.todo--; + 8002fa2: 4a07 ldr r2, [pc, #28] @ (8002fc0 ) + 8002fa4: 2380 movs r3, #128 @ 0x80 + 8002fa6: 005b lsls r3, r3, #1 + 8002fa8: 5cd3 ldrb r3, [r2, r3] + 8002faa: 3b01 subs r3, #1 + 8002fac: b2d9 uxtb r1, r3 + 8002fae: 4a04 ldr r2, [pc, #16] @ (8002fc0 ) + 8002fb0: 2380 movs r3, #128 @ 0x80 + 8002fb2: 005b lsls r3, r3, #1 + 8002fb4: 54d1 strb r1, [r2, r3] + } +} + 8002fb6: 46c0 nop @ (mov r8, r8) + 8002fb8: 46bd mov sp, r7 + 8002fba: b002 add sp, #8 + 8002fbc: bd80 pop {r7, pc} + 8002fbe: 46c0 nop @ (mov r8, r8) + 8002fc0: 2000053c .word 0x2000053c + +08002fc4 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8002fc4: b580 push {r7, lr} + 8002fc6: b082 sub sp, #8 + 8002fc8: af00 add r7, sp, #0 + 8002fca: 0002 movs r2, r0 + 8002fcc: 1dfb adds r3, r7, #7 + 8002fce: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8002fd0: 1dfb adds r3, r7, #7 + 8002fd2: 781b ldrb r3, [r3, #0] + 8002fd4: 2b7f cmp r3, #127 @ 0x7f + 8002fd6: d809 bhi.n 8002fec <__NVIC_EnableIRQ+0x28> + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8002fd8: 1dfb adds r3, r7, #7 + 8002fda: 781b ldrb r3, [r3, #0] + 8002fdc: 001a movs r2, r3 + 8002fde: 231f movs r3, #31 + 8002fe0: 401a ands r2, r3 + 8002fe2: 4b04 ldr r3, [pc, #16] @ (8002ff4 <__NVIC_EnableIRQ+0x30>) + 8002fe4: 2101 movs r1, #1 + 8002fe6: 4091 lsls r1, r2 + 8002fe8: 000a movs r2, r1 + 8002fea: 601a str r2, [r3, #0] + } +} + 8002fec: 46c0 nop @ (mov r8, r8) + 8002fee: 46bd mov sp, r7 + 8002ff0: b002 add sp, #8 + 8002ff2: bd80 pop {r7, pc} + 8002ff4: e000e100 .word 0xe000e100 + +08002ff8 <__NVIC_DisableIRQ>: + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8002ff8: b580 push {r7, lr} + 8002ffa: b082 sub sp, #8 + 8002ffc: af00 add r7, sp, #0 + 8002ffe: 0002 movs r2, r0 + 8003000: 1dfb adds r3, r7, #7 + 8003002: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8003004: 1dfb adds r3, r7, #7 + 8003006: 781b ldrb r3, [r3, #0] + 8003008: 2b7f cmp r3, #127 @ 0x7f + 800300a: d810 bhi.n 800302e <__NVIC_DisableIRQ+0x36> + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800300c: 1dfb adds r3, r7, #7 + 800300e: 781b ldrb r3, [r3, #0] + 8003010: 001a movs r2, r3 + 8003012: 231f movs r3, #31 + 8003014: 4013 ands r3, r2 + 8003016: 4908 ldr r1, [pc, #32] @ (8003038 <__NVIC_DisableIRQ+0x40>) + 8003018: 2201 movs r2, #1 + 800301a: 409a lsls r2, r3 + 800301c: 0013 movs r3, r2 + 800301e: 2280 movs r2, #128 @ 0x80 + 8003020: 508b str r3, [r1, r2] + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 8003022: f3bf 8f4f dsb sy +} + 8003026: 46c0 nop @ (mov r8, r8) + __ASM volatile ("isb 0xF":::"memory"); + 8003028: f3bf 8f6f isb sy +} + 800302c: 46c0 nop @ (mov r8, r8) + __DSB(); + __ISB(); + } +} + 800302e: 46c0 nop @ (mov r8, r8) + 8003030: 46bd mov sp, r7 + 8003032: b002 add sp, #8 + 8003034: bd80 pop {r7, pc} + 8003036: 46c0 nop @ (mov r8, r8) + 8003038: e000e100 .word 0xe000e100 + +0800303c : + tps1_offset, tps2_gain, tps2_offset; +volatile uint16_t dbw_fast_process_timer, dbw_slow_process_timer; +volatile int32_t vbat_corr, tps_slow_t, p_comp, i_comp, d_comp, tps_error_t, + can_target, spring_preload, idle_adder; + +void Apply_Sensor_Calibration(void) { + 800303c: b5b0 push {r4, r5, r7, lr} + 800303e: af00 add r7, sp, #0 + pps1_gain = (1000.0F / (float) (config->pps1_max - config->pps1_min)); + 8003040: 4b79 ldr r3, [pc, #484] @ (8003228 ) + 8003042: 681b ldr r3, [r3, #0] + 8003044: 889b ldrh r3, [r3, #4] + 8003046: b29b uxth r3, r3 + 8003048: 001a movs r2, r3 + 800304a: 4b77 ldr r3, [pc, #476] @ (8003228 ) + 800304c: 681b ldr r3, [r3, #0] + 800304e: 885b ldrh r3, [r3, #2] + 8003050: b29b uxth r3, r3 + 8003052: 1ad3 subs r3, r2, r3 + 8003054: 0018 movs r0, r3 + 8003056: f7fe f9cd bl 80013f4 <__aeabi_i2f> + 800305a: 1c03 adds r3, r0, #0 + 800305c: 1c19 adds r1, r3, #0 + 800305e: 4873 ldr r0, [pc, #460] @ (800322c ) + 8003060: f7fd fc46 bl 80008f0 <__aeabi_fdiv> + 8003064: 1c03 adds r3, r0, #0 + 8003066: 1c1a adds r2, r3, #0 + 8003068: 4b71 ldr r3, [pc, #452] @ (8003230 ) + 800306a: 601a str r2, [r3, #0] + pps1_offset = (config->pps1_min * 1000.0F + 800306c: 4b6e ldr r3, [pc, #440] @ (8003228 ) + 800306e: 681b ldr r3, [r3, #0] + 8003070: 885b ldrh r3, [r3, #2] + 8003072: b29b uxth r3, r3 + 8003074: 0018 movs r0, r3 + 8003076: f7fe f9bd bl 80013f4 <__aeabi_i2f> + 800307a: 1c03 adds r3, r0, #0 + 800307c: 496b ldr r1, [pc, #428] @ (800322c ) + 800307e: 1c18 adds r0, r3, #0 + 8003080: f7fd fe04 bl 8000c8c <__aeabi_fmul> + 8003084: 1c03 adds r3, r0, #0 + 8003086: 1c1c adds r4, r3, #0 + / (config->pps1_min - config->pps1_max)); + 8003088: 4b67 ldr r3, [pc, #412] @ (8003228 ) + 800308a: 681b ldr r3, [r3, #0] + 800308c: 885b ldrh r3, [r3, #2] + 800308e: b29b uxth r3, r3 + 8003090: 001a movs r2, r3 + 8003092: 4b65 ldr r3, [pc, #404] @ (8003228 ) + 8003094: 681b ldr r3, [r3, #0] + 8003096: 889b ldrh r3, [r3, #4] + 8003098: b29b uxth r3, r3 + 800309a: 1ad3 subs r3, r2, r3 + 800309c: 0018 movs r0, r3 + 800309e: f7fe f9a9 bl 80013f4 <__aeabi_i2f> + 80030a2: 1c03 adds r3, r0, #0 + 80030a4: 1c19 adds r1, r3, #0 + 80030a6: 1c20 adds r0, r4, #0 + 80030a8: f7fd fc22 bl 80008f0 <__aeabi_fdiv> + 80030ac: 1c03 adds r3, r0, #0 + 80030ae: 1c1a adds r2, r3, #0 + pps1_offset = (config->pps1_min * 1000.0F + 80030b0: 4b60 ldr r3, [pc, #384] @ (8003234 ) + 80030b2: 601a str r2, [r3, #0] + + pps2_gain = (1000.0F / (float) (config->pps2_max - config->pps2_min)); + 80030b4: 4b5c ldr r3, [pc, #368] @ (8003228 ) + 80030b6: 681b ldr r3, [r3, #0] + 80030b8: 899b ldrh r3, [r3, #12] + 80030ba: b29b uxth r3, r3 + 80030bc: 001a movs r2, r3 + 80030be: 4b5a ldr r3, [pc, #360] @ (8003228 ) + 80030c0: 681b ldr r3, [r3, #0] + 80030c2: 88db ldrh r3, [r3, #6] + 80030c4: b29b uxth r3, r3 + 80030c6: 1ad3 subs r3, r2, r3 + 80030c8: 0018 movs r0, r3 + 80030ca: f7fe f993 bl 80013f4 <__aeabi_i2f> + 80030ce: 1c03 adds r3, r0, #0 + 80030d0: 1c19 adds r1, r3, #0 + 80030d2: 4856 ldr r0, [pc, #344] @ (800322c ) + 80030d4: f7fd fc0c bl 80008f0 <__aeabi_fdiv> + 80030d8: 1c03 adds r3, r0, #0 + 80030da: 1c1a adds r2, r3, #0 + 80030dc: 4b56 ldr r3, [pc, #344] @ (8003238 ) + 80030de: 601a str r2, [r3, #0] + pps2_offset = (config->pps2_min * 1000.0F + 80030e0: 4b51 ldr r3, [pc, #324] @ (8003228 ) + 80030e2: 681b ldr r3, [r3, #0] + 80030e4: 88db ldrh r3, [r3, #6] + 80030e6: b29b uxth r3, r3 + 80030e8: 0018 movs r0, r3 + 80030ea: f7fe f983 bl 80013f4 <__aeabi_i2f> + 80030ee: 1c03 adds r3, r0, #0 + 80030f0: 494e ldr r1, [pc, #312] @ (800322c ) + 80030f2: 1c18 adds r0, r3, #0 + 80030f4: f7fd fdca bl 8000c8c <__aeabi_fmul> + 80030f8: 1c03 adds r3, r0, #0 + 80030fa: 1c1c adds r4, r3, #0 + / (config->pps2_min - config->pps2_max)); + 80030fc: 4b4a ldr r3, [pc, #296] @ (8003228 ) + 80030fe: 681b ldr r3, [r3, #0] + 8003100: 88db ldrh r3, [r3, #6] + 8003102: b29b uxth r3, r3 + 8003104: 001a movs r2, r3 + 8003106: 4b48 ldr r3, [pc, #288] @ (8003228 ) + 8003108: 681b ldr r3, [r3, #0] + 800310a: 899b ldrh r3, [r3, #12] + 800310c: b29b uxth r3, r3 + 800310e: 1ad3 subs r3, r2, r3 + 8003110: 0018 movs r0, r3 + 8003112: f7fe f96f bl 80013f4 <__aeabi_i2f> + 8003116: 1c03 adds r3, r0, #0 + 8003118: 1c19 adds r1, r3, #0 + 800311a: 1c20 adds r0, r4, #0 + 800311c: f7fd fbe8 bl 80008f0 <__aeabi_fdiv> + 8003120: 1c03 adds r3, r0, #0 + 8003122: 1c1a adds r2, r3, #0 + pps2_offset = (config->pps2_min * 1000.0F + 8003124: 4b45 ldr r3, [pc, #276] @ (800323c ) + 8003126: 601a str r2, [r3, #0] + + tps1_gain = (1000.0F / (float) (config->tps1_max - config->tps1_min)); + 8003128: 4b3f ldr r3, [pc, #252] @ (8003228 ) + 800312a: 681b ldr r3, [r3, #0] + 800312c: 8a1b ldrh r3, [r3, #16] + 800312e: b29b uxth r3, r3 + 8003130: 001a movs r2, r3 + 8003132: 4b3d ldr r3, [pc, #244] @ (8003228 ) + 8003134: 681b ldr r3, [r3, #0] + 8003136: 89db ldrh r3, [r3, #14] + 8003138: b29b uxth r3, r3 + 800313a: 1ad3 subs r3, r2, r3 + 800313c: 0018 movs r0, r3 + 800313e: f7fe f959 bl 80013f4 <__aeabi_i2f> + 8003142: 1c03 adds r3, r0, #0 + 8003144: 1c19 adds r1, r3, #0 + 8003146: 4839 ldr r0, [pc, #228] @ (800322c ) + 8003148: f7fd fbd2 bl 80008f0 <__aeabi_fdiv> + 800314c: 1c03 adds r3, r0, #0 + 800314e: 1c1a adds r2, r3, #0 + 8003150: 4b3b ldr r3, [pc, #236] @ (8003240 ) + 8003152: 601a str r2, [r3, #0] + tps1_offset = (short) (config->tps1_min * 1000.0F + 8003154: 4b34 ldr r3, [pc, #208] @ (8003228 ) + 8003156: 681b ldr r3, [r3, #0] + 8003158: 89db ldrh r3, [r3, #14] + 800315a: b29b uxth r3, r3 + 800315c: 0018 movs r0, r3 + 800315e: f7fe f949 bl 80013f4 <__aeabi_i2f> + 8003162: 1c03 adds r3, r0, #0 + 8003164: 4931 ldr r1, [pc, #196] @ (800322c ) + 8003166: 1c18 adds r0, r3, #0 + 8003168: f7fd fd90 bl 8000c8c <__aeabi_fmul> + 800316c: 1c03 adds r3, r0, #0 + 800316e: 1c1c adds r4, r3, #0 + / (config->tps1_min - config->tps1_max)); + 8003170: 4b2d ldr r3, [pc, #180] @ (8003228 ) + 8003172: 681b ldr r3, [r3, #0] + 8003174: 89db ldrh r3, [r3, #14] + 8003176: b29b uxth r3, r3 + 8003178: 001a movs r2, r3 + 800317a: 4b2b ldr r3, [pc, #172] @ (8003228 ) + 800317c: 681b ldr r3, [r3, #0] + 800317e: 8a1b ldrh r3, [r3, #16] + 8003180: b29b uxth r3, r3 + 8003182: 1ad3 subs r3, r2, r3 + 8003184: 0018 movs r0, r3 + 8003186: f7fe f935 bl 80013f4 <__aeabi_i2f> + 800318a: 1c03 adds r3, r0, #0 + 800318c: 1c19 adds r1, r3, #0 + 800318e: 1c20 adds r0, r4, #0 + 8003190: f7fd fbae bl 80008f0 <__aeabi_fdiv> + 8003194: 1c03 adds r3, r0, #0 + tps1_offset = (short) (config->tps1_min * 1000.0F + 8003196: 1c18 adds r0, r3, #0 + 8003198: f7fe f90c bl 80013b4 <__aeabi_f2iz> + 800319c: 0003 movs r3, r0 + 800319e: b21b sxth r3, r3 + 80031a0: 0018 movs r0, r3 + 80031a2: f7fe f927 bl 80013f4 <__aeabi_i2f> + 80031a6: 1c02 adds r2, r0, #0 + 80031a8: 4b26 ldr r3, [pc, #152] @ (8003244 ) + 80031aa: 601a str r2, [r3, #0] + + tps2_gain = (1000.0F / (float) (config->tps2_max - config->tps2_min)); + 80031ac: 4b1e ldr r3, [pc, #120] @ (8003228 ) + 80031ae: 681b ldr r3, [r3, #0] + 80031b0: 8b1b ldrh r3, [r3, #24] + 80031b2: b29b uxth r3, r3 + 80031b4: 001a movs r2, r3 + 80031b6: 4b1c ldr r3, [pc, #112] @ (8003228 ) + 80031b8: 681b ldr r3, [r3, #0] + 80031ba: 8a5b ldrh r3, [r3, #18] + 80031bc: b29b uxth r3, r3 + 80031be: 1ad3 subs r3, r2, r3 + 80031c0: 0018 movs r0, r3 + 80031c2: f7fe f917 bl 80013f4 <__aeabi_i2f> + 80031c6: 1c03 adds r3, r0, #0 + 80031c8: 1c19 adds r1, r3, #0 + 80031ca: 4818 ldr r0, [pc, #96] @ (800322c ) + 80031cc: f7fd fb90 bl 80008f0 <__aeabi_fdiv> + 80031d0: 1c03 adds r3, r0, #0 + 80031d2: 1c1a adds r2, r3, #0 + 80031d4: 4b1c ldr r3, [pc, #112] @ (8003248 ) + 80031d6: 601a str r2, [r3, #0] + tps2_offset = (config->tps2_min * 1000.0F + 80031d8: 4b13 ldr r3, [pc, #76] @ (8003228 ) + 80031da: 681b ldr r3, [r3, #0] + 80031dc: 8a5b ldrh r3, [r3, #18] + 80031de: b29b uxth r3, r3 + 80031e0: 0018 movs r0, r3 + 80031e2: f7fe f907 bl 80013f4 <__aeabi_i2f> + 80031e6: 1c03 adds r3, r0, #0 + 80031e8: 4910 ldr r1, [pc, #64] @ (800322c ) + 80031ea: 1c18 adds r0, r3, #0 + 80031ec: f7fd fd4e bl 8000c8c <__aeabi_fmul> + 80031f0: 1c03 adds r3, r0, #0 + 80031f2: 1c1c adds r4, r3, #0 + / (config->tps2_min - config->tps2_max)); + 80031f4: 4b0c ldr r3, [pc, #48] @ (8003228 ) + 80031f6: 681b ldr r3, [r3, #0] + 80031f8: 8a5b ldrh r3, [r3, #18] + 80031fa: b29b uxth r3, r3 + 80031fc: 001a movs r2, r3 + 80031fe: 4b0a ldr r3, [pc, #40] @ (8003228 ) + 8003200: 681b ldr r3, [r3, #0] + 8003202: 8b1b ldrh r3, [r3, #24] + 8003204: b29b uxth r3, r3 + 8003206: 1ad3 subs r3, r2, r3 + 8003208: 0018 movs r0, r3 + 800320a: f7fe f8f3 bl 80013f4 <__aeabi_i2f> + 800320e: 1c03 adds r3, r0, #0 + 8003210: 1c19 adds r1, r3, #0 + 8003212: 1c20 adds r0, r4, #0 + 8003214: f7fd fb6c bl 80008f0 <__aeabi_fdiv> + 8003218: 1c03 adds r3, r0, #0 + 800321a: 1c1a adds r2, r3, #0 + tps2_offset = (config->tps2_min * 1000.0F + 800321c: 4b0b ldr r3, [pc, #44] @ (800324c ) + 800321e: 601a str r2, [r3, #0] + +} + 8003220: 46c0 nop @ (mov r8, r8) + 8003222: 46bd mov sp, r7 + 8003224: bdb0 pop {r4, r5, r7, pc} + 8003226: 46c0 nop @ (mov r8, r8) + 8003228: 200009cc .word 0x200009cc + 800322c: 447a0000 .word 0x447a0000 + 8003230: 200009fc .word 0x200009fc + 8003234: 20000a00 .word 0x20000a00 + 8003238: 20000a04 .word 0x20000a04 + 800323c: 20000a08 .word 0x20000a08 + 8003240: 20000a0c .word 0x20000a0c + 8003244: 20000a10 .word 0x20000a10 + 8003248: 20000a14 .word 0x20000a14 + 800324c: 20000a18 .word 0x20000a18 + +08003250 : + +void DBW_Init(void) { + 8003250: b580 push {r7, lr} + 8003252: af00 add r7, sp, #0 + dbw_fast_process_timer = 1; + 8003254: 4b16 ldr r3, [pc, #88] @ (80032b0 ) + 8003256: 2201 movs r2, #1 + 8003258: 801a strh r2, [r3, #0] + dbw_slow_process_timer = config->motor_ctl_period; + 800325a: 4b16 ldr r3, [pc, #88] @ (80032b4 ) + 800325c: 681b ldr r3, [r3, #0] + 800325e: 227e movs r2, #126 @ 0x7e + 8003260: 5a9b ldrh r3, [r3, r2] + 8003262: b29a uxth r2, r3 + 8003264: 4b14 ldr r3, [pc, #80] @ (80032b8 ) + 8003266: 801a strh r2, [r3, #0] + vbat_corr = 0; + 8003268: 4b14 ldr r3, [pc, #80] @ (80032bc ) + 800326a: 2200 movs r2, #0 + 800326c: 601a str r2, [r3, #0] + tps_slow_t = var.tps; + 800326e: 4b14 ldr r3, [pc, #80] @ (80032c0 ) + 8003270: 8c5b ldrh r3, [r3, #34] @ 0x22 + 8003272: b21b sxth r3, r3 + 8003274: 001a movs r2, r3 + 8003276: 4b13 ldr r3, [pc, #76] @ (80032c4 ) + 8003278: 601a str r2, [r3, #0] + p_comp = 0; + 800327a: 4b13 ldr r3, [pc, #76] @ (80032c8 ) + 800327c: 2200 movs r2, #0 + 800327e: 601a str r2, [r3, #0] + i_comp = 0; + 8003280: 4b12 ldr r3, [pc, #72] @ (80032cc ) + 8003282: 2200 movs r2, #0 + 8003284: 601a str r2, [r3, #0] + d_comp = 0; + 8003286: 4b12 ldr r3, [pc, #72] @ (80032d0 ) + 8003288: 2200 movs r2, #0 + 800328a: 601a str r2, [r3, #0] + tps_error_t = var.tps_error; + 800328c: 4b0c ldr r3, [pc, #48] @ (80032c0 ) + 800328e: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8003290: b21b sxth r3, r3 + 8003292: 001a movs r2, r3 + 8003294: 4b0f ldr r3, [pc, #60] @ (80032d4 ) + 8003296: 601a str r2, [r3, #0] + can_target = 0; + 8003298: 4b0f ldr r3, [pc, #60] @ (80032d8 ) + 800329a: 2200 movs r2, #0 + 800329c: 601a str r2, [r3, #0] + spring_preload = 0; + 800329e: 4b0f ldr r3, [pc, #60] @ (80032dc ) + 80032a0: 2200 movs r2, #0 + 80032a2: 601a str r2, [r3, #0] + idle_adder = 0; + 80032a4: 4b0e ldr r3, [pc, #56] @ (80032e0 ) + 80032a6: 2200 movs r2, #0 + 80032a8: 601a str r2, [r3, #0] +} + 80032aa: 46c0 nop @ (mov r8, r8) + 80032ac: 46bd mov sp, r7 + 80032ae: bd80 pop {r7, pc} + 80032b0: 20000a1c .word 0x20000a1c + 80032b4: 200009cc .word 0x200009cc + 80032b8: 20000a1e .word 0x20000a1e + 80032bc: 20000a20 .word 0x20000a20 + 80032c0: 20000998 .word 0x20000998 + 80032c4: 20000a24 .word 0x20000a24 + 80032c8: 20000a28 .word 0x20000a28 + 80032cc: 20000a2c .word 0x20000a2c + 80032d0: 20000a30 .word 0x20000a30 + 80032d4: 20000a34 .word 0x20000a34 + 80032d8: 20000a38 .word 0x20000a38 + 80032dc: 20000a3c .word 0x20000a3c + 80032e0: 20000a40 .word 0x20000a40 + +080032e4 : + +int DBW_Process(void) { + 80032e4: b590 push {r4, r7, lr} + 80032e6: b085 sub sp, #20 + 80032e8: af02 add r7, sp, #8 + + int32_t pwm_output = 0; + 80032ea: 2300 movs r3, #0 + 80032ec: 607b str r3, [r7, #4] + int32_t pct = 0; + 80032ee: 2300 movs r3, #0 + 80032f0: 603b str r3, [r7, #0] + if (dbw_fast_process_timer == 0) { + 80032f2: 4ba6 ldr r3, [pc, #664] @ (800358c ) + 80032f4: 881b ldrh r3, [r3, #0] + 80032f6: b29b uxth r3, r3 + 80032f8: 2b00 cmp r3, #0 + 80032fa: d000 beq.n 80032fe + 80032fc: e2f4 b.n 80038e8 + //process DBW every 1 mS + dbw_fast_process_timer = 1; + 80032fe: 4ba3 ldr r3, [pc, #652] @ (800358c ) + 8003300: 2201 movs r2, #1 + 8003302: 801a strh r2, [r3, #0] + + // Read all sensors and calculate error + // calculate PPS sensor reading + var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc); + 8003304: 2000 movs r0, #0 + 8003306: f7ff fa9b bl 8002840 + 800330a: 0003 movs r3, r0 + 800330c: 0019 movs r1, r3 + 800330e: 4ba0 ldr r3, [pc, #640] @ (8003590 ) + 8003310: 899b ldrh r3, [r3, #12] + 8003312: b29a uxth r2, r3 + 8003314: 23af movs r3, #175 @ 0xaf + 8003316: 009b lsls r3, r3, #2 + 8003318: 0018 movs r0, r3 + 800331a: f7ff fa43 bl 80027a4 + 800331e: 0003 movs r3, r0 + 8003320: 001a movs r2, r3 + 8003322: 4b9b ldr r3, [pc, #620] @ (8003590 ) + 8003324: 819a strh r2, [r3, #12] + var.pps1 = var.pps1_adc * pps1_gain + pps1_offset; + 8003326: 4b9a ldr r3, [pc, #616] @ (8003590 ) + 8003328: 899b ldrh r3, [r3, #12] + 800332a: b29b uxth r3, r3 + 800332c: 0018 movs r0, r3 + 800332e: f7fe f861 bl 80013f4 <__aeabi_i2f> + 8003332: 1c02 adds r2, r0, #0 + 8003334: 4b97 ldr r3, [pc, #604] @ (8003594 ) + 8003336: 681b ldr r3, [r3, #0] + 8003338: 1c19 adds r1, r3, #0 + 800333a: 1c10 adds r0, r2, #0 + 800333c: f7fd fca6 bl 8000c8c <__aeabi_fmul> + 8003340: 1c03 adds r3, r0, #0 + 8003342: 1c1a adds r2, r3, #0 + 8003344: 4b94 ldr r3, [pc, #592] @ (8003598 ) + 8003346: 681b ldr r3, [r3, #0] + 8003348: 1c19 adds r1, r3, #0 + 800334a: 1c10 adds r0, r2, #0 + 800334c: f7fd f8c2 bl 80004d4 <__aeabi_fadd> + 8003350: 1c03 adds r3, r0, #0 + 8003352: 1c18 adds r0, r3, #0 + 8003354: f7fe f82e bl 80013b4 <__aeabi_f2iz> + 8003358: 0003 movs r3, r0 + 800335a: b21a sxth r2, r3 + 800335c: 4b8c ldr r3, [pc, #560] @ (8003590 ) + 800335e: 831a strh r2, [r3, #24] + + var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); //orig 1 + 8003360: 2003 movs r0, #3 + 8003362: f7ff fa6d bl 8002840 + 8003366: 0003 movs r3, r0 + 8003368: 0019 movs r1, r3 + 800336a: 4b89 ldr r3, [pc, #548] @ (8003590 ) + 800336c: 89db ldrh r3, [r3, #14] + 800336e: b29a uxth r2, r3 + 8003370: 23af movs r3, #175 @ 0xaf + 8003372: 009b lsls r3, r3, #2 + 8003374: 0018 movs r0, r3 + 8003376: f7ff fa15 bl 80027a4 + 800337a: 0003 movs r3, r0 + 800337c: 001a movs r2, r3 + 800337e: 4b84 ldr r3, [pc, #528] @ (8003590 ) + 8003380: 81da strh r2, [r3, #14] + var.pps2 = var.pps2_adc * pps2_gain + pps2_offset; + 8003382: 4b83 ldr r3, [pc, #524] @ (8003590 ) + 8003384: 89db ldrh r3, [r3, #14] + 8003386: b29b uxth r3, r3 + 8003388: 0018 movs r0, r3 + 800338a: f7fe f833 bl 80013f4 <__aeabi_i2f> + 800338e: 1c02 adds r2, r0, #0 + 8003390: 4b82 ldr r3, [pc, #520] @ (800359c ) + 8003392: 681b ldr r3, [r3, #0] + 8003394: 1c19 adds r1, r3, #0 + 8003396: 1c10 adds r0, r2, #0 + 8003398: f7fd fc78 bl 8000c8c <__aeabi_fmul> + 800339c: 1c03 adds r3, r0, #0 + 800339e: 1c1a adds r2, r3, #0 + 80033a0: 4b7f ldr r3, [pc, #508] @ (80035a0 ) + 80033a2: 681b ldr r3, [r3, #0] + 80033a4: 1c19 adds r1, r3, #0 + 80033a6: 1c10 adds r0, r2, #0 + 80033a8: f7fd f894 bl 80004d4 <__aeabi_fadd> + 80033ac: 1c03 adds r3, r0, #0 + 80033ae: 1c18 adds r0, r3, #0 + 80033b0: f7fe f800 bl 80013b4 <__aeabi_f2iz> + 80033b4: 0003 movs r3, r0 + 80033b6: b21a sxth r2, r3 + 80033b8: 4b75 ldr r3, [pc, #468] @ (8003590 ) + 80033ba: 835a strh r2, [r3, #26] + + var.pps_delta = var.pps1 - var.pps2; + 80033bc: 4b74 ldr r3, [pc, #464] @ (8003590 ) + 80033be: 8b1b ldrh r3, [r3, #24] + 80033c0: b21b sxth r3, r3 + 80033c2: b29a uxth r2, r3 + 80033c4: 4b72 ldr r3, [pc, #456] @ (8003590 ) + 80033c6: 8b5b ldrh r3, [r3, #26] + 80033c8: b21b sxth r3, r3 + 80033ca: b29b uxth r3, r3 + 80033cc: 1ad3 subs r3, r2, r3 + 80033ce: b29b uxth r3, r3 + 80033d0: b21a sxth r2, r3 + 80033d2: 4b6f ldr r3, [pc, #444] @ (8003590 ) + 80033d4: 855a strh r2, [r3, #42] @ 0x2a + var.pps = (var.pps1 + var.pps2) >> 1; + 80033d6: 4b6e ldr r3, [pc, #440] @ (8003590 ) + 80033d8: 8b1b ldrh r3, [r3, #24] + 80033da: b21b sxth r3, r3 + 80033dc: 001a movs r2, r3 + 80033de: 4b6c ldr r3, [pc, #432] @ (8003590 ) + 80033e0: 8b5b ldrh r3, [r3, #26] + 80033e2: b21b sxth r3, r3 + 80033e4: 18d3 adds r3, r2, r3 + 80033e6: 105b asrs r3, r3, #1 + 80033e8: b21a sxth r2, r3 + 80033ea: 4b69 ldr r3, [pc, #420] @ (8003590 ) + 80033ec: 841a strh r2, [r3, #32] + + //Calculate TPS sensor reading + var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc); + 80033ee: 2002 movs r0, #2 + 80033f0: f7ff fa26 bl 8002840 + 80033f4: 0003 movs r3, r0 + 80033f6: 0019 movs r1, r3 + 80033f8: 4b65 ldr r3, [pc, #404] @ (8003590 ) + 80033fa: 8a1b ldrh r3, [r3, #16] + 80033fc: b29a uxth r2, r3 + 80033fe: 23af movs r3, #175 @ 0xaf + 8003400: 009b lsls r3, r3, #2 + 8003402: 0018 movs r0, r3 + 8003404: f7ff f9ce bl 80027a4 + 8003408: 0003 movs r3, r0 + 800340a: 001a movs r2, r3 + 800340c: 4b60 ldr r3, [pc, #384] @ (8003590 ) + 800340e: 821a strh r2, [r3, #16] + var.tps1 = var.tps1_adc * tps1_gain + tps1_offset; + 8003410: 4b5f ldr r3, [pc, #380] @ (8003590 ) + 8003412: 8a1b ldrh r3, [r3, #16] + 8003414: b29b uxth r3, r3 + 8003416: 0018 movs r0, r3 + 8003418: f7fd ffec bl 80013f4 <__aeabi_i2f> + 800341c: 1c02 adds r2, r0, #0 + 800341e: 4b61 ldr r3, [pc, #388] @ (80035a4 ) + 8003420: 681b ldr r3, [r3, #0] + 8003422: 1c19 adds r1, r3, #0 + 8003424: 1c10 adds r0, r2, #0 + 8003426: f7fd fc31 bl 8000c8c <__aeabi_fmul> + 800342a: 1c03 adds r3, r0, #0 + 800342c: 1c1a adds r2, r3, #0 + 800342e: 4b5e ldr r3, [pc, #376] @ (80035a8 ) + 8003430: 681b ldr r3, [r3, #0] + 8003432: 1c19 adds r1, r3, #0 + 8003434: 1c10 adds r0, r2, #0 + 8003436: f7fd f84d bl 80004d4 <__aeabi_fadd> + 800343a: 1c03 adds r3, r0, #0 + 800343c: 1c18 adds r0, r3, #0 + 800343e: f7fd ffb9 bl 80013b4 <__aeabi_f2iz> + 8003442: 0003 movs r3, r0 + 8003444: b21a sxth r2, r3 + 8003446: 4b52 ldr r3, [pc, #328] @ (8003590 ) + 8003448: 839a strh r2, [r3, #28] + + var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //orig 3 + 800344a: 2001 movs r0, #1 + 800344c: f7ff f9f8 bl 8002840 + 8003450: 0003 movs r3, r0 + 8003452: 0019 movs r1, r3 + 8003454: 4b4e ldr r3, [pc, #312] @ (8003590 ) + 8003456: 8a5b ldrh r3, [r3, #18] + 8003458: b29a uxth r2, r3 + 800345a: 23af movs r3, #175 @ 0xaf + 800345c: 009b lsls r3, r3, #2 + 800345e: 0018 movs r0, r3 + 8003460: f7ff f9a0 bl 80027a4 + 8003464: 0003 movs r3, r0 + 8003466: 001a movs r2, r3 + 8003468: 4b49 ldr r3, [pc, #292] @ (8003590 ) + 800346a: 825a strh r2, [r3, #18] + var.tps2 = var.tps2_adc * tps2_gain + tps2_offset; + 800346c: 4b48 ldr r3, [pc, #288] @ (8003590 ) + 800346e: 8a5b ldrh r3, [r3, #18] + 8003470: b29b uxth r3, r3 + 8003472: 0018 movs r0, r3 + 8003474: f7fd ffbe bl 80013f4 <__aeabi_i2f> + 8003478: 1c02 adds r2, r0, #0 + 800347a: 4b4c ldr r3, [pc, #304] @ (80035ac ) + 800347c: 681b ldr r3, [r3, #0] + 800347e: 1c19 adds r1, r3, #0 + 8003480: 1c10 adds r0, r2, #0 + 8003482: f7fd fc03 bl 8000c8c <__aeabi_fmul> + 8003486: 1c03 adds r3, r0, #0 + 8003488: 1c1a adds r2, r3, #0 + 800348a: 4b49 ldr r3, [pc, #292] @ (80035b0 ) + 800348c: 681b ldr r3, [r3, #0] + 800348e: 1c19 adds r1, r3, #0 + 8003490: 1c10 adds r0, r2, #0 + 8003492: f7fd f81f bl 80004d4 <__aeabi_fadd> + 8003496: 1c03 adds r3, r0, #0 + 8003498: 1c18 adds r0, r3, #0 + 800349a: f7fd ff8b bl 80013b4 <__aeabi_f2iz> + 800349e: 0003 movs r3, r0 + 80034a0: b21a sxth r2, r3 + 80034a2: 4b3b ldr r3, [pc, #236] @ (8003590 ) + 80034a4: 83da strh r2, [r3, #30] + + // calculate tps and pps delta and values + var.tps_delta = var.tps1 - var.tps2; + 80034a6: 4b3a ldr r3, [pc, #232] @ (8003590 ) + 80034a8: 8b9b ldrh r3, [r3, #28] + 80034aa: b21b sxth r3, r3 + 80034ac: b29a uxth r2, r3 + 80034ae: 4b38 ldr r3, [pc, #224] @ (8003590 ) + 80034b0: 8bdb ldrh r3, [r3, #30] + 80034b2: b21b sxth r3, r3 + 80034b4: b29b uxth r3, r3 + 80034b6: 1ad3 subs r3, r2, r3 + 80034b8: b29b uxth r3, r3 + 80034ba: b21a sxth r2, r3 + 80034bc: 4b34 ldr r3, [pc, #208] @ (8003590 ) + 80034be: 859a strh r2, [r3, #44] @ 0x2c + var.tps = (var.tps1 + var.tps2) >> 1; + 80034c0: 4b33 ldr r3, [pc, #204] @ (8003590 ) + 80034c2: 8b9b ldrh r3, [r3, #28] + 80034c4: b21b sxth r3, r3 + 80034c6: 001a movs r2, r3 + 80034c8: 4b31 ldr r3, [pc, #196] @ (8003590 ) + 80034ca: 8bdb ldrh r3, [r3, #30] + 80034cc: b21b sxth r3, r3 + 80034ce: 18d3 adds r3, r2, r3 + 80034d0: 105b asrs r3, r3, #1 + 80034d2: b21a sxth r2, r3 + 80034d4: 4b2e ldr r3, [pc, #184] @ (8003590 ) + 80034d6: 845a strh r2, [r3, #34] @ 0x22 + + var.pps_delta = var.pps1 - var.pps2; + 80034d8: 4b2d ldr r3, [pc, #180] @ (8003590 ) + 80034da: 8b1b ldrh r3, [r3, #24] + 80034dc: b21b sxth r3, r3 + 80034de: b29a uxth r2, r3 + 80034e0: 4b2b ldr r3, [pc, #172] @ (8003590 ) + 80034e2: 8b5b ldrh r3, [r3, #26] + 80034e4: b21b sxth r3, r3 + 80034e6: b29b uxth r3, r3 + 80034e8: 1ad3 subs r3, r2, r3 + 80034ea: b29b uxth r3, r3 + 80034ec: b21a sxth r2, r3 + 80034ee: 4b28 ldr r3, [pc, #160] @ (8003590 ) + 80034f0: 855a strh r2, [r3, #42] @ 0x2a + var.pps = (var.pps1 + var.pps2) >> 1; + 80034f2: 4b27 ldr r3, [pc, #156] @ (8003590 ) + 80034f4: 8b1b ldrh r3, [r3, #24] + 80034f6: b21b sxth r3, r3 + 80034f8: 001a movs r2, r3 + 80034fa: 4b25 ldr r3, [pc, #148] @ (8003590 ) + 80034fc: 8b5b ldrh r3, [r3, #26] + 80034fe: b21b sxth r3, r3 + 8003500: 18d3 adds r3, r2, r3 + 8003502: 105b asrs r3, r3, #1 + 8003504: b21a sxth r2, r3 + 8003506: 4b22 ldr r3, [pc, #136] @ (8003590 ) + 8003508: 841a strh r2, [r3, #32] + + // set tps target + if (config->pps2tps_option == PPS2TPS_OPTION_CURVE) { + 800350a: 4b2a ldr r3, [pc, #168] @ (80035b4 ) + 800350c: 681b ldr r3, [r3, #0] + 800350e: 7e9b ldrb r3, [r3, #26] + 8003510: b2db uxtb r3, r3 + 8003512: 2b00 cmp r3, #0 + 8003514: d113 bne.n 800353e + var.tps_target = intrp_1d_ss_table(var.pps, 16, + 8003516: 4b1e ldr r3, [pc, #120] @ (8003590 ) + 8003518: 8c1b ldrh r3, [r3, #32] + 800351a: b218 sxth r0, r3 + (signed short*) config->pps_bins, 1, + 800351c: 4b25 ldr r3, [pc, #148] @ (80035b4 ) + 800351e: 681b ldr r3, [r3, #0] + 8003520: 331c adds r3, #28 + 8003522: 001a movs r2, r3 + (signed short*) config->tps_bins); + 8003524: 4b23 ldr r3, [pc, #140] @ (80035b4 ) + 8003526: 681b ldr r3, [r3, #0] + 8003528: 333c adds r3, #60 @ 0x3c + var.tps_target = intrp_1d_ss_table(var.pps, 16, + 800352a: 9300 str r3, [sp, #0] + 800352c: 2301 movs r3, #1 + 800352e: 2110 movs r1, #16 + 8003530: f000 fcce bl 8003ed0 + 8003534: 0003 movs r3, r0 + 8003536: 001a movs r2, r3 + 8003538: 4b15 ldr r3, [pc, #84] @ (8003590 ) + 800353a: 85da strh r2, [r3, #46] @ 0x2e + 800353c: e040 b.n 80035c0 + } + // if MS3 DBW protocol is used + else if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) { + 800353e: 4b1d ldr r3, [pc, #116] @ (80035b4 ) + 8003540: 681b ldr r3, [r3, #0] + 8003542: 7e9b ldrb r3, [r3, #26] + 8003544: b2db uxtb r3, r3 + 8003546: 2b01 cmp r3, #1 + 8003548: d138 bne.n 80035bc + // if no RX errors + //if(var.status0 & DBW_STATUS0_CAN_MSDBW_F) + if (config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) { + 800354a: 4b1a ldr r3, [pc, #104] @ (80035b4 ) + 800354c: 681b ldr r3, [r3, #0] + 800354e: 7e9b ldrb r3, [r3, #26] + 8003550: b2db uxtb r3, r3 + 8003552: 2b01 cmp r3, #1 + 8003554: d105 bne.n 8003562 + // use MS3 TPS TARGET + var.tps_target = can_target; + 8003556: 4b18 ldr r3, [pc, #96] @ (80035b8 ) + 8003558: 681b ldr r3, [r3, #0] + 800355a: b21a sxth r2, r3 + 800355c: 4b0c ldr r3, [pc, #48] @ (8003590 ) + 800355e: 85da strh r2, [r3, #46] @ 0x2e + 8003560: e02e b.n 80035c0 + } else { + // on CAN error fall back to internal curve + var.tps_target = intrp_1d_ss_table(var.pps, 16, + 8003562: 4b0b ldr r3, [pc, #44] @ (8003590 ) + 8003564: 8c1b ldrh r3, [r3, #32] + 8003566: b218 sxth r0, r3 + (signed short*) config->pps_bins, 1, + 8003568: 4b12 ldr r3, [pc, #72] @ (80035b4 ) + 800356a: 681b ldr r3, [r3, #0] + 800356c: 331c adds r3, #28 + 800356e: 001a movs r2, r3 + (signed short*) config->tps_bins); + 8003570: 4b10 ldr r3, [pc, #64] @ (80035b4 ) + 8003572: 681b ldr r3, [r3, #0] + 8003574: 333c adds r3, #60 @ 0x3c + var.tps_target = intrp_1d_ss_table(var.pps, 16, + 8003576: 9300 str r3, [sp, #0] + 8003578: 2301 movs r3, #1 + 800357a: 2110 movs r1, #16 + 800357c: f000 fca8 bl 8003ed0 + 8003580: 0003 movs r3, r0 + 8003582: 001a movs r2, r3 + 8003584: 4b02 ldr r3, [pc, #8] @ (8003590 ) + 8003586: 85da strh r2, [r3, #46] @ 0x2e + 8003588: e01a b.n 80035c0 + 800358a: 46c0 nop @ (mov r8, r8) + 800358c: 20000a1c .word 0x20000a1c + 8003590: 20000998 .word 0x20000998 + 8003594: 200009fc .word 0x200009fc + 8003598: 20000a00 .word 0x20000a00 + 800359c: 20000a04 .word 0x20000a04 + 80035a0: 20000a08 .word 0x20000a08 + 80035a4: 20000a0c .word 0x20000a0c + 80035a8: 20000a10 .word 0x20000a10 + 80035ac: 20000a14 .word 0x20000a14 + 80035b0: 20000a18 .word 0x20000a18 + 80035b4: 200009cc .word 0x200009cc + 80035b8: 20000a38 .word 0x20000a38 + } + } + + else { + // All other TPS target options are considered as fault + Error_Handler(); + 80035bc: f001 fbb0 bl 8004d20 + } + + // add idle TPS target adder + var.tps_target += idle_adder; + 80035c0: 4bcc ldr r3, [pc, #816] @ (80038f4 ) + 80035c2: 6819 ldr r1, [r3, #0] + 80035c4: 4bcc ldr r3, [pc, #816] @ (80038f8 ) + 80035c6: 8ddb ldrh r3, [r3, #46] @ 0x2e + 80035c8: b21b sxth r3, r3 + 80035ca: b29a uxth r2, r3 + 80035cc: b28b uxth r3, r1 + 80035ce: 18d3 adds r3, r2, r3 + 80035d0: b29b uxth r3, r3 + 80035d2: b21a sxth r2, r3 + 80035d4: 4bc8 ldr r3, [pc, #800] @ (80038f8 ) + 80035d6: 85da strh r2, [r3, #46] @ 0x2e + //limit TPS target + if (var.tps_target > 1000) + 80035d8: 4bc7 ldr r3, [pc, #796] @ (80038f8 ) + 80035da: 8ddb ldrh r3, [r3, #46] @ 0x2e + 80035dc: b21a sxth r2, r3 + 80035de: 23fa movs r3, #250 @ 0xfa + 80035e0: 009b lsls r3, r3, #2 + 80035e2: 429a cmp r2, r3 + 80035e4: dd03 ble.n 80035ee + var.tps_target = 1000; + 80035e6: 4bc4 ldr r3, [pc, #784] @ (80038f8 ) + 80035e8: 22fa movs r2, #250 @ 0xfa + 80035ea: 0092 lsls r2, r2, #2 + 80035ec: 85da strh r2, [r3, #46] @ 0x2e + if (var.tps_target < 0) + 80035ee: 4bc2 ldr r3, [pc, #776] @ (80038f8 ) + 80035f0: 8ddb ldrh r3, [r3, #46] @ 0x2e + 80035f2: b21b sxth r3, r3 + 80035f4: 2b00 cmp r3, #0 + 80035f6: da02 bge.n 80035fe + var.tps_target = 0; + 80035f8: 4bbf ldr r3, [pc, #764] @ (80038f8 ) + 80035fa: 2200 movs r2, #0 + 80035fc: 85da strh r2, [r3, #46] @ 0x2e + + //calculate regulation error + var.tps_error = var.tps_target - var.tps; + 80035fe: 4bbe ldr r3, [pc, #760] @ (80038f8 ) + 8003600: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8003602: b21b sxth r3, r3 + 8003604: b29a uxth r2, r3 + 8003606: 4bbc ldr r3, [pc, #752] @ (80038f8 ) + 8003608: 8c5b ldrh r3, [r3, #34] @ 0x22 + 800360a: b21b sxth r3, r3 + 800360c: b29b uxth r3, r3 + 800360e: 1ad3 subs r3, r2, r3 + 8003610: b29b uxth r3, r3 + 8003612: b21a sxth r2, r3 + 8003614: 4bb8 ldr r3, [pc, #736] @ (80038f8 ) + 8003616: 849a strh r2, [r3, #36] @ 0x24 + + // Proportional regulator + p_comp = (((int32_t) var.tps_error) * (int32_t) config->motor_fw_p) + 8003618: 4bb7 ldr r3, [pc, #732] @ (80038f8 ) + 800361a: 8c9b ldrh r3, [r3, #36] @ 0x24 + 800361c: b21b sxth r3, r3 + 800361e: 0019 movs r1, r3 + 8003620: 4bb6 ldr r3, [pc, #728] @ (80038fc ) + 8003622: 681b ldr r3, [r3, #0] + 8003624: 2282 movs r2, #130 @ 0x82 + 8003626: 5a9b ldrh r3, [r3, r2] + 8003628: b21b sxth r3, r3 + 800362a: 434b muls r3, r1 + / 10; + 800362c: 210a movs r1, #10 + 800362e: 0018 movs r0, r3 + 8003630: f7fc fdf4 bl 800021c <__divsi3> + 8003634: 0003 movs r3, r0 + 8003636: 001a movs r2, r3 + p_comp = (((int32_t) var.tps_error) * (int32_t) config->motor_fw_p) + 8003638: 4bb1 ldr r3, [pc, #708] @ (8003900 ) + 800363a: 601a str r2, [r3, #0] + + // calculate spring preload compensation using interpolation + spring_preload = intrp_1d_ss_table(var.tps_target, 16, + 800363c: 4bae ldr r3, [pc, #696] @ (80038f8 ) + 800363e: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8003640: b218 sxth r0, r3 + (signed short*) config->tps_dc_tps_bins, 1, + 8003642: 4bae ldr r3, [pc, #696] @ (80038fc ) + 8003644: 681b ldr r3, [r3, #0] + 8003646: 22b5 movs r2, #181 @ 0xb5 + 8003648: 0092 lsls r2, r2, #2 + 800364a: 189a adds r2, r3, r2 + (signed short*) config->tps_dc_offset_bins); + 800364c: 4bab ldr r3, [pc, #684] @ (80038fc ) + 800364e: 681b ldr r3, [r3, #0] + 8003650: 21bd movs r1, #189 @ 0xbd + 8003652: 0089 lsls r1, r1, #2 + 8003654: 468c mov ip, r1 + 8003656: 4463 add r3, ip + spring_preload = intrp_1d_ss_table(var.tps_target, 16, + 8003658: 9300 str r3, [sp, #0] + 800365a: 2301 movs r3, #1 + 800365c: 2110 movs r1, #16 + 800365e: f000 fc37 bl 8003ed0 + 8003662: 0003 movs r3, r0 + 8003664: 001a movs r2, r3 + 8003666: 4ba7 ldr r3, [pc, #668] @ (8003904 ) + 8003668: 601a str r2, [r3, #0] + + if (dbw_slow_process_timer > 0) { + 800366a: 4ba7 ldr r3, [pc, #668] @ (8003908 ) + 800366c: 881b ldrh r3, [r3, #0] + 800366e: b29b uxth r3, r3 + 8003670: 2b00 cmp r3, #0 + 8003672: d100 bne.n 8003676 + 8003674: e0ef b.n 8003856 + dbw_slow_process_timer--; + 8003676: 4ba4 ldr r3, [pc, #656] @ (8003908 ) + 8003678: 881b ldrh r3, [r3, #0] + 800367a: b29b uxth r3, r3 + 800367c: 3b01 subs r3, #1 + 800367e: b29a uxth r2, r3 + 8003680: 4ba1 ldr r3, [pc, #644] @ (8003908 ) + 8003682: 801a strh r2, [r3, #0] + if (dbw_slow_process_timer == 0) { + 8003684: 4ba0 ldr r3, [pc, #640] @ (8003908 ) + 8003686: 881b ldrh r3, [r3, #0] + 8003688: b29b uxth r3, r3 + 800368a: 2b00 cmp r3, #0 + 800368c: d000 beq.n 8003690 + 800368e: e0e2 b.n 8003856 + dbw_slow_process_timer = config->motor_ctl_period; + 8003690: 4b9a ldr r3, [pc, #616] @ (80038fc ) + 8003692: 681b ldr r3, [r3, #0] + 8003694: 227e movs r2, #126 @ 0x7e + 8003696: 5a9b ldrh r3, [r3, r2] + 8003698: b29a uxth r2, r3 + 800369a: 4b9b ldr r3, [pc, #620] @ (8003908 ) + 800369c: 801a strh r2, [r3, #0] + //calculate slow changing thinks + + //read Battery voltage and apply corrections + var.vbat_adc = LPF(700, Adc_Read(5), var.vbat_adc); + 800369e: 2005 movs r0, #5 + 80036a0: f7ff f8ce bl 8002840 + 80036a4: 0003 movs r3, r0 + 80036a6: 0019 movs r1, r3 + 80036a8: 4b93 ldr r3, [pc, #588] @ (80038f8 ) + 80036aa: 8adb ldrh r3, [r3, #22] + 80036ac: b29a uxth r2, r3 + 80036ae: 23af movs r3, #175 @ 0xaf + 80036b0: 009b lsls r3, r3, #2 + 80036b2: 0018 movs r0, r3 + 80036b4: f7ff f876 bl 80027a4 + 80036b8: 0003 movs r3, r0 + 80036ba: 001a movs r2, r3 + 80036bc: 4b8e ldr r3, [pc, #568] @ (80038f8 ) + 80036be: 82da strh r2, [r3, #22] + pct = intrp_1d_ss_table(var.vbat_adc, 8, + 80036c0: 4b8d ldr r3, [pc, #564] @ (80038f8 ) + 80036c2: 8adb ldrh r3, [r3, #22] + 80036c4: b29b uxth r3, r3 + 80036c6: b218 sxth r0, r3 + (signed short*) config->vbat_bins, 1, + 80036c8: 4b8c ldr r3, [pc, #560] @ (80038fc ) + 80036ca: 681b ldr r3, [r3, #0] + 80036cc: 22c5 movs r2, #197 @ 0xc5 + 80036ce: 0092 lsls r2, r2, #2 + 80036d0: 189a adds r2, r3, r2 + (signed short*) config->motor_pwm_corr_bins); + 80036d2: 4b8a ldr r3, [pc, #552] @ (80038fc ) + 80036d4: 681b ldr r3, [r3, #0] + 80036d6: 21c9 movs r1, #201 @ 0xc9 + 80036d8: 0089 lsls r1, r1, #2 + 80036da: 468c mov ip, r1 + 80036dc: 4463 add r3, ip + pct = intrp_1d_ss_table(var.vbat_adc, 8, + 80036de: 9300 str r3, [sp, #0] + 80036e0: 2301 movs r3, #1 + 80036e2: 2108 movs r1, #8 + 80036e4: f000 fbf4 bl 8003ed0 + 80036e8: 0003 movs r3, r0 + 80036ea: 603b str r3, [r7, #0] + + //read motor current + var.motor_current_adc = LPF(700, Adc_Read(4), + 80036ec: 2004 movs r0, #4 + 80036ee: f7ff f8a7 bl 8002840 + 80036f2: 0003 movs r3, r0 + 80036f4: 0019 movs r1, r3 + var.motor_current_adc); + 80036f6: 4b80 ldr r3, [pc, #512] @ (80038f8 ) + 80036f8: 8a9b ldrh r3, [r3, #20] + 80036fa: b29a uxth r2, r3 + var.motor_current_adc = LPF(700, Adc_Read(4), + 80036fc: 23af movs r3, #175 @ 0xaf + 80036fe: 009b lsls r3, r3, #2 + 8003700: 0018 movs r0, r3 + 8003702: f7ff f84f bl 80027a4 + 8003706: 0003 movs r3, r0 + 8003708: 001a movs r2, r3 + 800370a: 4b7b ldr r3, [pc, #492] @ (80038f8 ) + 800370c: 829a strh r2, [r3, #20] + + // calculate I component + + i_comp += ((int32_t) var.tps_error + 800370e: 4b7a ldr r3, [pc, #488] @ (80038f8 ) + 8003710: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8003712: b21b sxth r3, r3 + 8003714: 0019 movs r1, r3 + * (int32_t) config->motor_fw_i) / 100; + 8003716: 4b79 ldr r3, [pc, #484] @ (80038fc ) + 8003718: 681b ldr r3, [r3, #0] + 800371a: 2284 movs r2, #132 @ 0x84 + 800371c: 5a9b ldrh r3, [r3, r2] + 800371e: b21b sxth r3, r3 + 8003720: 434b muls r3, r1 + 8003722: 2164 movs r1, #100 @ 0x64 + 8003724: 0018 movs r0, r3 + 8003726: f7fc fd79 bl 800021c <__divsi3> + 800372a: 0003 movs r3, r0 + 800372c: 001a movs r2, r3 + i_comp += ((int32_t) var.tps_error + 800372e: 4b77 ldr r3, [pc, #476] @ (800390c ) + 8003730: 681b ldr r3, [r3, #0] + 8003732: 18d2 adds r2, r2, r3 + 8003734: 4b75 ldr r3, [pc, #468] @ (800390c ) + 8003736: 601a str r2, [r3, #0] + if (i_comp > config->i_limmit) + 8003738: 4b70 ldr r3, [pc, #448] @ (80038fc ) + 800373a: 681b ldr r3, [r3, #0] + 800373c: 4a74 ldr r2, [pc, #464] @ (8003910 ) + 800373e: 5a9b ldrh r3, [r3, r2] + 8003740: b21b sxth r3, r3 + 8003742: 001a movs r2, r3 + 8003744: 4b71 ldr r3, [pc, #452] @ (800390c ) + 8003746: 681b ldr r3, [r3, #0] + 8003748: 429a cmp r2, r3 + 800374a: da07 bge.n 800375c + i_comp = config->i_limmit; + 800374c: 4b6b ldr r3, [pc, #428] @ (80038fc ) + 800374e: 681b ldr r3, [r3, #0] + 8003750: 4a6f ldr r2, [pc, #444] @ (8003910 ) + 8003752: 5a9b ldrh r3, [r3, r2] + 8003754: b21b sxth r3, r3 + 8003756: 001a movs r2, r3 + 8003758: 4b6c ldr r3, [pc, #432] @ (800390c ) + 800375a: 601a str r2, [r3, #0] + if (i_comp < (-config->i_limmit)) + 800375c: 4b67 ldr r3, [pc, #412] @ (80038fc ) + 800375e: 681b ldr r3, [r3, #0] + 8003760: 4a6b ldr r2, [pc, #428] @ (8003910 ) + 8003762: 5a9b ldrh r3, [r3, r2] + 8003764: b21b sxth r3, r3 + 8003766: 425a negs r2, r3 + 8003768: 4b68 ldr r3, [pc, #416] @ (800390c ) + 800376a: 681b ldr r3, [r3, #0] + 800376c: 429a cmp r2, r3 + 800376e: dd07 ble.n 8003780 + i_comp = (-config->i_limmit); + 8003770: 4b62 ldr r3, [pc, #392] @ (80038fc ) + 8003772: 681b ldr r3, [r3, #0] + 8003774: 4a66 ldr r2, [pc, #408] @ (8003910 ) + 8003776: 5a9b ldrh r3, [r3, r2] + 8003778: b21b sxth r3, r3 + 800377a: 425a negs r2, r3 + 800377c: 4b63 ldr r3, [pc, #396] @ (800390c ) + 800377e: 601a str r2, [r3, #0] + + // calculate D component + d_comp = (((int32_t) var.tps_error - tps_error_t) + 8003780: 4b5d ldr r3, [pc, #372] @ (80038f8 ) + 8003782: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8003784: b21b sxth r3, r3 + 8003786: 001a movs r2, r3 + 8003788: 4b62 ldr r3, [pc, #392] @ (8003914 ) + 800378a: 681b ldr r3, [r3, #0] + 800378c: 1ad2 subs r2, r2, r3 + * (int32_t) config->motor_fw_d) / 10; + 800378e: 4b5b ldr r3, [pc, #364] @ (80038fc ) + 8003790: 681b ldr r3, [r3, #0] + 8003792: 2186 movs r1, #134 @ 0x86 + 8003794: 5a5b ldrh r3, [r3, r1] + 8003796: b21b sxth r3, r3 + 8003798: 4353 muls r3, r2 + 800379a: 210a movs r1, #10 + 800379c: 0018 movs r0, r3 + 800379e: f7fc fd3d bl 800021c <__divsi3> + 80037a2: 0003 movs r3, r0 + 80037a4: 001a movs r2, r3 + d_comp = (((int32_t) var.tps_error - tps_error_t) + 80037a6: 4b5c ldr r3, [pc, #368] @ (8003918 ) + 80037a8: 601a str r2, [r3, #0] + tps_error_t = var.tps_error; + 80037aa: 4b53 ldr r3, [pc, #332] @ (80038f8 ) + 80037ac: 8c9b ldrh r3, [r3, #36] @ 0x24 + 80037ae: b21b sxth r3, r3 + 80037b0: 001a movs r2, r3 + 80037b2: 4b58 ldr r3, [pc, #352] @ (8003914 ) + 80037b4: 601a str r2, [r3, #0] + + // calculate single shot + //single_shot = var.tps_error * + + // Calculate Idle adder + if (config->idle_input_option == IDLE_OPTION_NO_IDLE_INPUT) + 80037b6: 4b51 ldr r3, [pc, #324] @ (80038fc ) + 80037b8: 681b ldr r3, [r3, #0] + 80037ba: 7edb ldrb r3, [r3, #27] + 80037bc: b2db uxtb r3, r3 + 80037be: 2b00 cmp r3, #0 + 80037c0: d103 bne.n 80037ca + idle_adder = 0; + 80037c2: 4b4c ldr r3, [pc, #304] @ (80038f4 ) + 80037c4: 2200 movs r2, #0 + 80037c6: 601a str r2, [r3, #0] + 80037c8: e045 b.n 8003856 + else if (config->idle_input_option == IDLE_OPTION_MS_CAN) { + 80037ca: 4b4c ldr r3, [pc, #304] @ (80038fc ) + 80037cc: 681b ldr r3, [r3, #0] + 80037ce: 7edb ldrb r3, [r3, #27] + 80037d0: b2db uxtb r3, r3 + 80037d2: 2b03 cmp r3, #3 + 80037d4: d114 bne.n 8003800 + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + 80037d6: 4b48 ldr r3, [pc, #288] @ (80038f8 ) + 80037d8: 8d1b ldrh r3, [r3, #40] @ 0x28 + 80037da: b29b uxth r3, r3 + 80037dc: b218 sxth r0, r3 + (signed short*) config->idle_input_bins, 1, + 80037de: 4b47 ldr r3, [pc, #284] @ (80038fc ) + 80037e0: 681b ldr r3, [r3, #0] + 80037e2: 335c adds r3, #92 @ 0x5c + 80037e4: 001a movs r2, r3 + (signed short*) config->idle_tps_adder_bins); + 80037e6: 4b45 ldr r3, [pc, #276] @ (80038fc ) + 80037e8: 681b ldr r3, [r3, #0] + 80037ea: 336c adds r3, #108 @ 0x6c + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + 80037ec: 9300 str r3, [sp, #0] + 80037ee: 2301 movs r3, #1 + 80037f0: 2108 movs r1, #8 + 80037f2: f000 fb6d bl 8003ed0 + 80037f6: 0003 movs r3, r0 + 80037f8: 001a movs r2, r3 + 80037fa: 4b3e ldr r3, [pc, #248] @ (80038f4 ) + 80037fc: 601a str r2, [r3, #0] + 80037fe: e02a b.n 8003856 + + } else if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) { + 8003800: 4b3e ldr r3, [pc, #248] @ (80038fc ) + 8003802: 681b ldr r3, [r3, #0] + 8003804: 7edb ldrb r3, [r3, #27] + 8003806: b2db uxtb r3, r3 + 8003808: 2b01 cmp r3, #1 + 800380a: d124 bne.n 8003856 + + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + 800380c: 4b3a ldr r3, [pc, #232] @ (80038f8 ) + 800380e: 8d1b ldrh r3, [r3, #40] @ 0x28 + 8003810: b29b uxth r3, r3 + 8003812: b218 sxth r0, r3 + (signed short*) config->idle_input_bins, 1, + 8003814: 4b39 ldr r3, [pc, #228] @ (80038fc ) + 8003816: 681b ldr r3, [r3, #0] + 8003818: 335c adds r3, #92 @ 0x5c + 800381a: 001a movs r2, r3 + (signed short*) config->idle_tps_adder_bins) + 800381c: 4b37 ldr r3, [pc, #220] @ (80038fc ) + 800381e: 681b ldr r3, [r3, #0] + 8003820: 336c adds r3, #108 @ 0x6c + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + 8003822: 9300 str r3, [sp, #0] + 8003824: 2301 movs r3, #1 + 8003826: 2108 movs r1, #8 + 8003828: f000 fb52 bl 8003ed0 + 800382c: 0003 movs r3, r0 + 800382e: 001c movs r4, r3 + - (var.pps / 5); + 8003830: 4b31 ldr r3, [pc, #196] @ (80038f8 ) + 8003832: 8c1b ldrh r3, [r3, #32] + 8003834: b21b sxth r3, r3 + 8003836: 2105 movs r1, #5 + 8003838: 0018 movs r0, r3 + 800383a: f7fc fcef bl 800021c <__divsi3> + 800383e: 0003 movs r3, r0 + 8003840: b21b sxth r3, r3 + 8003842: 1ae2 subs r2, r4, r3 + idle_adder = intrp_1d_ss_table(var.idle_dc, 8, + 8003844: 4b2b ldr r3, [pc, #172] @ (80038f4 ) + 8003846: 601a str r2, [r3, #0] + if (idle_adder < 0) { + 8003848: 4b2a ldr r3, [pc, #168] @ (80038f4 ) + 800384a: 681b ldr r3, [r3, #0] + 800384c: 2b00 cmp r3, #0 + 800384e: da02 bge.n 8003856 + idle_adder = 0; + 8003850: 4b28 ldr r3, [pc, #160] @ (80038f4 ) + 8003852: 2200 movs r2, #0 + 8003854: 601a str r2, [r3, #0] + } + + } + } + + pwm_output = p_comp + i_comp + d_comp + spring_preload; + 8003856: 4b2a ldr r3, [pc, #168] @ (8003900 ) + 8003858: 681a ldr r2, [r3, #0] + 800385a: 4b2c ldr r3, [pc, #176] @ (800390c ) + 800385c: 681b ldr r3, [r3, #0] + 800385e: 18d2 adds r2, r2, r3 + 8003860: 4b2d ldr r3, [pc, #180] @ (8003918 ) + 8003862: 681b ldr r3, [r3, #0] + 8003864: 18d2 adds r2, r2, r3 + 8003866: 4b27 ldr r3, [pc, #156] @ (8003904 ) + 8003868: 681b ldr r3, [r3, #0] + 800386a: 18d3 adds r3, r2, r3 + 800386c: 607b str r3, [r7, #4] + + vbat_corr = (int16_t) (((int32_t) var.motor_pwm) * vbat_corr / 1000); + 800386e: 4b22 ldr r3, [pc, #136] @ (80038f8 ) + 8003870: 8cdb ldrh r3, [r3, #38] @ 0x26 + 8003872: b21b sxth r3, r3 + 8003874: 001a movs r2, r3 + 8003876: 4b29 ldr r3, [pc, #164] @ (800391c ) + 8003878: 681b ldr r3, [r3, #0] + 800387a: 4353 muls r3, r2 + 800387c: 22fa movs r2, #250 @ 0xfa + 800387e: 0091 lsls r1, r2, #2 + 8003880: 0018 movs r0, r3 + 8003882: f7fc fccb bl 800021c <__divsi3> + 8003886: 0003 movs r3, r0 + 8003888: b21b sxth r3, r3 + 800388a: 001a movs r2, r3 + 800388c: 4b23 ldr r3, [pc, #140] @ (800391c ) + 800388e: 601a str r2, [r3, #0] + + pwm_output += pct; + 8003890: 687a ldr r2, [r7, #4] + 8003892: 683b ldr r3, [r7, #0] + 8003894: 18d3 adds r3, r2, r3 + 8003896: 607b str r3, [r7, #4] + + //limmit pwm + if (pwm_output > config->motor_dc_max) + 8003898: 4b18 ldr r3, [pc, #96] @ (80038fc ) + 800389a: 681a ldr r2, [r3, #0] + 800389c: 23b4 movs r3, #180 @ 0xb4 + 800389e: 009b lsls r3, r3, #2 + 80038a0: 5ad3 ldrh r3, [r2, r3] + 80038a2: b21b sxth r3, r3 + 80038a4: 001a movs r2, r3 + 80038a6: 687b ldr r3, [r7, #4] + 80038a8: 4293 cmp r3, r2 + 80038aa: dd06 ble.n 80038ba + pwm_output = config->motor_dc_max; + 80038ac: 4b13 ldr r3, [pc, #76] @ (80038fc ) + 80038ae: 681a ldr r2, [r3, #0] + 80038b0: 23b4 movs r3, #180 @ 0xb4 + 80038b2: 009b lsls r3, r3, #2 + 80038b4: 5ad3 ldrh r3, [r2, r3] + 80038b6: b21b sxth r3, r3 + 80038b8: 607b str r3, [r7, #4] + if (pwm_output < config->motor_dc_min) + 80038ba: 4b10 ldr r3, [pc, #64] @ (80038fc ) + 80038bc: 681b ldr r3, [r3, #0] + 80038be: 4a18 ldr r2, [pc, #96] @ (8003920 ) + 80038c0: 5a9b ldrh r3, [r3, r2] + 80038c2: b21b sxth r3, r3 + 80038c4: 001a movs r2, r3 + 80038c6: 687b ldr r3, [r7, #4] + 80038c8: 4293 cmp r3, r2 + 80038ca: da05 bge.n 80038d8 + pwm_output = config->motor_dc_min; + 80038cc: 4b0b ldr r3, [pc, #44] @ (80038fc ) + 80038ce: 681b ldr r3, [r3, #0] + 80038d0: 4a13 ldr r2, [pc, #76] @ (8003920 ) + 80038d2: 5a9b ldrh r3, [r3, r2] + 80038d4: b21b sxth r3, r3 + 80038d6: 607b str r3, [r7, #4] + + //apply pwm + DBW_Pwm_Set_Duty((signed short) (pwm_output), (pwm_t*) &ttl1_pwm); + 80038d8: 687b ldr r3, [r7, #4] + 80038da: b21b sxth r3, r3 + 80038dc: 001a movs r2, r3 + 80038de: 4b11 ldr r3, [pc, #68] @ (8003924 ) + 80038e0: 0019 movs r1, r3 + 80038e2: 0010 movs r0, r2 + 80038e4: f000 fa1c bl 8003d20 + + } + + return 0; + 80038e8: 2300 movs r3, #0 +} + 80038ea: 0018 movs r0, r3 + 80038ec: 46bd mov sp, r7 + 80038ee: b003 add sp, #12 + 80038f0: bd90 pop {r4, r7, pc} + 80038f2: 46c0 nop @ (mov r8, r8) + 80038f4: 20000a40 .word 0x20000a40 + 80038f8: 20000998 .word 0x20000998 + 80038fc: 200009cc .word 0x200009cc + 8003900: 20000a28 .word 0x20000a28 + 8003904: 20000a3c .word 0x20000a3c + 8003908: 20000a1e .word 0x20000a1e + 800390c: 20000a2c .word 0x20000a2c + 8003910: 000002ce .word 0x000002ce + 8003914: 20000a34 .word 0x20000a34 + 8003918: 20000a30 .word 0x20000a30 + 800391c: 20000a20 .word 0x20000a20 + 8003920: 000002d2 .word 0x000002d2 + 8003924: 200009d4 .word 0x200009d4 + +08003928 : + +void DBW_Pwm_Init(void) { + 8003928: b580 push {r7, lr} + 800392a: af00 add r7, sp, #0 + +// Setup PWM ports + ttl1_pwm.pos_port = GPIOB; + 800392c: 4b4e ldr r3, [pc, #312] @ (8003a68 ) + 800392e: 4a4f ldr r2, [pc, #316] @ (8003a6c ) + 8003930: 605a str r2, [r3, #4] + ttl1_pwm.pos_pin = 10; + 8003932: 4b4d ldr r3, [pc, #308] @ (8003a68 ) + 8003934: 220a movs r2, #10 + 8003936: 811a strh r2, [r3, #8] + + ttl1_pwm.neg_port = GPIOB; + 8003938: 4b4b ldr r3, [pc, #300] @ (8003a68 ) + 800393a: 4a4c ldr r2, [pc, #304] @ (8003a6c ) + 800393c: 60da str r2, [r3, #12] + ttl1_pwm.neg_pin = 11; + 800393e: 4b4a ldr r3, [pc, #296] @ (8003a68 ) + 8003940: 220b movs r2, #11 + 8003942: 821a strh r2, [r3, #16] + +// setup pwm status default -> no drive + ttl1_pwm.status = PWM_STATUS_DEFAULT; + 8003944: 4b48 ldr r3, [pc, #288] @ (8003a68 ) + 8003946: 2200 movs r2, #0 + 8003948: 701a strb r2, [r3, #0] + +// calculate how many tick are in given freq period + ttl1_pwm.period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq; + 800394a: 4b49 ldr r3, [pc, #292] @ (8003a70 ) + 800394c: 681b ldr r3, [r3, #0] + 800394e: 227c movs r2, #124 @ 0x7c + 8003950: 5a9b ldrh r3, [r3, r2] + 8003952: b29b uxth r3, r3 + 8003954: 0019 movs r1, r3 + 8003956: 4847 ldr r0, [pc, #284] @ (8003a74 ) + 8003958: f7fc fbd6 bl 8000108 <__udivsi3> + 800395c: 0003 movs r3, r0 + 800395e: 001a movs r2, r3 + 8003960: 4b41 ldr r3, [pc, #260] @ (8003a68 ) + 8003962: 615a str r2, [r3, #20] + +// set initian pwm from current settings + ttl1_pwm.pwm = var.motor_pwm; + 8003964: 4b44 ldr r3, [pc, #272] @ (8003a78 ) + 8003966: 8cdb ldrh r3, [r3, #38] @ 0x26 + 8003968: b21b sxth r3, r3 + 800396a: 001a movs r2, r3 + 800396c: 4b3e ldr r3, [pc, #248] @ (8003a68 ) + 800396e: 61da str r2, [r3, #28] + ttl1_pwm.pwm_t = var.motor_pwm; + 8003970: 4b41 ldr r3, [pc, #260] @ (8003a78 ) + 8003972: 8cdb ldrh r3, [r3, #38] @ 0x26 + 8003974: b21b sxth r3, r3 + 8003976: 001a movs r2, r3 + 8003978: 4b3b ldr r3, [pc, #236] @ (8003a68 ) + 800397a: 621a str r2, [r3, #32] + ttl1_pwm.single_pulse = 0; + 800397c: 4b3a ldr r3, [pc, #232] @ (8003a68 ) + 800397e: 2200 movs r2, #0 + 8003980: 625a str r2, [r3, #36] @ 0x24 + + //tmp = (float)ttl1_pwm.period_ticks * (float)ttl1_pwm.pwm/10000.0F; + //ttl1_pwm.duty_ticks = (unsigned int) tmp; + + DBW_Pwm_Set_Duty(var.motor_pwm, (pwm_t*) &ttl1_pwm); + 8003982: 4b3d ldr r3, [pc, #244] @ (8003a78 ) + 8003984: 8cdb ldrh r3, [r3, #38] @ 0x26 + 8003986: b21b sxth r3, r3 + 8003988: 001a movs r2, r3 + 800398a: 4b37 ldr r3, [pc, #220] @ (8003a68 ) + 800398c: 0019 movs r1, r3 + 800398e: 0010 movs r0, r2 + 8003990: f000 f9c6 bl 8003d20 + + if (var.motor_pwm < 0) + 8003994: 4b38 ldr r3, [pc, #224] @ (8003a78 ) + 8003996: 8cdb ldrh r3, [r3, #38] @ 0x26 + 8003998: b21b sxth r3, r3 + 800399a: 2b00 cmp r3, #0 + 800399c: da03 bge.n 80039a6 + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + 800399e: 4b32 ldr r3, [pc, #200] @ (8003a68 ) + 80039a0: 2202 movs r2, #2 + 80039a2: 705a strb r2, [r3, #1] + 80039a4: e00b b.n 80039be + else if (var.motor_pwm > 0) + 80039a6: 4b34 ldr r3, [pc, #208] @ (8003a78 ) + 80039a8: 8cdb ldrh r3, [r3, #38] @ 0x26 + 80039aa: b21b sxth r3, r3 + 80039ac: 2b00 cmp r3, #0 + 80039ae: dd03 ble.n 80039b8 + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + 80039b0: 4b2d ldr r3, [pc, #180] @ (8003a68 ) + 80039b2: 2200 movs r2, #0 + 80039b4: 705a strb r2, [r3, #1] + 80039b6: e002 b.n 80039be + else + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + 80039b8: 4b2b ldr r3, [pc, #172] @ (8003a68 ) + 80039ba: 2200 movs r2, #0 + 80039bc: 705a strb r2, [r3, #1] + + ttl1_pwm.status = PWM_STATUS_IDLE; + 80039be: 4b2a ldr r3, [pc, #168] @ (8003a68 ) + 80039c0: 2201 movs r2, #1 + 80039c2: 701a strb r2, [r3, #0] + + DBW_Stop(); + 80039c4: f000 fb3c bl 8004040 + + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 80039c8: 4b27 ldr r3, [pc, #156] @ (8003a68 ) + 80039ca: 891b ldrh r3, [r3, #8] + 80039cc: b29b uxth r3, r3 + 80039ce: 3310 adds r3, #16 + 80039d0: 2201 movs r2, #1 + 80039d2: 409a lsls r2, r3 + 80039d4: 4b24 ldr r3, [pc, #144] @ (8003a68 ) + 80039d6: 685b ldr r3, [r3, #4] + 80039d8: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 80039da: 4b23 ldr r3, [pc, #140] @ (8003a68 ) + 80039dc: 8a1b ldrh r3, [r3, #16] + 80039de: b29b uxth r3, r3 + 80039e0: 3310 adds r3, #16 + 80039e2: 2201 movs r2, #1 + 80039e4: 409a lsls r2, r3 + 80039e6: 4b20 ldr r3, [pc, #128] @ (8003a68 ) + 80039e8: 68db ldr r3, [r3, #12] + 80039ea: 619a str r2, [r3, #24] + +// configure TIM2 to 1uS / tick timer +// setup CCR interrupt happen after sturtup delay is over + + RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; + 80039ec: 4b23 ldr r3, [pc, #140] @ (8003a7c ) + 80039ee: 69da ldr r2, [r3, #28] + 80039f0: 4b22 ldr r3, [pc, #136] @ (8003a7c ) + 80039f2: 2101 movs r1, #1 + 80039f4: 430a orrs r2, r1 + 80039f6: 61da str r2, [r3, #28] + TIM2->CNT = 0xFFFFFFFE; + 80039f8: 2380 movs r3, #128 @ 0x80 + 80039fa: 05db lsls r3, r3, #23 + 80039fc: 2202 movs r2, #2 + 80039fe: 4252 negs r2, r2 + 8003a00: 625a str r2, [r3, #36] @ 0x24 + TIM2->PSC = 48; //2400; // (1uS precision) + 8003a02: 2380 movs r3, #128 @ 0x80 + 8003a04: 05db lsls r3, r3, #23 + 8003a06: 2230 movs r2, #48 @ 0x30 + 8003a08: 629a str r2, [r3, #40] @ 0x28 + + TIM2->ARR = 0xFFFFFFFF; + 8003a0a: 2380 movs r3, #128 @ 0x80 + 8003a0c: 05db lsls r3, r3, #23 + 8003a0e: 2201 movs r2, #1 + 8003a10: 4252 negs r2, r2 + 8003a12: 62da str r2, [r3, #44] @ 0x2c + + TIM2->CR1 = (TIM_CR1_URS | TIM_CR1_CEN); + 8003a14: 2380 movs r3, #128 @ 0x80 + 8003a16: 05db lsls r3, r3, #23 + 8003a18: 2205 movs r2, #5 + 8003a1a: 601a str r2, [r3, #0] + TIM2->CCER = 0x0000; + 8003a1c: 2380 movs r3, #128 @ 0x80 + 8003a1e: 05db lsls r3, r3, #23 + 8003a20: 2200 movs r2, #0 + 8003a22: 621a str r2, [r3, #32] + TIM2->CCMR1 = 0x0000; + 8003a24: 2380 movs r3, #128 @ 0x80 + 8003a26: 05db lsls r3, r3, #23 + 8003a28: 2200 movs r2, #0 + 8003a2a: 619a str r2, [r3, #24] + + TIM2->CCR1 = (unsigned int) 20000; // startup delay + 8003a2c: 2380 movs r3, #128 @ 0x80 + 8003a2e: 05db lsls r3, r3, #23 + 8003a30: 4a13 ldr r2, [pc, #76] @ (8003a80 ) + 8003a32: 635a str r2, [r3, #52] @ 0x34 + TIM2->CCR2 = 0; + 8003a34: 2380 movs r3, #128 @ 0x80 + 8003a36: 05db lsls r3, r3, #23 + 8003a38: 2200 movs r2, #0 + 8003a3a: 639a str r2, [r3, #56] @ 0x38 + TIM2->SR &= ~TIM_SR_CC1IF; + 8003a3c: 2380 movs r3, #128 @ 0x80 + 8003a3e: 05db lsls r3, r3, #23 + 8003a40: 691a ldr r2, [r3, #16] + 8003a42: 2380 movs r3, #128 @ 0x80 + 8003a44: 05db lsls r3, r3, #23 + 8003a46: 2102 movs r1, #2 + 8003a48: 438a bics r2, r1 + 8003a4a: 611a str r2, [r3, #16] + TIM2->DIER |= TIM_DIER_CC1IE; + 8003a4c: 2380 movs r3, #128 @ 0x80 + 8003a4e: 05db lsls r3, r3, #23 + 8003a50: 68da ldr r2, [r3, #12] + 8003a52: 2380 movs r3, #128 @ 0x80 + 8003a54: 05db lsls r3, r3, #23 + 8003a56: 2102 movs r1, #2 + 8003a58: 430a orrs r2, r1 + 8003a5a: 60da str r2, [r3, #12] + NVIC_EnableIRQ(TIM2_IRQn); + 8003a5c: 200f movs r0, #15 + 8003a5e: f7ff fab1 bl 8002fc4 <__NVIC_EnableIRQ> + +} + 8003a62: 46c0 nop @ (mov r8, r8) + 8003a64: 46bd mov sp, r7 + 8003a66: bd80 pop {r7, pc} + 8003a68: 200009d4 .word 0x200009d4 + 8003a6c: 48000400 .word 0x48000400 + 8003a70: 200009cc .word 0x200009cc + 8003a74: 000f4240 .word 0x000f4240 + 8003a78: 20000998 .word 0x20000998 + 8003a7c: 40021000 .word 0x40021000 + 8003a80: 00004e20 .word 0x00004e20 + +08003a84 : + +void TIM2_IRQHandler(void) { + 8003a84: b580 push {r7, lr} + 8003a86: af00 add r7, sp, #0 + if (TIM2->SR & TIM_SR_CC1IF) { + 8003a88: 2380 movs r3, #128 @ 0x80 + 8003a8a: 05db lsls r3, r3, #23 + 8003a8c: 691b ldr r3, [r3, #16] + 8003a8e: 2202 movs r2, #2 + 8003a90: 4013 ands r3, r2 + 8003a92: d100 bne.n 8003a96 + 8003a94: e12f b.n 8003cf6 + // capture compare intrrupt + TIM2->SR &= ~TIM_SR_CC1IF; + 8003a96: 2380 movs r3, #128 @ 0x80 + 8003a98: 05db lsls r3, r3, #23 + 8003a9a: 691a ldr r2, [r3, #16] + 8003a9c: 2380 movs r3, #128 @ 0x80 + 8003a9e: 05db lsls r3, r3, #23 + 8003aa0: 2102 movs r1, #2 + 8003aa2: 438a bics r2, r1 + 8003aa4: 611a str r2, [r3, #16] + if (ttl1_pwm.status == PWM_STATUS_DEFAULT) { + 8003aa6: 4b9c ldr r3, [pc, #624] @ (8003d18 ) + 8003aa8: 781b ldrb r3, [r3, #0] + 8003aaa: b2db uxtb r3, r3 + 8003aac: 2b00 cmp r3, #0 + 8003aae: d102 bne.n 8003ab6 + // here ends startup delay + // enable drive here + ttl1_pwm.status = PWM_STATUS_STARTED; + 8003ab0: 4b99 ldr r3, [pc, #612] @ (8003d18 ) + 8003ab2: 2202 movs r2, #2 + 8003ab4: 701a strb r2, [r3, #0] + } + + //Set duty + if (ttl1_pwm.pwm > 0) { + 8003ab6: 4b98 ldr r3, [pc, #608] @ (8003d18 ) + 8003ab8: 69db ldr r3, [r3, #28] + 8003aba: 2b00 cmp r3, #0 + 8003abc: dc00 bgt.n 8003ac0 + 8003abe: e072 b.n 8003ba6 + // pwm > 0 + if ((ttl1_pwm.pwm > 0) && (ttl1_pwm.pwm_t < 0)) { + 8003ac0: 4b95 ldr r3, [pc, #596] @ (8003d18 ) + 8003ac2: 69db ldr r3, [r3, #28] + 8003ac4: 2b00 cmp r3, #0 + 8003ac6: dd27 ble.n 8003b18 + 8003ac8: 4b93 ldr r3, [pc, #588] @ (8003d18 ) + 8003aca: 6a1b ldr r3, [r3, #32] + 8003acc: 2b00 cmp r3, #0 + 8003ace: da23 bge.n 8003b18 + // if changeing PWM polarity insert dead time + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + 8003ad0: 4b91 ldr r3, [pc, #580] @ (8003d18 ) + 8003ad2: 2200 movs r2, #0 + 8003ad4: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003ad6: 4b90 ldr r3, [pc, #576] @ (8003d18 ) + 8003ad8: 891b ldrh r3, [r3, #8] + 8003ada: b29b uxth r3, r3 + 8003adc: 3310 adds r3, #16 + 8003ade: 2201 movs r2, #1 + 8003ae0: 409a lsls r2, r3 + 8003ae2: 4b8d ldr r3, [pc, #564] @ (8003d18 ) + 8003ae4: 685b ldr r3, [r3, #4] + 8003ae6: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003ae8: 4b8b ldr r3, [pc, #556] @ (8003d18 ) + 8003aea: 8a1b ldrh r3, [r3, #16] + 8003aec: b29b uxth r3, r3 + 8003aee: 3310 adds r3, #16 + 8003af0: 2201 movs r2, #1 + 8003af2: 409a lsls r2, r3 + 8003af4: 4b88 ldr r3, [pc, #544] @ (8003d18 ) + 8003af6: 68db ldr r3, [r3, #12] + 8003af8: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime; + 8003afa: 2380 movs r3, #128 @ 0x80 + 8003afc: 05db lsls r3, r3, #23 + 8003afe: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003b00: 4b86 ldr r3, [pc, #536] @ (8003d1c ) + 8003b02: 6819 ldr r1, [r3, #0] + 8003b04: 23cd movs r3, #205 @ 0xcd + 8003b06: 009b lsls r3, r3, #2 + 8003b08: 5acb ldrh r3, [r1, r3] + 8003b0a: b29b uxth r3, r3 + 8003b0c: 0019 movs r1, r3 + 8003b0e: 2380 movs r3, #128 @ 0x80 + 8003b10: 05db lsls r3, r3, #23 + 8003b12: 1852 adds r2, r2, r1 + 8003b14: 635a str r2, [r3, #52] @ 0x34 + 8003b16: e0ea b.n 8003cee + } else if (ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) { + 8003b18: 4b7f ldr r3, [pc, #508] @ (8003d18 ) + 8003b1a: 785b ldrb r3, [r3, #1] + 8003b1c: b2db uxtb r3, r3 + 8003b1e: 2b00 cmp r3, #0 + 8003b20: d11f bne.n 8003b62 + ttl1_pwm.state = PWM_STATE_POSITIVE_ACTIVE; + 8003b22: 4b7d ldr r3, [pc, #500] @ (8003d18 ) + 8003b24: 2201 movs r2, #1 + 8003b26: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << ttl1_pwm.pos_pin); + 8003b28: 4b7b ldr r3, [pc, #492] @ (8003d18 ) + 8003b2a: 891b ldrh r3, [r3, #8] + 8003b2c: b29b uxth r3, r3 + 8003b2e: 001a movs r2, r3 + 8003b30: 2301 movs r3, #1 + 8003b32: 4093 lsls r3, r2 + 8003b34: 001a movs r2, r3 + 8003b36: 4b78 ldr r3, [pc, #480] @ (8003d18 ) + 8003b38: 685b ldr r3, [r3, #4] + 8003b3a: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003b3c: 4b76 ldr r3, [pc, #472] @ (8003d18 ) + 8003b3e: 8a1b ldrh r3, [r3, #16] + 8003b40: b29b uxth r3, r3 + 8003b42: 3310 adds r3, #16 + 8003b44: 2201 movs r2, #1 + 8003b46: 409a lsls r2, r3 + 8003b48: 4b73 ldr r3, [pc, #460] @ (8003d18 ) + 8003b4a: 68db ldr r3, [r3, #12] + 8003b4c: 619a str r2, [r3, #24] + + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks; + 8003b4e: 2380 movs r3, #128 @ 0x80 + 8003b50: 05db lsls r3, r3, #23 + 8003b52: 6a59 ldr r1, [r3, #36] @ 0x24 + 8003b54: 4b70 ldr r3, [pc, #448] @ (8003d18 ) + 8003b56: 699a ldr r2, [r3, #24] + 8003b58: 2380 movs r3, #128 @ 0x80 + 8003b5a: 05db lsls r3, r3, #23 + 8003b5c: 188a adds r2, r1, r2 + 8003b5e: 635a str r2, [r3, #52] @ 0x34 + 8003b60: e0c5 b.n 8003cee + } else { + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + 8003b62: 4b6d ldr r3, [pc, #436] @ (8003d18 ) + 8003b64: 2200 movs r2, #0 + 8003b66: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003b68: 4b6b ldr r3, [pc, #428] @ (8003d18 ) + 8003b6a: 891b ldrh r3, [r3, #8] + 8003b6c: b29b uxth r3, r3 + 8003b6e: 3310 adds r3, #16 + 8003b70: 2201 movs r2, #1 + 8003b72: 409a lsls r2, r3 + 8003b74: 4b68 ldr r3, [pc, #416] @ (8003d18 ) + 8003b76: 685b ldr r3, [r3, #4] + 8003b78: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003b7a: 4b67 ldr r3, [pc, #412] @ (8003d18 ) + 8003b7c: 8a1b ldrh r3, [r3, #16] + 8003b7e: b29b uxth r3, r3 + 8003b80: 3310 adds r3, #16 + 8003b82: 2201 movs r2, #1 + 8003b84: 409a lsls r2, r3 + 8003b86: 4b64 ldr r3, [pc, #400] @ (8003d18 ) + 8003b88: 68db ldr r3, [r3, #12] + 8003b8a: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + 8003b8c: 2380 movs r3, #128 @ 0x80 + 8003b8e: 05db lsls r3, r3, #23 + 8003b90: 6a59 ldr r1, [r3, #36] @ 0x24 + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + 8003b92: 4b61 ldr r3, [pc, #388] @ (8003d18 ) + 8003b94: 695a ldr r2, [r3, #20] + 8003b96: 4b60 ldr r3, [pc, #384] @ (8003d18 ) + 8003b98: 699b ldr r3, [r3, #24] + 8003b9a: 1ad2 subs r2, r2, r3 + TIM2->CCR1 = TIM2->CNT + 8003b9c: 2380 movs r3, #128 @ 0x80 + 8003b9e: 05db lsls r3, r3, #23 + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + 8003ba0: 188a adds r2, r1, r2 + TIM2->CCR1 = TIM2->CNT + 8003ba2: 635a str r2, [r3, #52] @ 0x34 + 8003ba4: e0a3 b.n 8003cee + + } + } else if (ttl1_pwm.pwm < 0) { + 8003ba6: 4b5c ldr r3, [pc, #368] @ (8003d18 ) + 8003ba8: 69db ldr r3, [r3, #28] + 8003baa: 2b00 cmp r3, #0 + 8003bac: db00 blt.n 8003bb0 + 8003bae: e072 b.n 8003c96 + //pwm < 0 + //if((ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) && (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE)) + if ((ttl1_pwm.pwm < 0) && (ttl1_pwm.pwm_t > 0)) { + 8003bb0: 4b59 ldr r3, [pc, #356] @ (8003d18 ) + 8003bb2: 69db ldr r3, [r3, #28] + 8003bb4: 2b00 cmp r3, #0 + 8003bb6: da27 bge.n 8003c08 + 8003bb8: 4b57 ldr r3, [pc, #348] @ (8003d18 ) + 8003bba: 6a1b ldr r3, [r3, #32] + 8003bbc: 2b00 cmp r3, #0 + 8003bbe: dd23 ble.n 8003c08 + // if changeing PWM polarity insert dead time + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + 8003bc0: 4b55 ldr r3, [pc, #340] @ (8003d18 ) + 8003bc2: 2202 movs r2, #2 + 8003bc4: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003bc6: 4b54 ldr r3, [pc, #336] @ (8003d18 ) + 8003bc8: 891b ldrh r3, [r3, #8] + 8003bca: b29b uxth r3, r3 + 8003bcc: 3310 adds r3, #16 + 8003bce: 2201 movs r2, #1 + 8003bd0: 409a lsls r2, r3 + 8003bd2: 4b51 ldr r3, [pc, #324] @ (8003d18 ) + 8003bd4: 685b ldr r3, [r3, #4] + 8003bd6: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003bd8: 4b4f ldr r3, [pc, #316] @ (8003d18 ) + 8003bda: 8a1b ldrh r3, [r3, #16] + 8003bdc: b29b uxth r3, r3 + 8003bde: 3310 adds r3, #16 + 8003be0: 2201 movs r2, #1 + 8003be2: 409a lsls r2, r3 + 8003be4: 4b4c ldr r3, [pc, #304] @ (8003d18 ) + 8003be6: 68db ldr r3, [r3, #12] + 8003be8: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + config->pwm_deadtime; + 8003bea: 2380 movs r3, #128 @ 0x80 + 8003bec: 05db lsls r3, r3, #23 + 8003bee: 6a5a ldr r2, [r3, #36] @ 0x24 + 8003bf0: 4b4a ldr r3, [pc, #296] @ (8003d1c ) + 8003bf2: 6819 ldr r1, [r3, #0] + 8003bf4: 23cd movs r3, #205 @ 0xcd + 8003bf6: 009b lsls r3, r3, #2 + 8003bf8: 5acb ldrh r3, [r1, r3] + 8003bfa: b29b uxth r3, r3 + 8003bfc: 0019 movs r1, r3 + 8003bfe: 2380 movs r3, #128 @ 0x80 + 8003c00: 05db lsls r3, r3, #23 + 8003c02: 1852 adds r2, r2, r1 + 8003c04: 635a str r2, [r3, #52] @ 0x34 + 8003c06: e072 b.n 8003cee + } else if (ttl1_pwm.state == PWM_STATE_NEGATIVE_INACTIVE) { + 8003c08: 4b43 ldr r3, [pc, #268] @ (8003d18 ) + 8003c0a: 785b ldrb r3, [r3, #1] + 8003c0c: b2db uxtb r3, r3 + 8003c0e: 2b02 cmp r3, #2 + 8003c10: d11f bne.n 8003c52 + ttl1_pwm.state = PWM_STATE_NEGATIVE_ACTIVE; + 8003c12: 4b41 ldr r3, [pc, #260] @ (8003d18 ) + 8003c14: 2203 movs r2, #3 + 8003c16: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003c18: 4b3f ldr r3, [pc, #252] @ (8003d18 ) + 8003c1a: 891b ldrh r3, [r3, #8] + 8003c1c: b29b uxth r3, r3 + 8003c1e: 3310 adds r3, #16 + 8003c20: 2201 movs r2, #1 + 8003c22: 409a lsls r2, r3 + 8003c24: 4b3c ldr r3, [pc, #240] @ (8003d18 ) + 8003c26: 685b ldr r3, [r3, #4] + 8003c28: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << ttl1_pwm.neg_pin); + 8003c2a: 4b3b ldr r3, [pc, #236] @ (8003d18 ) + 8003c2c: 8a1b ldrh r3, [r3, #16] + 8003c2e: b29b uxth r3, r3 + 8003c30: 001a movs r2, r3 + 8003c32: 2301 movs r3, #1 + 8003c34: 4093 lsls r3, r2 + 8003c36: 001a movs r2, r3 + 8003c38: 4b37 ldr r3, [pc, #220] @ (8003d18 ) + 8003c3a: 68db ldr r3, [r3, #12] + 8003c3c: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.duty_ticks; + 8003c3e: 2380 movs r3, #128 @ 0x80 + 8003c40: 05db lsls r3, r3, #23 + 8003c42: 6a59 ldr r1, [r3, #36] @ 0x24 + 8003c44: 4b34 ldr r3, [pc, #208] @ (8003d18 ) + 8003c46: 699a ldr r2, [r3, #24] + 8003c48: 2380 movs r3, #128 @ 0x80 + 8003c4a: 05db lsls r3, r3, #23 + 8003c4c: 188a adds r2, r1, r2 + 8003c4e: 635a str r2, [r3, #52] @ 0x34 + 8003c50: e04d b.n 8003cee + } else { + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + 8003c52: 4b31 ldr r3, [pc, #196] @ (8003d18 ) + 8003c54: 2202 movs r2, #2 + 8003c56: 705a strb r2, [r3, #1] + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003c58: 4b2f ldr r3, [pc, #188] @ (8003d18 ) + 8003c5a: 891b ldrh r3, [r3, #8] + 8003c5c: b29b uxth r3, r3 + 8003c5e: 3310 adds r3, #16 + 8003c60: 2201 movs r2, #1 + 8003c62: 409a lsls r2, r3 + 8003c64: 4b2c ldr r3, [pc, #176] @ (8003d18 ) + 8003c66: 685b ldr r3, [r3, #4] + 8003c68: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003c6a: 4b2b ldr r3, [pc, #172] @ (8003d18 ) + 8003c6c: 8a1b ldrh r3, [r3, #16] + 8003c6e: b29b uxth r3, r3 + 8003c70: 3310 adds r3, #16 + 8003c72: 2201 movs r2, #1 + 8003c74: 409a lsls r2, r3 + 8003c76: 4b28 ldr r3, [pc, #160] @ (8003d18 ) + 8003c78: 68db ldr r3, [r3, #12] + 8003c7a: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + 8003c7c: 2380 movs r3, #128 @ 0x80 + 8003c7e: 05db lsls r3, r3, #23 + 8003c80: 6a59 ldr r1, [r3, #36] @ 0x24 + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + 8003c82: 4b25 ldr r3, [pc, #148] @ (8003d18 ) + 8003c84: 695a ldr r2, [r3, #20] + 8003c86: 4b24 ldr r3, [pc, #144] @ (8003d18 ) + 8003c88: 699b ldr r3, [r3, #24] + 8003c8a: 1ad2 subs r2, r2, r3 + TIM2->CCR1 = TIM2->CNT + 8003c8c: 2380 movs r3, #128 @ 0x80 + 8003c8e: 05db lsls r3, r3, #23 + + (ttl1_pwm.period_ticks - ttl1_pwm.duty_ticks); + 8003c90: 188a adds r2, r1, r2 + TIM2->CCR1 = TIM2->CNT + 8003c92: 635a str r2, [r3, #52] @ 0x34 + 8003c94: e02b b.n 8003cee + } + } else { + // if pwm == 0 + ttl1_pwm.pos_port->BSRR = (1 << (16 + ttl1_pwm.pos_pin)); + 8003c96: 4b20 ldr r3, [pc, #128] @ (8003d18 ) + 8003c98: 891b ldrh r3, [r3, #8] + 8003c9a: b29b uxth r3, r3 + 8003c9c: 3310 adds r3, #16 + 8003c9e: 2201 movs r2, #1 + 8003ca0: 409a lsls r2, r3 + 8003ca2: 4b1d ldr r3, [pc, #116] @ (8003d18 ) + 8003ca4: 685b ldr r3, [r3, #4] + 8003ca6: 619a str r2, [r3, #24] + ttl1_pwm.neg_port->BSRR = (1 << (16 + ttl1_pwm.neg_pin)); + 8003ca8: 4b1b ldr r3, [pc, #108] @ (8003d18 ) + 8003caa: 8a1b ldrh r3, [r3, #16] + 8003cac: b29b uxth r3, r3 + 8003cae: 3310 adds r3, #16 + 8003cb0: 2201 movs r2, #1 + 8003cb2: 409a lsls r2, r3 + 8003cb4: 4b18 ldr r3, [pc, #96] @ (8003d18 ) + 8003cb6: 68db ldr r3, [r3, #12] + 8003cb8: 619a str r2, [r3, #24] + TIM2->CCR1 = TIM2->CNT + ttl1_pwm.period_ticks; + 8003cba: 2380 movs r3, #128 @ 0x80 + 8003cbc: 05db lsls r3, r3, #23 + 8003cbe: 6a59 ldr r1, [r3, #36] @ 0x24 + 8003cc0: 4b15 ldr r3, [pc, #84] @ (8003d18 ) + 8003cc2: 695a ldr r2, [r3, #20] + 8003cc4: 2380 movs r3, #128 @ 0x80 + 8003cc6: 05db lsls r3, r3, #23 + 8003cc8: 188a adds r2, r1, r2 + 8003cca: 635a str r2, [r3, #52] @ 0x34 + if (ttl1_pwm.state == PWM_STATE_POSITIVE_ACTIVE + 8003ccc: 4b12 ldr r3, [pc, #72] @ (8003d18 ) + 8003cce: 785b ldrb r3, [r3, #1] + 8003cd0: b2db uxtb r3, r3 + 8003cd2: 2b01 cmp r3, #1 + 8003cd4: d004 beq.n 8003ce0 + || ttl1_pwm.state == PWM_STATE_POSITIVE_INACTIVE) { + 8003cd6: 4b10 ldr r3, [pc, #64] @ (8003d18 ) + 8003cd8: 785b ldrb r3, [r3, #1] + 8003cda: b2db uxtb r3, r3 + 8003cdc: 2b00 cmp r3, #0 + 8003cde: d103 bne.n 8003ce8 + ttl1_pwm.state = PWM_STATE_POSITIVE_INACTIVE; + 8003ce0: 4b0d ldr r3, [pc, #52] @ (8003d18 ) + 8003ce2: 2200 movs r2, #0 + 8003ce4: 705a strb r2, [r3, #1] + 8003ce6: e002 b.n 8003cee + } else { + ttl1_pwm.state = PWM_STATE_NEGATIVE_INACTIVE; + 8003ce8: 4b0b ldr r3, [pc, #44] @ (8003d18 ) + 8003cea: 2202 movs r2, #2 + 8003cec: 705a strb r2, [r3, #1] + } + + } + // store new pwm value as old pwm value for the nex iteration + ttl1_pwm.pwm_t = ttl1_pwm.pwm; + 8003cee: 4b0a ldr r3, [pc, #40] @ (8003d18 ) + 8003cf0: 69da ldr r2, [r3, #28] + 8003cf2: 4b09 ldr r3, [pc, #36] @ (8003d18 ) + 8003cf4: 621a str r2, [r3, #32] + } + if (TIM2->SR & TIM_SR_UIF) { + 8003cf6: 2380 movs r3, #128 @ 0x80 + 8003cf8: 05db lsls r3, r3, #23 + 8003cfa: 691b ldr r3, [r3, #16] + 8003cfc: 2201 movs r2, #1 + 8003cfe: 4013 ands r3, r2 + 8003d00: d007 beq.n 8003d12 + //TIM2 overflow interrupt jaust clear update interrupt flag + TIM2->SR &= ~TIM_SR_UIF; + 8003d02: 2380 movs r3, #128 @ 0x80 + 8003d04: 05db lsls r3, r3, #23 + 8003d06: 691a ldr r2, [r3, #16] + 8003d08: 2380 movs r3, #128 @ 0x80 + 8003d0a: 05db lsls r3, r3, #23 + 8003d0c: 2101 movs r1, #1 + 8003d0e: 438a bics r2, r1 + 8003d10: 611a str r2, [r3, #16] + + } + +} + 8003d12: 46c0 nop @ (mov r8, r8) + 8003d14: 46bd mov sp, r7 + 8003d16: bd80 pop {r7, pc} + 8003d18: 200009d4 .word 0x200009d4 + 8003d1c: 200009cc .word 0x200009cc + +08003d20 : +void DBW_Pwm_Set_Duty(signed int duty, pwm_t *ttl) { + 8003d20: b590 push {r4, r7, lr} + 8003d22: b085 sub sp, #20 + 8003d24: af00 add r7, sp, #0 + 8003d26: 6078 str r0, [r7, #4] + 8003d28: 6039 str r1, [r7, #0] + float tmp; + unsigned int period_ticks; + + //check limmits + if (duty > 10000) + 8003d2a: 687b ldr r3, [r7, #4] + 8003d2c: 4a61 ldr r2, [pc, #388] @ (8003eb4 ) + 8003d2e: 4293 cmp r3, r2 + 8003d30: dd02 ble.n 8003d38 + duty = 10000; + 8003d32: 4b60 ldr r3, [pc, #384] @ (8003eb4 ) + 8003d34: 607b str r3, [r7, #4] + 8003d36: e005 b.n 8003d44 + else if (duty < -10000) + 8003d38: 687b ldr r3, [r7, #4] + 8003d3a: 4a5f ldr r2, [pc, #380] @ (8003eb8 ) + 8003d3c: 4293 cmp r3, r2 + 8003d3e: da01 bge.n 8003d44 + duty = -10000; + 8003d40: 4b5d ldr r3, [pc, #372] @ (8003eb8 ) + 8003d42: 607b str r3, [r7, #4] + + //calculate period - needed to change frequency on-the-fly + period_ticks = (unsigned int) 1000000UL / config->motor_pwm_fq; + 8003d44: 4b5d ldr r3, [pc, #372] @ (8003ebc ) + 8003d46: 681b ldr r3, [r3, #0] + 8003d48: 227c movs r2, #124 @ 0x7c + 8003d4a: 5a9b ldrh r3, [r3, r2] + 8003d4c: b29b uxth r3, r3 + 8003d4e: 0019 movs r1, r3 + 8003d50: 485b ldr r0, [pc, #364] @ (8003ec0 ) + 8003d52: f7fc f9d9 bl 8000108 <__udivsi3> + 8003d56: 0003 movs r3, r0 + 8003d58: 60bb str r3, [r7, #8] + if (duty > 0) + 8003d5a: 687b ldr r3, [r7, #4] + 8003d5c: 2b00 cmp r3, #0 + 8003d5e: dd13 ble.n 8003d88 + tmp = (float) period_ticks * (float) duty / 10000.0F; + 8003d60: 68b8 ldr r0, [r7, #8] + 8003d62: f7fd fb97 bl 8001494 <__aeabi_ui2f> + 8003d66: 1c04 adds r4, r0, #0 + 8003d68: 6878 ldr r0, [r7, #4] + 8003d6a: f7fd fb43 bl 80013f4 <__aeabi_i2f> + 8003d6e: 1c03 adds r3, r0, #0 + 8003d70: 1c19 adds r1, r3, #0 + 8003d72: 1c20 adds r0, r4, #0 + 8003d74: f7fc ff8a bl 8000c8c <__aeabi_fmul> + 8003d78: 1c03 adds r3, r0, #0 + 8003d7a: 4952 ldr r1, [pc, #328] @ (8003ec4 ) + 8003d7c: 1c18 adds r0, r3, #0 + 8003d7e: f7fc fdb7 bl 80008f0 <__aeabi_fdiv> + 8003d82: 1c03 adds r3, r0, #0 + 8003d84: 60fb str r3, [r7, #12] + 8003d86: e01b b.n 8003dc0 + else if (duty < 0) + 8003d88: 687b ldr r3, [r7, #4] + 8003d8a: 2b00 cmp r3, #0 + 8003d8c: da16 bge.n 8003dbc + tmp = (float) period_ticks * (0 - ((float) duty)) / 10000.0F; + 8003d8e: 68b8 ldr r0, [r7, #8] + 8003d90: f7fd fb80 bl 8001494 <__aeabi_ui2f> + 8003d94: 1c04 adds r4, r0, #0 + 8003d96: 6878 ldr r0, [r7, #4] + 8003d98: f7fd fb2c bl 80013f4 <__aeabi_i2f> + 8003d9c: 1c02 adds r2, r0, #0 + 8003d9e: 2380 movs r3, #128 @ 0x80 + 8003da0: 061b lsls r3, r3, #24 + 8003da2: 4053 eors r3, r2 + 8003da4: 1c19 adds r1, r3, #0 + 8003da6: 1c20 adds r0, r4, #0 + 8003da8: f7fc ff70 bl 8000c8c <__aeabi_fmul> + 8003dac: 1c03 adds r3, r0, #0 + 8003dae: 4945 ldr r1, [pc, #276] @ (8003ec4 ) + 8003db0: 1c18 adds r0, r3, #0 + 8003db2: f7fc fd9d bl 80008f0 <__aeabi_fdiv> + 8003db6: 1c03 adds r3, r0, #0 + 8003db8: 60fb str r3, [r7, #12] + 8003dba: e001 b.n 8003dc0 + else + tmp = 20; + 8003dbc: 4b42 ldr r3, [pc, #264] @ (8003ec8 ) + 8003dbe: 60fb str r3, [r7, #12] + + // check minimum duty period; + + // do not allow duty cylce <20uS + if ((period_ticks - (unsigned int) tmp) < 20) { + 8003dc0: 68f8 ldr r0, [r7, #12] + 8003dc2: f7fc fb51 bl 8000468 <__aeabi_f2uiz> + 8003dc6: 0002 movs r2, r0 + 8003dc8: 68bb ldr r3, [r7, #8] + 8003dca: 1a9b subs r3, r3, r2 + 8003dcc: 2b13 cmp r3, #19 + 8003dce: d84f bhi.n 8003e70 + tmp = period_ticks - 20; + 8003dd0: 68bb ldr r3, [r7, #8] + 8003dd2: 3b14 subs r3, #20 + 8003dd4: 0018 movs r0, r3 + 8003dd6: f7fd fb5d bl 8001494 <__aeabi_ui2f> + 8003dda: 1c03 adds r3, r0, #0 + 8003ddc: 60fb str r3, [r7, #12] + if (duty > 0) + 8003dde: 687b ldr r3, [r7, #4] + 8003de0: 2b00 cmp r3, #0 + 8003de2: dd1e ble.n 8003e22 + duty = (signed int) tmp * 10000.0F / ttl->period_ticks; + 8003de4: 68f8 ldr r0, [r7, #12] + 8003de6: f7fd fae5 bl 80013b4 <__aeabi_f2iz> + 8003dea: 0003 movs r3, r0 + 8003dec: 0018 movs r0, r3 + 8003dee: f7fd fb01 bl 80013f4 <__aeabi_i2f> + 8003df2: 1c03 adds r3, r0, #0 + 8003df4: 4933 ldr r1, [pc, #204] @ (8003ec4 ) + 8003df6: 1c18 adds r0, r3, #0 + 8003df8: f7fc ff48 bl 8000c8c <__aeabi_fmul> + 8003dfc: 1c03 adds r3, r0, #0 + 8003dfe: 1c1c adds r4, r3, #0 + 8003e00: 683b ldr r3, [r7, #0] + 8003e02: 695b ldr r3, [r3, #20] + 8003e04: 0018 movs r0, r3 + 8003e06: f7fd fb45 bl 8001494 <__aeabi_ui2f> + 8003e0a: 1c03 adds r3, r0, #0 + 8003e0c: 1c19 adds r1, r3, #0 + 8003e0e: 1c20 adds r0, r4, #0 + 8003e10: f7fc fd6e bl 80008f0 <__aeabi_fdiv> + 8003e14: 1c03 adds r3, r0, #0 + 8003e16: 1c18 adds r0, r3, #0 + 8003e18: f7fd facc bl 80013b4 <__aeabi_f2iz> + 8003e1c: 0003 movs r3, r0 + 8003e1e: 607b str r3, [r7, #4] + 8003e20: e030 b.n 8003e84 + else if (duty < 0) + 8003e22: 687b ldr r3, [r7, #4] + 8003e24: 2b00 cmp r3, #0 + 8003e26: da2d bge.n 8003e84 + duty = 0 - (signed int) tmp * 10000.0F / ttl->period_ticks; + 8003e28: 68f8 ldr r0, [r7, #12] + 8003e2a: f7fd fac3 bl 80013b4 <__aeabi_f2iz> + 8003e2e: 0003 movs r3, r0 + 8003e30: 0018 movs r0, r3 + 8003e32: f7fd fadf bl 80013f4 <__aeabi_i2f> + 8003e36: 1c03 adds r3, r0, #0 + 8003e38: 4922 ldr r1, [pc, #136] @ (8003ec4 ) + 8003e3a: 1c18 adds r0, r3, #0 + 8003e3c: f7fc ff26 bl 8000c8c <__aeabi_fmul> + 8003e40: 1c03 adds r3, r0, #0 + 8003e42: 1c1c adds r4, r3, #0 + 8003e44: 683b ldr r3, [r7, #0] + 8003e46: 695b ldr r3, [r3, #20] + 8003e48: 0018 movs r0, r3 + 8003e4a: f7fd fb23 bl 8001494 <__aeabi_ui2f> + 8003e4e: 1c03 adds r3, r0, #0 + 8003e50: 1c19 adds r1, r3, #0 + 8003e52: 1c20 adds r0, r4, #0 + 8003e54: f7fc fd4c bl 80008f0 <__aeabi_fdiv> + 8003e58: 1c03 adds r3, r0, #0 + 8003e5a: 1c19 adds r1, r3, #0 + 8003e5c: 2000 movs r0, #0 + 8003e5e: f7fd f867 bl 8000f30 <__aeabi_fsub> + 8003e62: 1c03 adds r3, r0, #0 + 8003e64: 1c18 adds r0, r3, #0 + 8003e66: f7fd faa5 bl 80013b4 <__aeabi_f2iz> + 8003e6a: 0003 movs r3, r0 + 8003e6c: 607b str r3, [r7, #4] + 8003e6e: e009 b.n 8003e84 + } else if (tmp < 20) { + 8003e70: 4915 ldr r1, [pc, #84] @ (8003ec8 ) + 8003e72: 68f8 ldr r0, [r7, #12] + 8003e74: f7fc fad0 bl 8000418 <__aeabi_fcmplt> + 8003e78: 1e03 subs r3, r0, #0 + 8003e7a: d003 beq.n 8003e84 + tmp = 20; + 8003e7c: 4b12 ldr r3, [pc, #72] @ (8003ec8 ) + 8003e7e: 60fb str r3, [r7, #12] + duty = 0; + 8003e80: 2300 movs r3, #0 + 8003e82: 607b str r3, [r7, #4] + } + + //update variables + var.motor_pwm = duty; + 8003e84: 687b ldr r3, [r7, #4] + 8003e86: b21a sxth r2, r3 + 8003e88: 4b10 ldr r3, [pc, #64] @ (8003ecc ) + 8003e8a: 84da strh r2, [r3, #38] @ 0x26 + __ASM volatile ("cpsid i" : : : "memory"); + 8003e8c: b672 cpsid i +} + 8003e8e: 46c0 nop @ (mov r8, r8) + + //apply new settings + __disable_irq(); + ttl->duty_ticks = (unsigned int) tmp; + 8003e90: 68f8 ldr r0, [r7, #12] + 8003e92: f7fc fae9 bl 8000468 <__aeabi_f2uiz> + 8003e96: 0002 movs r2, r0 + 8003e98: 683b ldr r3, [r7, #0] + 8003e9a: 619a str r2, [r3, #24] + ttl->period_ticks = period_ticks; + 8003e9c: 683b ldr r3, [r7, #0] + 8003e9e: 68ba ldr r2, [r7, #8] + 8003ea0: 615a str r2, [r3, #20] + ttl->pwm = duty; + 8003ea2: 683b ldr r3, [r7, #0] + 8003ea4: 687a ldr r2, [r7, #4] + 8003ea6: 61da str r2, [r3, #28] + __ASM volatile ("cpsie i" : : : "memory"); + 8003ea8: b662 cpsie i +} + 8003eaa: 46c0 nop @ (mov r8, r8) + __enable_irq(); + +} + 8003eac: 46c0 nop @ (mov r8, r8) + 8003eae: 46bd mov sp, r7 + 8003eb0: b005 add sp, #20 + 8003eb2: bd90 pop {r4, r7, pc} + 8003eb4: 00002710 .word 0x00002710 + 8003eb8: ffffd8f0 .word 0xffffd8f0 + 8003ebc: 200009cc .word 0x200009cc + 8003ec0: 000f4240 .word 0x000f4240 + 8003ec4: 461c4000 .word 0x461c4000 + 8003ec8: 41a00000 .word 0x41a00000 + 8003ecc: 20000998 .word 0x20000998 + +08003ed0 : + return ((unsigned int) (z_table[ix] + + interp * (int) (z_table[ix + 1] - z_table[ix]) / 100)); +} + +signed short intrp_1d_ss_table(signed short x, unsigned char n, + signed short *x_table, char sgn, signed short *z_table) { + 8003ed0: b590 push {r4, r7, lr} + 8003ed2: b087 sub sp, #28 + 8003ed4: af00 add r7, sp, #0 + 8003ed6: 0004 movs r4, r0 + 8003ed8: 0008 movs r0, r1 + 8003eda: 603a str r2, [r7, #0] + 8003edc: 0019 movs r1, r3 + 8003ede: 1dbb adds r3, r7, #6 + 8003ee0: 1c22 adds r2, r4, #0 + 8003ee2: 801a strh r2, [r3, #0] + 8003ee4: 1d7b adds r3, r7, #5 + 8003ee6: 1c02 adds r2, r0, #0 + 8003ee8: 701a strb r2, [r3, #0] + 8003eea: 1d3b adds r3, r7, #4 + 8003eec: 1c0a adds r2, r1, #0 + 8003eee: 701a strb r2, [r3, #0] + int ix; + int interp, interp3; + // bound input arguments + if (x > x_table[n - 1]) + 8003ef0: 1d7b adds r3, r7, #5 + 8003ef2: 781b ldrb r3, [r3, #0] + 8003ef4: 4a46 ldr r2, [pc, #280] @ (8004010 ) + 8003ef6: 4694 mov ip, r2 + 8003ef8: 4463 add r3, ip + 8003efa: 005b lsls r3, r3, #1 + 8003efc: 683a ldr r2, [r7, #0] + 8003efe: 18d3 adds r3, r2, r3 + 8003f00: 2200 movs r2, #0 + 8003f02: 5e9b ldrsh r3, [r3, r2] + 8003f04: 1dba adds r2, r7, #6 + 8003f06: 2100 movs r1, #0 + 8003f08: 5e52 ldrsh r2, [r2, r1] + 8003f0a: 429a cmp r2, r3 + 8003f0c: dd0a ble.n 8003f24 + return z_table[n - 1]; + 8003f0e: 1d7b adds r3, r7, #5 + 8003f10: 781b ldrb r3, [r3, #0] + 8003f12: 4a3f ldr r2, [pc, #252] @ (8004010 ) + 8003f14: 4694 mov ip, r2 + 8003f16: 4463 add r3, ip + 8003f18: 005b lsls r3, r3, #1 + 8003f1a: 6aba ldr r2, [r7, #40] @ 0x28 + 8003f1c: 18d3 adds r3, r2, r3 + 8003f1e: 2200 movs r2, #0 + 8003f20: 5e9b ldrsh r3, [r3, r2] + 8003f22: e071 b.n 8004008 + + if (x < x_table[0]) + 8003f24: 683b ldr r3, [r7, #0] + 8003f26: 2200 movs r2, #0 + 8003f28: 5e9b ldrsh r3, [r3, r2] + 8003f2a: 1dba adds r2, r7, #6 + 8003f2c: 2100 movs r1, #0 + 8003f2e: 5e52 ldrsh r2, [r2, r1] + 8003f30: 429a cmp r2, r3 + 8003f32: da03 bge.n 8003f3c + return z_table[0]; + 8003f34: 6abb ldr r3, [r7, #40] @ 0x28 + 8003f36: 2200 movs r2, #0 + 8003f38: 5e9b ldrsh r3, [r3, r2] + 8003f3a: e065 b.n 8004008 + + for (ix = n - 2; ix > -1; ix--) { + 8003f3c: 1d7b adds r3, r7, #5 + 8003f3e: 781b ldrb r3, [r3, #0] + 8003f40: 3b02 subs r3, #2 + 8003f42: 617b str r3, [r7, #20] + 8003f44: e00d b.n 8003f62 + if (x > x_table[ix]) { + 8003f46: 697b ldr r3, [r7, #20] + 8003f48: 005b lsls r3, r3, #1 + 8003f4a: 683a ldr r2, [r7, #0] + 8003f4c: 18d3 adds r3, r2, r3 + 8003f4e: 2200 movs r2, #0 + 8003f50: 5e9b ldrsh r3, [r3, r2] + 8003f52: 1dba adds r2, r7, #6 + 8003f54: 2100 movs r1, #0 + 8003f56: 5e52 ldrsh r2, [r2, r1] + 8003f58: 429a cmp r2, r3 + 8003f5a: dc06 bgt.n 8003f6a + for (ix = n - 2; ix > -1; ix--) { + 8003f5c: 697b ldr r3, [r7, #20] + 8003f5e: 3b01 subs r3, #1 + 8003f60: 617b str r3, [r7, #20] + 8003f62: 697b ldr r3, [r7, #20] + 8003f64: 2b00 cmp r3, #0 + 8003f66: daee bge.n 8003f46 + 8003f68: e000 b.n 8003f6c + break; + 8003f6a: 46c0 nop @ (mov r8, r8) + } + } + if (ix < 0) + 8003f6c: 697b ldr r3, [r7, #20] + 8003f6e: 2b00 cmp r3, #0 + 8003f70: da01 bge.n 8003f76 + ix = 0; + 8003f72: 2300 movs r3, #0 + 8003f74: 617b str r3, [r7, #20] + + interp = x_table[ix + 1] - x_table[ix]; + 8003f76: 697b ldr r3, [r7, #20] + 8003f78: 3301 adds r3, #1 + 8003f7a: 005b lsls r3, r3, #1 + 8003f7c: 683a ldr r2, [r7, #0] + 8003f7e: 18d3 adds r3, r2, r3 + 8003f80: 2200 movs r2, #0 + 8003f82: 5e9b ldrsh r3, [r3, r2] + 8003f84: 0019 movs r1, r3 + 8003f86: 697b ldr r3, [r7, #20] + 8003f88: 005b lsls r3, r3, #1 + 8003f8a: 683a ldr r2, [r7, #0] + 8003f8c: 18d3 adds r3, r2, r3 + 8003f8e: 2200 movs r2, #0 + 8003f90: 5e9b ldrsh r3, [r3, r2] + 8003f92: 1acb subs r3, r1, r3 + 8003f94: 613b str r3, [r7, #16] + if (interp != 0) { + 8003f96: 693b ldr r3, [r7, #16] + 8003f98: 2b00 cmp r3, #0 + 8003f9a: d014 beq.n 8003fc6 + interp3 = (x - x_table[ix]); + 8003f9c: 1dbb adds r3, r7, #6 + 8003f9e: 2200 movs r2, #0 + 8003fa0: 5e9b ldrsh r3, [r3, r2] + 8003fa2: 697a ldr r2, [r7, #20] + 8003fa4: 0052 lsls r2, r2, #1 + 8003fa6: 6839 ldr r1, [r7, #0] + 8003fa8: 188a adds r2, r1, r2 + 8003faa: 2100 movs r1, #0 + 8003fac: 5e52 ldrsh r2, [r2, r1] + 8003fae: 1a9b subs r3, r3, r2 + 8003fb0: 60fb str r3, [r7, #12] + interp3 = (100 * interp3); + 8003fb2: 68fb ldr r3, [r7, #12] + 8003fb4: 2264 movs r2, #100 @ 0x64 + 8003fb6: 4353 muls r3, r2 + 8003fb8: 60fb str r3, [r7, #12] + interp = interp3 / interp; + 8003fba: 6939 ldr r1, [r7, #16] + 8003fbc: 68f8 ldr r0, [r7, #12] + 8003fbe: f7fc f92d bl 800021c <__divsi3> + 8003fc2: 0003 movs r3, r0 + 8003fc4: 613b str r3, [r7, #16] + } + + return ((short) ((int) z_table[ix] + 8003fc6: 697b ldr r3, [r7, #20] + 8003fc8: 005b lsls r3, r3, #1 + 8003fca: 6aba ldr r2, [r7, #40] @ 0x28 + 8003fcc: 18d3 adds r3, r2, r3 + 8003fce: 2200 movs r2, #0 + 8003fd0: 5e9b ldrsh r3, [r3, r2] + 8003fd2: b29c uxth r4, r3 + + interp * ((int) z_table[ix + 1] - (int) z_table[ix]) / 100)); + 8003fd4: 697b ldr r3, [r7, #20] + 8003fd6: 3301 adds r3, #1 + 8003fd8: 005b lsls r3, r3, #1 + 8003fda: 6aba ldr r2, [r7, #40] @ 0x28 + 8003fdc: 18d3 adds r3, r2, r3 + 8003fde: 2200 movs r2, #0 + 8003fe0: 5e9b ldrsh r3, [r3, r2] + 8003fe2: 0019 movs r1, r3 + 8003fe4: 697b ldr r3, [r7, #20] + 8003fe6: 005b lsls r3, r3, #1 + 8003fe8: 6aba ldr r2, [r7, #40] @ 0x28 + 8003fea: 18d3 adds r3, r2, r3 + 8003fec: 2200 movs r2, #0 + 8003fee: 5e9b ldrsh r3, [r3, r2] + 8003ff0: 1acb subs r3, r1, r3 + 8003ff2: 693a ldr r2, [r7, #16] + 8003ff4: 4353 muls r3, r2 + 8003ff6: 2164 movs r1, #100 @ 0x64 + 8003ff8: 0018 movs r0, r3 + 8003ffa: f7fc f90f bl 800021c <__divsi3> + 8003ffe: 0003 movs r3, r0 + 8004000: b29b uxth r3, r3 + 8004002: 18e3 adds r3, r4, r3 + 8004004: b29b uxth r3, r3 + return ((short) ((int) z_table[ix] + 8004006: b21b sxth r3, r3 +} + 8004008: 0018 movs r0, r3 + 800400a: 46bd mov sp, r7 + 800400c: b007 add sp, #28 + 800400e: bd90 pop {r4, r7, pc} + 8004010: 7fffffff .word 0x7fffffff + +08004014 : + + interp + * ((signed short) z_table[ix + 1] + - (signed short) z_table[ix]) / 100)); +} + +void DBW_Start(void) { + 8004014: b580 push {r7, lr} + 8004016: af00 add r7, sp, #0 + GPIOB->ODR &= ~D1_Pin; + 8004018: 4b07 ldr r3, [pc, #28] @ (8004038 ) + 800401a: 695a ldr r2, [r3, #20] + 800401c: 4b06 ldr r3, [pc, #24] @ (8004038 ) + 800401e: 4907 ldr r1, [pc, #28] @ (800403c ) + 8004020: 400a ands r2, r1 + 8004022: 615a str r2, [r3, #20] + GPIOB->ODR |= D2_Pin; + 8004024: 4b04 ldr r3, [pc, #16] @ (8004038 ) + 8004026: 695a ldr r2, [r3, #20] + 8004028: 4b03 ldr r3, [pc, #12] @ (8004038 ) + 800402a: 2180 movs r1, #128 @ 0x80 + 800402c: 0189 lsls r1, r1, #6 + 800402e: 430a orrs r2, r1 + 8004030: 615a str r2, [r3, #20] +} + 8004032: 46c0 nop @ (mov r8, r8) + 8004034: 46bd mov sp, r7 + 8004036: bd80 pop {r7, pc} + 8004038: 48000400 .word 0x48000400 + 800403c: ffffbfff .word 0xffffbfff + +08004040 : +void DBW_Stop(void) { + 8004040: b580 push {r7, lr} + 8004042: af00 add r7, sp, #0 + GPIOB->ODR |= D1_Pin; + 8004044: 4b07 ldr r3, [pc, #28] @ (8004064 ) + 8004046: 695a ldr r2, [r3, #20] + 8004048: 4b06 ldr r3, [pc, #24] @ (8004064 ) + 800404a: 2180 movs r1, #128 @ 0x80 + 800404c: 01c9 lsls r1, r1, #7 + 800404e: 430a orrs r2, r1 + 8004050: 615a str r2, [r3, #20] + GPIOB->ODR &= ~D2_Pin; + 8004052: 4b04 ldr r3, [pc, #16] @ (8004064 ) + 8004054: 695a ldr r2, [r3, #20] + 8004056: 4b03 ldr r3, [pc, #12] @ (8004064 ) + 8004058: 4903 ldr r1, [pc, #12] @ (8004068 ) + 800405a: 400a ands r2, r1 + 800405c: 615a str r2, [r3, #20] + +} + 800405e: 46c0 nop @ (mov r8, r8) + 8004060: 46bd mov sp, r7 + 8004062: bd80 pop {r7, pc} + 8004064: 48000400 .word 0x48000400 + 8004068: ffffdfff .word 0xffffdfff + +0800406c : + +void DBW_TPS_AutoCal(void) { + 800406c: b580 push {r7, lr} + 800406e: b086 sub sp, #24 + 8004070: af00 add r7, sp, #0 +// if time to process autocal + if ((ac_timer == 0) && (ac_mode != 0)) { + 8004072: 4b77 ldr r3, [pc, #476] @ (8004250 ) + 8004074: 681b ldr r3, [r3, #0] + 8004076: 2b00 cmp r3, #0 + 8004078: d000 beq.n 800407c + 800407a: e0e4 b.n 8004246 + 800407c: 4b75 ldr r3, [pc, #468] @ (8004254 ) + 800407e: 681b ldr r3, [r3, #0] + 8004080: 2b00 cmp r3, #0 + 8004082: d100 bne.n 8004086 + 8004084: e0df b.n 8004246 + if (ac_mode == 1) { + 8004086: 4b73 ldr r3, [pc, #460] @ (8004254 ) + 8004088: 681b ldr r3, [r3, #0] + 800408a: 2b01 cmp r3, #1 + 800408c: d117 bne.n 80040be + var.status0 |= DBW_STATUS0_PPSTPS_CAL_F; + 800408e: 4b72 ldr r3, [pc, #456] @ (8004258 ) + 8004090: 889b ldrh r3, [r3, #4] + 8004092: b29b uxth r3, r3 + 8004094: 2280 movs r2, #128 @ 0x80 + 8004096: 0112 lsls r2, r2, #4 + 8004098: 4313 orrs r3, r2 + 800409a: b29a uxth r2, r3 + 800409c: 4b6e ldr r3, [pc, #440] @ (8004258 ) + 800409e: 809a strh r2, [r3, #4] + DBW_Pwm_Set_Duty((signed short) (-6000), (pwm_t*) &ttl1_pwm); + 80040a0: 4b6e ldr r3, [pc, #440] @ (800425c ) + 80040a2: 4a6f ldr r2, [pc, #444] @ (8004260 ) + 80040a4: 0019 movs r1, r3 + 80040a6: 0010 movs r0, r2 + 80040a8: f7ff fe3a bl 8003d20 + DBW_Start(); + 80040ac: f7ff ffb2 bl 8004014 + ac_timer = 1500; + 80040b0: 4b67 ldr r3, [pc, #412] @ (8004250 ) + 80040b2: 4a6c ldr r2, [pc, #432] @ (8004264 ) + 80040b4: 601a str r2, [r3, #0] + ac_mode = 2; + 80040b6: 4b67 ldr r3, [pc, #412] @ (8004254 ) + 80040b8: 2202 movs r2, #2 + 80040ba: 601a str r2, [r3, #0] + NVIC_EnableIRQ(USART1_IRQn); + + } + } + +} + 80040bc: e0c3 b.n 8004246 + } else if (ac_mode == 2) { + 80040be: 4b65 ldr r3, [pc, #404] @ (8004254 ) + 80040c0: 681b ldr r3, [r3, #0] + 80040c2: 2b02 cmp r3, #2 + 80040c4: d13b bne.n 800413e + uint32_t tmp = 0; + 80040c6: 2300 movs r3, #0 + 80040c8: 617b str r3, [r7, #20] + for (int i = 0; i < 16; i++) + 80040ca: 2300 movs r3, #0 + 80040cc: 613b str r3, [r7, #16] + 80040ce: e00a b.n 80040e6 + tmp += Adc_Read(2); + 80040d0: 2002 movs r0, #2 + 80040d2: f7fe fbb5 bl 8002840 + 80040d6: 0003 movs r3, r0 + 80040d8: 001a movs r2, r3 + 80040da: 697b ldr r3, [r7, #20] + 80040dc: 189b adds r3, r3, r2 + 80040de: 617b str r3, [r7, #20] + for (int i = 0; i < 16; i++) + 80040e0: 693b ldr r3, [r7, #16] + 80040e2: 3301 adds r3, #1 + 80040e4: 613b str r3, [r7, #16] + 80040e6: 693b ldr r3, [r7, #16] + 80040e8: 2b0f cmp r3, #15 + 80040ea: ddf1 ble.n 80040d0 + config->tps1_min = tmp >> 4; + 80040ec: 697b ldr r3, [r7, #20] + 80040ee: 091a lsrs r2, r3, #4 + 80040f0: 4b5d ldr r3, [pc, #372] @ (8004268 ) + 80040f2: 681b ldr r3, [r3, #0] + 80040f4: b292 uxth r2, r2 + 80040f6: 81da strh r2, [r3, #14] + tmp = 0; + 80040f8: 2300 movs r3, #0 + 80040fa: 617b str r3, [r7, #20] + for (int i = 0; i < 16; i++) + 80040fc: 2300 movs r3, #0 + 80040fe: 60fb str r3, [r7, #12] + 8004100: e00a b.n 8004118 + tmp += Adc_Read(3); + 8004102: 2003 movs r0, #3 + 8004104: f7fe fb9c bl 8002840 + 8004108: 0003 movs r3, r0 + 800410a: 001a movs r2, r3 + 800410c: 697b ldr r3, [r7, #20] + 800410e: 189b adds r3, r3, r2 + 8004110: 617b str r3, [r7, #20] + for (int i = 0; i < 16; i++) + 8004112: 68fb ldr r3, [r7, #12] + 8004114: 3301 adds r3, #1 + 8004116: 60fb str r3, [r7, #12] + 8004118: 68fb ldr r3, [r7, #12] + 800411a: 2b0f cmp r3, #15 + 800411c: ddf1 ble.n 8004102 + config->tps2_min = tmp >> 4; + 800411e: 697b ldr r3, [r7, #20] + 8004120: 091a lsrs r2, r3, #4 + 8004122: 4b51 ldr r3, [pc, #324] @ (8004268 ) + 8004124: 681b ldr r3, [r3, #0] + 8004126: b292 uxth r2, r2 + 8004128: 825a strh r2, [r3, #18] + DBW_Stop(); + 800412a: f7ff ff89 bl 8004040 + ac_timer = 2000; + 800412e: 4b48 ldr r3, [pc, #288] @ (8004250 ) + 8004130: 22fa movs r2, #250 @ 0xfa + 8004132: 00d2 lsls r2, r2, #3 + 8004134: 601a str r2, [r3, #0] + ac_mode = 3; + 8004136: 4b47 ldr r3, [pc, #284] @ (8004254 ) + 8004138: 2203 movs r2, #3 + 800413a: 601a str r2, [r3, #0] +} + 800413c: e083 b.n 8004246 + } else if (ac_mode == 3) { + 800413e: 4b45 ldr r3, [pc, #276] @ (8004254 ) + 8004140: 681b ldr r3, [r3, #0] + 8004142: 2b03 cmp r3, #3 + 8004144: d10e bne.n 8004164 + DBW_Pwm_Set_Duty((signed short) (9000), (pwm_t*) &ttl1_pwm); + 8004146: 4b45 ldr r3, [pc, #276] @ (800425c ) + 8004148: 4a48 ldr r2, [pc, #288] @ (800426c ) + 800414a: 0019 movs r1, r3 + 800414c: 0010 movs r0, r2 + 800414e: f7ff fde7 bl 8003d20 + DBW_Start(); + 8004152: f7ff ff5f bl 8004014 + ac_timer = 1500; + 8004156: 4b3e ldr r3, [pc, #248] @ (8004250 ) + 8004158: 4a42 ldr r2, [pc, #264] @ (8004264 ) + 800415a: 601a str r2, [r3, #0] + ac_mode = 4; + 800415c: 4b3d ldr r3, [pc, #244] @ (8004254 ) + 800415e: 2204 movs r2, #4 + 8004160: 601a str r2, [r3, #0] +} + 8004162: e070 b.n 8004246 + } else if (ac_mode == 4) { + 8004164: 4b3b ldr r3, [pc, #236] @ (8004254 ) + 8004166: 681b ldr r3, [r3, #0] + 8004168: 2b04 cmp r3, #4 + 800416a: d154 bne.n 8004216 + uint32_t tmp = 0; + 800416c: 2300 movs r3, #0 + 800416e: 60bb str r3, [r7, #8] + for (int i = 0; i < 16; i++) + 8004170: 2300 movs r3, #0 + 8004172: 607b str r3, [r7, #4] + 8004174: e00a b.n 800418c + tmp += Adc_Read(2); + 8004176: 2002 movs r0, #2 + 8004178: f7fe fb62 bl 8002840 + 800417c: 0003 movs r3, r0 + 800417e: 001a movs r2, r3 + 8004180: 68bb ldr r3, [r7, #8] + 8004182: 189b adds r3, r3, r2 + 8004184: 60bb str r3, [r7, #8] + for (int i = 0; i < 16; i++) + 8004186: 687b ldr r3, [r7, #4] + 8004188: 3301 adds r3, #1 + 800418a: 607b str r3, [r7, #4] + 800418c: 687b ldr r3, [r7, #4] + 800418e: 2b0f cmp r3, #15 + 8004190: ddf1 ble.n 8004176 + config->tps1_max = tmp >> 4; + 8004192: 68bb ldr r3, [r7, #8] + 8004194: 091a lsrs r2, r3, #4 + 8004196: 4b34 ldr r3, [pc, #208] @ (8004268 ) + 8004198: 681b ldr r3, [r3, #0] + 800419a: b292 uxth r2, r2 + 800419c: 821a strh r2, [r3, #16] + tmp = 0; + 800419e: 2300 movs r3, #0 + 80041a0: 60bb str r3, [r7, #8] + for (int i = 0; i < 16; i++) + 80041a2: 2300 movs r3, #0 + 80041a4: 603b str r3, [r7, #0] + 80041a6: e00a b.n 80041be + tmp += Adc_Read(3); + 80041a8: 2003 movs r0, #3 + 80041aa: f7fe fb49 bl 8002840 + 80041ae: 0003 movs r3, r0 + 80041b0: 001a movs r2, r3 + 80041b2: 68bb ldr r3, [r7, #8] + 80041b4: 189b adds r3, r3, r2 + 80041b6: 60bb str r3, [r7, #8] + for (int i = 0; i < 16; i++) + 80041b8: 683b ldr r3, [r7, #0] + 80041ba: 3301 adds r3, #1 + 80041bc: 603b str r3, [r7, #0] + 80041be: 683b ldr r3, [r7, #0] + 80041c0: 2b0f cmp r3, #15 + 80041c2: ddf1 ble.n 80041a8 + config->tps2_max = tmp >> 4; + 80041c4: 68bb ldr r3, [r7, #8] + 80041c6: 091a lsrs r2, r3, #4 + 80041c8: 4b27 ldr r3, [pc, #156] @ (8004268 ) + 80041ca: 681b ldr r3, [r3, #0] + 80041cc: b292 uxth r2, r2 + 80041ce: 831a strh r2, [r3, #24] + DBW_Stop(); + 80041d0: f7ff ff36 bl 8004040 + DBW_Pwm_Set_Duty((signed short) (0), (pwm_t*) &ttl1_pwm); + 80041d4: 4b21 ldr r3, [pc, #132] @ (800425c ) + 80041d6: 0019 movs r1, r3 + 80041d8: 2000 movs r0, #0 + 80041da: f7ff fda1 bl 8003d20 + Apply_Sensor_Calibration(); + 80041de: f7fe ff2d bl 800303c + Write_Config(); + 80041e2: f002 fa8b bl 80066fc + ac_timer = 10000; + 80041e6: 4b1a ldr r3, [pc, #104] @ (8004250 ) + 80041e8: 4a21 ldr r2, [pc, #132] @ (8004270 ) + 80041ea: 601a str r2, [r3, #0] + ac_mode = 5; + 80041ec: 4b19 ldr r3, [pc, #100] @ (8004254 ) + 80041ee: 2205 movs r2, #5 + 80041f0: 601a str r2, [r3, #0] + Comms_Reset(&RX); + 80041f2: 4b20 ldr r3, [pc, #128] @ (8004274 ) + 80041f4: 0018 movs r0, r3 + 80041f6: f001 ff2d bl 8006054 + Comms_Reset(&TX); + 80041fa: 4b1f ldr r3, [pc, #124] @ (8004278 ) + 80041fc: 0018 movs r0, r3 + 80041fe: f001 ff29 bl 8006054 + USART1->ICR &= ~USART_CR1_RXNEIE; + 8004202: 4b1e ldr r3, [pc, #120] @ (800427c ) + 8004204: 6a1a ldr r2, [r3, #32] + 8004206: 4b1d ldr r3, [pc, #116] @ (800427c ) + 8004208: 2120 movs r1, #32 + 800420a: 438a bics r2, r1 + 800420c: 621a str r2, [r3, #32] + NVIC_DisableIRQ(USART1_IRQn); + 800420e: 201b movs r0, #27 + 8004210: f7fe fef2 bl 8002ff8 <__NVIC_DisableIRQ> +} + 8004214: e017 b.n 8004246 + } else if (ac_mode == 5) { + 8004216: 4b0f ldr r3, [pc, #60] @ (8004254 ) + 8004218: 681b ldr r3, [r3, #0] + 800421a: 2b05 cmp r3, #5 + 800421c: d113 bne.n 8004246 + ac_mode = 0; + 800421e: 4b0d ldr r3, [pc, #52] @ (8004254 ) + 8004220: 2200 movs r2, #0 + 8004222: 601a str r2, [r3, #0] + var.status0 &= ~DBW_STATUS0_PPSTPS_CAL_F; + 8004224: 4b0c ldr r3, [pc, #48] @ (8004258 ) + 8004226: 889b ldrh r3, [r3, #4] + 8004228: b29b uxth r3, r3 + 800422a: 4a15 ldr r2, [pc, #84] @ (8004280 ) + 800422c: 4013 ands r3, r2 + 800422e: b29a uxth r2, r3 + 8004230: 4b09 ldr r3, [pc, #36] @ (8004258 ) + 8004232: 809a strh r2, [r3, #4] + USART1->ICR |= USART_CR1_RXNEIE; + 8004234: 4b11 ldr r3, [pc, #68] @ (800427c ) + 8004236: 6a1a ldr r2, [r3, #32] + 8004238: 4b10 ldr r3, [pc, #64] @ (800427c ) + 800423a: 2120 movs r1, #32 + 800423c: 430a orrs r2, r1 + 800423e: 621a str r2, [r3, #32] + NVIC_EnableIRQ(USART1_IRQn); + 8004240: 201b movs r0, #27 + 8004242: f7fe febf bl 8002fc4 <__NVIC_EnableIRQ> +} + 8004246: 46c0 nop @ (mov r8, r8) + 8004248: 46bd mov sp, r7 + 800424a: b006 add sp, #24 + 800424c: bd80 pop {r7, pc} + 800424e: 46c0 nop @ (mov r8, r8) + 8004250: 20000000 .word 0x20000000 + 8004254: 200009d0 .word 0x200009d0 + 8004258: 20000998 .word 0x20000998 + 800425c: 200009d4 .word 0x200009d4 + 8004260: ffffe890 .word 0xffffe890 + 8004264: 000005dc .word 0x000005dc + 8004268: 200009cc .word 0x200009cc + 800426c: 00002328 .word 0x00002328 + 8004270: 00002710 .word 0x00002710 + 8004274: 20000b34 .word 0x20000b34 + 8004278: 20000c50 .word 0x20000c50 + 800427c: 40013800 .word 0x40013800 + 8004280: fffff7ff .word 0xfffff7ff + +08004284 : + +void DBW_Read_sensors(void) { + 8004284: b580 push {r7, lr} + 8004286: af00 add r7, sp, #0 + var.pps1_adc = LPF(700, Adc_Read(0), var.pps1_adc); + 8004288: 2000 movs r0, #0 + 800428a: f7fe fad9 bl 8002840 + 800428e: 0003 movs r3, r0 + 8004290: 0019 movs r1, r3 + 8004292: 4b80 ldr r3, [pc, #512] @ (8004494 ) + 8004294: 899b ldrh r3, [r3, #12] + 8004296: b29a uxth r2, r3 + 8004298: 23af movs r3, #175 @ 0xaf + 800429a: 009b lsls r3, r3, #2 + 800429c: 0018 movs r0, r3 + 800429e: f7fe fa81 bl 80027a4 + 80042a2: 0003 movs r3, r0 + 80042a4: 001a movs r2, r3 + 80042a6: 4b7b ldr r3, [pc, #492] @ (8004494 ) + 80042a8: 819a strh r2, [r3, #12] + var.pps1 = var.pps1_adc * pps1_gain + pps1_offset; + 80042aa: 4b7a ldr r3, [pc, #488] @ (8004494 ) + 80042ac: 899b ldrh r3, [r3, #12] + 80042ae: b29b uxth r3, r3 + 80042b0: 0018 movs r0, r3 + 80042b2: f7fd f89f bl 80013f4 <__aeabi_i2f> + 80042b6: 1c02 adds r2, r0, #0 + 80042b8: 4b77 ldr r3, [pc, #476] @ (8004498 ) + 80042ba: 681b ldr r3, [r3, #0] + 80042bc: 1c19 adds r1, r3, #0 + 80042be: 1c10 adds r0, r2, #0 + 80042c0: f7fc fce4 bl 8000c8c <__aeabi_fmul> + 80042c4: 1c03 adds r3, r0, #0 + 80042c6: 1c1a adds r2, r3, #0 + 80042c8: 4b74 ldr r3, [pc, #464] @ (800449c ) + 80042ca: 681b ldr r3, [r3, #0] + 80042cc: 1c19 adds r1, r3, #0 + 80042ce: 1c10 adds r0, r2, #0 + 80042d0: f7fc f900 bl 80004d4 <__aeabi_fadd> + 80042d4: 1c03 adds r3, r0, #0 + 80042d6: 1c18 adds r0, r3, #0 + 80042d8: f7fd f86c bl 80013b4 <__aeabi_f2iz> + 80042dc: 0003 movs r3, r0 + 80042de: b21a sxth r2, r3 + 80042e0: 4b6c ldr r3, [pc, #432] @ (8004494 ) + 80042e2: 831a strh r2, [r3, #24] + + var.pps2_adc = LPF(700, Adc_Read(3), var.pps2_adc); // 1 is orig + 80042e4: 2003 movs r0, #3 + 80042e6: f7fe faab bl 8002840 + 80042ea: 0003 movs r3, r0 + 80042ec: 0019 movs r1, r3 + 80042ee: 4b69 ldr r3, [pc, #420] @ (8004494 ) + 80042f0: 89db ldrh r3, [r3, #14] + 80042f2: b29a uxth r2, r3 + 80042f4: 23af movs r3, #175 @ 0xaf + 80042f6: 009b lsls r3, r3, #2 + 80042f8: 0018 movs r0, r3 + 80042fa: f7fe fa53 bl 80027a4 + 80042fe: 0003 movs r3, r0 + 8004300: 001a movs r2, r3 + 8004302: 4b64 ldr r3, [pc, #400] @ (8004494 ) + 8004304: 81da strh r2, [r3, #14] + var.pps2 = var.pps2_adc * pps2_gain + pps2_offset; + 8004306: 4b63 ldr r3, [pc, #396] @ (8004494 ) + 8004308: 89db ldrh r3, [r3, #14] + 800430a: b29b uxth r3, r3 + 800430c: 0018 movs r0, r3 + 800430e: f7fd f871 bl 80013f4 <__aeabi_i2f> + 8004312: 1c02 adds r2, r0, #0 + 8004314: 4b62 ldr r3, [pc, #392] @ (80044a0 ) + 8004316: 681b ldr r3, [r3, #0] + 8004318: 1c19 adds r1, r3, #0 + 800431a: 1c10 adds r0, r2, #0 + 800431c: f7fc fcb6 bl 8000c8c <__aeabi_fmul> + 8004320: 1c03 adds r3, r0, #0 + 8004322: 1c1a adds r2, r3, #0 + 8004324: 4b5f ldr r3, [pc, #380] @ (80044a4 ) + 8004326: 681b ldr r3, [r3, #0] + 8004328: 1c19 adds r1, r3, #0 + 800432a: 1c10 adds r0, r2, #0 + 800432c: f7fc f8d2 bl 80004d4 <__aeabi_fadd> + 8004330: 1c03 adds r3, r0, #0 + 8004332: 1c18 adds r0, r3, #0 + 8004334: f7fd f83e bl 80013b4 <__aeabi_f2iz> + 8004338: 0003 movs r3, r0 + 800433a: b21a sxth r2, r3 + 800433c: 4b55 ldr r3, [pc, #340] @ (8004494 ) + 800433e: 835a strh r2, [r3, #26] + + var.pps_delta = var.pps1 - var.pps2; + 8004340: 4b54 ldr r3, [pc, #336] @ (8004494 ) + 8004342: 8b1b ldrh r3, [r3, #24] + 8004344: b21b sxth r3, r3 + 8004346: b29a uxth r2, r3 + 8004348: 4b52 ldr r3, [pc, #328] @ (8004494 ) + 800434a: 8b5b ldrh r3, [r3, #26] + 800434c: b21b sxth r3, r3 + 800434e: b29b uxth r3, r3 + 8004350: 1ad3 subs r3, r2, r3 + 8004352: b29b uxth r3, r3 + 8004354: b21a sxth r2, r3 + 8004356: 4b4f ldr r3, [pc, #316] @ (8004494 ) + 8004358: 855a strh r2, [r3, #42] @ 0x2a + var.pps = (var.pps1 + var.pps2) >> 1; + 800435a: 4b4e ldr r3, [pc, #312] @ (8004494 ) + 800435c: 8b1b ldrh r3, [r3, #24] + 800435e: b21b sxth r3, r3 + 8004360: 001a movs r2, r3 + 8004362: 4b4c ldr r3, [pc, #304] @ (8004494 ) + 8004364: 8b5b ldrh r3, [r3, #26] + 8004366: b21b sxth r3, r3 + 8004368: 18d3 adds r3, r2, r3 + 800436a: 105b asrs r3, r3, #1 + 800436c: b21a sxth r2, r3 + 800436e: 4b49 ldr r3, [pc, #292] @ (8004494 ) + 8004370: 841a strh r2, [r3, #32] + + //Calculate TPS sensor reading + var.tps1_adc = LPF(700, Adc_Read(2), var.tps1_adc); + 8004372: 2002 movs r0, #2 + 8004374: f7fe fa64 bl 8002840 + 8004378: 0003 movs r3, r0 + 800437a: 0019 movs r1, r3 + 800437c: 4b45 ldr r3, [pc, #276] @ (8004494 ) + 800437e: 8a1b ldrh r3, [r3, #16] + 8004380: b29a uxth r2, r3 + 8004382: 23af movs r3, #175 @ 0xaf + 8004384: 009b lsls r3, r3, #2 + 8004386: 0018 movs r0, r3 + 8004388: f7fe fa0c bl 80027a4 + 800438c: 0003 movs r3, r0 + 800438e: 001a movs r2, r3 + 8004390: 4b40 ldr r3, [pc, #256] @ (8004494 ) + 8004392: 821a strh r2, [r3, #16] + var.tps1 = var.tps1_adc * tps1_gain + tps1_offset; + 8004394: 4b3f ldr r3, [pc, #252] @ (8004494 ) + 8004396: 8a1b ldrh r3, [r3, #16] + 8004398: b29b uxth r3, r3 + 800439a: 0018 movs r0, r3 + 800439c: f7fd f82a bl 80013f4 <__aeabi_i2f> + 80043a0: 1c02 adds r2, r0, #0 + 80043a2: 4b41 ldr r3, [pc, #260] @ (80044a8 ) + 80043a4: 681b ldr r3, [r3, #0] + 80043a6: 1c19 adds r1, r3, #0 + 80043a8: 1c10 adds r0, r2, #0 + 80043aa: f7fc fc6f bl 8000c8c <__aeabi_fmul> + 80043ae: 1c03 adds r3, r0, #0 + 80043b0: 1c1a adds r2, r3, #0 + 80043b2: 4b3e ldr r3, [pc, #248] @ (80044ac ) + 80043b4: 681b ldr r3, [r3, #0] + 80043b6: 1c19 adds r1, r3, #0 + 80043b8: 1c10 adds r0, r2, #0 + 80043ba: f7fc f88b bl 80004d4 <__aeabi_fadd> + 80043be: 1c03 adds r3, r0, #0 + 80043c0: 1c18 adds r0, r3, #0 + 80043c2: f7fc fff7 bl 80013b4 <__aeabi_f2iz> + 80043c6: 0003 movs r3, r0 + 80043c8: b21a sxth r2, r3 + 80043ca: 4b32 ldr r3, [pc, #200] @ (8004494 ) + 80043cc: 839a strh r2, [r3, #28] + + var.tps2_adc = LPF(700, Adc_Read(1), var.tps2_adc); //3 is orig + 80043ce: 2001 movs r0, #1 + 80043d0: f7fe fa36 bl 8002840 + 80043d4: 0003 movs r3, r0 + 80043d6: 0019 movs r1, r3 + 80043d8: 4b2e ldr r3, [pc, #184] @ (8004494 ) + 80043da: 8a5b ldrh r3, [r3, #18] + 80043dc: b29a uxth r2, r3 + 80043de: 23af movs r3, #175 @ 0xaf + 80043e0: 009b lsls r3, r3, #2 + 80043e2: 0018 movs r0, r3 + 80043e4: f7fe f9de bl 80027a4 + 80043e8: 0003 movs r3, r0 + 80043ea: 001a movs r2, r3 + 80043ec: 4b29 ldr r3, [pc, #164] @ (8004494 ) + 80043ee: 825a strh r2, [r3, #18] + var.tps2 = var.tps2_adc * tps2_gain + tps2_offset; + 80043f0: 4b28 ldr r3, [pc, #160] @ (8004494 ) + 80043f2: 8a5b ldrh r3, [r3, #18] + 80043f4: b29b uxth r3, r3 + 80043f6: 0018 movs r0, r3 + 80043f8: f7fc fffc bl 80013f4 <__aeabi_i2f> + 80043fc: 1c02 adds r2, r0, #0 + 80043fe: 4b2c ldr r3, [pc, #176] @ (80044b0 ) + 8004400: 681b ldr r3, [r3, #0] + 8004402: 1c19 adds r1, r3, #0 + 8004404: 1c10 adds r0, r2, #0 + 8004406: f7fc fc41 bl 8000c8c <__aeabi_fmul> + 800440a: 1c03 adds r3, r0, #0 + 800440c: 1c1a adds r2, r3, #0 + 800440e: 4b29 ldr r3, [pc, #164] @ (80044b4 ) + 8004410: 681b ldr r3, [r3, #0] + 8004412: 1c19 adds r1, r3, #0 + 8004414: 1c10 adds r0, r2, #0 + 8004416: f7fc f85d bl 80004d4 <__aeabi_fadd> + 800441a: 1c03 adds r3, r0, #0 + 800441c: 1c18 adds r0, r3, #0 + 800441e: f7fc ffc9 bl 80013b4 <__aeabi_f2iz> + 8004422: 0003 movs r3, r0 + 8004424: b21a sxth r2, r3 + 8004426: 4b1b ldr r3, [pc, #108] @ (8004494 ) + 8004428: 83da strh r2, [r3, #30] + + // calculate tps and pps delta and values + var.tps_delta = var.tps1 - var.tps2; + 800442a: 4b1a ldr r3, [pc, #104] @ (8004494 ) + 800442c: 8b9b ldrh r3, [r3, #28] + 800442e: b21b sxth r3, r3 + 8004430: b29a uxth r2, r3 + 8004432: 4b18 ldr r3, [pc, #96] @ (8004494 ) + 8004434: 8bdb ldrh r3, [r3, #30] + 8004436: b21b sxth r3, r3 + 8004438: b29b uxth r3, r3 + 800443a: 1ad3 subs r3, r2, r3 + 800443c: b29b uxth r3, r3 + 800443e: b21a sxth r2, r3 + 8004440: 4b14 ldr r3, [pc, #80] @ (8004494 ) + 8004442: 859a strh r2, [r3, #44] @ 0x2c + var.tps = (var.tps1 + var.tps2) >> 1; + 8004444: 4b13 ldr r3, [pc, #76] @ (8004494 ) + 8004446: 8b9b ldrh r3, [r3, #28] + 8004448: b21b sxth r3, r3 + 800444a: 001a movs r2, r3 + 800444c: 4b11 ldr r3, [pc, #68] @ (8004494 ) + 800444e: 8bdb ldrh r3, [r3, #30] + 8004450: b21b sxth r3, r3 + 8004452: 18d3 adds r3, r2, r3 + 8004454: 105b asrs r3, r3, #1 + 8004456: b21a sxth r2, r3 + 8004458: 4b0e ldr r3, [pc, #56] @ (8004494 ) + 800445a: 845a strh r2, [r3, #34] @ 0x22 + + var.pps_delta = var.pps1 - var.pps2; + 800445c: 4b0d ldr r3, [pc, #52] @ (8004494 ) + 800445e: 8b1b ldrh r3, [r3, #24] + 8004460: b21b sxth r3, r3 + 8004462: b29a uxth r2, r3 + 8004464: 4b0b ldr r3, [pc, #44] @ (8004494 ) + 8004466: 8b5b ldrh r3, [r3, #26] + 8004468: b21b sxth r3, r3 + 800446a: b29b uxth r3, r3 + 800446c: 1ad3 subs r3, r2, r3 + 800446e: b29b uxth r3, r3 + 8004470: b21a sxth r2, r3 + 8004472: 4b08 ldr r3, [pc, #32] @ (8004494 ) + 8004474: 855a strh r2, [r3, #42] @ 0x2a + var.pps = (var.pps1 + var.pps2) >> 1; + 8004476: 4b07 ldr r3, [pc, #28] @ (8004494 ) + 8004478: 8b1b ldrh r3, [r3, #24] + 800447a: b21b sxth r3, r3 + 800447c: 001a movs r2, r3 + 800447e: 4b05 ldr r3, [pc, #20] @ (8004494 ) + 8004480: 8b5b ldrh r3, [r3, #26] + 8004482: b21b sxth r3, r3 + 8004484: 18d3 adds r3, r2, r3 + 8004486: 105b asrs r3, r3, #1 + 8004488: b21a sxth r2, r3 + 800448a: 4b02 ldr r3, [pc, #8] @ (8004494 ) + 800448c: 841a strh r2, [r3, #32] +} + 800448e: 46c0 nop @ (mov r8, r8) + 8004490: 46bd mov sp, r7 + 8004492: bd80 pop {r7, pc} + 8004494: 20000998 .word 0x20000998 + 8004498: 200009fc .word 0x200009fc + 800449c: 20000a00 .word 0x20000a00 + 80044a0: 20000a04 .word 0x20000a04 + 80044a4: 20000a08 .word 0x20000a08 + 80044a8: 20000a0c .word 0x20000a0c + 80044ac: 20000a10 .word 0x20000a10 + 80044b0: 20000a14 .word 0x20000a14 + 80044b4: 20000a18 .word 0x20000a18 + +080044b8 <__NVIC_EnableIRQ>: +{ + 80044b8: b580 push {r7, lr} + 80044ba: b082 sub sp, #8 + 80044bc: af00 add r7, sp, #0 + 80044be: 0002 movs r2, r0 + 80044c0: 1dfb adds r3, r7, #7 + 80044c2: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 80044c4: 1dfb adds r3, r7, #7 + 80044c6: 781b ldrb r3, [r3, #0] + 80044c8: 2b7f cmp r3, #127 @ 0x7f + 80044ca: d809 bhi.n 80044e0 <__NVIC_EnableIRQ+0x28> + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80044cc: 1dfb adds r3, r7, #7 + 80044ce: 781b ldrb r3, [r3, #0] + 80044d0: 001a movs r2, r3 + 80044d2: 231f movs r3, #31 + 80044d4: 401a ands r2, r3 + 80044d6: 4b04 ldr r3, [pc, #16] @ (80044e8 <__NVIC_EnableIRQ+0x30>) + 80044d8: 2101 movs r1, #1 + 80044da: 4091 lsls r1, r2 + 80044dc: 000a movs r2, r1 + 80044de: 601a str r2, [r3, #0] +} + 80044e0: 46c0 nop @ (mov r8, r8) + 80044e2: 46bd mov sp, r7 + 80044e4: b002 add sp, #8 + 80044e6: bd80 pop {r7, pc} + 80044e8: e000e100 .word 0xe000e100 + +080044ec : +#include "main.h" +//Variables +uint32_t counter0 = 0, counter1 = 0, Counter = 0; +uint8_t gap = 0; +// idle in section +void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3 + 80044ec: b580 push {r7, lr} + 80044ee: af00 add r7, sp, #0 + // PB4 AF1 TIM3 Input1 + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + 80044f0: 4b2e ldr r3, [pc, #184] @ (80045ac ) + 80044f2: 695a ldr r2, [r3, #20] + 80044f4: 4b2d ldr r3, [pc, #180] @ (80045ac ) + 80044f6: 2180 movs r1, #128 @ 0x80 + 80044f8: 02c9 lsls r1, r1, #11 + 80044fa: 430a orrs r2, r1 + 80044fc: 615a str r2, [r3, #20] + GPIOB->MODER &= ~(3 << (4 * 2)); + 80044fe: 4b2c ldr r3, [pc, #176] @ (80045b0 ) + 8004500: 681a ldr r2, [r3, #0] + 8004502: 4b2b ldr r3, [pc, #172] @ (80045b0 ) + 8004504: 492b ldr r1, [pc, #172] @ (80045b4 ) + 8004506: 400a ands r2, r1 + 8004508: 601a str r2, [r3, #0] + GPIOB->MODER |= (2 << (4 * 2)); + 800450a: 4b29 ldr r3, [pc, #164] @ (80045b0 ) + 800450c: 681a ldr r2, [r3, #0] + 800450e: 4b28 ldr r3, [pc, #160] @ (80045b0 ) + 8004510: 2180 movs r1, #128 @ 0x80 + 8004512: 0089 lsls r1, r1, #2 + 8004514: 430a orrs r2, r1 + 8004516: 601a str r2, [r3, #0] + GPIOB->OTYPER &= ~(1 << 4 * 1); + 8004518: 4b25 ldr r3, [pc, #148] @ (80045b0 ) + 800451a: 685a ldr r2, [r3, #4] + 800451c: 4b24 ldr r3, [pc, #144] @ (80045b0 ) + 800451e: 2110 movs r1, #16 + 8004520: 438a bics r2, r1 + 8004522: 605a str r2, [r3, #4] + GPIOB->OSPEEDR &= ~(3 << (4 * 2)); + 8004524: 4b22 ldr r3, [pc, #136] @ (80045b0 ) + 8004526: 689a ldr r2, [r3, #8] + 8004528: 4b21 ldr r3, [pc, #132] @ (80045b0 ) + 800452a: 4922 ldr r1, [pc, #136] @ (80045b4 ) + 800452c: 400a ands r2, r1 + 800452e: 609a str r2, [r3, #8] + GPIOB->PUPDR &= ~(3 << (4 * 2)); + 8004530: 4b1f ldr r3, [pc, #124] @ (80045b0 ) + 8004532: 68da ldr r2, [r3, #12] + 8004534: 4b1e ldr r3, [pc, #120] @ (80045b0 ) + 8004536: 491f ldr r1, [pc, #124] @ (80045b4 ) + 8004538: 400a ands r2, r1 + 800453a: 60da str r2, [r3, #12] + GPIOB->AFR[0] &= ~(15 << (4 * 4)); + 800453c: 4b1c ldr r3, [pc, #112] @ (80045b0 ) + 800453e: 6a1a ldr r2, [r3, #32] + 8004540: 4b1b ldr r3, [pc, #108] @ (80045b0 ) + 8004542: 491d ldr r1, [pc, #116] @ (80045b8 ) + 8004544: 400a ands r2, r1 + 8004546: 621a str r2, [r3, #32] + GPIOB->AFR[0] |= (1 << (4 * 4)); + 8004548: 4b19 ldr r3, [pc, #100] @ (80045b0 ) + 800454a: 6a1a ldr r2, [r3, #32] + 800454c: 4b18 ldr r3, [pc, #96] @ (80045b0 ) + 800454e: 2180 movs r1, #128 @ 0x80 + 8004550: 0249 lsls r1, r1, #9 + 8004552: 430a orrs r2, r1 + 8004554: 621a str r2, [r3, #32] + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + 8004556: 4b15 ldr r3, [pc, #84] @ (80045ac ) + 8004558: 69da ldr r2, [r3, #28] + 800455a: 4b14 ldr r3, [pc, #80] @ (80045ac ) + 800455c: 2102 movs r1, #2 + 800455e: 430a orrs r2, r1 + 8004560: 61da str r2, [r3, #28] + select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset + value), + select the falling edge on CC2 (CC2P = 1). */ + /* (4) Enable interrupt on Capture/Compare 1 */ + /* (5) Enable counter */ + TIM3->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/ + 8004562: 4b16 ldr r3, [pc, #88] @ (80045bc ) + 8004564: 699a ldr r2, [r3, #24] + 8004566: 4b15 ldr r3, [pc, #84] @ (80045bc ) + 8004568: 4915 ldr r1, [pc, #84] @ (80045c0 ) + 800456a: 430a orrs r2, r1 + 800456c: 619a str r2, [r3, #24] + TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */ + 800456e: 4b13 ldr r3, [pc, #76] @ (80045bc ) + 8004570: 689a ldr r2, [r3, #8] + 8004572: 4b12 ldr r3, [pc, #72] @ (80045bc ) + 8004574: 2154 movs r1, #84 @ 0x54 + 8004576: 430a orrs r2, r1 + 8004578: 609a str r2, [r3, #8] + TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */ + 800457a: 4b10 ldr r3, [pc, #64] @ (80045bc ) + 800457c: 6a1a ldr r2, [r3, #32] + 800457e: 4b0f ldr r3, [pc, #60] @ (80045bc ) + 8004580: 2131 movs r1, #49 @ 0x31 + 8004582: 430a orrs r2, r1 + 8004584: 621a str r2, [r3, #32] + TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */ + 8004586: 4b0d ldr r3, [pc, #52] @ (80045bc ) + 8004588: 68da ldr r2, [r3, #12] + 800458a: 4b0c ldr r3, [pc, #48] @ (80045bc ) + 800458c: 2102 movs r1, #2 + 800458e: 430a orrs r2, r1 + 8004590: 60da str r2, [r3, #12] + TIM3->CR1 |= TIM_CR1_CEN; /* (5) */ + 8004592: 4b0a ldr r3, [pc, #40] @ (80045bc ) + 8004594: 681a ldr r2, [r3, #0] + 8004596: 4b09 ldr r3, [pc, #36] @ (80045bc ) + 8004598: 2101 movs r1, #1 + 800459a: 430a orrs r2, r1 + 800459c: 601a str r2, [r3, #0] + NVIC_EnableIRQ(TIM3_IRQn); + 800459e: 2010 movs r0, #16 + 80045a0: f7ff ff8a bl 80044b8 <__NVIC_EnableIRQ> +} + 80045a4: 46c0 nop @ (mov r8, r8) + 80045a6: 46bd mov sp, r7 + 80045a8: bd80 pop {r7, pc} + 80045aa: 46c0 nop @ (mov r8, r8) + 80045ac: 40021000 .word 0x40021000 + 80045b0: 48000400 .word 0x48000400 + 80045b4: fffffcff .word 0xfffffcff + 80045b8: fff0ffff .word 0xfff0ffff + 80045bc: 40000400 .word 0x40000400 + 80045c0: 00000201 .word 0x00000201 + +080045c4 : +void TIM14_Init(void) { //configure IN2 as rpm input PB1 TIM14 + 80045c4: b580 push {r7, lr} + 80045c6: af00 add r7, sp, #0 + // PB1 AF0 TIM14 Input1 + // prescaler 1:21 ->1/4uS tick (since APBx presc !=1, timer clocks = APBx_cls x 2) + RCC->AHBENR |= RCC_AHBENR_GPIOBEN; + 80045c8: 4b2c ldr r3, [pc, #176] @ (800467c ) + 80045ca: 695a ldr r2, [r3, #20] + 80045cc: 4b2b ldr r3, [pc, #172] @ (800467c ) + 80045ce: 2180 movs r1, #128 @ 0x80 + 80045d0: 02c9 lsls r1, r1, #11 + 80045d2: 430a orrs r2, r1 + 80045d4: 615a str r2, [r3, #20] + GPIOB->MODER &= ~(3 << (1 * 2)); + 80045d6: 4b2a ldr r3, [pc, #168] @ (8004680 ) + 80045d8: 681a ldr r2, [r3, #0] + 80045da: 4b29 ldr r3, [pc, #164] @ (8004680 ) + 80045dc: 210c movs r1, #12 + 80045de: 438a bics r2, r1 + 80045e0: 601a str r2, [r3, #0] + GPIOB->MODER |= (2 << (1 * 2)); + 80045e2: 4b27 ldr r3, [pc, #156] @ (8004680 ) + 80045e4: 681a ldr r2, [r3, #0] + 80045e6: 4b26 ldr r3, [pc, #152] @ (8004680 ) + 80045e8: 2108 movs r1, #8 + 80045ea: 430a orrs r2, r1 + 80045ec: 601a str r2, [r3, #0] + GPIOB->OTYPER &= ~(1 << 1 * 1); + 80045ee: 4b24 ldr r3, [pc, #144] @ (8004680 ) + 80045f0: 685a ldr r2, [r3, #4] + 80045f2: 4b23 ldr r3, [pc, #140] @ (8004680 ) + 80045f4: 2102 movs r1, #2 + 80045f6: 438a bics r2, r1 + 80045f8: 605a str r2, [r3, #4] + GPIOB->OSPEEDR &= ~(3 << (1 * 2)); + 80045fa: 4b21 ldr r3, [pc, #132] @ (8004680 ) + 80045fc: 689a ldr r2, [r3, #8] + 80045fe: 4b20 ldr r3, [pc, #128] @ (8004680 ) + 8004600: 210c movs r1, #12 + 8004602: 438a bics r2, r1 + 8004604: 609a str r2, [r3, #8] + GPIOB->PUPDR &= ~(3 << (1 * 2)); + 8004606: 4b1e ldr r3, [pc, #120] @ (8004680 ) + 8004608: 68da ldr r2, [r3, #12] + 800460a: 4b1d ldr r3, [pc, #116] @ (8004680 ) + 800460c: 210c movs r1, #12 + 800460e: 438a bics r2, r1 + 8004610: 60da str r2, [r3, #12] + GPIOB->AFR[0] &= ~(15 << (1 * 4)); + 8004612: 4b1b ldr r3, [pc, #108] @ (8004680 ) + 8004614: 6a1a ldr r2, [r3, #32] + 8004616: 4b1a ldr r3, [pc, #104] @ (8004680 ) + 8004618: 21f0 movs r1, #240 @ 0xf0 + 800461a: 438a bics r2, r1 + 800461c: 621a str r2, [r3, #32] + GPIOB->AFR[0] |= (0 << (1 * 4)); + 800461e: 4a18 ldr r2, [pc, #96] @ (8004680 ) + 8004620: 4b17 ldr r3, [pc, #92] @ (8004680 ) + 8004622: 6a12 ldr r2, [r2, #32] + 8004624: 621a str r2, [r3, #32] + RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; + 8004626: 4b15 ldr r3, [pc, #84] @ (800467c ) + 8004628: 69da ldr r2, [r3, #28] + 800462a: 4b14 ldr r3, [pc, #80] @ (800467c ) + 800462c: 2180 movs r1, #128 @ 0x80 + 800462e: 0049 lsls r1, r1, #1 + 8004630: 430a orrs r2, r1 + 8004632: 61da str r2, [r3, #28] + TIM14->ARR = 0xFFFF; + 8004634: 4b13 ldr r3, [pc, #76] @ (8004684 ) + 8004636: 4a14 ldr r2, [pc, #80] @ (8004688 ) + 8004638: 62da str r2, [r3, #44] @ 0x2c + TIM14->PSC = 599; + 800463a: 4b12 ldr r3, [pc, #72] @ (8004684 ) + 800463c: 4a13 ldr r2, [pc, #76] @ (800468c ) + 800463e: 629a str r2, [r3, #40] @ 0x28 + select the rising edge on CC1 (CC1P = 0, reset value) + and prescaler at each valid transition (IC1PS = 00, reset value) */ + /* (2) Enable capture by setting CC1E */ + /* (3) Enable interrupt on Capture/Compare */ + /* (4) Enable counter */ + TIM14->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/ + 8004640: 4b10 ldr r3, [pc, #64] @ (8004684 ) + 8004642: 699a ldr r2, [r3, #24] + 8004644: 4b0f ldr r3, [pc, #60] @ (8004684 ) + 8004646: 2131 movs r1, #49 @ 0x31 + 8004648: 430a orrs r2, r1 + 800464a: 619a str r2, [r3, #24] + TIM14->CCER |= TIM_CCER_CC1E; /* (2) */ + 800464c: 4b0d ldr r3, [pc, #52] @ (8004684 ) + 800464e: 6a1a ldr r2, [r3, #32] + 8004650: 4b0c ldr r3, [pc, #48] @ (8004684 ) + 8004652: 2101 movs r1, #1 + 8004654: 430a orrs r2, r1 + 8004656: 621a str r2, [r3, #32] + TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */ + 8004658: 4b0a ldr r3, [pc, #40] @ (8004684 ) + 800465a: 68da ldr r2, [r3, #12] + 800465c: 4b09 ldr r3, [pc, #36] @ (8004684 ) + 800465e: 2102 movs r1, #2 + 8004660: 430a orrs r2, r1 + 8004662: 60da str r2, [r3, #12] + TIM14->CR1 |= TIM_CR1_CEN; /* (4) */ + 8004664: 4b07 ldr r3, [pc, #28] @ (8004684 ) + 8004666: 681a ldr r2, [r3, #0] + 8004668: 4b06 ldr r3, [pc, #24] @ (8004684 ) + 800466a: 2101 movs r1, #1 + 800466c: 430a orrs r2, r1 + 800466e: 601a str r2, [r3, #0] + NVIC_EnableIRQ(TIM14_IRQn); + 8004670: 2013 movs r0, #19 + 8004672: f7ff ff21 bl 80044b8 <__NVIC_EnableIRQ> +} + 8004676: 46c0 nop @ (mov r8, r8) + 8004678: 46bd mov sp, r7 + 800467a: bd80 pop {r7, pc} + 800467c: 40021000 .word 0x40021000 + 8004680: 48000400 .word 0x48000400 + 8004684: 40002000 .word 0x40002000 + 8004688: 0000ffff .word 0x0000ffff + 800468c: 00000257 .word 0x00000257 + +08004690 : +void TIM3_IRQHandler(void) { + 8004690: b580 push {r7, lr} + 8004692: af00 add r7, sp, #0 + if ((TIM3->SR & TIM_SR_CC1IF) != 0) { + 8004694: 4b15 ldr r3, [pc, #84] @ (80046ec ) + 8004696: 691b ldr r3, [r3, #16] + 8004698: 2202 movs r2, #2 + 800469a: 4013 ands r3, r2 + 800469c: d023 beq.n 80046e6 + if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */ + 800469e: 4b13 ldr r3, [pc, #76] @ (80046ec ) + 80046a0: 691a ldr r2, [r3, #16] + 80046a2: 2380 movs r3, #128 @ 0x80 + 80046a4: 009b lsls r3, r3, #2 + 80046a6: 4013 ands r3, r2 + 80046a8: d006 beq.n 80046b8 + { + /* Overflow error management */ + /* Reinitialize the laps computing */ + TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */ + 80046aa: 4b10 ldr r3, [pc, #64] @ (80046ec ) + 80046ac: 691a ldr r2, [r3, #16] + 80046ae: 4b0f ldr r3, [pc, #60] @ (80046ec ) + 80046b0: 490f ldr r1, [pc, #60] @ (80046f0 ) + 80046b2: 400a ands r2, r1 + 80046b4: 611a str r2, [r3, #16] + return; + 80046b6: e016 b.n 80046e6 + } else { + counter0 = TIM3->CCR1; + 80046b8: 4b0c ldr r3, [pc, #48] @ (80046ec ) + 80046ba: 6b5a ldr r2, [r3, #52] @ 0x34 + 80046bc: 4b0d ldr r3, [pc, #52] @ (80046f4 ) + 80046be: 601a str r2, [r3, #0] + var.idle_dc = (TIM3->CCR2) * 1000 / TIM3->CCR1; //Get DC + 80046c0: 4b0a ldr r3, [pc, #40] @ (80046ec ) + 80046c2: 6b9a ldr r2, [r3, #56] @ 0x38 + 80046c4: 0013 movs r3, r2 + 80046c6: 015b lsls r3, r3, #5 + 80046c8: 1a9b subs r3, r3, r2 + 80046ca: 009b lsls r3, r3, #2 + 80046cc: 189b adds r3, r3, r2 + 80046ce: 00db lsls r3, r3, #3 + 80046d0: 001a movs r2, r3 + 80046d2: 4b06 ldr r3, [pc, #24] @ (80046ec ) + 80046d4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80046d6: 0019 movs r1, r3 + 80046d8: 0010 movs r0, r2 + 80046da: f7fb fd15 bl 8000108 <__udivsi3> + 80046de: 0003 movs r3, r0 + 80046e0: b29a uxth r2, r3 + 80046e2: 4b05 ldr r3, [pc, #20] @ (80046f8 ) + 80046e4: 851a strh r2, [r3, #40] @ 0x28 + } + } else { + /* Unexpected Interrupt */ + /* Manage an error for robust application */ + } +} + 80046e6: 46bd mov sp, r7 + 80046e8: bd80 pop {r7, pc} + 80046ea: 46c0 nop @ (mov r8, r8) + 80046ec: 40000400 .word 0x40000400 + 80046f0: fffffdfd .word 0xfffffdfd + 80046f4: 20000a44 .word 0x20000a44 + 80046f8: 20000998 .word 0x20000998 + +080046fc : +void TIM14_IRQHandler(void) { + 80046fc: b580 push {r7, lr} + 80046fe: af00 add r7, sp, #0 + if ((TIM14->SR & TIM_SR_CC1IF) != 0) { + 8004700: 4b25 ldr r3, [pc, #148] @ (8004798 ) + 8004702: 691b ldr r3, [r3, #16] + 8004704: 2202 movs r2, #2 + 8004706: 4013 ands r3, r2 + 8004708: d043 beq.n 8004792 + if ((TIM14->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */ + 800470a: 4b23 ldr r3, [pc, #140] @ (8004798 ) + 800470c: 691a ldr r2, [r3, #16] + 800470e: 2380 movs r3, #128 @ 0x80 + 8004710: 009b lsls r3, r3, #2 + 8004712: 4013 ands r3, r2 + 8004714: d00c beq.n 8004730 + { + /* Overflow error management */ + /* Reinitialize the laps computing */ + TIM14->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */ + 8004716: 4b20 ldr r3, [pc, #128] @ (8004798 ) + 8004718: 691a ldr r2, [r3, #16] + 800471a: 4b1f ldr r3, [pc, #124] @ (8004798 ) + 800471c: 491f ldr r1, [pc, #124] @ (800479c ) + 800471e: 400a ands r2, r1 + 8004720: 611a str r2, [r3, #16] + var.rpm = 0; + 8004722: 4b1f ldr r3, [pc, #124] @ (80047a0 ) + 8004724: 2200 movs r2, #0 + 8004726: 865a strh r2, [r3, #50] @ 0x32 + gap = 0; + 8004728: 4b1e ldr r3, [pc, #120] @ (80047a4 ) + 800472a: 2200 movs r2, #0 + 800472c: 701a strb r2, [r3, #0] + return; + 800472e: e030 b.n 8004792 + } + if (gap == 0) /* Test if it is the first rising edge */ + 8004730: 4b1c ldr r3, [pc, #112] @ (80047a4 ) + 8004732: 781b ldrb r3, [r3, #0] + 8004734: 2b00 cmp r3, #0 + 8004736: d107 bne.n 8004748 + { + counter0 = TIM14->CCR1; /* Read the capture counter which clears the + 8004738: 4b17 ldr r3, [pc, #92] @ (8004798 ) + 800473a: 6b5a ldr r2, [r3, #52] @ 0x34 + 800473c: 4b1a ldr r3, [pc, #104] @ (80047a8 ) + 800473e: 601a str r2, [r3, #0] + CC1ICF */ + gap = 1; /* Indicate that the first rising edge has yet been detected */ + 8004740: 4b18 ldr r3, [pc, #96] @ (80047a4 ) + 8004742: 2201 movs r2, #1 + 8004744: 701a strb r2, [r3, #0] + 8004746: e024 b.n 8004792 + } else { + counter1 = TIM14->CCR1; /* Read the capture counter which clears the + 8004748: 4b13 ldr r3, [pc, #76] @ (8004798 ) + 800474a: 6b5a ldr r2, [r3, #52] @ 0x34 + 800474c: 4b17 ldr r3, [pc, #92] @ (80047ac ) + 800474e: 601a str r2, [r3, #0] + CC1ICF */ + if (counter1 > counter0) /* Check capture counter overflow */ + 8004750: 4b16 ldr r3, [pc, #88] @ (80047ac ) + 8004752: 681a ldr r2, [r3, #0] + 8004754: 4b14 ldr r3, [pc, #80] @ (80047a8 ) + 8004756: 681b ldr r3, [r3, #0] + 8004758: 429a cmp r2, r3 + 800475a: d907 bls.n 800476c + { + Counter = counter1 - counter0; + 800475c: 4b13 ldr r3, [pc, #76] @ (80047ac ) + 800475e: 681a ldr r2, [r3, #0] + 8004760: 4b11 ldr r3, [pc, #68] @ (80047a8 ) + 8004762: 681b ldr r3, [r3, #0] + 8004764: 1ad2 subs r2, r2, r3 + 8004766: 4b12 ldr r3, [pc, #72] @ (80047b0 ) + 8004768: 601a str r2, [r3, #0] + 800476a: e009 b.n 8004780 + } else { + Counter = counter1 + 0xFFFF - counter0 + 1; + 800476c: 4b0f ldr r3, [pc, #60] @ (80047ac ) + 800476e: 681a ldr r2, [r3, #0] + 8004770: 4b0d ldr r3, [pc, #52] @ (80047a8 ) + 8004772: 681b ldr r3, [r3, #0] + 8004774: 1ad3 subs r3, r2, r3 + 8004776: 2280 movs r2, #128 @ 0x80 + 8004778: 0252 lsls r2, r2, #9 + 800477a: 189a adds r2, r3, r2 + 800477c: 4b0c ldr r3, [pc, #48] @ (80047b0 ) + 800477e: 601a str r2, [r3, #0] + } + counter0 = counter1; + 8004780: 4b0a ldr r3, [pc, #40] @ (80047ac ) + 8004782: 681a ldr r2, [r3, #0] + 8004784: 4b08 ldr r3, [pc, #32] @ (80047a8 ) + 8004786: 601a str r2, [r3, #0] + var.rpm = Counter; + 8004788: 4b09 ldr r3, [pc, #36] @ (80047b0 ) + 800478a: 681b ldr r3, [r3, #0] + 800478c: b29a uxth r2, r3 + 800478e: 4b04 ldr r3, [pc, #16] @ (80047a0 ) + 8004790: 865a strh r2, [r3, #50] @ 0x32 + } + } else { + /* Unexpected Interrupt */ + /* Manage an error for robust application */ + } +} + 8004792: 46bd mov sp, r7 + 8004794: bd80 pop {r7, pc} + 8004796: 46c0 nop @ (mov r8, r8) + 8004798: 40002000 .word 0x40002000 + 800479c: fffffdfd .word 0xfffffdfd + 80047a0: 20000998 .word 0x20000998 + 80047a4: 20000a50 .word 0x20000a50 + 80047a8: 20000a44 .word 0x20000a44 + 80047ac: 20000a48 .word 0x20000a48 + 80047b0: 20000a4c .word 0x20000a4c + +080047b4 <__NVIC_EnableIRQ>: +{ + 80047b4: b580 push {r7, lr} + 80047b6: b082 sub sp, #8 + 80047b8: af00 add r7, sp, #0 + 80047ba: 0002 movs r2, r0 + 80047bc: 1dfb adds r3, r7, #7 + 80047be: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 80047c0: 1dfb adds r3, r7, #7 + 80047c2: 781b ldrb r3, [r3, #0] + 80047c4: 2b7f cmp r3, #127 @ 0x7f + 80047c6: d809 bhi.n 80047dc <__NVIC_EnableIRQ+0x28> + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80047c8: 1dfb adds r3, r7, #7 + 80047ca: 781b ldrb r3, [r3, #0] + 80047cc: 001a movs r2, r3 + 80047ce: 231f movs r3, #31 + 80047d0: 401a ands r2, r3 + 80047d2: 4b04 ldr r3, [pc, #16] @ (80047e4 <__NVIC_EnableIRQ+0x30>) + 80047d4: 2101 movs r1, #1 + 80047d6: 4091 lsls r1, r2 + 80047d8: 000a movs r2, r1 + 80047da: 601a str r2, [r3, #0] +} + 80047dc: 46c0 nop @ (mov r8, r8) + 80047de: 46bd mov sp, r7 + 80047e0: b002 add sp, #8 + 80047e2: bd80 pop {r7, pc} + 80047e4: e000e100 .word 0xe000e100 + +080047e8
: + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + 80047e8: b580 push {r7, lr} + 80047ea: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80047ec: f002 f824 bl 8006838 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80047f0: f000 f90c bl 8004a0c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80047f4: f000 fa3c bl 8004c70 + MX_ADC_Init(); + 80047f8: f000 f96e bl 8004ad8 +// MX_CAN_Init(); + MX_USART1_UART_Init(); + 80047fc: f000 fa08 bl 8004c10 + /* USER CODE BEGIN 2 */ + + //load flash copy of config to RAM + // memcpy((void*)&config_ram,(void*)(0x0800F000), sizeof(config_t)); + memcpy((void*) &config_ram, (void*) &config_flash, sizeof(config_t)); + 8004800: 4a7a ldr r2, [pc, #488] @ (80049ec ) + 8004802: 4b7b ldr r3, [pc, #492] @ (80049f0 ) + 8004804: 0010 movs r0, r2 + 8004806: 0019 movs r1, r3 + 8004808: 23d6 movs r3, #214 @ 0xd6 + 800480a: 009b lsls r3, r3, #2 + 800480c: 001a movs r2, r3 + 800480e: f004 f8ab bl 8008968 + config = &config_ram; + 8004812: 4b78 ldr r3, [pc, #480] @ (80049f4 ) + 8004814: 4a75 ldr r2, [pc, #468] @ (80049ec ) + 8004816: 601a str r2, [r3, #0] + + //calculate gain and offset for PPS and TPS calc + Apply_Sensor_Calibration(); + 8004818: f7fe fc10 bl 800303c + config->config_bits &= ~CONFIG_TESTMODE_F; + 800481c: 4b75 ldr r3, [pc, #468] @ (80049f4 ) + 800481e: 681b ldr r3, [r3, #0] + 8004820: 4a75 ldr r2, [pc, #468] @ (80049f8 ) + 8004822: 5a9b ldrh r3, [r3, r2] + 8004824: b29a uxth r2, r3 + 8004826: 4b73 ldr r3, [pc, #460] @ (80049f4 ) + 8004828: 681b ldr r3, [r3, #0] + 800482a: 2104 movs r1, #4 + 800482c: 438a bics r2, r1 + 800482e: b291 uxth r1, r2 + 8004830: 4a71 ldr r2, [pc, #452] @ (80049f8 ) + 8004832: 5299 strh r1, [r3, r2] + +//clear momms + memset((void*) &var, 0, sizeof(var_t)); + 8004834: 4b71 ldr r3, [pc, #452] @ (80049fc ) + 8004836: 2234 movs r2, #52 @ 0x34 + 8004838: 2100 movs r1, #0 + 800483a: 0018 movs r0, r3 + 800483c: f004 f868 bl 8008910 + //Initialize TS Comms + Comms_Init(); + 8004840: f001 fb98 bl 8005f74 + NVIC_EnableIRQ(USART1_IRQn); + 8004844: 201b movs r0, #27 + 8004846: f7ff ffb5 bl 80047b4 <__NVIC_EnableIRQ> + +// check if safety features are enabled + if (config->config_bits & CONFIG_SAFETY_FEATURES_F) { + 800484a: 4b6a ldr r3, [pc, #424] @ (80049f4 ) + 800484c: 681b ldr r3, [r3, #0] + 800484e: 4a6a ldr r2, [pc, #424] @ (80049f8 ) + 8004850: 5a9b ldrh r3, [r3, r2] + 8004852: b29b uxth r3, r3 + 8004854: 001a movs r2, r3 + 8004856: 2308 movs r3, #8 + 8004858: 4013 ands r3, r2 + 800485a: d00c beq.n 8004876 + Check_Safety_Limits(); + 800485c: f000 fd6a bl 8005334 + Safety_TPS_Safety_Timer_Start(); + 8004860: f001 f9a6 bl 8005bb0 + //TODO Watch_Dog_Init(); + // change status + var.status1 |= DBW_STATUS1_SAFETY_F; + 8004864: 4b65 ldr r3, [pc, #404] @ (80049fc ) + 8004866: 88db ldrh r3, [r3, #6] + 8004868: b29b uxth r3, r3 + 800486a: 2201 movs r2, #1 + 800486c: 4313 orrs r3, r2 + 800486e: b29a uxth r2, r3 + 8004870: 4b62 ldr r3, [pc, #392] @ (80049fc ) + 8004872: 80da strh r2, [r3, #6] + 8004874: e007 b.n 8004886 + } +// if not change status to safy disabled + else + var.status1 &= ~DBW_STATUS1_SAFETY_F; + 8004876: 4b61 ldr r3, [pc, #388] @ (80049fc ) + 8004878: 88db ldrh r3, [r3, #6] + 800487a: b29b uxth r3, r3 + 800487c: 2201 movs r2, #1 + 800487e: 4393 bics r3, r2 + 8004880: b29a uxth r2, r3 + 8004882: 4b5e ldr r3, [pc, #376] @ (80049fc ) + 8004884: 80da strh r2, [r3, #6] + +// Check if CAN has to be initialized + if ((config->pps2tps_option == PPS2TPS_OPTION_MS3_CAN) + 8004886: 4b5b ldr r3, [pc, #364] @ (80049f4 ) + 8004888: 681b ldr r3, [r3, #0] + 800488a: 7e9b ldrb r3, [r3, #26] + 800488c: b2db uxtb r3, r3 + 800488e: 2b01 cmp r3, #1 + 8004890: d009 beq.n 80048a6 + || (config->idle_input_option == IDLE_OPTION_MS_CAN) + 8004892: 4b58 ldr r3, [pc, #352] @ (80049f4 ) + 8004894: 681b ldr r3, [r3, #0] + 8004896: 7edb ldrb r3, [r3, #27] + 8004898: b2db uxtb r3, r3 + 800489a: 2b03 cmp r3, #3 + 800489c: d003 beq.n 80048a6 + || config->can_ms29bit_options == 0x01) { + 800489e: 4b55 ldr r3, [pc, #340] @ (80049f4 ) + 80048a0: 681b ldr r3, [r3, #0] + 80048a2: 4a57 ldr r2, [pc, #348] @ (8004a00 ) + 80048a4: 5c9b ldrb r3, [r3, r2] +// Can_Init(); + + } + if (config->idle_input_option == IDLE_OPTION_PWM_INPUT1) { + 80048a6: 4b53 ldr r3, [pc, #332] @ (80049f4 ) + 80048a8: 681b ldr r3, [r3, #0] + 80048aa: 7edb ldrb r3, [r3, #27] + 80048ac: b2db uxtb r3, r3 + 80048ae: 2b01 cmp r3, #1 + 80048b0: d101 bne.n 80048b6 + TIM3_Init(); + 80048b2: f7ff fe1b bl 80044ec + } + if (1) { + TIM14_Init(); //rpm input init + 80048b6: f7ff fe85 bl 80045c4 + TIM16_Init(); // vss out init + 80048ba: f000 fc79 bl 80051b0 + TIM17_Init(); //Mazda rx8 can message init + 80048be: f000 fcb1 bl 8005224 + } + Adc_Init(); + 80048c2: f7fd ff17 bl 80026f4 + DBW_Init(); + 80048c6: f7fe fcc3 bl 8003250 + DBW_Pwm_Init(); + 80048ca: f7ff f82d bl 8003928 + +//check if program flash is write protected and set status + if (FLASH->WRPR & 0x00003FFF) + 80048ce: 4b4d ldr r3, [pc, #308] @ (8004a04 ) + 80048d0: 6a1b ldr r3, [r3, #32] + 80048d2: 049b lsls r3, r3, #18 + 80048d4: 0c9b lsrs r3, r3, #18 + 80048d6: d009 beq.n 80048ec + var.status0 |= DBW_STATUS0_UNPROTECTED_F; + 80048d8: 4b48 ldr r3, [pc, #288] @ (80049fc ) + 80048da: 889b ldrh r3, [r3, #4] + 80048dc: b29b uxth r3, r3 + 80048de: 2280 movs r2, #128 @ 0x80 + 80048e0: 0152 lsls r2, r2, #5 + 80048e2: 4313 orrs r3, r2 + 80048e4: b29a uxth r2, r3 + 80048e6: 4b45 ldr r3, [pc, #276] @ (80049fc ) + 80048e8: 809a strh r2, [r3, #4] + 80048ea: e007 b.n 80048fc + else + var.status0 &= ~DBW_STATUS0_UNPROTECTED_F; + 80048ec: 4b43 ldr r3, [pc, #268] @ (80049fc ) + 80048ee: 889b ldrh r3, [r3, #4] + 80048f0: b29b uxth r3, r3 + 80048f2: 4a45 ldr r2, [pc, #276] @ (8004a08 ) + 80048f4: 4013 ands r3, r2 + 80048f6: b29a uxth r2, r3 + 80048f8: 4b40 ldr r3, [pc, #256] @ (80049fc ) + 80048fa: 809a strh r2, [r3, #4] + +//check if agreement is set if so start DBW drive + if (config->config_bits & CONFIG_AGREEMENT_F) { + 80048fc: 4b3d ldr r3, [pc, #244] @ (80049f4 ) + 80048fe: 681b ldr r3, [r3, #0] + 8004900: 4a3d ldr r2, [pc, #244] @ (80049f8 ) + 8004902: 5a9b ldrh r3, [r3, r2] + 8004904: b29b uxth r3, r3 + 8004906: 001a movs r2, r3 + 8004908: 2301 movs r3, #1 + 800490a: 4013 ands r3, r2 + 800490c: d008 beq.n 8004920 + var.status0 |= DBW_STATUS0_AGREEMENT_F; + 800490e: 4b3b ldr r3, [pc, #236] @ (80049fc ) + 8004910: 889b ldrh r3, [r3, #4] + 8004912: b29b uxth r3, r3 + 8004914: 2202 movs r2, #2 + 8004916: 4313 orrs r3, r2 + 8004918: b29a uxth r2, r3 + 800491a: 4b38 ldr r3, [pc, #224] @ (80049fc ) + 800491c: 809a strh r2, [r3, #4] + 800491e: e007 b.n 8004930 + } else + var.status0 &= ~DBW_STATUS0_AGREEMENT_F; + 8004920: 4b36 ldr r3, [pc, #216] @ (80049fc ) + 8004922: 889b ldrh r3, [r3, #4] + 8004924: b29b uxth r3, r3 + 8004926: 2202 movs r2, #2 + 8004928: 4393 bics r3, r2 + 800492a: b29a uxth r2, r3 + 800492c: 4b33 ldr r3, [pc, #204] @ (80049fc ) + 800492e: 809a strh r2, [r3, #4] + +// check if TPS and PPS are calibrated + + if (config->config_bits & CONFIG_SENSORS_CALIBRATED_F) { + 8004930: 4b30 ldr r3, [pc, #192] @ (80049f4 ) + 8004932: 681b ldr r3, [r3, #0] + 8004934: 4a30 ldr r2, [pc, #192] @ (80049f8 ) + 8004936: 5a9b ldrh r3, [r3, r2] + 8004938: b29b uxth r3, r3 + 800493a: 001a movs r2, r3 + 800493c: 2302 movs r3, #2 + 800493e: 4013 ands r3, r2 + 8004940: d008 beq.n 8004954 + var.status0 |= DBW_STATUS0_SENSOR_CAL_F; + 8004942: 4b2e ldr r3, [pc, #184] @ (80049fc ) + 8004944: 889b ldrh r3, [r3, #4] + 8004946: b29b uxth r3, r3 + 8004948: 2204 movs r2, #4 + 800494a: 4313 orrs r3, r2 + 800494c: b29a uxth r2, r3 + 800494e: 4b2b ldr r3, [pc, #172] @ (80049fc ) + 8004950: 809a strh r2, [r3, #4] + 8004952: e007 b.n 8004964 + } + + else { + var.status0 &= ~DBW_STATUS0_SENSOR_CAL_F; + 8004954: 4b29 ldr r3, [pc, #164] @ (80049fc ) + 8004956: 889b ldrh r3, [r3, #4] + 8004958: b29b uxth r3, r3 + 800495a: 2204 movs r2, #4 + 800495c: 4393 bics r3, r2 + 800495e: b29a uxth r2, r3 + 8004960: 4b26 ldr r3, [pc, #152] @ (80049fc ) + 8004962: 809a strh r2, [r3, #4] + } + +// start DBW if sensors are calibrated and agreement is accepted + if ((var.status0 & DBW_STATUS0_AGREEMENT_F) + 8004964: 4b25 ldr r3, [pc, #148] @ (80049fc ) + 8004966: 889b ldrh r3, [r3, #4] + 8004968: b29b uxth r3, r3 + 800496a: 001a movs r2, r3 + 800496c: 2302 movs r3, #2 + 800496e: 4013 ands r3, r2 + 8004970: d009 beq.n 8004986 + && (var.status0 & DBW_STATUS0_SENSOR_CAL_F)) { + 8004972: 4b22 ldr r3, [pc, #136] @ (80049fc ) + 8004974: 889b ldrh r3, [r3, #4] + 8004976: b29b uxth r3, r3 + 8004978: 001a movs r2, r3 + 800497a: 2304 movs r3, #4 + 800497c: 4013 ands r3, r2 + 800497e: d002 beq.n 8004986 + DBW_Start(); + 8004980: f7ff fb48 bl 8004014 + 8004984: e001 b.n 800498a + } else + DBW_Stop(); + 8004986: f7ff fb5b bl 8004040 + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ + +// is something to be transmitted on serial + Poll_Tx(); + 800498a: f001 fd85 bl 8006498 + +// Update WDT and check ADC range if safety features are enabled + if ((var.status1 & DBW_STATUS1_SAFETY_F) && var.clock > 1000) { + 800498e: 4b1b ldr r3, [pc, #108] @ (80049fc ) + 8004990: 88db ldrh r3, [r3, #6] + 8004992: b29b uxth r3, r3 + 8004994: 001a movs r2, r3 + 8004996: 2301 movs r3, #1 + 8004998: 4013 ands r3, r2 + 800499a: d009 beq.n 80049b0 + 800499c: 4b17 ldr r3, [pc, #92] @ (80049fc ) + 800499e: 681a ldr r2, [r3, #0] + 80049a0: 23fa movs r3, #250 @ 0xfa + 80049a2: 009b lsls r3, r3, #2 + 80049a4: 429a cmp r2, r3 + 80049a6: d903 bls.n 80049b0 + //TODO Watch_Dog_Update(); + Check_Adc_Range(); + 80049a8: f000 fe5e bl 8005668 + Check_TPS_Target(); + 80049ac: f001 f922 bl 8005bf4 + } + +//check if tesmode is turned on + if (config->config_bits & CONFIG_TESTMODE_F) { + 80049b0: 4b10 ldr r3, [pc, #64] @ (80049f4 ) + 80049b2: 681b ldr r3, [r3, #0] + 80049b4: 4a10 ldr r2, [pc, #64] @ (80049f8 ) + 80049b6: 5a9b ldrh r3, [r3, r2] + 80049b8: b29b uxth r3, r3 + 80049ba: 001a movs r2, r3 + 80049bc: 2304 movs r3, #4 + 80049be: 4013 ands r3, r2 + 80049c0: d00c beq.n 80049dc + var.status0 &= ~DBW_STATUS0_READY_F; + 80049c2: 4b0e ldr r3, [pc, #56] @ (80049fc ) + 80049c4: 889b ldrh r3, [r3, #4] + 80049c6: b29b uxth r3, r3 + 80049c8: 2201 movs r2, #1 + 80049ca: 4393 bics r3, r2 + 80049cc: b29a uxth r2, r3 + 80049ce: 4b0b ldr r3, [pc, #44] @ (80049fc ) + 80049d0: 809a strh r2, [r3, #4] + DBW_TPS_AutoCal(); + 80049d2: f7ff fb4b bl 800406c + DBW_Read_sensors(); + 80049d6: f7ff fc55 bl 8004284 + 80049da: e001 b.n 80049e0 + } else { + DBW_Process(); + 80049dc: f7fe fc82 bl 80032e4 + } + + CAN_Send_TX_Buffer(); + 80049e0: f7fe f830 bl 8002a44 + if (1) { + MAZDA_CAN_Read(); + 80049e4: f000 fb54 bl 8005090 + Poll_Tx(); + 80049e8: e7cf b.n 800498a + 80049ea: 46c0 nop @ (mov r8, r8) + 80049ec: 20000640 .word 0x20000640 + 80049f0: 0800f000 .word 0x0800f000 + 80049f4: 200009cc .word 0x200009cc + 80049f8: 0000033a .word 0x0000033a + 80049fc: 20000998 .word 0x20000998 + 8004a00: 00000353 .word 0x00000353 + 8004a04: 40022000 .word 0x40022000 + 8004a08: ffffefff .word 0xffffefff + +08004a0c : + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) { + 8004a0c: b590 push {r4, r7, lr} + 8004a0e: b099 sub sp, #100 @ 0x64 + 8004a10: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + 8004a12: 242c movs r4, #44 @ 0x2c + 8004a14: 193b adds r3, r7, r4 + 8004a16: 0018 movs r0, r3 + 8004a18: 2334 movs r3, #52 @ 0x34 + 8004a1a: 001a movs r2, r3 + 8004a1c: 2100 movs r1, #0 + 8004a1e: f003 ff77 bl 8008910 + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + 8004a22: 231c movs r3, #28 + 8004a24: 18fb adds r3, r7, r3 + 8004a26: 0018 movs r0, r3 + 8004a28: 2310 movs r3, #16 + 8004a2a: 001a movs r2, r3 + 8004a2c: 2100 movs r1, #0 + 8004a2e: f003 ff6f bl 8008910 + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; + 8004a32: 003b movs r3, r7 + 8004a34: 0018 movs r0, r3 + 8004a36: 231c movs r3, #28 + 8004a38: 001a movs r2, r3 + 8004a3a: 2100 movs r1, #0 + 8004a3c: f003 ff68 bl 8008910 + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI14 + 8004a40: 0021 movs r1, r4 + 8004a42: 187b adds r3, r7, r1 + 8004a44: 2211 movs r2, #17 + 8004a46: 601a str r2, [r3, #0] + | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8004a48: 187b adds r3, r7, r1 + 8004a4a: 2201 movs r2, #1 + 8004a4c: 605a str r2, [r3, #4] + RCC_OscInitStruct.HSI14State = RCC_HSI14_ON; + 8004a4e: 187b adds r3, r7, r1 + 8004a50: 2201 movs r2, #1 + 8004a52: 615a str r2, [r3, #20] + RCC_OscInitStruct.HSI14CalibrationValue = 16; + 8004a54: 187b adds r3, r7, r1 + 8004a56: 2210 movs r2, #16 + 8004a58: 619a str r2, [r3, #24] + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8004a5a: 187b adds r3, r7, r1 + 8004a5c: 2202 movs r2, #2 + 8004a5e: 625a str r2, [r3, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8004a60: 187b adds r3, r7, r1 + 8004a62: 2280 movs r2, #128 @ 0x80 + 8004a64: 0252 lsls r2, r2, #9 + 8004a66: 629a str r2, [r3, #40] @ 0x28 + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; + 8004a68: 187b adds r3, r7, r1 + 8004a6a: 22a0 movs r2, #160 @ 0xa0 + 8004a6c: 0392 lsls r2, r2, #14 + 8004a6e: 62da str r2, [r3, #44] @ 0x2c + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; + 8004a70: 187b adds r3, r7, r1 + 8004a72: 2201 movs r2, #1 + 8004a74: 631a str r2, [r3, #48] @ 0x30 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + 8004a76: 187b adds r3, r7, r1 + 8004a78: 0018 movs r0, r3 + 8004a7a: f002 fdf5 bl 8007668 + 8004a7e: 1e03 subs r3, r0, #0 + 8004a80: d001 beq.n 8004a86 + Error_Handler(); + 8004a82: f000 f94d bl 8004d20 + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + 8004a86: 211c movs r1, #28 + 8004a88: 187b adds r3, r7, r1 + 8004a8a: 2207 movs r2, #7 + 8004a8c: 601a str r2, [r3, #0] + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8004a8e: 187b adds r3, r7, r1 + 8004a90: 2202 movs r2, #2 + 8004a92: 605a str r2, [r3, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8004a94: 187b adds r3, r7, r1 + 8004a96: 2200 movs r2, #0 + 8004a98: 609a str r2, [r3, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8004a9a: 187b adds r3, r7, r1 + 8004a9c: 2200 movs r2, #0 + 8004a9e: 60da str r2, [r3, #12] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + 8004aa0: 187b adds r3, r7, r1 + 8004aa2: 2101 movs r1, #1 + 8004aa4: 0018 movs r0, r3 + 8004aa6: f003 f965 bl 8007d74 + 8004aaa: 1e03 subs r3, r0, #0 + 8004aac: d001 beq.n 8004ab2 + Error_Handler(); + 8004aae: f000 f937 bl 8004d20 + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; + 8004ab2: 003b movs r3, r7 + 8004ab4: 2201 movs r2, #1 + 8004ab6: 601a str r2, [r3, #0] + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + 8004ab8: 003b movs r3, r7 + 8004aba: 2200 movs r2, #0 + 8004abc: 609a str r2, [r3, #8] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + 8004abe: 003b movs r3, r7 + 8004ac0: 0018 movs r0, r3 + 8004ac2: f003 fad1 bl 8008068 + 8004ac6: 1e03 subs r3, r0, #0 + 8004ac8: d001 beq.n 8004ace + Error_Handler(); + 8004aca: f000 f929 bl 8004d20 + } +} + 8004ace: 46c0 nop @ (mov r8, r8) + 8004ad0: 46bd mov sp, r7 + 8004ad2: b019 add sp, #100 @ 0x64 + 8004ad4: bd90 pop {r4, r7, pc} + ... + +08004ad8 : +/** + * @brief ADC Initialization Function + * @param None + * @retval None + */ +static void MX_ADC_Init(void) { + 8004ad8: b580 push {r7, lr} + 8004ada: b084 sub sp, #16 + 8004adc: af00 add r7, sp, #0 + + /* USER CODE BEGIN ADC_Init 0 */ + + /* USER CODE END ADC_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = { 0 }; + 8004ade: 1d3b adds r3, r7, #4 + 8004ae0: 0018 movs r0, r3 + 8004ae2: 230c movs r3, #12 + 8004ae4: 001a movs r2, r3 + 8004ae6: 2100 movs r1, #0 + 8004ae8: f003 ff12 bl 8008910 + /* USER CODE BEGIN ADC_Init 1 */ + + /* USER CODE END ADC_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc.Instance = ADC1; + 8004aec: 4b46 ldr r3, [pc, #280] @ (8004c08 ) + 8004aee: 4a47 ldr r2, [pc, #284] @ (8004c0c ) + 8004af0: 601a str r2, [r3, #0] + hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; + 8004af2: 4b45 ldr r3, [pc, #276] @ (8004c08 ) + 8004af4: 2200 movs r2, #0 + 8004af6: 605a str r2, [r3, #4] + hadc.Init.Resolution = ADC_RESOLUTION_12B; + 8004af8: 4b43 ldr r3, [pc, #268] @ (8004c08 ) + 8004afa: 2200 movs r2, #0 + 8004afc: 609a str r2, [r3, #8] + hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 8004afe: 4b42 ldr r3, [pc, #264] @ (8004c08 ) + 8004b00: 2200 movs r2, #0 + 8004b02: 60da str r2, [r3, #12] + hadc.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + 8004b04: 4b40 ldr r3, [pc, #256] @ (8004c08 ) + 8004b06: 2201 movs r2, #1 + 8004b08: 611a str r2, [r3, #16] + hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 8004b0a: 4b3f ldr r3, [pc, #252] @ (8004c08 ) + 8004b0c: 2204 movs r2, #4 + 8004b0e: 615a str r2, [r3, #20] + hadc.Init.LowPowerAutoWait = DISABLE; + 8004b10: 4b3d ldr r3, [pc, #244] @ (8004c08 ) + 8004b12: 2200 movs r2, #0 + 8004b14: 761a strb r2, [r3, #24] + hadc.Init.LowPowerAutoPowerOff = DISABLE; + 8004b16: 4b3c ldr r3, [pc, #240] @ (8004c08 ) + 8004b18: 2200 movs r2, #0 + 8004b1a: 765a strb r2, [r3, #25] + hadc.Init.ContinuousConvMode = DISABLE; + 8004b1c: 4b3a ldr r3, [pc, #232] @ (8004c08 ) + 8004b1e: 2200 movs r2, #0 + 8004b20: 769a strb r2, [r3, #26] + hadc.Init.DiscontinuousConvMode = DISABLE; + 8004b22: 4b39 ldr r3, [pc, #228] @ (8004c08 ) + 8004b24: 2200 movs r2, #0 + 8004b26: 76da strb r2, [r3, #27] + hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 8004b28: 4b37 ldr r3, [pc, #220] @ (8004c08 ) + 8004b2a: 22c2 movs r2, #194 @ 0xc2 + 8004b2c: 32ff adds r2, #255 @ 0xff + 8004b2e: 61da str r2, [r3, #28] + hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 8004b30: 4b35 ldr r3, [pc, #212] @ (8004c08 ) + 8004b32: 2200 movs r2, #0 + 8004b34: 621a str r2, [r3, #32] + hadc.Init.DMAContinuousRequests = DISABLE; + 8004b36: 4b34 ldr r3, [pc, #208] @ (8004c08 ) + 8004b38: 2224 movs r2, #36 @ 0x24 + 8004b3a: 2100 movs r1, #0 + 8004b3c: 5499 strb r1, [r3, r2] + hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + 8004b3e: 4b32 ldr r3, [pc, #200] @ (8004c08 ) + 8004b40: 2201 movs r2, #1 + 8004b42: 629a str r2, [r3, #40] @ 0x28 + if (HAL_ADC_Init(&hadc) != HAL_OK) { + 8004b44: 4b30 ldr r3, [pc, #192] @ (8004c08 ) + 8004b46: 0018 movs r0, r3 + 8004b48: f001 feda bl 8006900 + 8004b4c: 1e03 subs r3, r0, #0 + 8004b4e: d001 beq.n 8004b54 + Error_Handler(); + 8004b50: f000 f8e6 bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_0; + 8004b54: 1d3b adds r3, r7, #4 + 8004b56: 2200 movs r2, #0 + 8004b58: 601a str r2, [r3, #0] + sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; + 8004b5a: 1d3b adds r3, r7, #4 + 8004b5c: 2280 movs r2, #128 @ 0x80 + 8004b5e: 0152 lsls r2, r2, #5 + 8004b60: 605a str r2, [r3, #4] + sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; + 8004b62: 1d3b adds r3, r7, #4 + 8004b64: 2280 movs r2, #128 @ 0x80 + 8004b66: 0552 lsls r2, r2, #21 + 8004b68: 609a str r2, [r3, #8] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004b6a: 1d3a adds r2, r7, #4 + 8004b6c: 4b26 ldr r3, [pc, #152] @ (8004c08 ) + 8004b6e: 0011 movs r1, r2 + 8004b70: 0018 movs r0, r3 + 8004b72: f002 f805 bl 8006b80 + 8004b76: 1e03 subs r3, r0, #0 + 8004b78: d001 beq.n 8004b7e + Error_Handler(); + 8004b7a: f000 f8d1 bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_1; + 8004b7e: 1d3b adds r3, r7, #4 + 8004b80: 2201 movs r2, #1 + 8004b82: 601a str r2, [r3, #0] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004b84: 1d3a adds r2, r7, #4 + 8004b86: 4b20 ldr r3, [pc, #128] @ (8004c08 ) + 8004b88: 0011 movs r1, r2 + 8004b8a: 0018 movs r0, r3 + 8004b8c: f001 fff8 bl 8006b80 + 8004b90: 1e03 subs r3, r0, #0 + 8004b92: d001 beq.n 8004b98 + Error_Handler(); + 8004b94: f000 f8c4 bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_2; + 8004b98: 1d3b adds r3, r7, #4 + 8004b9a: 2202 movs r2, #2 + 8004b9c: 601a str r2, [r3, #0] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004b9e: 1d3a adds r2, r7, #4 + 8004ba0: 4b19 ldr r3, [pc, #100] @ (8004c08 ) + 8004ba2: 0011 movs r1, r2 + 8004ba4: 0018 movs r0, r3 + 8004ba6: f001 ffeb bl 8006b80 + 8004baa: 1e03 subs r3, r0, #0 + 8004bac: d001 beq.n 8004bb2 + Error_Handler(); + 8004bae: f000 f8b7 bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_3; + 8004bb2: 1d3b adds r3, r7, #4 + 8004bb4: 2203 movs r2, #3 + 8004bb6: 601a str r2, [r3, #0] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004bb8: 1d3a adds r2, r7, #4 + 8004bba: 4b13 ldr r3, [pc, #76] @ (8004c08 ) + 8004bbc: 0011 movs r1, r2 + 8004bbe: 0018 movs r0, r3 + 8004bc0: f001 ffde bl 8006b80 + 8004bc4: 1e03 subs r3, r0, #0 + 8004bc6: d001 beq.n 8004bcc + Error_Handler(); + 8004bc8: f000 f8aa bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_4; + 8004bcc: 1d3b adds r3, r7, #4 + 8004bce: 2204 movs r2, #4 + 8004bd0: 601a str r2, [r3, #0] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004bd2: 1d3a adds r2, r7, #4 + 8004bd4: 4b0c ldr r3, [pc, #48] @ (8004c08 ) + 8004bd6: 0011 movs r1, r2 + 8004bd8: 0018 movs r0, r3 + 8004bda: f001 ffd1 bl 8006b80 + 8004bde: 1e03 subs r3, r0, #0 + 8004be0: d001 beq.n 8004be6 + Error_Handler(); + 8004be2: f000 f89d bl 8004d20 + } + /** Configure for the selected ADC regular channel to be converted. + */ + sConfig.Channel = ADC_CHANNEL_5; + 8004be6: 1d3b adds r3, r7, #4 + 8004be8: 2205 movs r2, #5 + 8004bea: 601a str r2, [r3, #0] + if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK) { + 8004bec: 1d3a adds r2, r7, #4 + 8004bee: 4b06 ldr r3, [pc, #24] @ (8004c08 ) + 8004bf0: 0011 movs r1, r2 + 8004bf2: 0018 movs r0, r3 + 8004bf4: f001 ffc4 bl 8006b80 + 8004bf8: 1e03 subs r3, r0, #0 + 8004bfa: d001 beq.n 8004c00 + Error_Handler(); + 8004bfc: f000 f890 bl 8004d20 + } + /* USER CODE BEGIN ADC_Init 2 */ + + /* USER CODE END ADC_Init 2 */ + +} + 8004c00: 46c0 nop @ (mov r8, r8) + 8004c02: 46bd mov sp, r7 + 8004c04: b004 add sp, #16 + 8004c06: bd80 pop {r7, pc} + 8004c08: 20000a54 .word 0x20000a54 + 8004c0c: 40012400 .word 0x40012400 + +08004c10 : +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) { + 8004c10: b580 push {r7, lr} + 8004c12: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 8004c14: 4b14 ldr r3, [pc, #80] @ (8004c68 ) + 8004c16: 4a15 ldr r2, [pc, #84] @ (8004c6c ) + 8004c18: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 8004c1a: 4b13 ldr r3, [pc, #76] @ (8004c68 ) + 8004c1c: 22e1 movs r2, #225 @ 0xe1 + 8004c1e: 0252 lsls r2, r2, #9 + 8004c20: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 8004c22: 4b11 ldr r3, [pc, #68] @ (8004c68 ) + 8004c24: 2200 movs r2, #0 + 8004c26: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 8004c28: 4b0f ldr r3, [pc, #60] @ (8004c68 ) + 8004c2a: 2200 movs r2, #0 + 8004c2c: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 8004c2e: 4b0e ldr r3, [pc, #56] @ (8004c68 ) + 8004c30: 2200 movs r2, #0 + 8004c32: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8004c34: 4b0c ldr r3, [pc, #48] @ (8004c68 ) + 8004c36: 220c movs r2, #12 + 8004c38: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8004c3a: 4b0b ldr r3, [pc, #44] @ (8004c68 ) + 8004c3c: 2200 movs r2, #0 + 8004c3e: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 8004c40: 4b09 ldr r3, [pc, #36] @ (8004c68 ) + 8004c42: 2200 movs r2, #0 + 8004c44: 61da str r2, [r3, #28] + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8004c46: 4b08 ldr r3, [pc, #32] @ (8004c68 ) + 8004c48: 2200 movs r2, #0 + 8004c4a: 621a str r2, [r3, #32] + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8004c4c: 4b06 ldr r3, [pc, #24] @ (8004c68 ) + 8004c4e: 2200 movs r2, #0 + 8004c50: 625a str r2, [r3, #36] @ 0x24 + if (HAL_UART_Init(&huart1) != HAL_OK) { + 8004c52: 4b05 ldr r3, [pc, #20] @ (8004c68 ) + 8004c54: 0018 movs r0, r3 + 8004c56: f003 fb05 bl 8008264 + 8004c5a: 1e03 subs r3, r0, #0 + 8004c5c: d001 beq.n 8004c62 + Error_Handler(); + 8004c5e: f000 f85f bl 8004d20 + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 8004c62: 46c0 nop @ (mov r8, r8) + 8004c64: 46bd mov sp, r7 + 8004c66: bd80 pop {r7, pc} + 8004c68: 20000a94 .word 0x20000a94 + 8004c6c: 40013800 .word 0x40013800 + +08004c70 : +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + 8004c70: b590 push {r4, r7, lr} + 8004c72: b089 sub sp, #36 @ 0x24 + 8004c74: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + 8004c76: 240c movs r4, #12 + 8004c78: 193b adds r3, r7, r4 + 8004c7a: 0018 movs r0, r3 + 8004c7c: 2314 movs r3, #20 + 8004c7e: 001a movs r2, r3 + 8004c80: 2100 movs r1, #0 + 8004c82: f003 fe45 bl 8008910 + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8004c86: 4b23 ldr r3, [pc, #140] @ (8004d14 ) + 8004c88: 695a ldr r2, [r3, #20] + 8004c8a: 4b22 ldr r3, [pc, #136] @ (8004d14 ) + 8004c8c: 2180 movs r1, #128 @ 0x80 + 8004c8e: 03c9 lsls r1, r1, #15 + 8004c90: 430a orrs r2, r1 + 8004c92: 615a str r2, [r3, #20] + 8004c94: 4b1f ldr r3, [pc, #124] @ (8004d14 ) + 8004c96: 695a ldr r2, [r3, #20] + 8004c98: 2380 movs r3, #128 @ 0x80 + 8004c9a: 03db lsls r3, r3, #15 + 8004c9c: 4013 ands r3, r2 + 8004c9e: 60bb str r3, [r7, #8] + 8004ca0: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8004ca2: 4b1c ldr r3, [pc, #112] @ (8004d14 ) + 8004ca4: 695a ldr r2, [r3, #20] + 8004ca6: 4b1b ldr r3, [pc, #108] @ (8004d14 ) + 8004ca8: 2180 movs r1, #128 @ 0x80 + 8004caa: 0289 lsls r1, r1, #10 + 8004cac: 430a orrs r2, r1 + 8004cae: 615a str r2, [r3, #20] + 8004cb0: 4b18 ldr r3, [pc, #96] @ (8004d14 ) + 8004cb2: 695a ldr r2, [r3, #20] + 8004cb4: 2380 movs r3, #128 @ 0x80 + 8004cb6: 029b lsls r3, r3, #10 + 8004cb8: 4013 ands r3, r2 + 8004cba: 607b str r3, [r7, #4] + 8004cbc: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8004cbe: 4b15 ldr r3, [pc, #84] @ (8004d14 ) + 8004cc0: 695a ldr r2, [r3, #20] + 8004cc2: 4b14 ldr r3, [pc, #80] @ (8004d14 ) + 8004cc4: 2180 movs r1, #128 @ 0x80 + 8004cc6: 02c9 lsls r1, r1, #11 + 8004cc8: 430a orrs r2, r1 + 8004cca: 615a str r2, [r3, #20] + 8004ccc: 4b11 ldr r3, [pc, #68] @ (8004d14 ) + 8004cce: 695a ldr r2, [r3, #20] + 8004cd0: 2380 movs r3, #128 @ 0x80 + 8004cd2: 02db lsls r3, r3, #11 + 8004cd4: 4013 ands r3, r2 + 8004cd6: 603b str r3, [r7, #0] + 8004cd8: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, + 8004cda: 490f ldr r1, [pc, #60] @ (8004d18 ) + 8004cdc: 4b0f ldr r3, [pc, #60] @ (8004d1c ) + 8004cde: 2200 movs r2, #0 + 8004ce0: 0018 movs r0, r3 + 8004ce2: f002 fc89 bl 80075f8 +// GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +// GPIO_InitStruct.Pull = GPIO_NOPULL; +// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pins : PWM1_Pin PWM2_Pin FAULT_Pin D2_Pin + D1_Pin GPO1_Pin GPO2_1_Pin GPO2_2_Pin */ + GPIO_InitStruct.Pin = PWM1_Pin | PWM2_Pin | FAULT_Pin | D2_Pin | D1_Pin + 8004ce6: 0021 movs r1, r4 + 8004ce8: 187b adds r3, r7, r1 + 8004cea: 4a0b ldr r2, [pc, #44] @ (8004d18 ) + 8004cec: 601a str r2, [r3, #0] + | GPO1_Pin | GPO2_1_Pin | GPO2_2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8004cee: 187b adds r3, r7, r1 + 8004cf0: 2201 movs r2, #1 + 8004cf2: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004cf4: 187b adds r3, r7, r1 + 8004cf6: 2200 movs r2, #0 + 8004cf8: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8004cfa: 187b adds r3, r7, r1 + 8004cfc: 2200 movs r2, #0 + 8004cfe: 60da str r2, [r3, #12] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8004d00: 187b adds r3, r7, r1 + 8004d02: 4a06 ldr r2, [pc, #24] @ (8004d1c ) + 8004d04: 0019 movs r1, r3 + 8004d06: 0010 movs r0, r2 + 8004d08: f002 fafe bl 8007308 + +} + 8004d0c: 46c0 nop @ (mov r8, r8) + 8004d0e: 46bd mov sp, r7 + 8004d10: b009 add sp, #36 @ 0x24 + 8004d12: bd90 pop {r4, r7, pc} + 8004d14: 40021000 .word 0x40021000 + 8004d18: 00007ce0 .word 0x00007ce0 + 8004d1c: 48000400 .word 0x48000400 + +08004d20 : + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + 8004d20: b580 push {r7, lr} + 8004d22: af00 add r7, sp, #0 + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + 8004d24: 46c0 nop @ (mov r8, r8) + 8004d26: 46bd mov sp, r7 + 8004d28: bd80 pop {r7, pc} + ... + +08004d2c : + */ +#include "main.h" +uint32_t var_time = 0, rpm_time = 0, can_tim = 0; +can_msg_typedef tmpCanMsg; +//https://www.chamberofunderstanding.co.uk/2021/06/11/rx8-project-part-21-canbus-6-working-code/ +void MAZDA_Send_Data(void) { + 8004d2c: b580 push {r7, lr} + 8004d2e: af00 add r7, sp, #0 + can_tim++; + 8004d30: 4bcd ldr r3, [pc, #820] @ (8005068 ) + 8004d32: 681b ldr r3, [r3, #0] + 8004d34: 1c5a adds r2, r3, #1 + 8004d36: 4bcc ldr r3, [pc, #816] @ (8005068 ) + 8004d38: 601a str r2, [r3, #0] + tmpCanMsg.id = 0x201; // Send RPM = Actual RPM * 3.85 Throttle Pedal 0x00 - 0xC8 in 0.5% increments Send KPH = (Actual KPH * 100) + 10000 + 8004d3a: 4bcc ldr r3, [pc, #816] @ (800506c ) + 8004d3c: 4acc ldr r2, [pc, #816] @ (8005070 ) + 8004d3e: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004d40: 4bca ldr r3, [pc, #808] @ (800506c ) + 8004d42: 2200 movs r2, #0 + 8004d44: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004d46: 4bc9 ldr r3, [pc, #804] @ (800506c ) + 8004d48: 2200 movs r2, #0 + 8004d4a: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 7; + 8004d4c: 4bc7 ldr r3, [pc, #796] @ (800506c ) + 8004d4e: 2207 movs r2, #7 + 8004d50: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = (((uint16_t) (var.rpm * 3.85)) >> 8); // RPM high + 8004d52: 4bc8 ldr r3, [pc, #800] @ (8005074 ) + 8004d54: 8e5b ldrh r3, [r3, #50] @ 0x32 + 8004d56: b29b uxth r3, r3 + 8004d58: 0018 movs r0, r3 + 8004d5a: f7fd fb1d bl 8002398 <__aeabi_i2d> + 8004d5e: 4ac6 ldr r2, [pc, #792] @ (8005078 ) + 8004d60: 4bc6 ldr r3, [pc, #792] @ (800507c ) + 8004d62: f7fc fbdd bl 8001520 <__aeabi_dmul> + 8004d66: 0002 movs r2, r0 + 8004d68: 000b movs r3, r1 + 8004d6a: 0010 movs r0, r2 + 8004d6c: 0019 movs r1, r3 + 8004d6e: f7fb fb93 bl 8000498 <__aeabi_d2uiz> + 8004d72: 0003 movs r3, r0 + 8004d74: b29b uxth r3, r3 + 8004d76: 0a1b lsrs r3, r3, #8 + 8004d78: b29b uxth r3, r3 + 8004d7a: b2da uxtb r2, r3 + 8004d7c: 4bbb ldr r3, [pc, #748] @ (800506c ) + 8004d7e: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = (uint8_t) ((var.rpm) * 3.85); // RPM low + 8004d80: 4bbc ldr r3, [pc, #752] @ (8005074 ) + 8004d82: 8e5b ldrh r3, [r3, #50] @ 0x32 + 8004d84: b29b uxth r3, r3 + 8004d86: 0018 movs r0, r3 + 8004d88: f7fd fb06 bl 8002398 <__aeabi_i2d> + 8004d8c: 4aba ldr r2, [pc, #744] @ (8005078 ) + 8004d8e: 4bbb ldr r3, [pc, #748] @ (800507c ) + 8004d90: f7fc fbc6 bl 8001520 <__aeabi_dmul> + 8004d94: 0002 movs r2, r0 + 8004d96: 000b movs r3, r1 + 8004d98: 0010 movs r0, r2 + 8004d9a: 0019 movs r1, r3 + 8004d9c: f7fb fb7c bl 8000498 <__aeabi_d2uiz> + 8004da0: 0003 movs r3, r0 + 8004da2: b2da uxtb r2, r3 + 8004da4: 4bb1 ldr r3, [pc, #708] @ (800506c ) + 8004da6: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0xFF; + 8004da8: 4bb0 ldr r3, [pc, #704] @ (800506c ) + 8004daa: 22ff movs r2, #255 @ 0xff + 8004dac: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0xFF; + 8004dae: 4baf ldr r3, [pc, #700] @ (800506c ) + 8004db0: 22ff movs r2, #255 @ 0xff + 8004db2: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = (var.vss * 100 + 10000) >> 8; // VSS KPH high + 8004db4: 4baf ldr r3, [pc, #700] @ (8005074 ) + 8004db6: 8e1b ldrh r3, [r3, #48] @ 0x30 + 8004db8: b29b uxth r3, r3 + 8004dba: 001a movs r2, r3 + 8004dbc: 2364 movs r3, #100 @ 0x64 + 8004dbe: 4353 muls r3, r2 + 8004dc0: 4aaf ldr r2, [pc, #700] @ (8005080 ) + 8004dc2: 4694 mov ip, r2 + 8004dc4: 4463 add r3, ip + 8004dc6: 121b asrs r3, r3, #8 + 8004dc8: b2da uxtb r2, r3 + 8004dca: 4ba8 ldr r3, [pc, #672] @ (800506c ) + 8004dcc: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = (var.vss * 100 + 10000); // VSS KPH low + 8004dce: 4ba9 ldr r3, [pc, #676] @ (8005074 ) + 8004dd0: 8e1b ldrh r3, [r3, #48] @ 0x30 + 8004dd2: b29b uxth r3, r3 + 8004dd4: b2db uxtb r3, r3 + 8004dd6: 2264 movs r2, #100 @ 0x64 + 8004dd8: 4353 muls r3, r2 + 8004dda: b2db uxtb r3, r3 + 8004ddc: 3310 adds r3, #16 + 8004dde: b2da uxtb r2, r3 + 8004de0: 4ba2 ldr r3, [pc, #648] @ (800506c ) + 8004de2: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = var.pps / 5; // TPS + 8004de4: 4ba3 ldr r3, [pc, #652] @ (8005074 ) + 8004de6: 8c1b ldrh r3, [r3, #32] + 8004de8: b21b sxth r3, r3 + 8004dea: 2105 movs r1, #5 + 8004dec: 0018 movs r0, r3 + 8004dee: f7fb fa15 bl 800021c <__divsi3> + 8004df2: 0003 movs r3, r0 + 8004df4: b21b sxth r3, r3 + 8004df6: b2da uxtb r2, r3 + 8004df8: 4b9c ldr r3, [pc, #624] @ (800506c ) + 8004dfa: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0xFF; + 8004dfc: 4b9b ldr r3, [pc, #620] @ (800506c ) + 8004dfe: 22ff movs r2, #255 @ 0xff + 8004e00: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004e02: 4b9a ldr r3, [pc, #616] @ (800506c ) + 8004e04: 0018 movs r0, r3 + 8004e06: f7fd fe55 bl 8002ab4 + + tmpCanMsg.id = 0x250; + 8004e0a: 4b98 ldr r3, [pc, #608] @ (800506c ) + 8004e0c: 2294 movs r2, #148 @ 0x94 + 8004e0e: 0092 lsls r2, r2, #2 + 8004e10: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004e12: 4b96 ldr r3, [pc, #600] @ (800506c ) + 8004e14: 2200 movs r2, #0 + 8004e16: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004e18: 4b94 ldr r3, [pc, #592] @ (800506c ) + 8004e1a: 2200 movs r2, #0 + 8004e1c: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 8; + 8004e1e: 4b93 ldr r3, [pc, #588] @ (800506c ) + 8004e20: 2208 movs r2, #8 + 8004e22: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x00; + 8004e24: 4b91 ldr r3, [pc, #580] @ (800506c ) + 8004e26: 2200 movs r2, #0 + 8004e28: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0x00; + 8004e2a: 4b90 ldr r3, [pc, #576] @ (800506c ) + 8004e2c: 2200 movs r2, #0 + 8004e2e: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0xCF; + 8004e30: 4b8e ldr r3, [pc, #568] @ (800506c ) + 8004e32: 22cf movs r2, #207 @ 0xcf + 8004e34: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x87; + 8004e36: 4b8d ldr r3, [pc, #564] @ (800506c ) + 8004e38: 2287 movs r2, #135 @ 0x87 + 8004e3a: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x7F; + 8004e3c: 4b8b ldr r3, [pc, #556] @ (800506c ) + 8004e3e: 227f movs r2, #127 @ 0x7f + 8004e40: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 0x83; + 8004e42: 4b8a ldr r3, [pc, #552] @ (800506c ) + 8004e44: 2283 movs r2, #131 @ 0x83 + 8004e46: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x00; + 8004e48: 4b88 ldr r3, [pc, #544] @ (800506c ) + 8004e4a: 2200 movs r2, #0 + 8004e4c: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0x00; + 8004e4e: 4b87 ldr r3, [pc, #540] @ (800506c ) + 8004e50: 2200 movs r2, #0 + 8004e52: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004e54: 4b85 ldr r3, [pc, #532] @ (800506c ) + 8004e56: 0018 movs r0, r3 + 8004e58: f7fd fe2c bl 8002ab4 + + tmpCanMsg.id = 0x620; // Type of ABS + 8004e5c: 4b83 ldr r3, [pc, #524] @ (800506c ) + 8004e5e: 22c4 movs r2, #196 @ 0xc4 + 8004e60: 00d2 lsls r2, r2, #3 + 8004e62: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004e64: 4b81 ldr r3, [pc, #516] @ (800506c ) + 8004e66: 2200 movs r2, #0 + 8004e68: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004e6a: 4b80 ldr r3, [pc, #512] @ (800506c ) + 8004e6c: 2200 movs r2, #0 + 8004e6e: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 1; + 8004e70: 4b7e ldr r3, [pc, #504] @ (800506c ) + 8004e72: 2201 movs r2, #1 + 8004e74: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x00; + 8004e76: 4b7d ldr r3, [pc, #500] @ (800506c ) + 8004e78: 2200 movs r2, #0 + 8004e7a: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0x00; + 8004e7c: 4b7b ldr r3, [pc, #492] @ (800506c ) + 8004e7e: 2200 movs r2, #0 + 8004e80: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0x00; + 8004e82: 4b7a ldr r3, [pc, #488] @ (800506c ) + 8004e84: 2200 movs r2, #0 + 8004e86: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x00; + 8004e88: 4b78 ldr r3, [pc, #480] @ (800506c ) + 8004e8a: 2200 movs r2, #0 + 8004e8c: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x00; + 8004e8e: 4b77 ldr r3, [pc, #476] @ (800506c ) + 8004e90: 2200 movs r2, #0 + 8004e92: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 0x00; + 8004e94: 4b75 ldr r3, [pc, #468] @ (800506c ) + 8004e96: 2200 movs r2, #0 + 8004e98: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x02; // ABS type 2,3 or 4 + 8004e9a: 4b74 ldr r3, [pc, #464] @ (800506c ) + 8004e9c: 2202 movs r2, #2 + 8004e9e: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0x00; + 8004ea0: 4b72 ldr r3, [pc, #456] @ (800506c ) + 8004ea2: 2200 movs r2, #0 + 8004ea4: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004ea6: 4b71 ldr r3, [pc, #452] @ (800506c ) + 8004ea8: 0018 movs r0, r3 + 8004eaa: f7fd fe03 bl 8002ab4 + tmpCanMsg.id = 0x630; // Type of Transmission and Wheel Size + 8004eae: 4b6f ldr r3, [pc, #444] @ (800506c ) + 8004eb0: 22c6 movs r2, #198 @ 0xc6 + 8004eb2: 00d2 lsls r2, r2, #3 + 8004eb4: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004eb6: 4b6d ldr r3, [pc, #436] @ (800506c ) + 8004eb8: 2200 movs r2, #0 + 8004eba: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004ebc: 4b6b ldr r3, [pc, #428] @ (800506c ) + 8004ebe: 2200 movs r2, #0 + 8004ec0: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 1; + 8004ec2: 4b6a ldr r3, [pc, #424] @ (800506c ) + 8004ec4: 2201 movs r2, #1 + 8004ec6: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x08; //8 = MT, 2 = AT + 8004ec8: 4b68 ldr r3, [pc, #416] @ (800506c ) + 8004eca: 2208 movs r2, #8 + 8004ecc: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0x00; + 8004ece: 4b67 ldr r3, [pc, #412] @ (800506c ) + 8004ed0: 2200 movs r2, #0 + 8004ed2: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0x00; + 8004ed4: 4b65 ldr r3, [pc, #404] @ (800506c ) + 8004ed6: 2200 movs r2, #0 + 8004ed8: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x00; + 8004eda: 4b64 ldr r3, [pc, #400] @ (800506c ) + 8004edc: 2200 movs r2, #0 + 8004ede: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x00; + 8004ee0: 4b62 ldr r3, [pc, #392] @ (800506c ) + 8004ee2: 2200 movs r2, #0 + 8004ee4: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 0x00; + 8004ee6: 4b61 ldr r3, [pc, #388] @ (800506c ) + 8004ee8: 2200 movs r2, #0 + 8004eea: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x6A; // Wheel Size + 8004eec: 4b5f ldr r3, [pc, #380] @ (800506c ) + 8004eee: 226a movs r2, #106 @ 0x6a + 8004ef0: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0x6A; // Wheel Size + 8004ef2: 4b5e ldr r3, [pc, #376] @ (800506c ) + 8004ef4: 226a movs r2, #106 @ 0x6a + 8004ef6: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004ef8: 4b5c ldr r3, [pc, #368] @ (800506c ) + 8004efa: 0018 movs r0, r3 + 8004efc: f7fd fdda bl 8002ab4 + tmpCanMsg.id = 0x650; // CRUISE CONTROL + 8004f00: 4b5a ldr r3, [pc, #360] @ (800506c ) + 8004f02: 22ca movs r2, #202 @ 0xca + 8004f04: 00d2 lsls r2, r2, #3 + 8004f06: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004f08: 4b58 ldr r3, [pc, #352] @ (800506c ) + 8004f0a: 2200 movs r2, #0 + 8004f0c: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004f0e: 4b57 ldr r3, [pc, #348] @ (800506c ) + 8004f10: 2200 movs r2, #0 + 8004f12: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 1; + 8004f14: 4b55 ldr r3, [pc, #340] @ (800506c ) + 8004f16: 2201 movs r2, #1 + 8004f18: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x00; // 0x40 Green 0x80 Yellow 0xC0 Both + 8004f1a: 4b54 ldr r3, [pc, #336] @ (800506c ) + 8004f1c: 2200 movs r2, #0 + 8004f1e: 711a strb r2, [r3, #4] + //tmpCanMsg.data[3] = 0x87; + //tmpCanMsg.data[4] = 0x7f; + //tmpCanMsg.data[5] = 0x83; + //tmpCanMsg.data[6] = 0; + //tmpCanMsg.data[7] = 0; + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004f20: 4b52 ldr r3, [pc, #328] @ (800506c ) + 8004f22: 0018 movs r0, r3 + 8004f24: f7fd fdc6 bl 8002ab4 + if (can_tim>4){ + 8004f28: 4b4f ldr r3, [pc, #316] @ (8005068 ) + 8004f2a: 681b ldr r3, [r3, #0] + 8004f2c: 2b04 cmp r3, #4 + 8004f2e: d800 bhi.n 8004f32 + 8004f30: e097 b.n 8005062 + can_tim = 0; + 8004f32: 4b4d ldr r3, [pc, #308] @ (8005068 ) + 8004f34: 2200 movs r2, #0 + 8004f36: 601a str r2, [r3, #0] + tmpCanMsg.id = 0x203; //This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + 8004f38: 4b4c ldr r3, [pc, #304] @ (800506c ) + 8004f3a: 4a52 ldr r2, [pc, #328] @ (8005084 ) + 8004f3c: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004f3e: 4b4b ldr r3, [pc, #300] @ (800506c ) + 8004f40: 2200 movs r2, #0 + 8004f42: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004f44: 4b49 ldr r3, [pc, #292] @ (800506c ) + 8004f46: 2200 movs r2, #0 + 8004f48: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 7; + 8004f4a: 4b48 ldr r3, [pc, #288] @ (800506c ) + 8004f4c: 2207 movs r2, #7 + 8004f4e: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x16; + 8004f50: 4b46 ldr r3, [pc, #280] @ (800506c ) + 8004f52: 2216 movs r2, #22 + 8004f54: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0x16; + 8004f56: 4b45 ldr r3, [pc, #276] @ (800506c ) + 8004f58: 2216 movs r2, #22 + 8004f5a: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0x16; + 8004f5c: 4b43 ldr r3, [pc, #268] @ (800506c ) + 8004f5e: 2216 movs r2, #22 + 8004f60: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x16; + 8004f62: 4b42 ldr r3, [pc, #264] @ (800506c ) + 8004f64: 2216 movs r2, #22 + 8004f66: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0xAF; + 8004f68: 4b40 ldr r3, [pc, #256] @ (800506c ) + 8004f6a: 22af movs r2, #175 @ 0xaf + 8004f6c: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 3; + 8004f6e: 4b3f ldr r3, [pc, #252] @ (800506c ) + 8004f70: 2203 movs r2, #3 + 8004f72: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x16; + 8004f74: 4b3d ldr r3, [pc, #244] @ (800506c ) + 8004f76: 2216 movs r2, #22 + 8004f78: 729a strb r2, [r3, #10] + //tmpCanMsg.data[7] = ; + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004f7a: 4b3c ldr r3, [pc, #240] @ (800506c ) + 8004f7c: 0018 movs r0, r3 + 8004f7e: f7fd fd99 bl 8002ab4 + tmpCanMsg.id = 0x215; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + 8004f82: 4b3a ldr r3, [pc, #232] @ (800506c ) + 8004f84: 4a40 ldr r2, [pc, #256] @ (8005088 ) + 8004f86: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004f88: 4b38 ldr r3, [pc, #224] @ (800506c ) + 8004f8a: 2200 movs r2, #0 + 8004f8c: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004f8e: 4b37 ldr r3, [pc, #220] @ (800506c ) + 8004f90: 2200 movs r2, #0 + 8004f92: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 8; + 8004f94: 4b35 ldr r3, [pc, #212] @ (800506c ) + 8004f96: 2208 movs r2, #8 + 8004f98: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x02; + 8004f9a: 4b34 ldr r3, [pc, #208] @ (800506c ) + 8004f9c: 2202 movs r2, #2 + 8004f9e: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0x2D; + 8004fa0: 4b32 ldr r3, [pc, #200] @ (800506c ) + 8004fa2: 222d movs r2, #45 @ 0x2d + 8004fa4: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0x02; + 8004fa6: 4b31 ldr r3, [pc, #196] @ (800506c ) + 8004fa8: 2202 movs r2, #2 + 8004faa: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x2D; + 8004fac: 4b2f ldr r3, [pc, #188] @ (800506c ) + 8004fae: 222d movs r2, #45 @ 0x2d + 8004fb0: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x02; + 8004fb2: 4b2e ldr r3, [pc, #184] @ (800506c ) + 8004fb4: 2202 movs r2, #2 + 8004fb6: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 0x2A; + 8004fb8: 4b2c ldr r3, [pc, #176] @ (800506c ) + 8004fba: 222a movs r2, #42 @ 0x2a + 8004fbc: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x06; + 8004fbe: 4b2b ldr r3, [pc, #172] @ (800506c ) + 8004fc0: 2206 movs r2, #6 + 8004fc2: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0x81; + 8004fc4: 4b29 ldr r3, [pc, #164] @ (800506c ) + 8004fc6: 2281 movs r2, #129 @ 0x81 + 8004fc8: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8004fca: 4b28 ldr r3, [pc, #160] @ (800506c ) + 8004fcc: 0018 movs r0, r3 + 8004fce: f7fd fd71 bl 8002ab4 + tmpCanMsg.id = 0x231; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + 8004fd2: 4b26 ldr r3, [pc, #152] @ (800506c ) + 8004fd4: 4a2d ldr r2, [pc, #180] @ (800508c ) + 8004fd6: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8004fd8: 4b24 ldr r3, [pc, #144] @ (800506c ) + 8004fda: 2200 movs r2, #0 + 8004fdc: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 8004fde: 4b23 ldr r3, [pc, #140] @ (800506c ) + 8004fe0: 2200 movs r2, #0 + 8004fe2: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 5; + 8004fe4: 4b21 ldr r3, [pc, #132] @ (800506c ) + 8004fe6: 2205 movs r2, #5 + 8004fe8: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 15; + 8004fea: 4b20 ldr r3, [pc, #128] @ (800506c ) + 8004fec: 220f movs r2, #15 + 8004fee: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0; + 8004ff0: 4b1e ldr r3, [pc, #120] @ (800506c ) + 8004ff2: 2200 movs r2, #0 + 8004ff4: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0xff; + 8004ff6: 4b1d ldr r3, [pc, #116] @ (800506c ) + 8004ff8: 22ff movs r2, #255 @ 0xff + 8004ffa: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0xff; + 8004ffc: 4b1b ldr r3, [pc, #108] @ (800506c ) + 8004ffe: 22ff movs r2, #255 @ 0xff + 8005000: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x00; + 8005002: 4b1a ldr r3, [pc, #104] @ (800506c ) + 8005004: 2200 movs r2, #0 + 8005006: 721a strb r2, [r3, #8] + //tmpCanMsg.data[5] = 0x37; + //tmpCanMsg.data[6] = 0x06; + //tmpCanMsg.data[7] = 0x81; + CAN_Add_TX_Buffer(&tmpCanMsg); + 8005008: 4b18 ldr r3, [pc, #96] @ (800506c ) + 800500a: 0018 movs r0, r3 + 800500c: f7fd fd52 bl 8002ab4 + tmpCanMsg.id = 0x240; // This needs sending witin 0.5 seconds of ignition otherwise traction light will come on + 8005010: 4b16 ldr r3, [pc, #88] @ (800506c ) + 8005012: 2290 movs r2, #144 @ 0x90 + 8005014: 0092 lsls r2, r2, #2 + 8005016: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 8005018: 4b14 ldr r3, [pc, #80] @ (800506c ) + 800501a: 2200 movs r2, #0 + 800501c: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 800501e: 4b13 ldr r3, [pc, #76] @ (800506c ) + 8005020: 2200 movs r2, #0 + 8005022: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 8; + 8005024: 4b11 ldr r3, [pc, #68] @ (800506c ) + 8005026: 2208 movs r2, #8 + 8005028: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x04; + 800502a: 4b10 ldr r3, [pc, #64] @ (800506c ) + 800502c: 2204 movs r2, #4 + 800502e: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = 0; + 8005030: 4b0e ldr r3, [pc, #56] @ (800506c ) + 8005032: 2200 movs r2, #0 + 8005034: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 40; + 8005036: 4b0d ldr r3, [pc, #52] @ (800506c ) + 8005038: 2228 movs r2, #40 @ 0x28 + 800503a: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x00; + 800503c: 4b0b ldr r3, [pc, #44] @ (800506c ) + 800503e: 2200 movs r2, #0 + 8005040: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x02; + 8005042: 4b0a ldr r3, [pc, #40] @ (800506c ) + 8005044: 2202 movs r2, #2 + 8005046: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 55; + 8005048: 4b08 ldr r3, [pc, #32] @ (800506c ) + 800504a: 2237 movs r2, #55 @ 0x37 + 800504c: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0x06; + 800504e: 4b07 ldr r3, [pc, #28] @ (800506c ) + 8005050: 2206 movs r2, #6 + 8005052: 729a strb r2, [r3, #10] + tmpCanMsg.data[7] = 0x81; + 8005054: 4b05 ldr r3, [pc, #20] @ (800506c ) + 8005056: 2281 movs r2, #129 @ 0x81 + 8005058: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 800505a: 4b04 ldr r3, [pc, #16] @ (800506c ) + 800505c: 0018 movs r0, r3 + 800505e: f7fd fd29 bl 8002ab4 + } +} + 8005062: 46c0 nop @ (mov r8, r8) + 8005064: 46bd mov sp, r7 + 8005066: bd80 pop {r7, pc} + 8005068: 20000b18 .word 0x20000b18 + 800506c: 20000b1c .word 0x20000b1c + 8005070: 00000201 .word 0x00000201 + 8005074: 20000998 .word 0x20000998 + 8005078: cccccccd .word 0xcccccccd + 800507c: 400ecccc .word 0x400ecccc + 8005080: 00002710 .word 0x00002710 + 8005084: 00000203 .word 0x00000203 + 8005088: 00000215 .word 0x00000215 + 800508c: 00000231 .word 0x00000231 + +08005090 : +void MAZDA_CAN_Read(void) { + 8005090: b580 push {r7, lr} + 8005092: af00 add r7, sp, #0 + CAN_Read_RX_Buffer(&tmpCanMsg); + 8005094: 4b36 ldr r3, [pc, #216] @ (8005170 ) + 8005096: 0018 movs r0, r3 + 8005098: f7fd fee4 bl 8002e64 + if (tmpCanMsg.id == 0x4c0) { + 800509c: 4b34 ldr r3, [pc, #208] @ (8005170 ) + 800509e: 681a ldr r2, [r3, #0] + 80050a0: 2398 movs r3, #152 @ 0x98 + 80050a2: 00db lsls r3, r3, #3 + 80050a4: 429a cmp r2, r3 + 80050a6: d140 bne.n 800512a + tmpCanMsg.id = 0x420; // Engine Temp Odometer from 4c0 Oil Pressure Check Engine Low Water Bat Charge Oil Pressure + 80050a8: 4b31 ldr r3, [pc, #196] @ (8005170 ) + 80050aa: 2284 movs r2, #132 @ 0x84 + 80050ac: 00d2 lsls r2, r2, #3 + 80050ae: 601a str r2, [r3, #0] + tmpCanMsg.format = STD_FORMAT; + 80050b0: 4b2f ldr r3, [pc, #188] @ (8005170 ) + 80050b2: 2200 movs r2, #0 + 80050b4: 735a strb r2, [r3, #13] + tmpCanMsg.frame = DATA_FRAME; + 80050b6: 4b2e ldr r3, [pc, #184] @ (8005170 ) + 80050b8: 2200 movs r2, #0 + 80050ba: 739a strb r2, [r3, #14] + tmpCanMsg.lenght = 8; + 80050bc: 4b2c ldr r3, [pc, #176] @ (8005170 ) + 80050be: 2208 movs r2, #8 + 80050c0: 731a strb r2, [r3, #12] + tmpCanMsg.data[0] = 0x00; // clt + 80050c2: 4b2b ldr r3, [pc, #172] @ (8005170 ) + 80050c4: 2200 movs r2, #0 + 80050c6: 711a strb r2, [r3, #4] + tmpCanMsg.data[1] = tmpCanMsg.data[1]; // Odometer from 4c0 (pwm) + 80050c8: 4b29 ldr r3, [pc, #164] @ (8005170 ) + 80050ca: 795a ldrb r2, [r3, #5] + 80050cc: 4b28 ldr r3, [pc, #160] @ (8005170 ) + 80050ce: 715a strb r2, [r3, #5] + tmpCanMsg.data[2] = 0x00; + 80050d0: 4b27 ldr r3, [pc, #156] @ (8005170 ) + 80050d2: 2200 movs r2, #0 + 80050d4: 719a strb r2, [r3, #6] + tmpCanMsg.data[3] = 0x00; + 80050d6: 4b26 ldr r3, [pc, #152] @ (8005170 ) + 80050d8: 2200 movs r2, #0 + 80050da: 71da strb r2, [r3, #7] + tmpCanMsg.data[4] = 0x00; //Oil Pressure 0x00 - 0x01 (pwm) + 80050dc: 4b24 ldr r3, [pc, #144] @ (8005170 ) + 80050de: 2200 movs r2, #0 + 80050e0: 721a strb r2, [r3, #8] + tmpCanMsg.data[5] = 0x00; // Check Engine Bit 7 MIL Check Engine Bit 8 BL + 80050e2: 4b23 ldr r3, [pc, #140] @ (8005170 ) + 80050e4: 2200 movs r2, #0 + 80050e6: 725a strb r2, [r3, #9] + tmpCanMsg.data[6] = 0; + 80050e8: 4b21 ldr r3, [pc, #132] @ (8005170 ) + 80050ea: 2200 movs r2, #0 + 80050ec: 729a strb r2, [r3, #10] + if (var.vbat_adc < 1200) { + 80050ee: 4b21 ldr r3, [pc, #132] @ (8005174 ) + 80050f0: 8adb ldrh r3, [r3, #22] + 80050f2: b29a uxth r2, r3 + 80050f4: 2396 movs r3, #150 @ 0x96 + 80050f6: 00db lsls r3, r3, #3 + 80050f8: 429a cmp r2, r3 + 80050fa: d207 bcs.n 800510c + tmpCanMsg.data[6] |= 1 << 2; + 80050fc: 4b1c ldr r3, [pc, #112] @ (8005170 ) + 80050fe: 7a9b ldrb r3, [r3, #10] + 8005100: 2204 movs r2, #4 + 8005102: 4313 orrs r3, r2 + 8005104: b2da uxtb r2, r3 + 8005106: 4b1a ldr r3, [pc, #104] @ (8005170 ) + 8005108: 729a strb r2, [r3, #10] + 800510a: e006 b.n 800511a + } else { + tmpCanMsg.data[6] &= ~(1 << 2); + 800510c: 4b18 ldr r3, [pc, #96] @ (8005170 ) + 800510e: 7a9b ldrb r3, [r3, #10] + 8005110: 2204 movs r2, #4 + 8005112: 4393 bics r3, r2 + 8005114: b2da uxtb r2, r3 + 8005116: 4b16 ldr r3, [pc, #88] @ (8005170 ) + 8005118: 729a strb r2, [r3, #10] + } + //tmpCanMsg.data[6] = var.ic_status2; //Low Water Bit 2 MIL Bat Charge Bit 7 MIL Oil Pressure Bit 8 MIL + tmpCanMsg.data[7] = 0x00; + 800511a: 4b15 ldr r3, [pc, #84] @ (8005170 ) + 800511c: 2200 movs r2, #0 + 800511e: 72da strb r2, [r3, #11] + CAN_Add_TX_Buffer(&tmpCanMsg); + 8005120: 4b13 ldr r3, [pc, #76] @ (8005170 ) + 8005122: 0018 movs r0, r3 + 8005124: f7fd fcc6 bl 8002ab4 + } else if (tmpCanMsg.id == 0x4B1) { + var.vss = ((tmpCanMsg.data[4] << 8) + tmpCanMsg.data[5] + (tmpCanMsg.data[6] << 8) + tmpCanMsg.data[7]) / 4; + //todo // add option to make vss output on/off + VSS_Set((uint8_t)var.vss); + } +} + 8005128: e01f b.n 800516a + } else if (tmpCanMsg.id == 0x4B1) { + 800512a: 4b11 ldr r3, [pc, #68] @ (8005170 ) + 800512c: 681b ldr r3, [r3, #0] + 800512e: 4a12 ldr r2, [pc, #72] @ (8005178 ) + 8005130: 4293 cmp r3, r2 + 8005132: d11a bne.n 800516a + var.vss = ((tmpCanMsg.data[4] << 8) + tmpCanMsg.data[5] + (tmpCanMsg.data[6] << 8) + tmpCanMsg.data[7]) / 4; + 8005134: 4b0e ldr r3, [pc, #56] @ (8005170 ) + 8005136: 7a1b ldrb r3, [r3, #8] + 8005138: 021b lsls r3, r3, #8 + 800513a: 4a0d ldr r2, [pc, #52] @ (8005170 ) + 800513c: 7a52 ldrb r2, [r2, #9] + 800513e: 189a adds r2, r3, r2 + 8005140: 4b0b ldr r3, [pc, #44] @ (8005170 ) + 8005142: 7a9b ldrb r3, [r3, #10] + 8005144: 021b lsls r3, r3, #8 + 8005146: 18d3 adds r3, r2, r3 + 8005148: 4a09 ldr r2, [pc, #36] @ (8005170 ) + 800514a: 7ad2 ldrb r2, [r2, #11] + 800514c: 189b adds r3, r3, r2 + 800514e: 2b00 cmp r3, #0 + 8005150: da00 bge.n 8005154 + 8005152: 3303 adds r3, #3 + 8005154: 109b asrs r3, r3, #2 + 8005156: b29a uxth r2, r3 + 8005158: 4b06 ldr r3, [pc, #24] @ (8005174 ) + 800515a: 861a strh r2, [r3, #48] @ 0x30 + VSS_Set((uint8_t)var.vss); + 800515c: 4b05 ldr r3, [pc, #20] @ (8005174 ) + 800515e: 8e1b ldrh r3, [r3, #48] @ 0x30 + 8005160: b29b uxth r3, r3 + 8005162: b2db uxtb r3, r3 + 8005164: 0018 movs r0, r3 + 8005166: f000 f897 bl 8005298 +} + 800516a: 46c0 nop @ (mov r8, r8) + 800516c: 46bd mov sp, r7 + 800516e: bd80 pop {r7, pc} + 8005170: 20000b1c .word 0x20000b1c + 8005174: 20000998 .word 0x20000998 + 8005178: 000004b1 .word 0x000004b1 + +0800517c <__NVIC_EnableIRQ>: +{ + 800517c: b580 push {r7, lr} + 800517e: b082 sub sp, #8 + 8005180: af00 add r7, sp, #0 + 8005182: 0002 movs r2, r0 + 8005184: 1dfb adds r3, r7, #7 + 8005186: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8005188: 1dfb adds r3, r7, #7 + 800518a: 781b ldrb r3, [r3, #0] + 800518c: 2b7f cmp r3, #127 @ 0x7f + 800518e: d809 bhi.n 80051a4 <__NVIC_EnableIRQ+0x28> + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8005190: 1dfb adds r3, r7, #7 + 8005192: 781b ldrb r3, [r3, #0] + 8005194: 001a movs r2, r3 + 8005196: 231f movs r3, #31 + 8005198: 401a ands r2, r3 + 800519a: 4b04 ldr r3, [pc, #16] @ (80051ac <__NVIC_EnableIRQ+0x30>) + 800519c: 2101 movs r1, #1 + 800519e: 4091 lsls r1, r2 + 80051a0: 000a movs r2, r1 + 80051a2: 601a str r2, [r3, #0] +} + 80051a4: 46c0 nop @ (mov r8, r8) + 80051a6: 46bd mov sp, r7 + 80051a8: b002 add sp, #8 + 80051aa: bd80 pop {r7, pc} + 80051ac: e000e100 .word 0xe000e100 + +080051b0 : + * Author: v0stap + */ + +#include "main.h" + +void TIM16_Init(void) { + 80051b0: b580 push {r7, lr} + 80051b2: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; + 80051b4: 4b17 ldr r3, [pc, #92] @ (8005214 ) + 80051b6: 699a ldr r2, [r3, #24] + 80051b8: 4b16 ldr r3, [pc, #88] @ (8005214 ) + 80051ba: 2180 movs r1, #128 @ 0x80 + 80051bc: 0289 lsls r1, r1, #10 + 80051be: 430a orrs r2, r1 + 80051c0: 619a str r2, [r3, #24] + TIM16->PSC = 480; + 80051c2: 4b15 ldr r3, [pc, #84] @ (8005218 ) + 80051c4: 22f0 movs r2, #240 @ 0xf0 + 80051c6: 0052 lsls r2, r2, #1 + 80051c8: 629a str r2, [r3, #40] @ 0x28 + TIM16->ARR = 70287; + 80051ca: 4b13 ldr r3, [pc, #76] @ (8005218 ) + 80051cc: 4a13 ldr r2, [pc, #76] @ (800521c ) + 80051ce: 62da str r2, [r3, #44] @ 0x2c + TIM16->CR1 |= 1 << 0 | 1 << 7; + 80051d0: 4b11 ldr r3, [pc, #68] @ (8005218 ) + 80051d2: 681a ldr r2, [r3, #0] + 80051d4: 4b10 ldr r3, [pc, #64] @ (8005218 ) + 80051d6: 2181 movs r1, #129 @ 0x81 + 80051d8: 430a orrs r2, r1 + 80051da: 601a str r2, [r3, #0] + TIM16->CR2 = 0; + 80051dc: 4b0e ldr r3, [pc, #56] @ (8005218 ) + 80051de: 2200 movs r2, #0 + 80051e0: 605a str r2, [r3, #4] + TIM16->SMCR = 0; + 80051e2: 4b0d ldr r3, [pc, #52] @ (8005218 ) + 80051e4: 2200 movs r2, #0 + 80051e6: 609a str r2, [r3, #8] + TIM16->DIER = 1 << 0; + 80051e8: 4b0b ldr r3, [pc, #44] @ (8005218 ) + 80051ea: 2201 movs r2, #1 + 80051ec: 60da str r2, [r3, #12] + TIM16->CCMR1 = 0; + 80051ee: 4b0a ldr r3, [pc, #40] @ (8005218 ) + 80051f0: 2200 movs r2, #0 + 80051f2: 619a str r2, [r3, #24] + TIM16->CCMR2 = 0; + 80051f4: 4b08 ldr r3, [pc, #32] @ (8005218 ) + 80051f6: 2200 movs r2, #0 + 80051f8: 61da str r2, [r3, #28] + TIM16->CCER = 0x1111; + 80051fa: 4b07 ldr r3, [pc, #28] @ (8005218 ) + 80051fc: 4a08 ldr r2, [pc, #32] @ (8005220 ) + 80051fe: 621a str r2, [r3, #32] + TIM16->SR = 0; + 8005200: 4b05 ldr r3, [pc, #20] @ (8005218 ) + 8005202: 2200 movs r2, #0 + 8005204: 611a str r2, [r3, #16] + NVIC_EnableIRQ(TIM16_IRQn); + 8005206: 2015 movs r0, #21 + 8005208: f7ff ffb8 bl 800517c <__NVIC_EnableIRQ> +} + 800520c: 46c0 nop @ (mov r8, r8) + 800520e: 46bd mov sp, r7 + 8005210: bd80 pop {r7, pc} + 8005212: 46c0 nop @ (mov r8, r8) + 8005214: 40021000 .word 0x40021000 + 8005218: 40014400 .word 0x40014400 + 800521c: 0001128f .word 0x0001128f + 8005220: 00001111 .word 0x00001111 + +08005224 : + +void TIM17_Init(void) { + 8005224: b580 push {r7, lr} + 8005226: af00 add r7, sp, #0 + RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; + 8005228: 4b17 ldr r3, [pc, #92] @ (8005288 ) + 800522a: 699a ldr r2, [r3, #24] + 800522c: 4b16 ldr r3, [pc, #88] @ (8005288 ) + 800522e: 2180 movs r1, #128 @ 0x80 + 8005230: 02c9 lsls r1, r1, #11 + 8005232: 430a orrs r2, r1 + 8005234: 619a str r2, [r3, #24] + TIM17->PSC = 479; + 8005236: 4b15 ldr r3, [pc, #84] @ (800528c ) + 8005238: 22e0 movs r2, #224 @ 0xe0 + 800523a: 32ff adds r2, #255 @ 0xff + 800523c: 629a str r2, [r3, #40] @ 0x28 + TIM17->ARR = 10000; + 800523e: 4b13 ldr r3, [pc, #76] @ (800528c ) + 8005240: 4a13 ldr r2, [pc, #76] @ (8005290 ) + 8005242: 62da str r2, [r3, #44] @ 0x2c + TIM17->CR1 |= 1 << 0 | 1 << 7; + 8005244: 4b11 ldr r3, [pc, #68] @ (800528c ) + 8005246: 681a ldr r2, [r3, #0] + 8005248: 4b10 ldr r3, [pc, #64] @ (800528c ) + 800524a: 2181 movs r1, #129 @ 0x81 + 800524c: 430a orrs r2, r1 + 800524e: 601a str r2, [r3, #0] + TIM17->CR2 = 0; + 8005250: 4b0e ldr r3, [pc, #56] @ (800528c ) + 8005252: 2200 movs r2, #0 + 8005254: 605a str r2, [r3, #4] + TIM17->SMCR = 0; + 8005256: 4b0d ldr r3, [pc, #52] @ (800528c ) + 8005258: 2200 movs r2, #0 + 800525a: 609a str r2, [r3, #8] + TIM17->DIER = 1 << 0; + 800525c: 4b0b ldr r3, [pc, #44] @ (800528c ) + 800525e: 2201 movs r2, #1 + 8005260: 60da str r2, [r3, #12] + TIM17->CCMR1 = 0; + 8005262: 4b0a ldr r3, [pc, #40] @ (800528c ) + 8005264: 2200 movs r2, #0 + 8005266: 619a str r2, [r3, #24] + TIM17->CCMR2 = 0; + 8005268: 4b08 ldr r3, [pc, #32] @ (800528c ) + 800526a: 2200 movs r2, #0 + 800526c: 61da str r2, [r3, #28] + TIM17->CCER = 0x1111; + 800526e: 4b07 ldr r3, [pc, #28] @ (800528c ) + 8005270: 4a08 ldr r2, [pc, #32] @ (8005294 ) + 8005272: 621a str r2, [r3, #32] + TIM17->SR = 0; + 8005274: 4b05 ldr r3, [pc, #20] @ (800528c ) + 8005276: 2200 movs r2, #0 + 8005278: 611a str r2, [r3, #16] + NVIC_EnableIRQ(TIM17_IRQn); + 800527a: 2016 movs r0, #22 + 800527c: f7ff ff7e bl 800517c <__NVIC_EnableIRQ> +} + 8005280: 46c0 nop @ (mov r8, r8) + 8005282: 46bd mov sp, r7 + 8005284: bd80 pop {r7, pc} + 8005286: 46c0 nop @ (mov r8, r8) + 8005288: 40021000 .word 0x40021000 + 800528c: 40014800 .word 0x40014800 + 8005290: 00002710 .word 0x00002710 + 8005294: 00001111 .word 0x00001111 + +08005298 : + +void VSS_Set(uint8_t vss) { + 8005298: b580 push {r7, lr} + 800529a: b082 sub sp, #8 + 800529c: af00 add r7, sp, #0 + 800529e: 0002 movs r2, r0 + 80052a0: 1dfb adds r3, r7, #7 + 80052a2: 701a strb r2, [r3, #0] + if (vss < 3) { + 80052a4: 1dfb adds r3, r7, #7 + 80052a6: 781b ldrb r3, [r3, #0] + 80052a8: 2b02 cmp r3, #2 + 80052aa: d806 bhi.n 80052ba + TIM16->CR1 &= ~(1 << 0); + 80052ac: 4b0d ldr r3, [pc, #52] @ (80052e4 ) + 80052ae: 681a ldr r2, [r3, #0] + 80052b0: 4b0c ldr r3, [pc, #48] @ (80052e4 ) + 80052b2: 2101 movs r1, #1 + 80052b4: 438a bics r2, r1 + 80052b6: 601a str r2, [r3, #0] + } else { + TIM16->CR1 |= 1 << 0; + TIM16->ARR = 70287 / vss; + } +} + 80052b8: e00f b.n 80052da + TIM16->CR1 |= 1 << 0; + 80052ba: 4b0a ldr r3, [pc, #40] @ (80052e4 ) + 80052bc: 681a ldr r2, [r3, #0] + 80052be: 4b09 ldr r3, [pc, #36] @ (80052e4 ) + 80052c0: 2101 movs r1, #1 + 80052c2: 430a orrs r2, r1 + 80052c4: 601a str r2, [r3, #0] + TIM16->ARR = 70287 / vss; + 80052c6: 1dfb adds r3, r7, #7 + 80052c8: 781b ldrb r3, [r3, #0] + 80052ca: 0019 movs r1, r3 + 80052cc: 4806 ldr r0, [pc, #24] @ (80052e8 ) + 80052ce: f7fa ffa5 bl 800021c <__divsi3> + 80052d2: 0003 movs r3, r0 + 80052d4: 001a movs r2, r3 + 80052d6: 4b03 ldr r3, [pc, #12] @ (80052e4 ) + 80052d8: 62da str r2, [r3, #44] @ 0x2c +} + 80052da: 46c0 nop @ (mov r8, r8) + 80052dc: 46bd mov sp, r7 + 80052de: b002 add sp, #8 + 80052e0: bd80 pop {r7, pc} + 80052e2: 46c0 nop @ (mov r8, r8) + 80052e4: 40014400 .word 0x40014400 + 80052e8: 0001128f .word 0x0001128f + +080052ec : + + +void TIM16_IRQHandler(void) { + 80052ec: b580 push {r7, lr} + 80052ee: af00 add r7, sp, #0 + TIM16->SR &= ~(1 << 0); + 80052f0: 4b06 ldr r3, [pc, #24] @ (800530c ) + 80052f2: 691a ldr r2, [r3, #16] + 80052f4: 4b05 ldr r3, [pc, #20] @ (800530c ) + 80052f6: 2101 movs r1, #1 + 80052f8: 438a bics r2, r1 + 80052fa: 611a str r2, [r3, #16] + //TIM2->CNT = 600; + HAL_GPIO_TogglePin(GPIOB, GPO1_Pin); + 80052fc: 4b04 ldr r3, [pc, #16] @ (8005310 ) + 80052fe: 2120 movs r1, #32 + 8005300: 0018 movs r0, r3 + 8005302: f002 f996 bl 8007632 +} + 8005306: 46c0 nop @ (mov r8, r8) + 8005308: 46bd mov sp, r7 + 800530a: bd80 pop {r7, pc} + 800530c: 40014400 .word 0x40014400 + 8005310: 48000400 .word 0x48000400 + +08005314 : +void TIM17_IRQHandler(void) { + 8005314: b580 push {r7, lr} + 8005316: af00 add r7, sp, #0 + TIM17->SR &= ~(1 << 0); + 8005318: 4b05 ldr r3, [pc, #20] @ (8005330 ) + 800531a: 691a ldr r2, [r3, #16] + 800531c: 4b04 ldr r3, [pc, #16] @ (8005330 ) + 800531e: 2101 movs r1, #1 + 8005320: 438a bics r2, r1 + 8005322: 611a str r2, [r3, #16] + //TIM2->CNT = 600; + MAZDA_Send_Data(); + 8005324: f7ff fd02 bl 8004d2c +} + 8005328: 46c0 nop @ (mov r8, r8) + 800532a: 46bd mov sp, r7 + 800532c: bd80 pop {r7, pc} + 800532e: 46c0 nop @ (mov r8, r8) + 8005330: 40014800 .word 0x40014800 + +08005334 : + while (IWDG->SR) + ; + +} + +void Check_Safety_Limits(void) { + 8005334: b580 push {r7, lr} + 8005336: af00 add r7, sp, #0 + +//PPS1 + + if (config->pps1_min < config->pps1_max) { + 8005338: 4bc3 ldr r3, [pc, #780] @ (8005648 ) + 800533a: 681b ldr r3, [r3, #0] + 800533c: 885b ldrh r3, [r3, #2] + 800533e: b29a uxth r2, r3 + 8005340: 4bc1 ldr r3, [pc, #772] @ (8005648 ) + 8005342: 681b ldr r3, [r3, #0] + 8005344: 889b ldrh r3, [r3, #4] + 8005346: b29b uxth r3, r3 + 8005348: 429a cmp r2, r3 + 800534a: d22c bcs.n 80053a6 + if ((config->pps1_margin > config->pps1_min) + 800534c: 4bbe ldr r3, [pc, #760] @ (8005648 ) + 800534e: 681a ldr r2, [r3, #0] + 8005350: 23cf movs r3, #207 @ 0xcf + 8005352: 009b lsls r3, r3, #2 + 8005354: 5ad3 ldrh r3, [r2, r3] + 8005356: b29a uxth r2, r3 + 8005358: 4bbb ldr r3, [pc, #748] @ (8005648 ) + 800535a: 681b ldr r3, [r3, #0] + 800535c: 885b ldrh r3, [r3, #2] + 800535e: b29b uxth r3, r3 + 8005360: 429a cmp r2, r3 + 8005362: d80f bhi.n 8005384 + || ((config->pps1_max + config->pps1_margin) > 4095)) { + 8005364: 4bb8 ldr r3, [pc, #736] @ (8005648 ) + 8005366: 681b ldr r3, [r3, #0] + 8005368: 889b ldrh r3, [r3, #4] + 800536a: b29b uxth r3, r3 + 800536c: 0019 movs r1, r3 + 800536e: 4bb6 ldr r3, [pc, #728] @ (8005648 ) + 8005370: 681a ldr r2, [r3, #0] + 8005372: 23cf movs r3, #207 @ 0xcf + 8005374: 009b lsls r3, r3, #2 + 8005376: 5ad3 ldrh r3, [r2, r3] + 8005378: b29b uxth r3, r3 + 800537a: 18ca adds r2, r1, r3 + 800537c: 2380 movs r3, #128 @ 0x80 + 800537e: 015b lsls r3, r3, #5 + 8005380: 429a cmp r2, r3 + 8005382: db3c blt.n 80053fe + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 8005384: 4bb1 ldr r3, [pc, #708] @ (800564c ) + 8005386: 889b ldrh r3, [r3, #4] + 8005388: b29b uxth r3, r3 + 800538a: 2280 movs r2, #128 @ 0x80 + 800538c: 0192 lsls r2, r2, #6 + 800538e: 4313 orrs r3, r2 + 8005390: b29a uxth r2, r3 + 8005392: 4bae ldr r3, [pc, #696] @ (800564c ) + 8005394: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005396: f7fe fe53 bl 8004040 + TX_Schedule((unsigned char*) msg1, 42); + 800539a: 4bad ldr r3, [pc, #692] @ (8005650 ) + 800539c: 212a movs r1, #42 @ 0x2a + 800539e: 0018 movs r0, r3 + 80053a0: f001 f842 bl 8006428 + 80053a4: e02b b.n 80053fe + } + } else { + //config->pps1_min > config->pps1_max + if ((config->pps1_margin > config->pps1_max) + 80053a6: 4ba8 ldr r3, [pc, #672] @ (8005648 ) + 80053a8: 681a ldr r2, [r3, #0] + 80053aa: 23cf movs r3, #207 @ 0xcf + 80053ac: 009b lsls r3, r3, #2 + 80053ae: 5ad3 ldrh r3, [r2, r3] + 80053b0: b29a uxth r2, r3 + 80053b2: 4ba5 ldr r3, [pc, #660] @ (8005648 ) + 80053b4: 681b ldr r3, [r3, #0] + 80053b6: 889b ldrh r3, [r3, #4] + 80053b8: b29b uxth r3, r3 + 80053ba: 429a cmp r2, r3 + 80053bc: d80f bhi.n 80053de + || ((config->pps1_min + config->pps1_margin) > 4095)) { + 80053be: 4ba2 ldr r3, [pc, #648] @ (8005648 ) + 80053c0: 681b ldr r3, [r3, #0] + 80053c2: 885b ldrh r3, [r3, #2] + 80053c4: b29b uxth r3, r3 + 80053c6: 0019 movs r1, r3 + 80053c8: 4b9f ldr r3, [pc, #636] @ (8005648 ) + 80053ca: 681a ldr r2, [r3, #0] + 80053cc: 23cf movs r3, #207 @ 0xcf + 80053ce: 009b lsls r3, r3, #2 + 80053d0: 5ad3 ldrh r3, [r2, r3] + 80053d2: b29b uxth r3, r3 + 80053d4: 18ca adds r2, r1, r3 + 80053d6: 2380 movs r3, #128 @ 0x80 + 80053d8: 015b lsls r3, r3, #5 + 80053da: 429a cmp r2, r3 + 80053dc: db0f blt.n 80053fe + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 80053de: 4b9b ldr r3, [pc, #620] @ (800564c ) + 80053e0: 889b ldrh r3, [r3, #4] + 80053e2: b29b uxth r3, r3 + 80053e4: 2280 movs r2, #128 @ 0x80 + 80053e6: 0192 lsls r2, r2, #6 + 80053e8: 4313 orrs r3, r2 + 80053ea: b29a uxth r2, r3 + 80053ec: 4b97 ldr r3, [pc, #604] @ (800564c ) + 80053ee: 809a strh r2, [r3, #4] + DBW_Stop(); + 80053f0: f7fe fe26 bl 8004040 + TX_Schedule((unsigned char*) msg1, 42); + 80053f4: 4b96 ldr r3, [pc, #600] @ (8005650 ) + 80053f6: 212a movs r1, #42 @ 0x2a + 80053f8: 0018 movs r0, r3 + 80053fa: f001 f815 bl 8006428 + } + } +//PPS2 + + if (config->pps2_min < config->pps2_max) { + 80053fe: 4b92 ldr r3, [pc, #584] @ (8005648 ) + 8005400: 681b ldr r3, [r3, #0] + 8005402: 88db ldrh r3, [r3, #6] + 8005404: b29a uxth r2, r3 + 8005406: 4b90 ldr r3, [pc, #576] @ (8005648 ) + 8005408: 681b ldr r3, [r3, #0] + 800540a: 899b ldrh r3, [r3, #12] + 800540c: b29b uxth r3, r3 + 800540e: 429a cmp r2, r3 + 8005410: d22a bcs.n 8005468 + if ((config->pps2_margin > config->pps2_min) + 8005412: 4b8d ldr r3, [pc, #564] @ (8005648 ) + 8005414: 681b ldr r3, [r3, #0] + 8005416: 4a8f ldr r2, [pc, #572] @ (8005654 ) + 8005418: 5a9b ldrh r3, [r3, r2] + 800541a: b29a uxth r2, r3 + 800541c: 4b8a ldr r3, [pc, #552] @ (8005648 ) + 800541e: 681b ldr r3, [r3, #0] + 8005420: 88db ldrh r3, [r3, #6] + 8005422: b29b uxth r3, r3 + 8005424: 429a cmp r2, r3 + 8005426: d80e bhi.n 8005446 + || ((config->pps2_max + config->pps2_margin) > 4095)) { + 8005428: 4b87 ldr r3, [pc, #540] @ (8005648 ) + 800542a: 681b ldr r3, [r3, #0] + 800542c: 899b ldrh r3, [r3, #12] + 800542e: b29b uxth r3, r3 + 8005430: 0019 movs r1, r3 + 8005432: 4b85 ldr r3, [pc, #532] @ (8005648 ) + 8005434: 681b ldr r3, [r3, #0] + 8005436: 4a87 ldr r2, [pc, #540] @ (8005654 ) + 8005438: 5a9b ldrh r3, [r3, r2] + 800543a: b29b uxth r3, r3 + 800543c: 18ca adds r2, r1, r3 + 800543e: 2380 movs r3, #128 @ 0x80 + 8005440: 015b lsls r3, r3, #5 + 8005442: 429a cmp r2, r3 + 8005444: db3a blt.n 80054bc + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 8005446: 4b81 ldr r3, [pc, #516] @ (800564c ) + 8005448: 889b ldrh r3, [r3, #4] + 800544a: b29b uxth r3, r3 + 800544c: 2280 movs r2, #128 @ 0x80 + 800544e: 0192 lsls r2, r2, #6 + 8005450: 4313 orrs r3, r2 + 8005452: b29a uxth r2, r3 + 8005454: 4b7d ldr r3, [pc, #500] @ (800564c ) + 8005456: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005458: f7fe fdf2 bl 8004040 + TX_Schedule((unsigned char*) msg2, 42); + 800545c: 4b7e ldr r3, [pc, #504] @ (8005658 ) + 800545e: 212a movs r1, #42 @ 0x2a + 8005460: 0018 movs r0, r3 + 8005462: f000 ffe1 bl 8006428 + 8005466: e029 b.n 80054bc + } + } else { + //config->pps2_min > config->pps1_max + if ((config->pps2_margin > config->pps2_max) + 8005468: 4b77 ldr r3, [pc, #476] @ (8005648 ) + 800546a: 681b ldr r3, [r3, #0] + 800546c: 4a79 ldr r2, [pc, #484] @ (8005654 ) + 800546e: 5a9b ldrh r3, [r3, r2] + 8005470: b29a uxth r2, r3 + 8005472: 4b75 ldr r3, [pc, #468] @ (8005648 ) + 8005474: 681b ldr r3, [r3, #0] + 8005476: 899b ldrh r3, [r3, #12] + 8005478: b29b uxth r3, r3 + 800547a: 429a cmp r2, r3 + 800547c: d80e bhi.n 800549c + || ((config->pps2_min + config->pps2_margin) > 4095)) { + 800547e: 4b72 ldr r3, [pc, #456] @ (8005648 ) + 8005480: 681b ldr r3, [r3, #0] + 8005482: 88db ldrh r3, [r3, #6] + 8005484: b29b uxth r3, r3 + 8005486: 0019 movs r1, r3 + 8005488: 4b6f ldr r3, [pc, #444] @ (8005648 ) + 800548a: 681b ldr r3, [r3, #0] + 800548c: 4a71 ldr r2, [pc, #452] @ (8005654 ) + 800548e: 5a9b ldrh r3, [r3, r2] + 8005490: b29b uxth r3, r3 + 8005492: 18ca adds r2, r1, r3 + 8005494: 2380 movs r3, #128 @ 0x80 + 8005496: 015b lsls r3, r3, #5 + 8005498: 429a cmp r2, r3 + 800549a: db0f blt.n 80054bc + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 800549c: 4b6b ldr r3, [pc, #428] @ (800564c ) + 800549e: 889b ldrh r3, [r3, #4] + 80054a0: b29b uxth r3, r3 + 80054a2: 2280 movs r2, #128 @ 0x80 + 80054a4: 0192 lsls r2, r2, #6 + 80054a6: 4313 orrs r3, r2 + 80054a8: b29a uxth r2, r3 + 80054aa: 4b68 ldr r3, [pc, #416] @ (800564c ) + 80054ac: 809a strh r2, [r3, #4] + DBW_Stop(); + 80054ae: f7fe fdc7 bl 8004040 + TX_Schedule((unsigned char*) msg2, 42); + 80054b2: 4b69 ldr r3, [pc, #420] @ (8005658 ) + 80054b4: 212a movs r1, #42 @ 0x2a + 80054b6: 0018 movs r0, r3 + 80054b8: f000 ffb6 bl 8006428 + } + } + +//TPS1 + + if (config->tps1_min < config->tps1_max) { + 80054bc: 4b62 ldr r3, [pc, #392] @ (8005648 ) + 80054be: 681b ldr r3, [r3, #0] + 80054c0: 89db ldrh r3, [r3, #14] + 80054c2: b29a uxth r2, r3 + 80054c4: 4b60 ldr r3, [pc, #384] @ (8005648 ) + 80054c6: 681b ldr r3, [r3, #0] + 80054c8: 8a1b ldrh r3, [r3, #16] + 80054ca: b29b uxth r3, r3 + 80054cc: 429a cmp r2, r3 + 80054ce: d22a bcs.n 8005526 + if ((config->tps1_margin > config->tps1_min) + 80054d0: 4b5d ldr r3, [pc, #372] @ (8005648 ) + 80054d2: 681b ldr r3, [r3, #0] + 80054d4: 4a61 ldr r2, [pc, #388] @ (800565c ) + 80054d6: 5a9b ldrh r3, [r3, r2] + 80054d8: b29a uxth r2, r3 + 80054da: 4b5b ldr r3, [pc, #364] @ (8005648 ) + 80054dc: 681b ldr r3, [r3, #0] + 80054de: 89db ldrh r3, [r3, #14] + 80054e0: b29b uxth r3, r3 + 80054e2: 429a cmp r2, r3 + 80054e4: d80e bhi.n 8005504 + || ((config->tps1_max + config->tps1_margin) > 4095)) { + 80054e6: 4b58 ldr r3, [pc, #352] @ (8005648 ) + 80054e8: 681b ldr r3, [r3, #0] + 80054ea: 8a1b ldrh r3, [r3, #16] + 80054ec: b29b uxth r3, r3 + 80054ee: 0019 movs r1, r3 + 80054f0: 4b55 ldr r3, [pc, #340] @ (8005648 ) + 80054f2: 681b ldr r3, [r3, #0] + 80054f4: 4a59 ldr r2, [pc, #356] @ (800565c ) + 80054f6: 5a9b ldrh r3, [r3, r2] + 80054f8: b29b uxth r3, r3 + 80054fa: 18ca adds r2, r1, r3 + 80054fc: 2380 movs r3, #128 @ 0x80 + 80054fe: 015b lsls r3, r3, #5 + 8005500: 429a cmp r2, r3 + 8005502: db3a blt.n 800557a + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 8005504: 4b51 ldr r3, [pc, #324] @ (800564c ) + 8005506: 889b ldrh r3, [r3, #4] + 8005508: b29b uxth r3, r3 + 800550a: 2280 movs r2, #128 @ 0x80 + 800550c: 0192 lsls r2, r2, #6 + 800550e: 4313 orrs r3, r2 + 8005510: b29a uxth r2, r3 + 8005512: 4b4e ldr r3, [pc, #312] @ (800564c ) + 8005514: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005516: f7fe fd93 bl 8004040 + TX_Schedule((unsigned char*) msg3, 42); + 800551a: 4b51 ldr r3, [pc, #324] @ (8005660 ) + 800551c: 212a movs r1, #42 @ 0x2a + 800551e: 0018 movs r0, r3 + 8005520: f000 ff82 bl 8006428 + 8005524: e029 b.n 800557a + } + } else { + //config->tps1_min > config->tps1_max + if ((config->tps1_margin > config->tps1_max) + 8005526: 4b48 ldr r3, [pc, #288] @ (8005648 ) + 8005528: 681b ldr r3, [r3, #0] + 800552a: 4a4c ldr r2, [pc, #304] @ (800565c ) + 800552c: 5a9b ldrh r3, [r3, r2] + 800552e: b29a uxth r2, r3 + 8005530: 4b45 ldr r3, [pc, #276] @ (8005648 ) + 8005532: 681b ldr r3, [r3, #0] + 8005534: 8a1b ldrh r3, [r3, #16] + 8005536: b29b uxth r3, r3 + 8005538: 429a cmp r2, r3 + 800553a: d80e bhi.n 800555a + || ((config->tps1_min + config->tps1_margin) > 4095)) { + 800553c: 4b42 ldr r3, [pc, #264] @ (8005648 ) + 800553e: 681b ldr r3, [r3, #0] + 8005540: 89db ldrh r3, [r3, #14] + 8005542: b29b uxth r3, r3 + 8005544: 0019 movs r1, r3 + 8005546: 4b40 ldr r3, [pc, #256] @ (8005648 ) + 8005548: 681b ldr r3, [r3, #0] + 800554a: 4a44 ldr r2, [pc, #272] @ (800565c ) + 800554c: 5a9b ldrh r3, [r3, r2] + 800554e: b29b uxth r3, r3 + 8005550: 18ca adds r2, r1, r3 + 8005552: 2380 movs r3, #128 @ 0x80 + 8005554: 015b lsls r3, r3, #5 + 8005556: 429a cmp r2, r3 + 8005558: db0f blt.n 800557a + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 800555a: 4b3c ldr r3, [pc, #240] @ (800564c ) + 800555c: 889b ldrh r3, [r3, #4] + 800555e: b29b uxth r3, r3 + 8005560: 2280 movs r2, #128 @ 0x80 + 8005562: 0192 lsls r2, r2, #6 + 8005564: 4313 orrs r3, r2 + 8005566: b29a uxth r2, r3 + 8005568: 4b38 ldr r3, [pc, #224] @ (800564c ) + 800556a: 809a strh r2, [r3, #4] + DBW_Stop(); + 800556c: f7fe fd68 bl 8004040 + TX_Schedule((unsigned char*) msg3, 42); + 8005570: 4b3b ldr r3, [pc, #236] @ (8005660 ) + 8005572: 212a movs r1, #42 @ 0x2a + 8005574: 0018 movs r0, r3 + 8005576: f000 ff57 bl 8006428 + } + } +//TPS2 + + if (config->tps2_min < config->tps2_max) { + 800557a: 4b33 ldr r3, [pc, #204] @ (8005648 ) + 800557c: 681b ldr r3, [r3, #0] + 800557e: 8a5b ldrh r3, [r3, #18] + 8005580: b29a uxth r2, r3 + 8005582: 4b31 ldr r3, [pc, #196] @ (8005648 ) + 8005584: 681b ldr r3, [r3, #0] + 8005586: 8b1b ldrh r3, [r3, #24] + 8005588: b29b uxth r3, r3 + 800558a: 429a cmp r2, r3 + 800558c: d22c bcs.n 80055e8 + if ((config->tps2_margin > config->tps2_min) + 800558e: 4b2e ldr r3, [pc, #184] @ (8005648 ) + 8005590: 681a ldr r2, [r3, #0] + 8005592: 23d1 movs r3, #209 @ 0xd1 + 8005594: 009b lsls r3, r3, #2 + 8005596: 5ad3 ldrh r3, [r2, r3] + 8005598: b29a uxth r2, r3 + 800559a: 4b2b ldr r3, [pc, #172] @ (8005648 ) + 800559c: 681b ldr r3, [r3, #0] + 800559e: 8a5b ldrh r3, [r3, #18] + 80055a0: b29b uxth r3, r3 + 80055a2: 429a cmp r2, r3 + 80055a4: d80f bhi.n 80055c6 + || ((config->tps2_max + config->tps2_margin) > 4095)) { + 80055a6: 4b28 ldr r3, [pc, #160] @ (8005648 ) + 80055a8: 681b ldr r3, [r3, #0] + 80055aa: 8b1b ldrh r3, [r3, #24] + 80055ac: b29b uxth r3, r3 + 80055ae: 0019 movs r1, r3 + 80055b0: 4b25 ldr r3, [pc, #148] @ (8005648 ) + 80055b2: 681a ldr r2, [r3, #0] + 80055b4: 23d1 movs r3, #209 @ 0xd1 + 80055b6: 009b lsls r3, r3, #2 + 80055b8: 5ad3 ldrh r3, [r2, r3] + 80055ba: b29b uxth r3, r3 + 80055bc: 18ca adds r2, r1, r3 + 80055be: 2380 movs r3, #128 @ 0x80 + 80055c0: 015b lsls r3, r3, #5 + 80055c2: 429a cmp r2, r3 + 80055c4: db3c blt.n 8005640 + //config errror + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 80055c6: 4b21 ldr r3, [pc, #132] @ (800564c ) + 80055c8: 889b ldrh r3, [r3, #4] + 80055ca: b29b uxth r3, r3 + 80055cc: 2280 movs r2, #128 @ 0x80 + 80055ce: 0192 lsls r2, r2, #6 + 80055d0: 4313 orrs r3, r2 + 80055d2: b29a uxth r2, r3 + 80055d4: 4b1d ldr r3, [pc, #116] @ (800564c ) + 80055d6: 809a strh r2, [r3, #4] + DBW_Stop(); + 80055d8: f7fe fd32 bl 8004040 + TX_Schedule((unsigned char*) msg4, 42); + 80055dc: 4b21 ldr r3, [pc, #132] @ (8005664 ) + 80055de: 212a movs r1, #42 @ 0x2a + 80055e0: 0018 movs r0, r3 + 80055e2: f000 ff21 bl 8006428 + DBW_Stop(); + TX_Schedule((unsigned char*) msg4, 42); + } + } + +} + 80055e6: e02b b.n 8005640 + if ((config->tps2_margin > config->tps2_max) + 80055e8: 4b17 ldr r3, [pc, #92] @ (8005648 ) + 80055ea: 681a ldr r2, [r3, #0] + 80055ec: 23d1 movs r3, #209 @ 0xd1 + 80055ee: 009b lsls r3, r3, #2 + 80055f0: 5ad3 ldrh r3, [r2, r3] + 80055f2: b29a uxth r2, r3 + 80055f4: 4b14 ldr r3, [pc, #80] @ (8005648 ) + 80055f6: 681b ldr r3, [r3, #0] + 80055f8: 8b1b ldrh r3, [r3, #24] + 80055fa: b29b uxth r3, r3 + 80055fc: 429a cmp r2, r3 + 80055fe: d80f bhi.n 8005620 + || ((config->tps2_min + config->tps2_margin) > 4095)) { + 8005600: 4b11 ldr r3, [pc, #68] @ (8005648 ) + 8005602: 681b ldr r3, [r3, #0] + 8005604: 8a5b ldrh r3, [r3, #18] + 8005606: b29b uxth r3, r3 + 8005608: 0019 movs r1, r3 + 800560a: 4b0f ldr r3, [pc, #60] @ (8005648 ) + 800560c: 681a ldr r2, [r3, #0] + 800560e: 23d1 movs r3, #209 @ 0xd1 + 8005610: 009b lsls r3, r3, #2 + 8005612: 5ad3 ldrh r3, [r2, r3] + 8005614: b29b uxth r3, r3 + 8005616: 18ca adds r2, r1, r3 + 8005618: 2380 movs r3, #128 @ 0x80 + 800561a: 015b lsls r3, r3, #5 + 800561c: 429a cmp r2, r3 + 800561e: db0f blt.n 8005640 + var.status0 |= DBW_STATUS0_CONF_ERROR_F; + 8005620: 4b0a ldr r3, [pc, #40] @ (800564c ) + 8005622: 889b ldrh r3, [r3, #4] + 8005624: b29b uxth r3, r3 + 8005626: 2280 movs r2, #128 @ 0x80 + 8005628: 0192 lsls r2, r2, #6 + 800562a: 4313 orrs r3, r2 + 800562c: b29a uxth r2, r3 + 800562e: 4b07 ldr r3, [pc, #28] @ (800564c ) + 8005630: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005632: f7fe fd05 bl 8004040 + TX_Schedule((unsigned char*) msg4, 42); + 8005636: 4b0b ldr r3, [pc, #44] @ (8005664 ) + 8005638: 212a movs r1, #42 @ 0x2a + 800563a: 0018 movs r0, r3 + 800563c: f000 fef4 bl 8006428 +} + 8005640: 46c0 nop @ (mov r8, r8) + 8005642: 46bd mov sp, r7 + 8005644: bd80 pop {r7, pc} + 8005646: 46c0 nop @ (mov r8, r8) + 8005648: 200009cc .word 0x200009cc + 800564c: 20000998 .word 0x20000998 + 8005650: 08008a30 .word 0x08008a30 + 8005654: 0000033e .word 0x0000033e + 8005658: 08008a5c .word 0x08008a5c + 800565c: 00000342 .word 0x00000342 + 8005660: 08008a88 .word 0x08008a88 + 8005664: 08008ab4 .word 0x08008ab4 + +08005668 : + +void Check_Adc_Range(void) { + 8005668: b580 push {r7, lr} + 800566a: af00 add r7, sp, #0 + +//PPS1 + if (config->pps1_min < config->pps1_max) { + 800566c: 4bc1 ldr r3, [pc, #772] @ (8005974 ) + 800566e: 681b ldr r3, [r3, #0] + 8005670: 885b ldrh r3, [r3, #2] + 8005672: b29a uxth r2, r3 + 8005674: 4bbf ldr r3, [pc, #764] @ (8005974 ) + 8005676: 681b ldr r3, [r3, #0] + 8005678: 889b ldrh r3, [r3, #4] + 800567a: b29b uxth r3, r3 + 800567c: 429a cmp r2, r3 + 800567e: d240 bcs.n 8005702 + + if (var.pps1_adc < (config->pps1_min - config->pps1_margin)) { + 8005680: 4bbd ldr r3, [pc, #756] @ (8005978 ) + 8005682: 899b ldrh r3, [r3, #12] + 8005684: b29b uxth r3, r3 + 8005686: 0019 movs r1, r3 + 8005688: 4bba ldr r3, [pc, #744] @ (8005974 ) + 800568a: 681b ldr r3, [r3, #0] + 800568c: 885b ldrh r3, [r3, #2] + 800568e: b29b uxth r3, r3 + 8005690: 0018 movs r0, r3 + 8005692: 4bb8 ldr r3, [pc, #736] @ (8005974 ) + 8005694: 681a ldr r2, [r3, #0] + 8005696: 23cf movs r3, #207 @ 0xcf + 8005698: 009b lsls r3, r3, #2 + 800569a: 5ad3 ldrh r3, [r2, r3] + 800569c: b29b uxth r3, r3 + 800569e: 1ac3 subs r3, r0, r3 + 80056a0: 4299 cmp r1, r3 + 80056a2: da0d bge.n 80056c0 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80056a4: 4bb4 ldr r3, [pc, #720] @ (8005978 ) + 80056a6: 889b ldrh r3, [r3, #4] + 80056a8: b29b uxth r3, r3 + 80056aa: 2280 movs r2, #128 @ 0x80 + 80056ac: 01d2 lsls r2, r2, #7 + 80056ae: 4313 orrs r3, r2 + 80056b0: b29a uxth r2, r3 + 80056b2: 4bb1 ldr r3, [pc, #708] @ (8005978 ) + 80056b4: 809a strh r2, [r3, #4] + DBW_Stop(); + 80056b6: f7fe fcc3 bl 8004040 + var.status3 = STATUS3_PPS1_SS_GND; + 80056ba: 4baf ldr r3, [pc, #700] @ (8005978 ) + 80056bc: 2201 movs r2, #1 + 80056be: 815a strh r2, [r3, #10] + } + + if (var.pps1_adc > (config->pps1_max + config->pps1_margin)) { + 80056c0: 4bad ldr r3, [pc, #692] @ (8005978 ) + 80056c2: 899b ldrh r3, [r3, #12] + 80056c4: b29b uxth r3, r3 + 80056c6: 0019 movs r1, r3 + 80056c8: 4baa ldr r3, [pc, #680] @ (8005974 ) + 80056ca: 681b ldr r3, [r3, #0] + 80056cc: 889b ldrh r3, [r3, #4] + 80056ce: b29b uxth r3, r3 + 80056d0: 0018 movs r0, r3 + 80056d2: 4ba8 ldr r3, [pc, #672] @ (8005974 ) + 80056d4: 681a ldr r2, [r3, #0] + 80056d6: 23cf movs r3, #207 @ 0xcf + 80056d8: 009b lsls r3, r3, #2 + 80056da: 5ad3 ldrh r3, [r2, r3] + 80056dc: b29b uxth r3, r3 + 80056de: 18c3 adds r3, r0, r3 + 80056e0: 4299 cmp r1, r3 + 80056e2: dd4e ble.n 8005782 + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80056e4: 4ba4 ldr r3, [pc, #656] @ (8005978 ) + 80056e6: 889b ldrh r3, [r3, #4] + 80056e8: b29b uxth r3, r3 + 80056ea: 2280 movs r2, #128 @ 0x80 + 80056ec: 01d2 lsls r2, r2, #7 + 80056ee: 4313 orrs r3, r2 + 80056f0: b29a uxth r2, r3 + 80056f2: 4ba1 ldr r3, [pc, #644] @ (8005978 ) + 80056f4: 809a strh r2, [r3, #4] + DBW_Stop(); + 80056f6: f7fe fca3 bl 8004040 + var.status3 = STATUS3_PPS1_SS_VREF; + 80056fa: 4b9f ldr r3, [pc, #636] @ (8005978 ) + 80056fc: 2202 movs r2, #2 + 80056fe: 815a strh r2, [r3, #10] + 8005700: e03f b.n 8005782 + } + } else { + //config->pps1_min < config->pps1_max + if (var.pps1_adc < (config->pps1_max - config->pps1_margin)) { + 8005702: 4b9d ldr r3, [pc, #628] @ (8005978 ) + 8005704: 899b ldrh r3, [r3, #12] + 8005706: b29b uxth r3, r3 + 8005708: 0019 movs r1, r3 + 800570a: 4b9a ldr r3, [pc, #616] @ (8005974 ) + 800570c: 681b ldr r3, [r3, #0] + 800570e: 889b ldrh r3, [r3, #4] + 8005710: b29b uxth r3, r3 + 8005712: 0018 movs r0, r3 + 8005714: 4b97 ldr r3, [pc, #604] @ (8005974 ) + 8005716: 681a ldr r2, [r3, #0] + 8005718: 23cf movs r3, #207 @ 0xcf + 800571a: 009b lsls r3, r3, #2 + 800571c: 5ad3 ldrh r3, [r2, r3] + 800571e: b29b uxth r3, r3 + 8005720: 1ac3 subs r3, r0, r3 + 8005722: 4299 cmp r1, r3 + 8005724: da0d bge.n 8005742 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005726: 4b94 ldr r3, [pc, #592] @ (8005978 ) + 8005728: 889b ldrh r3, [r3, #4] + 800572a: b29b uxth r3, r3 + 800572c: 2280 movs r2, #128 @ 0x80 + 800572e: 01d2 lsls r2, r2, #7 + 8005730: 4313 orrs r3, r2 + 8005732: b29a uxth r2, r3 + 8005734: 4b90 ldr r3, [pc, #576] @ (8005978 ) + 8005736: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005738: f7fe fc82 bl 8004040 + var.status3 = STATUS3_PPS1_SS_GND; + 800573c: 4b8e ldr r3, [pc, #568] @ (8005978 ) + 800573e: 2201 movs r2, #1 + 8005740: 815a strh r2, [r3, #10] + } + + if (var.pps1_adc > (config->pps1_min + config->pps1_margin)) { + 8005742: 4b8d ldr r3, [pc, #564] @ (8005978 ) + 8005744: 899b ldrh r3, [r3, #12] + 8005746: b29b uxth r3, r3 + 8005748: 0019 movs r1, r3 + 800574a: 4b8a ldr r3, [pc, #552] @ (8005974 ) + 800574c: 681b ldr r3, [r3, #0] + 800574e: 885b ldrh r3, [r3, #2] + 8005750: b29b uxth r3, r3 + 8005752: 0018 movs r0, r3 + 8005754: 4b87 ldr r3, [pc, #540] @ (8005974 ) + 8005756: 681a ldr r2, [r3, #0] + 8005758: 23cf movs r3, #207 @ 0xcf + 800575a: 009b lsls r3, r3, #2 + 800575c: 5ad3 ldrh r3, [r2, r3] + 800575e: b29b uxth r3, r3 + 8005760: 18c3 adds r3, r0, r3 + 8005762: 4299 cmp r1, r3 + 8005764: dd0d ble.n 8005782 + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005766: 4b84 ldr r3, [pc, #528] @ (8005978 ) + 8005768: 889b ldrh r3, [r3, #4] + 800576a: b29b uxth r3, r3 + 800576c: 2280 movs r2, #128 @ 0x80 + 800576e: 01d2 lsls r2, r2, #7 + 8005770: 4313 orrs r3, r2 + 8005772: b29a uxth r2, r3 + 8005774: 4b80 ldr r3, [pc, #512] @ (8005978 ) + 8005776: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005778: f7fe fc62 bl 8004040 + var.status3 = STATUS3_PPS1_SS_VREF; + 800577c: 4b7e ldr r3, [pc, #504] @ (8005978 ) + 800577e: 2202 movs r2, #2 + 8005780: 815a strh r2, [r3, #10] + } + } + +//PPS2 + if (config->pps2_min < config->pps2_max) { + 8005782: 4b7c ldr r3, [pc, #496] @ (8005974 ) + 8005784: 681b ldr r3, [r3, #0] + 8005786: 88db ldrh r3, [r3, #6] + 8005788: b29a uxth r2, r3 + 800578a: 4b7a ldr r3, [pc, #488] @ (8005974 ) + 800578c: 681b ldr r3, [r3, #0] + 800578e: 899b ldrh r3, [r3, #12] + 8005790: b29b uxth r3, r3 + 8005792: 429a cmp r2, r3 + 8005794: d23e bcs.n 8005814 + if (var.pps2_adc < (config->pps2_min - config->pps2_margin)) { + 8005796: 4b78 ldr r3, [pc, #480] @ (8005978 ) + 8005798: 89db ldrh r3, [r3, #14] + 800579a: b29b uxth r3, r3 + 800579c: 0019 movs r1, r3 + 800579e: 4b75 ldr r3, [pc, #468] @ (8005974 ) + 80057a0: 681b ldr r3, [r3, #0] + 80057a2: 88db ldrh r3, [r3, #6] + 80057a4: b29b uxth r3, r3 + 80057a6: 0018 movs r0, r3 + 80057a8: 4b72 ldr r3, [pc, #456] @ (8005974 ) + 80057aa: 681b ldr r3, [r3, #0] + 80057ac: 4a73 ldr r2, [pc, #460] @ (800597c ) + 80057ae: 5a9b ldrh r3, [r3, r2] + 80057b0: b29b uxth r3, r3 + 80057b2: 1ac3 subs r3, r0, r3 + 80057b4: 4299 cmp r1, r3 + 80057b6: da0d bge.n 80057d4 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80057b8: 4b6f ldr r3, [pc, #444] @ (8005978 ) + 80057ba: 889b ldrh r3, [r3, #4] + 80057bc: b29b uxth r3, r3 + 80057be: 2280 movs r2, #128 @ 0x80 + 80057c0: 01d2 lsls r2, r2, #7 + 80057c2: 4313 orrs r3, r2 + 80057c4: b29a uxth r2, r3 + 80057c6: 4b6c ldr r3, [pc, #432] @ (8005978 ) + 80057c8: 809a strh r2, [r3, #4] + DBW_Stop(); + 80057ca: f7fe fc39 bl 8004040 + var.status3 = STATUS3_PPS2_SS_GND; + 80057ce: 4b6a ldr r3, [pc, #424] @ (8005978 ) + 80057d0: 2203 movs r2, #3 + 80057d2: 815a strh r2, [r3, #10] + } + + if (var.pps2_adc > (config->pps2_max + config->pps2_margin)) { + 80057d4: 4b68 ldr r3, [pc, #416] @ (8005978 ) + 80057d6: 89db ldrh r3, [r3, #14] + 80057d8: b29b uxth r3, r3 + 80057da: 0019 movs r1, r3 + 80057dc: 4b65 ldr r3, [pc, #404] @ (8005974 ) + 80057de: 681b ldr r3, [r3, #0] + 80057e0: 899b ldrh r3, [r3, #12] + 80057e2: b29b uxth r3, r3 + 80057e4: 0018 movs r0, r3 + 80057e6: 4b63 ldr r3, [pc, #396] @ (8005974 ) + 80057e8: 681b ldr r3, [r3, #0] + 80057ea: 4a64 ldr r2, [pc, #400] @ (800597c ) + 80057ec: 5a9b ldrh r3, [r3, r2] + 80057ee: b29b uxth r3, r3 + 80057f0: 18c3 adds r3, r0, r3 + 80057f2: 4299 cmp r1, r3 + 80057f4: dd4c ble.n 8005890 + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80057f6: 4b60 ldr r3, [pc, #384] @ (8005978 ) + 80057f8: 889b ldrh r3, [r3, #4] + 80057fa: b29b uxth r3, r3 + 80057fc: 2280 movs r2, #128 @ 0x80 + 80057fe: 01d2 lsls r2, r2, #7 + 8005800: 4313 orrs r3, r2 + 8005802: b29a uxth r2, r3 + 8005804: 4b5c ldr r3, [pc, #368] @ (8005978 ) + 8005806: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005808: f7fe fc1a bl 8004040 + var.status3 = STATUS3_PPS1_SS_VREF; + 800580c: 4b5a ldr r3, [pc, #360] @ (8005978 ) + 800580e: 2202 movs r2, #2 + 8005810: 815a strh r2, [r3, #10] + 8005812: e03d b.n 8005890 + } + } else { + + if (var.pps2_adc < (config->pps2_max - config->pps2_margin)) { + 8005814: 4b58 ldr r3, [pc, #352] @ (8005978 ) + 8005816: 89db ldrh r3, [r3, #14] + 8005818: b29b uxth r3, r3 + 800581a: 0019 movs r1, r3 + 800581c: 4b55 ldr r3, [pc, #340] @ (8005974 ) + 800581e: 681b ldr r3, [r3, #0] + 8005820: 899b ldrh r3, [r3, #12] + 8005822: b29b uxth r3, r3 + 8005824: 0018 movs r0, r3 + 8005826: 4b53 ldr r3, [pc, #332] @ (8005974 ) + 8005828: 681b ldr r3, [r3, #0] + 800582a: 4a54 ldr r2, [pc, #336] @ (800597c ) + 800582c: 5a9b ldrh r3, [r3, r2] + 800582e: b29b uxth r3, r3 + 8005830: 1ac3 subs r3, r0, r3 + 8005832: 4299 cmp r1, r3 + 8005834: da0d bge.n 8005852 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005836: 4b50 ldr r3, [pc, #320] @ (8005978 ) + 8005838: 889b ldrh r3, [r3, #4] + 800583a: b29b uxth r3, r3 + 800583c: 2280 movs r2, #128 @ 0x80 + 800583e: 01d2 lsls r2, r2, #7 + 8005840: 4313 orrs r3, r2 + 8005842: b29a uxth r2, r3 + 8005844: 4b4c ldr r3, [pc, #304] @ (8005978 ) + 8005846: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005848: f7fe fbfa bl 8004040 + var.status3 = STATUS3_PPS2_SS_GND; + 800584c: 4b4a ldr r3, [pc, #296] @ (8005978 ) + 800584e: 2203 movs r2, #3 + 8005850: 815a strh r2, [r3, #10] + } + + if (var.pps2_adc > (config->pps2_min + config->pps2_margin)) { + 8005852: 4b49 ldr r3, [pc, #292] @ (8005978 ) + 8005854: 89db ldrh r3, [r3, #14] + 8005856: b29b uxth r3, r3 + 8005858: 0019 movs r1, r3 + 800585a: 4b46 ldr r3, [pc, #280] @ (8005974 ) + 800585c: 681b ldr r3, [r3, #0] + 800585e: 88db ldrh r3, [r3, #6] + 8005860: b29b uxth r3, r3 + 8005862: 0018 movs r0, r3 + 8005864: 4b43 ldr r3, [pc, #268] @ (8005974 ) + 8005866: 681b ldr r3, [r3, #0] + 8005868: 4a44 ldr r2, [pc, #272] @ (800597c ) + 800586a: 5a9b ldrh r3, [r3, r2] + 800586c: b29b uxth r3, r3 + 800586e: 18c3 adds r3, r0, r3 + 8005870: 4299 cmp r1, r3 + 8005872: dd0d ble.n 8005890 + //Fault condition PPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005874: 4b40 ldr r3, [pc, #256] @ (8005978 ) + 8005876: 889b ldrh r3, [r3, #4] + 8005878: b29b uxth r3, r3 + 800587a: 2280 movs r2, #128 @ 0x80 + 800587c: 01d2 lsls r2, r2, #7 + 800587e: 4313 orrs r3, r2 + 8005880: b29a uxth r2, r3 + 8005882: 4b3d ldr r3, [pc, #244] @ (8005978 ) + 8005884: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005886: f7fe fbdb bl 8004040 + var.status3 = STATUS3_PPS1_SS_VREF; + 800588a: 4b3b ldr r3, [pc, #236] @ (8005978 ) + 800588c: 2202 movs r2, #2 + 800588e: 815a strh r2, [r3, #10] + } + } + +//PPS Delta + if ((var.pps_delta > config->pps_delta_margin) + 8005890: 4b39 ldr r3, [pc, #228] @ (8005978 ) + 8005892: 8d5b ldrh r3, [r3, #42] @ 0x2a + 8005894: b21a sxth r2, r3 + 8005896: 4b37 ldr r3, [pc, #220] @ (8005974 ) + 8005898: 6819 ldr r1, [r3, #0] + 800589a: 23d0 movs r3, #208 @ 0xd0 + 800589c: 009b lsls r3, r3, #2 + 800589e: 5acb ldrh r3, [r1, r3] + 80058a0: b21b sxth r3, r3 + 80058a2: 429a cmp r2, r3 + 80058a4: dc0e bgt.n 80058c4 + || (var.pps_delta < ((int16_t) -config->pps_delta_margin))) { + 80058a6: 4b34 ldr r3, [pc, #208] @ (8005978 ) + 80058a8: 8d5b ldrh r3, [r3, #42] @ 0x2a + 80058aa: b21a sxth r2, r3 + 80058ac: 4b31 ldr r3, [pc, #196] @ (8005974 ) + 80058ae: 6819 ldr r1, [r3, #0] + 80058b0: 23d0 movs r3, #208 @ 0xd0 + 80058b2: 009b lsls r3, r3, #2 + 80058b4: 5acb ldrh r3, [r1, r3] + 80058b6: b21b sxth r3, r3 + 80058b8: b29b uxth r3, r3 + 80058ba: 425b negs r3, r3 + 80058bc: b29b uxth r3, r3 + 80058be: b21b sxth r3, r3 + 80058c0: 429a cmp r2, r3 + 80058c2: da0d bge.n 80058e0 + //Fault condition PPS DELTA + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80058c4: 4b2c ldr r3, [pc, #176] @ (8005978 ) + 80058c6: 889b ldrh r3, [r3, #4] + 80058c8: b29b uxth r3, r3 + 80058ca: 2280 movs r2, #128 @ 0x80 + 80058cc: 01d2 lsls r2, r2, #7 + 80058ce: 4313 orrs r3, r2 + 80058d0: b29a uxth r2, r3 + 80058d2: 4b29 ldr r3, [pc, #164] @ (8005978 ) + 80058d4: 809a strh r2, [r3, #4] + DBW_Stop(); + 80058d6: f7fe fbb3 bl 8004040 + var.status3 = STATUS3_PPS_DELTA; + 80058da: 4b27 ldr r3, [pc, #156] @ (8005978 ) + 80058dc: 2205 movs r2, #5 + 80058de: 815a strh r2, [r3, #10] + } + +//########################################## + //TPS1 + if (config->tps1_min < config->tps1_max) { + 80058e0: 4b24 ldr r3, [pc, #144] @ (8005974 ) + 80058e2: 681b ldr r3, [r3, #0] + 80058e4: 89db ldrh r3, [r3, #14] + 80058e6: b29a uxth r2, r3 + 80058e8: 4b22 ldr r3, [pc, #136] @ (8005974 ) + 80058ea: 681b ldr r3, [r3, #0] + 80058ec: 8a1b ldrh r3, [r3, #16] + 80058ee: b29b uxth r3, r3 + 80058f0: 429a cmp r2, r3 + 80058f2: d247 bcs.n 8005984 + if (var.tps1_adc < (config->tps1_min - config->tps1_margin)) { + 80058f4: 4b20 ldr r3, [pc, #128] @ (8005978 ) + 80058f6: 8a1b ldrh r3, [r3, #16] + 80058f8: b29b uxth r3, r3 + 80058fa: 0019 movs r1, r3 + 80058fc: 4b1d ldr r3, [pc, #116] @ (8005974 ) + 80058fe: 681b ldr r3, [r3, #0] + 8005900: 89db ldrh r3, [r3, #14] + 8005902: b29b uxth r3, r3 + 8005904: 0018 movs r0, r3 + 8005906: 4b1b ldr r3, [pc, #108] @ (8005974 ) + 8005908: 681b ldr r3, [r3, #0] + 800590a: 4a1d ldr r2, [pc, #116] @ (8005980 ) + 800590c: 5a9b ldrh r3, [r3, r2] + 800590e: b29b uxth r3, r3 + 8005910: 1ac3 subs r3, r0, r3 + 8005912: 4299 cmp r1, r3 + 8005914: da0d bge.n 8005932 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005916: 4b18 ldr r3, [pc, #96] @ (8005978 ) + 8005918: 889b ldrh r3, [r3, #4] + 800591a: b29b uxth r3, r3 + 800591c: 2280 movs r2, #128 @ 0x80 + 800591e: 01d2 lsls r2, r2, #7 + 8005920: 4313 orrs r3, r2 + 8005922: b29a uxth r2, r3 + 8005924: 4b14 ldr r3, [pc, #80] @ (8005978 ) + 8005926: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005928: f7fe fb8a bl 8004040 + var.status3 = STATUS3_TPS1_SS_GND; + 800592c: 4b12 ldr r3, [pc, #72] @ (8005978 ) + 800592e: 2206 movs r2, #6 + 8005930: 815a strh r2, [r3, #10] + } + + if (var.tps1_adc > (config->tps1_max + config->tps1_margin)) { + 8005932: 4b11 ldr r3, [pc, #68] @ (8005978 ) + 8005934: 8a1b ldrh r3, [r3, #16] + 8005936: b29b uxth r3, r3 + 8005938: 0019 movs r1, r3 + 800593a: 4b0e ldr r3, [pc, #56] @ (8005974 ) + 800593c: 681b ldr r3, [r3, #0] + 800593e: 8a1b ldrh r3, [r3, #16] + 8005940: b29b uxth r3, r3 + 8005942: 0018 movs r0, r3 + 8005944: 4b0b ldr r3, [pc, #44] @ (8005974 ) + 8005946: 681b ldr r3, [r3, #0] + 8005948: 4a0d ldr r2, [pc, #52] @ (8005980 ) + 800594a: 5a9b ldrh r3, [r3, r2] + 800594c: b29b uxth r3, r3 + 800594e: 18c3 adds r3, r0, r3 + 8005950: 4299 cmp r1, r3 + 8005952: dd55 ble.n 8005a00 + //Fault condition TPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005954: 4b08 ldr r3, [pc, #32] @ (8005978 ) + 8005956: 889b ldrh r3, [r3, #4] + 8005958: b29b uxth r3, r3 + 800595a: 2280 movs r2, #128 @ 0x80 + 800595c: 01d2 lsls r2, r2, #7 + 800595e: 4313 orrs r3, r2 + 8005960: b29a uxth r2, r3 + 8005962: 4b05 ldr r3, [pc, #20] @ (8005978 ) + 8005964: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005966: f7fe fb6b bl 8004040 + var.status3 = STATUS3_TPS1_SS_VREF; + 800596a: 4b03 ldr r3, [pc, #12] @ (8005978 ) + 800596c: 2207 movs r2, #7 + 800596e: 815a strh r2, [r3, #10] + 8005970: e046 b.n 8005a00 + 8005972: 46c0 nop @ (mov r8, r8) + 8005974: 200009cc .word 0x200009cc + 8005978: 20000998 .word 0x20000998 + 800597c: 0000033e .word 0x0000033e + 8005980: 00000342 .word 0x00000342 + } + } else { + + if (var.tps1_adc < (config->tps1_max - config->tps1_margin)) { + 8005984: 4b78 ldr r3, [pc, #480] @ (8005b68 ) + 8005986: 8a1b ldrh r3, [r3, #16] + 8005988: b29b uxth r3, r3 + 800598a: 0019 movs r1, r3 + 800598c: 4b77 ldr r3, [pc, #476] @ (8005b6c ) + 800598e: 681b ldr r3, [r3, #0] + 8005990: 8a1b ldrh r3, [r3, #16] + 8005992: b29b uxth r3, r3 + 8005994: 0018 movs r0, r3 + 8005996: 4b75 ldr r3, [pc, #468] @ (8005b6c ) + 8005998: 681b ldr r3, [r3, #0] + 800599a: 4a75 ldr r2, [pc, #468] @ (8005b70 ) + 800599c: 5a9b ldrh r3, [r3, r2] + 800599e: b29b uxth r3, r3 + 80059a0: 1ac3 subs r3, r0, r3 + 80059a2: 4299 cmp r1, r3 + 80059a4: da0d bge.n 80059c2 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80059a6: 4b70 ldr r3, [pc, #448] @ (8005b68 ) + 80059a8: 889b ldrh r3, [r3, #4] + 80059aa: b29b uxth r3, r3 + 80059ac: 2280 movs r2, #128 @ 0x80 + 80059ae: 01d2 lsls r2, r2, #7 + 80059b0: 4313 orrs r3, r2 + 80059b2: b29a uxth r2, r3 + 80059b4: 4b6c ldr r3, [pc, #432] @ (8005b68 ) + 80059b6: 809a strh r2, [r3, #4] + DBW_Stop(); + 80059b8: f7fe fb42 bl 8004040 + var.status3 = STATUS3_TPS1_SS_GND; + 80059bc: 4b6a ldr r3, [pc, #424] @ (8005b68 ) + 80059be: 2206 movs r2, #6 + 80059c0: 815a strh r2, [r3, #10] + } + + if (var.tps1_adc > (config->tps1_min + config->tps1_margin)) { + 80059c2: 4b69 ldr r3, [pc, #420] @ (8005b68 ) + 80059c4: 8a1b ldrh r3, [r3, #16] + 80059c6: b29b uxth r3, r3 + 80059c8: 0019 movs r1, r3 + 80059ca: 4b68 ldr r3, [pc, #416] @ (8005b6c ) + 80059cc: 681b ldr r3, [r3, #0] + 80059ce: 89db ldrh r3, [r3, #14] + 80059d0: b29b uxth r3, r3 + 80059d2: 0018 movs r0, r3 + 80059d4: 4b65 ldr r3, [pc, #404] @ (8005b6c ) + 80059d6: 681b ldr r3, [r3, #0] + 80059d8: 4a65 ldr r2, [pc, #404] @ (8005b70 ) + 80059da: 5a9b ldrh r3, [r3, r2] + 80059dc: b29b uxth r3, r3 + 80059de: 18c3 adds r3, r0, r3 + 80059e0: 4299 cmp r1, r3 + 80059e2: dd0d ble.n 8005a00 + //Fault condition TPS1 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 80059e4: 4b60 ldr r3, [pc, #384] @ (8005b68 ) + 80059e6: 889b ldrh r3, [r3, #4] + 80059e8: b29b uxth r3, r3 + 80059ea: 2280 movs r2, #128 @ 0x80 + 80059ec: 01d2 lsls r2, r2, #7 + 80059ee: 4313 orrs r3, r2 + 80059f0: b29a uxth r2, r3 + 80059f2: 4b5d ldr r3, [pc, #372] @ (8005b68 ) + 80059f4: 809a strh r2, [r3, #4] + DBW_Stop(); + 80059f6: f7fe fb23 bl 8004040 + var.status3 = STATUS3_TPS1_SS_VREF; + 80059fa: 4b5b ldr r3, [pc, #364] @ (8005b68 ) + 80059fc: 2207 movs r2, #7 + 80059fe: 815a strh r2, [r3, #10] + } + } + + //TPS2 + if (config->tps2_min < config->tps2_max) { + 8005a00: 4b5a ldr r3, [pc, #360] @ (8005b6c ) + 8005a02: 681b ldr r3, [r3, #0] + 8005a04: 8a5b ldrh r3, [r3, #18] + 8005a06: b29a uxth r2, r3 + 8005a08: 4b58 ldr r3, [pc, #352] @ (8005b6c ) + 8005a0a: 681b ldr r3, [r3, #0] + 8005a0c: 8b1b ldrh r3, [r3, #24] + 8005a0e: b29b uxth r3, r3 + 8005a10: 429a cmp r2, r3 + 8005a12: d240 bcs.n 8005a96 + if (var.tps2_adc < (config->tps2_min - config->tps2_margin)) { + 8005a14: 4b54 ldr r3, [pc, #336] @ (8005b68 ) + 8005a16: 8a5b ldrh r3, [r3, #18] + 8005a18: b29b uxth r3, r3 + 8005a1a: 0019 movs r1, r3 + 8005a1c: 4b53 ldr r3, [pc, #332] @ (8005b6c ) + 8005a1e: 681b ldr r3, [r3, #0] + 8005a20: 8a5b ldrh r3, [r3, #18] + 8005a22: b29b uxth r3, r3 + 8005a24: 0018 movs r0, r3 + 8005a26: 4b51 ldr r3, [pc, #324] @ (8005b6c ) + 8005a28: 681a ldr r2, [r3, #0] + 8005a2a: 23d1 movs r3, #209 @ 0xd1 + 8005a2c: 009b lsls r3, r3, #2 + 8005a2e: 5ad3 ldrh r3, [r2, r3] + 8005a30: b29b uxth r3, r3 + 8005a32: 1ac3 subs r3, r0, r3 + 8005a34: 4299 cmp r1, r3 + 8005a36: da0d bge.n 8005a54 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005a38: 4b4b ldr r3, [pc, #300] @ (8005b68 ) + 8005a3a: 889b ldrh r3, [r3, #4] + 8005a3c: b29b uxth r3, r3 + 8005a3e: 2280 movs r2, #128 @ 0x80 + 8005a40: 01d2 lsls r2, r2, #7 + 8005a42: 4313 orrs r3, r2 + 8005a44: b29a uxth r2, r3 + 8005a46: 4b48 ldr r3, [pc, #288] @ (8005b68 ) + 8005a48: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005a4a: f7fe faf9 bl 8004040 + var.status3 = STATUS3_TPS2_SS_GND; + 8005a4e: 4b46 ldr r3, [pc, #280] @ (8005b68 ) + 8005a50: 2208 movs r2, #8 + 8005a52: 815a strh r2, [r3, #10] + } + + if (var.tps2_adc > (config->tps2_max + config->tps2_margin)) { + 8005a54: 4b44 ldr r3, [pc, #272] @ (8005b68 ) + 8005a56: 8a5b ldrh r3, [r3, #18] + 8005a58: b29b uxth r3, r3 + 8005a5a: 0019 movs r1, r3 + 8005a5c: 4b43 ldr r3, [pc, #268] @ (8005b6c ) + 8005a5e: 681b ldr r3, [r3, #0] + 8005a60: 8b1b ldrh r3, [r3, #24] + 8005a62: b29b uxth r3, r3 + 8005a64: 0018 movs r0, r3 + 8005a66: 4b41 ldr r3, [pc, #260] @ (8005b6c ) + 8005a68: 681a ldr r2, [r3, #0] + 8005a6a: 23d1 movs r3, #209 @ 0xd1 + 8005a6c: 009b lsls r3, r3, #2 + 8005a6e: 5ad3 ldrh r3, [r2, r3] + 8005a70: b29b uxth r3, r3 + 8005a72: 18c3 adds r3, r0, r3 + 8005a74: 4299 cmp r1, r3 + 8005a76: dd4e ble.n 8005b16 + //Fault condition TPS2 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005a78: 4b3b ldr r3, [pc, #236] @ (8005b68 ) + 8005a7a: 889b ldrh r3, [r3, #4] + 8005a7c: b29b uxth r3, r3 + 8005a7e: 2280 movs r2, #128 @ 0x80 + 8005a80: 01d2 lsls r2, r2, #7 + 8005a82: 4313 orrs r3, r2 + 8005a84: b29a uxth r2, r3 + 8005a86: 4b38 ldr r3, [pc, #224] @ (8005b68 ) + 8005a88: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005a8a: f7fe fad9 bl 8004040 + var.status3 = STATUS3_TPS2_SS_VREF; + 8005a8e: 4b36 ldr r3, [pc, #216] @ (8005b68 ) + 8005a90: 2209 movs r2, #9 + 8005a92: 815a strh r2, [r3, #10] + 8005a94: e03f b.n 8005b16 + } + } else { + if (var.tps2_adc < (config->tps2_max - config->tps2_margin)) { + 8005a96: 4b34 ldr r3, [pc, #208] @ (8005b68 ) + 8005a98: 8a5b ldrh r3, [r3, #18] + 8005a9a: b29b uxth r3, r3 + 8005a9c: 0019 movs r1, r3 + 8005a9e: 4b33 ldr r3, [pc, #204] @ (8005b6c ) + 8005aa0: 681b ldr r3, [r3, #0] + 8005aa2: 8b1b ldrh r3, [r3, #24] + 8005aa4: b29b uxth r3, r3 + 8005aa6: 0018 movs r0, r3 + 8005aa8: 4b30 ldr r3, [pc, #192] @ (8005b6c ) + 8005aaa: 681a ldr r2, [r3, #0] + 8005aac: 23d1 movs r3, #209 @ 0xd1 + 8005aae: 009b lsls r3, r3, #2 + 8005ab0: 5ad3 ldrh r3, [r2, r3] + 8005ab2: b29b uxth r3, r3 + 8005ab4: 1ac3 subs r3, r0, r3 + 8005ab6: 4299 cmp r1, r3 + 8005ab8: da0d bge.n 8005ad6 + //Fault condition PPS1 min + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005aba: 4b2b ldr r3, [pc, #172] @ (8005b68 ) + 8005abc: 889b ldrh r3, [r3, #4] + 8005abe: b29b uxth r3, r3 + 8005ac0: 2280 movs r2, #128 @ 0x80 + 8005ac2: 01d2 lsls r2, r2, #7 + 8005ac4: 4313 orrs r3, r2 + 8005ac6: b29a uxth r2, r3 + 8005ac8: 4b27 ldr r3, [pc, #156] @ (8005b68 ) + 8005aca: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005acc: f7fe fab8 bl 8004040 + var.status3 = STATUS3_TPS2_SS_GND; + 8005ad0: 4b25 ldr r3, [pc, #148] @ (8005b68 ) + 8005ad2: 2208 movs r2, #8 + 8005ad4: 815a strh r2, [r3, #10] + } + + if (var.tps2_adc > (config->tps2_min + config->tps2_margin)) { + 8005ad6: 4b24 ldr r3, [pc, #144] @ (8005b68 ) + 8005ad8: 8a5b ldrh r3, [r3, #18] + 8005ada: b29b uxth r3, r3 + 8005adc: 0019 movs r1, r3 + 8005ade: 4b23 ldr r3, [pc, #140] @ (8005b6c ) + 8005ae0: 681b ldr r3, [r3, #0] + 8005ae2: 8a5b ldrh r3, [r3, #18] + 8005ae4: b29b uxth r3, r3 + 8005ae6: 0018 movs r0, r3 + 8005ae8: 4b20 ldr r3, [pc, #128] @ (8005b6c ) + 8005aea: 681a ldr r2, [r3, #0] + 8005aec: 23d1 movs r3, #209 @ 0xd1 + 8005aee: 009b lsls r3, r3, #2 + 8005af0: 5ad3 ldrh r3, [r2, r3] + 8005af2: b29b uxth r3, r3 + 8005af4: 18c3 adds r3, r0, r3 + 8005af6: 4299 cmp r1, r3 + 8005af8: dd0d ble.n 8005b16 + //Fault condition TPS2 MAX + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005afa: 4b1b ldr r3, [pc, #108] @ (8005b68 ) + 8005afc: 889b ldrh r3, [r3, #4] + 8005afe: b29b uxth r3, r3 + 8005b00: 2280 movs r2, #128 @ 0x80 + 8005b02: 01d2 lsls r2, r2, #7 + 8005b04: 4313 orrs r3, r2 + 8005b06: b29a uxth r2, r3 + 8005b08: 4b17 ldr r3, [pc, #92] @ (8005b68 ) + 8005b0a: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005b0c: f7fe fa98 bl 8004040 + var.status3 = STATUS3_TPS2_SS_VREF; + 8005b10: 4b15 ldr r3, [pc, #84] @ (8005b68 ) + 8005b12: 2209 movs r2, #9 + 8005b14: 815a strh r2, [r3, #10] + } + } + + //TPS Delta + if ((var.tps_delta > config->tps_delta_margin) + 8005b16: 4b14 ldr r3, [pc, #80] @ (8005b68 ) + 8005b18: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8005b1a: b21b sxth r3, r3 + 8005b1c: 0019 movs r1, r3 + 8005b1e: 4b13 ldr r3, [pc, #76] @ (8005b6c ) + 8005b20: 681b ldr r3, [r3, #0] + 8005b22: 4a14 ldr r2, [pc, #80] @ (8005b74 ) + 8005b24: 5a9b ldrh r3, [r3, r2] + 8005b26: b29b uxth r3, r3 + 8005b28: 4299 cmp r1, r3 + 8005b2a: dc0c bgt.n 8005b46 + || (var.tps_delta < ((int16_t) -config->tps_delta_margin))) { + 8005b2c: 4b0e ldr r3, [pc, #56] @ (8005b68 ) + 8005b2e: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8005b30: b21a sxth r2, r3 + 8005b32: 4b0e ldr r3, [pc, #56] @ (8005b6c ) + 8005b34: 681b ldr r3, [r3, #0] + 8005b36: 490f ldr r1, [pc, #60] @ (8005b74 ) + 8005b38: 5a5b ldrh r3, [r3, r1] + 8005b3a: b29b uxth r3, r3 + 8005b3c: 425b negs r3, r3 + 8005b3e: b29b uxth r3, r3 + 8005b40: b21b sxth r3, r3 + 8005b42: 429a cmp r2, r3 + 8005b44: da0d bge.n 8005b62 + //Fault condition PPS DELTA + var.status0 |= DBW_STATUS0_SENSOR_FAULT_F; + 8005b46: 4b08 ldr r3, [pc, #32] @ (8005b68 ) + 8005b48: 889b ldrh r3, [r3, #4] + 8005b4a: b29b uxth r3, r3 + 8005b4c: 2280 movs r2, #128 @ 0x80 + 8005b4e: 01d2 lsls r2, r2, #7 + 8005b50: 4313 orrs r3, r2 + 8005b52: b29a uxth r2, r3 + 8005b54: 4b04 ldr r3, [pc, #16] @ (8005b68 ) + 8005b56: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005b58: f7fe fa72 bl 8004040 + var.status3 = STATUS3_TPS_DELTA; + 8005b5c: 4b02 ldr r3, [pc, #8] @ (8005b68 ) + 8005b5e: 220a movs r2, #10 + 8005b60: 815a strh r2, [r3, #10] + } + +} + 8005b62: 46c0 nop @ (mov r8, r8) + 8005b64: 46bd mov sp, r7 + 8005b66: bd80 pop {r7, pc} + 8005b68: 20000998 .word 0x20000998 + 8005b6c: 200009cc .word 0x200009cc + 8005b70: 00000342 .word 0x00000342 + 8005b74: 00000346 .word 0x00000346 + +08005b78 : + +volatile int dbw_target_tmr1, dbw_target_tmr2; + +void Safety_TPS_Safety_Timer(void) { + 8005b78: b580 push {r7, lr} + 8005b7a: af00 add r7, sp, #0 + if (dbw_target_tmr1 > 0) + 8005b7c: 4b0a ldr r3, [pc, #40] @ (8005ba8 ) + 8005b7e: 681b ldr r3, [r3, #0] + 8005b80: 2b00 cmp r3, #0 + 8005b82: dd04 ble.n 8005b8e + dbw_target_tmr1--; + 8005b84: 4b08 ldr r3, [pc, #32] @ (8005ba8 ) + 8005b86: 681b ldr r3, [r3, #0] + 8005b88: 1e5a subs r2, r3, #1 + 8005b8a: 4b07 ldr r3, [pc, #28] @ (8005ba8 ) + 8005b8c: 601a str r2, [r3, #0] + if (dbw_target_tmr2 > 0) + 8005b8e: 4b07 ldr r3, [pc, #28] @ (8005bac ) + 8005b90: 681b ldr r3, [r3, #0] + 8005b92: 2b00 cmp r3, #0 + 8005b94: dd04 ble.n 8005ba0 + dbw_target_tmr2--; + 8005b96: 4b05 ldr r3, [pc, #20] @ (8005bac ) + 8005b98: 681b ldr r3, [r3, #0] + 8005b9a: 1e5a subs r2, r3, #1 + 8005b9c: 4b03 ldr r3, [pc, #12] @ (8005bac ) + 8005b9e: 601a str r2, [r3, #0] +} + 8005ba0: 46c0 nop @ (mov r8, r8) + 8005ba2: 46bd mov sp, r7 + 8005ba4: bd80 pop {r7, pc} + 8005ba6: 46c0 nop @ (mov r8, r8) + 8005ba8: 20000b2c .word 0x20000b2c + 8005bac: 20000b30 .word 0x20000b30 + +08005bb0 : + +void Safety_TPS_Safety_Timer_Start(void) { + 8005bb0: b580 push {r7, lr} + 8005bb2: af00 add r7, sp, #0 +//enable timers. add 1S time to start, because safety system starts in 1S after startup + dbw_target_tmr1 = config->tps_error_time1 + 1000; + 8005bb4: 4b0a ldr r3, [pc, #40] @ (8005be0 ) + 8005bb6: 681b ldr r3, [r3, #0] + 8005bb8: 4a0a ldr r2, [pc, #40] @ (8005be4 ) + 8005bba: 5a9b ldrh r3, [r3, r2] + 8005bbc: b29b uxth r3, r3 + 8005bbe: 21fa movs r1, #250 @ 0xfa + 8005bc0: 0089 lsls r1, r1, #2 + 8005bc2: 185a adds r2, r3, r1 + 8005bc4: 4b08 ldr r3, [pc, #32] @ (8005be8 ) + 8005bc6: 601a str r2, [r3, #0] + dbw_target_tmr2 = config->tps_error_time2 + 1000; + 8005bc8: 4b05 ldr r3, [pc, #20] @ (8005be0 ) + 8005bca: 681b ldr r3, [r3, #0] + 8005bcc: 4a07 ldr r2, [pc, #28] @ (8005bec ) + 8005bce: 5a9b ldrh r3, [r3, r2] + 8005bd0: b29b uxth r3, r3 + 8005bd2: 185a adds r2, r3, r1 + 8005bd4: 4b06 ldr r3, [pc, #24] @ (8005bf0 ) + 8005bd6: 601a str r2, [r3, #0] +} + 8005bd8: 46c0 nop @ (mov r8, r8) + 8005bda: 46bd mov sp, r7 + 8005bdc: bd80 pop {r7, pc} + 8005bde: 46c0 nop @ (mov r8, r8) + 8005be0: 200009cc .word 0x200009cc + 8005be4: 0000034a .word 0x0000034a + 8005be8: 20000b2c .word 0x20000b2c + 8005bec: 0000034e .word 0x0000034e + 8005bf0: 20000b30 .word 0x20000b30 + +08005bf4 : + +void Check_TPS_Target() { + 8005bf4: b580 push {r7, lr} + 8005bf6: af00 add r7, sp, #0 + if (var.tps_error > 0) { + 8005bf8: 4b50 ldr r3, [pc, #320] @ (8005d3c ) + 8005bfa: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005bfc: b21b sxth r3, r3 + 8005bfe: 2b00 cmp r3, #0 + 8005c00: dd4a ble.n 8005c98 + //check if tps is within specified target + if (var.tps_error < config->tps_error_margin1) + 8005c02: 4b4e ldr r3, [pc, #312] @ (8005d3c ) + 8005c04: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005c06: b21a sxth r2, r3 + 8005c08: 4b4d ldr r3, [pc, #308] @ (8005d40 ) + 8005c0a: 6819 ldr r1, [r3, #0] + 8005c0c: 23d2 movs r3, #210 @ 0xd2 + 8005c0e: 009b lsls r3, r3, #2 + 8005c10: 5acb ldrh r3, [r1, r3] + 8005c12: b21b sxth r3, r3 + 8005c14: 429a cmp r2, r3 + 8005c16: da08 bge.n 8005c2a + dbw_target_tmr1 = config->tps_error_time1; + 8005c18: 4b49 ldr r3, [pc, #292] @ (8005d40 ) + 8005c1a: 681b ldr r3, [r3, #0] + 8005c1c: 4a49 ldr r2, [pc, #292] @ (8005d44 ) + 8005c1e: 5a9b ldrh r3, [r3, r2] + 8005c20: b29b uxth r3, r3 + 8005c22: 001a movs r2, r3 + 8005c24: 4b48 ldr r3, [pc, #288] @ (8005d48 ) + 8005c26: 601a str r2, [r3, #0] + 8005c28: e010 b.n 8005c4c + else { + // if not in range in specified time + if (dbw_target_tmr1 == 0) { + 8005c2a: 4b47 ldr r3, [pc, #284] @ (8005d48 ) + 8005c2c: 681b ldr r3, [r3, #0] + 8005c2e: 2b00 cmp r3, #0 + 8005c30: d10c bne.n 8005c4c + //fault + var.status0 |= DBW_STATUS0_FAULT_F; + 8005c32: 4b42 ldr r3, [pc, #264] @ (8005d3c ) + 8005c34: 889b ldrh r3, [r3, #4] + 8005c36: b29b uxth r3, r3 + 8005c38: 2208 movs r2, #8 + 8005c3a: 4313 orrs r3, r2 + 8005c3c: b29a uxth r2, r3 + 8005c3e: 4b3f ldr r3, [pc, #252] @ (8005d3c ) + 8005c40: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005c42: f7fe f9fd bl 8004040 + var.status2 = STATUS3_TARGET1_FAULT; + 8005c46: 4b3d ldr r3, [pc, #244] @ (8005d3c ) + 8005c48: 220b movs r2, #11 + 8005c4a: 811a strh r2, [r3, #8] + } + } + + if (var.tps_error < config->tps_error_margin2) + 8005c4c: 4b3b ldr r3, [pc, #236] @ (8005d3c ) + 8005c4e: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005c50: b21a sxth r2, r3 + 8005c52: 4b3b ldr r3, [pc, #236] @ (8005d40 ) + 8005c54: 6819 ldr r1, [r3, #0] + 8005c56: 23d3 movs r3, #211 @ 0xd3 + 8005c58: 009b lsls r3, r3, #2 + 8005c5a: 5acb ldrh r3, [r1, r3] + 8005c5c: b21b sxth r3, r3 + 8005c5e: 429a cmp r2, r3 + 8005c60: da08 bge.n 8005c74 + dbw_target_tmr2 = config->tps_error_time2; + 8005c62: 4b37 ldr r3, [pc, #220] @ (8005d40 ) + 8005c64: 681b ldr r3, [r3, #0] + 8005c66: 4a39 ldr r2, [pc, #228] @ (8005d4c ) + 8005c68: 5a9b ldrh r3, [r3, r2] + 8005c6a: b29b uxth r3, r3 + 8005c6c: 001a movs r2, r3 + 8005c6e: 4b38 ldr r3, [pc, #224] @ (8005d50 ) + 8005c70: 601a str r2, [r3, #0] + var.status2 = STATUS3_TARGET2_FAULT; + } + } + } + +} + 8005c72: e05f b.n 8005d34 + if (dbw_target_tmr2 == 0) { + 8005c74: 4b36 ldr r3, [pc, #216] @ (8005d50 ) + 8005c76: 681b ldr r3, [r3, #0] + 8005c78: 2b00 cmp r3, #0 + 8005c7a: d15b bne.n 8005d34 + var.status0 |= DBW_STATUS0_FAULT_F; + 8005c7c: 4b2f ldr r3, [pc, #188] @ (8005d3c ) + 8005c7e: 889b ldrh r3, [r3, #4] + 8005c80: b29b uxth r3, r3 + 8005c82: 2208 movs r2, #8 + 8005c84: 4313 orrs r3, r2 + 8005c86: b29a uxth r2, r3 + 8005c88: 4b2c ldr r3, [pc, #176] @ (8005d3c ) + 8005c8a: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005c8c: f7fe f9d8 bl 8004040 + var.status2 = STATUS3_TARGET2_FAULT; + 8005c90: 4b2a ldr r3, [pc, #168] @ (8005d3c ) + 8005c92: 220c movs r2, #12 + 8005c94: 811a strh r2, [r3, #8] +} + 8005c96: e04d b.n 8005d34 + if (var.tps_error > (-config->tps_error_margin1)) + 8005c98: 4b28 ldr r3, [pc, #160] @ (8005d3c ) + 8005c9a: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005c9c: b21b sxth r3, r3 + 8005c9e: 0019 movs r1, r3 + 8005ca0: 4b27 ldr r3, [pc, #156] @ (8005d40 ) + 8005ca2: 681a ldr r2, [r3, #0] + 8005ca4: 23d2 movs r3, #210 @ 0xd2 + 8005ca6: 009b lsls r3, r3, #2 + 8005ca8: 5ad3 ldrh r3, [r2, r3] + 8005caa: b21b sxth r3, r3 + 8005cac: 425b negs r3, r3 + 8005cae: 4299 cmp r1, r3 + 8005cb0: dd08 ble.n 8005cc4 + dbw_target_tmr1 = config->tps_error_time1; + 8005cb2: 4b23 ldr r3, [pc, #140] @ (8005d40 ) + 8005cb4: 681b ldr r3, [r3, #0] + 8005cb6: 4a23 ldr r2, [pc, #140] @ (8005d44 ) + 8005cb8: 5a9b ldrh r3, [r3, r2] + 8005cba: b29b uxth r3, r3 + 8005cbc: 001a movs r2, r3 + 8005cbe: 4b22 ldr r3, [pc, #136] @ (8005d48 ) + 8005cc0: 601a str r2, [r3, #0] + 8005cc2: e010 b.n 8005ce6 + if (dbw_target_tmr1 == 0) { + 8005cc4: 4b20 ldr r3, [pc, #128] @ (8005d48 ) + 8005cc6: 681b ldr r3, [r3, #0] + 8005cc8: 2b00 cmp r3, #0 + 8005cca: d10c bne.n 8005ce6 + var.status0 |= DBW_STATUS0_FAULT_F; + 8005ccc: 4b1b ldr r3, [pc, #108] @ (8005d3c ) + 8005cce: 889b ldrh r3, [r3, #4] + 8005cd0: b29b uxth r3, r3 + 8005cd2: 2208 movs r2, #8 + 8005cd4: 4313 orrs r3, r2 + 8005cd6: b29a uxth r2, r3 + 8005cd8: 4b18 ldr r3, [pc, #96] @ (8005d3c ) + 8005cda: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005cdc: f7fe f9b0 bl 8004040 + var.status2 = STATUS3_TARGET1_FAULT; + 8005ce0: 4b16 ldr r3, [pc, #88] @ (8005d3c ) + 8005ce2: 220b movs r2, #11 + 8005ce4: 811a strh r2, [r3, #8] + if (var.tps_error > (-config->tps_error_margin2)) + 8005ce6: 4b15 ldr r3, [pc, #84] @ (8005d3c ) + 8005ce8: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005cea: b21b sxth r3, r3 + 8005cec: 0019 movs r1, r3 + 8005cee: 4b14 ldr r3, [pc, #80] @ (8005d40 ) + 8005cf0: 681a ldr r2, [r3, #0] + 8005cf2: 23d3 movs r3, #211 @ 0xd3 + 8005cf4: 009b lsls r3, r3, #2 + 8005cf6: 5ad3 ldrh r3, [r2, r3] + 8005cf8: b21b sxth r3, r3 + 8005cfa: 425b negs r3, r3 + 8005cfc: 4299 cmp r1, r3 + 8005cfe: dd08 ble.n 8005d12 + dbw_target_tmr2 = config->tps_error_time2; + 8005d00: 4b0f ldr r3, [pc, #60] @ (8005d40 ) + 8005d02: 681b ldr r3, [r3, #0] + 8005d04: 4a11 ldr r2, [pc, #68] @ (8005d4c ) + 8005d06: 5a9b ldrh r3, [r3, r2] + 8005d08: b29b uxth r3, r3 + 8005d0a: 001a movs r2, r3 + 8005d0c: 4b10 ldr r3, [pc, #64] @ (8005d50 ) + 8005d0e: 601a str r2, [r3, #0] +} + 8005d10: e010 b.n 8005d34 + if (dbw_target_tmr2 == 0) { + 8005d12: 4b0f ldr r3, [pc, #60] @ (8005d50 ) + 8005d14: 681b ldr r3, [r3, #0] + 8005d16: 2b00 cmp r3, #0 + 8005d18: d10c bne.n 8005d34 + var.status0 |= DBW_STATUS0_FAULT_F; + 8005d1a: 4b08 ldr r3, [pc, #32] @ (8005d3c ) + 8005d1c: 889b ldrh r3, [r3, #4] + 8005d1e: b29b uxth r3, r3 + 8005d20: 2208 movs r2, #8 + 8005d22: 4313 orrs r3, r2 + 8005d24: b29a uxth r2, r3 + 8005d26: 4b05 ldr r3, [pc, #20] @ (8005d3c ) + 8005d28: 809a strh r2, [r3, #4] + DBW_Stop(); + 8005d2a: f7fe f989 bl 8004040 + var.status2 = STATUS3_TARGET2_FAULT; + 8005d2e: 4b03 ldr r3, [pc, #12] @ (8005d3c ) + 8005d30: 220c movs r2, #12 + 8005d32: 811a strh r2, [r3, #8] +} + 8005d34: 46c0 nop @ (mov r8, r8) + 8005d36: 46bd mov sp, r7 + 8005d38: bd80 pop {r7, pc} + 8005d3a: 46c0 nop @ (mov r8, r8) + 8005d3c: 20000998 .word 0x20000998 + 8005d40: 200009cc .word 0x200009cc + 8005d44: 0000034a .word 0x0000034a + 8005d48: 20000b2c .word 0x20000b2c + 8005d4c: 0000034e .word 0x0000034e + 8005d50: 20000b30 .word 0x20000b30 + +08005d54 : + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) { + 8005d54: b580 push {r7, lr} + 8005d56: b082 sub sp, #8 + 8005d58: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8005d5a: 4b0f ldr r3, [pc, #60] @ (8005d98 ) + 8005d5c: 699a ldr r2, [r3, #24] + 8005d5e: 4b0e ldr r3, [pc, #56] @ (8005d98 ) + 8005d60: 2101 movs r1, #1 + 8005d62: 430a orrs r2, r1 + 8005d64: 619a str r2, [r3, #24] + 8005d66: 4b0c ldr r3, [pc, #48] @ (8005d98 ) + 8005d68: 699b ldr r3, [r3, #24] + 8005d6a: 2201 movs r2, #1 + 8005d6c: 4013 ands r3, r2 + 8005d6e: 607b str r3, [r7, #4] + 8005d70: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 8005d72: 4b09 ldr r3, [pc, #36] @ (8005d98 ) + 8005d74: 69da ldr r2, [r3, #28] + 8005d76: 4b08 ldr r3, [pc, #32] @ (8005d98 ) + 8005d78: 2180 movs r1, #128 @ 0x80 + 8005d7a: 0549 lsls r1, r1, #21 + 8005d7c: 430a orrs r2, r1 + 8005d7e: 61da str r2, [r3, #28] + 8005d80: 4b05 ldr r3, [pc, #20] @ (8005d98 ) + 8005d82: 69da ldr r2, [r3, #28] + 8005d84: 2380 movs r3, #128 @ 0x80 + 8005d86: 055b lsls r3, r3, #21 + 8005d88: 4013 ands r3, r2 + 8005d8a: 603b str r3, [r7, #0] + 8005d8c: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8005d8e: 46c0 nop @ (mov r8, r8) + 8005d90: 46bd mov sp, r7 + 8005d92: b002 add sp, #8 + 8005d94: bd80 pop {r7, pc} + 8005d96: 46c0 nop @ (mov r8, r8) + 8005d98: 40021000 .word 0x40021000 + +08005d9c : + * @brief ADC MSP Initialization + * This function configures the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { + 8005d9c: b590 push {r4, r7, lr} + 8005d9e: b08b sub sp, #44 @ 0x2c + 8005da0: af00 add r7, sp, #0 + 8005da2: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + 8005da4: 2414 movs r4, #20 + 8005da6: 193b adds r3, r7, r4 + 8005da8: 0018 movs r0, r3 + 8005daa: 2314 movs r3, #20 + 8005dac: 001a movs r2, r3 + 8005dae: 2100 movs r1, #0 + 8005db0: f002 fdae bl 8008910 + if (hadc->Instance == ADC1) { + 8005db4: 687b ldr r3, [r7, #4] + 8005db6: 681b ldr r3, [r3, #0] + 8005db8: 4a19 ldr r2, [pc, #100] @ (8005e20 ) + 8005dba: 4293 cmp r3, r2 + 8005dbc: d12b bne.n 8005e16 + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + 8005dbe: 4b19 ldr r3, [pc, #100] @ (8005e24 ) + 8005dc0: 699a ldr r2, [r3, #24] + 8005dc2: 4b18 ldr r3, [pc, #96] @ (8005e24 ) + 8005dc4: 2180 movs r1, #128 @ 0x80 + 8005dc6: 0089 lsls r1, r1, #2 + 8005dc8: 430a orrs r2, r1 + 8005dca: 619a str r2, [r3, #24] + 8005dcc: 4b15 ldr r3, [pc, #84] @ (8005e24 ) + 8005dce: 699a ldr r2, [r3, #24] + 8005dd0: 2380 movs r3, #128 @ 0x80 + 8005dd2: 009b lsls r3, r3, #2 + 8005dd4: 4013 ands r3, r2 + 8005dd6: 613b str r3, [r7, #16] + 8005dd8: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8005dda: 4b12 ldr r3, [pc, #72] @ (8005e24 ) + 8005ddc: 695a ldr r2, [r3, #20] + 8005dde: 4b11 ldr r3, [pc, #68] @ (8005e24 ) + 8005de0: 2180 movs r1, #128 @ 0x80 + 8005de2: 0289 lsls r1, r1, #10 + 8005de4: 430a orrs r2, r1 + 8005de6: 615a str r2, [r3, #20] + 8005de8: 4b0e ldr r3, [pc, #56] @ (8005e24 ) + 8005dea: 695a ldr r2, [r3, #20] + 8005dec: 2380 movs r3, #128 @ 0x80 + 8005dee: 029b lsls r3, r3, #10 + 8005df0: 4013 ands r3, r2 + 8005df2: 60fb str r3, [r7, #12] + 8005df4: 68fb ldr r3, [r7, #12] + PA2 ------> ADC_IN2 + PA3 ------> ADC_IN3 + PA4 ------> ADC_IN4 + PA5 ------> ADC_IN5 + */ + GPIO_InitStruct.Pin = PPS1_Pin | PPS2_Pin | TPS1_Pin | TPS2_Pin + 8005df6: 193b adds r3, r7, r4 + 8005df8: 223f movs r2, #63 @ 0x3f + 8005dfa: 601a str r2, [r3, #0] + | TTL_FB_Pin | VBAT_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8005dfc: 193b adds r3, r7, r4 + 8005dfe: 2203 movs r2, #3 + 8005e00: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005e02: 193b adds r3, r7, r4 + 8005e04: 2200 movs r2, #0 + 8005e06: 609a str r2, [r3, #8] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005e08: 193a adds r2, r7, r4 + 8005e0a: 2390 movs r3, #144 @ 0x90 + 8005e0c: 05db lsls r3, r3, #23 + 8005e0e: 0011 movs r1, r2 + 8005e10: 0018 movs r0, r3 + 8005e12: f001 fa79 bl 8007308 + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + 8005e16: 46c0 nop @ (mov r8, r8) + 8005e18: 46bd mov sp, r7 + 8005e1a: b00b add sp, #44 @ 0x2c + 8005e1c: bd90 pop {r4, r7, pc} + 8005e1e: 46c0 nop @ (mov r8, r8) + 8005e20: 40012400 .word 0x40012400 + 8005e24: 40021000 .word 0x40021000 + +08005e28 : + * @brief UART MSP Initialization + * This function configures the hardware resources used in this example + * @param huart: UART handle pointer + * @retval None + */ +void HAL_UART_MspInit(UART_HandleTypeDef *huart) { + 8005e28: b590 push {r4, r7, lr} + 8005e2a: b08b sub sp, #44 @ 0x2c + 8005e2c: af00 add r7, sp, #0 + 8005e2e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = { 0 }; + 8005e30: 2414 movs r4, #20 + 8005e32: 193b adds r3, r7, r4 + 8005e34: 0018 movs r0, r3 + 8005e36: 2314 movs r3, #20 + 8005e38: 001a movs r2, r3 + 8005e3a: 2100 movs r1, #0 + 8005e3c: f002 fd68 bl 8008910 + if (huart->Instance == USART1) { + 8005e40: 687b ldr r3, [r7, #4] + 8005e42: 681b ldr r3, [r3, #0] + 8005e44: 4a1d ldr r2, [pc, #116] @ (8005ebc ) + 8005e46: 4293 cmp r3, r2 + 8005e48: d133 bne.n 8005eb2 + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + 8005e4a: 4b1d ldr r3, [pc, #116] @ (8005ec0 ) + 8005e4c: 699a ldr r2, [r3, #24] + 8005e4e: 4b1c ldr r3, [pc, #112] @ (8005ec0 ) + 8005e50: 2180 movs r1, #128 @ 0x80 + 8005e52: 01c9 lsls r1, r1, #7 + 8005e54: 430a orrs r2, r1 + 8005e56: 619a str r2, [r3, #24] + 8005e58: 4b19 ldr r3, [pc, #100] @ (8005ec0 ) + 8005e5a: 699a ldr r2, [r3, #24] + 8005e5c: 2380 movs r3, #128 @ 0x80 + 8005e5e: 01db lsls r3, r3, #7 + 8005e60: 4013 ands r3, r2 + 8005e62: 613b str r3, [r7, #16] + 8005e64: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8005e66: 4b16 ldr r3, [pc, #88] @ (8005ec0 ) + 8005e68: 695a ldr r2, [r3, #20] + 8005e6a: 4b15 ldr r3, [pc, #84] @ (8005ec0 ) + 8005e6c: 2180 movs r1, #128 @ 0x80 + 8005e6e: 0289 lsls r1, r1, #10 + 8005e70: 430a orrs r2, r1 + 8005e72: 615a str r2, [r3, #20] + 8005e74: 4b12 ldr r3, [pc, #72] @ (8005ec0 ) + 8005e76: 695a ldr r2, [r3, #20] + 8005e78: 2380 movs r3, #128 @ 0x80 + 8005e7a: 029b lsls r3, r3, #10 + 8005e7c: 4013 ands r3, r2 + 8005e7e: 60fb str r3, [r7, #12] + 8005e80: 68fb ldr r3, [r7, #12] + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10; + 8005e82: 193b adds r3, r7, r4 + 8005e84: 22c0 movs r2, #192 @ 0xc0 + 8005e86: 00d2 lsls r2, r2, #3 + 8005e88: 601a str r2, [r3, #0] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8005e8a: 0021 movs r1, r4 + 8005e8c: 187b adds r3, r7, r1 + 8005e8e: 2202 movs r2, #2 + 8005e90: 605a str r2, [r3, #4] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8005e92: 187b adds r3, r7, r1 + 8005e94: 2200 movs r2, #0 + 8005e96: 609a str r2, [r3, #8] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8005e98: 187b adds r3, r7, r1 + 8005e9a: 2203 movs r2, #3 + 8005e9c: 60da str r2, [r3, #12] + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + 8005e9e: 187b adds r3, r7, r1 + 8005ea0: 2201 movs r2, #1 + 8005ea2: 611a str r2, [r3, #16] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8005ea4: 187a adds r2, r7, r1 + 8005ea6: 2390 movs r3, #144 @ 0x90 + 8005ea8: 05db lsls r3, r3, #23 + 8005eaa: 0011 movs r1, r2 + 8005eac: 0018 movs r0, r3 + 8005eae: f001 fa2b bl 8007308 + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + 8005eb2: 46c0 nop @ (mov r8, r8) + 8005eb4: 46bd mov sp, r7 + 8005eb6: b00b add sp, #44 @ 0x2c + 8005eb8: bd90 pop {r4, r7, pc} + 8005eba: 46c0 nop @ (mov r8, r8) + 8005ebc: 40013800 .word 0x40013800 + 8005ec0: 40021000 .word 0x40021000 + +08005ec4 : +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) { + 8005ec4: b580 push {r7, lr} + 8005ec6: af00 add r7, sp, #0 + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + 8005ec8: 46c0 nop @ (mov r8, r8) + 8005eca: 46bd mov sp, r7 + 8005ecc: bd80 pop {r7, pc} + +08005ece : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) { + 8005ece: b580 push {r7, lr} + 8005ed0: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + 8005ed2: 46c0 nop @ (mov r8, r8) + 8005ed4: e7fd b.n 8005ed2 + +08005ed6 : +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) { + 8005ed6: b580 push {r7, lr} + 8005ed8: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8005eda: 46c0 nop @ (mov r8, r8) + 8005edc: 46bd mov sp, r7 + 8005ede: bd80 pop {r7, pc} + +08005ee0 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) { + 8005ee0: b580 push {r7, lr} + 8005ee2: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8005ee4: 46c0 nop @ (mov r8, r8) + 8005ee6: 46bd mov sp, r7 + 8005ee8: bd80 pop {r7, pc} + ... + +08005eec : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) { + 8005eec: b580 push {r7, lr} + 8005eee: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8005ef0: f000 fcea bl 80068c8 + /* USER CODE BEGIN SysTick_IRQn 1 */ + var.clock++; + 8005ef4: 4b16 ldr r3, [pc, #88] @ (8005f50 ) + 8005ef6: 681b ldr r3, [r3, #0] + 8005ef8: 1c5a adds r2, r3, #1 + 8005efa: 4b15 ldr r3, [pc, #84] @ (8005f50 ) + 8005efc: 601a str r2, [r3, #0] + TS_Comms_RX_Timeout(); + 8005efe: f000 fc53 bl 80067a8 + + if (dbw_fast_process_timer) + 8005f02: 4b14 ldr r3, [pc, #80] @ (8005f54 ) + 8005f04: 881b ldrh r3, [r3, #0] + 8005f06: b29b uxth r3, r3 + 8005f08: 2b00 cmp r3, #0 + 8005f0a: d006 beq.n 8005f1a + dbw_fast_process_timer--; + 8005f0c: 4b11 ldr r3, [pc, #68] @ (8005f54 ) + 8005f0e: 881b ldrh r3, [r3, #0] + 8005f10: b29b uxth r3, r3 + 8005f12: 3b01 subs r3, #1 + 8005f14: b29a uxth r2, r3 + 8005f16: 4b0f ldr r3, [pc, #60] @ (8005f54 ) + 8005f18: 801a strh r2, [r3, #0] + + //Can_Timeouts(); + + if ((ac_mode != 0) && (config->config_bits & CONFIG_TESTMODE_F)) { + 8005f1a: 4b0f ldr r3, [pc, #60] @ (8005f58 ) + 8005f1c: 681b ldr r3, [r3, #0] + 8005f1e: 2b00 cmp r3, #0 + 8005f20: d011 beq.n 8005f46 + 8005f22: 4b0e ldr r3, [pc, #56] @ (8005f5c ) + 8005f24: 681b ldr r3, [r3, #0] + 8005f26: 4a0e ldr r2, [pc, #56] @ (8005f60 ) + 8005f28: 5a9b ldrh r3, [r3, r2] + 8005f2a: b29b uxth r3, r3 + 8005f2c: 001a movs r2, r3 + 8005f2e: 2304 movs r3, #4 + 8005f30: 4013 ands r3, r2 + 8005f32: d008 beq.n 8005f46 + if (ac_timer) + 8005f34: 4b0b ldr r3, [pc, #44] @ (8005f64 ) + 8005f36: 681b ldr r3, [r3, #0] + 8005f38: 2b00 cmp r3, #0 + 8005f3a: d004 beq.n 8005f46 + ac_timer--; + 8005f3c: 4b09 ldr r3, [pc, #36] @ (8005f64 ) + 8005f3e: 681b ldr r3, [r3, #0] + 8005f40: 1e5a subs r2, r3, #1 + 8005f42: 4b08 ldr r3, [pc, #32] @ (8005f64 ) + 8005f44: 601a str r2, [r3, #0] + } + + Safety_TPS_Safety_Timer(); + 8005f46: f7ff fe17 bl 8005b78 + /* USER CODE END SysTick_IRQn 1 */ +} + 8005f4a: 46c0 nop @ (mov r8, r8) + 8005f4c: 46bd mov sp, r7 + 8005f4e: bd80 pop {r7, pc} + 8005f50: 20000998 .word 0x20000998 + 8005f54: 20000a1c .word 0x20000a1c + 8005f58: 200009d0 .word 0x200009d0 + 8005f5c: 200009cc .word 0x200009cc + 8005f60: 0000033a .word 0x0000033a + 8005f64: 20000000 .word 0x20000000 + +08005f68 : +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) { + 8005f68: b580 push {r7, lr} + 8005f6a: af00 add r7, sp, #0 + before branch to main program. This call is made inside + the "startup_stm32f0xx.s" file. + User can setups the default system clock (System clock source, PLL Multiplier + and Divider factors, AHB/APBx prescalers and Flash settings). + */ +} + 8005f6c: 46c0 nop @ (mov r8, r8) + 8005f6e: 46bd mov sp, r7 + 8005f70: bd80 pop {r7, pc} + ... + +08005f74 : +const char Signature[20] = { "speeduino DBW 2.0.0" }; +const char Revision[20] = { "speeduino DBW 2.0.0" }; + +volatile var_t tx_bufer; + +void Comms_Init(void) { + 8005f74: b580 push {r7, lr} + 8005f76: af00 add r7, sp, #0 + Comms_Reset(&TX); + 8005f78: 4b0b ldr r3, [pc, #44] @ (8005fa8 ) + 8005f7a: 0018 movs r0, r3 + 8005f7c: f000 f86a bl 8006054 + Comms_Reset(&RX); + 8005f80: 4b0a ldr r3, [pc, #40] @ (8005fac ) + 8005f82: 0018 movs r0, r3 + 8005f84: f000 f866 bl 8006054 + + USART1->ISR &= ~USART_ISR_RXNE; + 8005f88: 4b09 ldr r3, [pc, #36] @ (8005fb0 ) + 8005f8a: 69da ldr r2, [r3, #28] + 8005f8c: 4b08 ldr r3, [pc, #32] @ (8005fb0 ) + 8005f8e: 2120 movs r1, #32 + 8005f90: 438a bics r2, r1 + 8005f92: 61da str r2, [r3, #28] + USART1->CR1 |= USART_CR1_RXNEIE; + 8005f94: 4b06 ldr r3, [pc, #24] @ (8005fb0 ) + 8005f96: 681a ldr r2, [r3, #0] + 8005f98: 4b05 ldr r3, [pc, #20] @ (8005fb0 ) + 8005f9a: 2120 movs r1, #32 + 8005f9c: 430a orrs r2, r1 + 8005f9e: 601a str r2, [r3, #0] + +} + 8005fa0: 46c0 nop @ (mov r8, r8) + 8005fa2: 46bd mov sp, r7 + 8005fa4: bd80 pop {r7, pc} + 8005fa6: 46c0 nop @ (mov r8, r8) + 8005fa8: 20000c50 .word 0x20000c50 + 8005fac: 20000b34 .word 0x20000b34 + 8005fb0: 40013800 .word 0x40013800 + +08005fb4 : + +void USART1_IRQHandler(void) { + 8005fb4: b580 push {r7, lr} + 8005fb6: b082 sub sp, #8 + 8005fb8: af00 add r7, sp, #0 + uint8_t tmp; + if (USART1->ISR & USART_ISR_RXNE) { + 8005fba: 4b23 ldr r3, [pc, #140] @ (8006048 ) + 8005fbc: 69db ldr r3, [r3, #28] + 8005fbe: 2220 movs r2, #32 + 8005fc0: 4013 ands r3, r2 + 8005fc2: d01f beq.n 8006004 + tmp = USART1->RDR; + 8005fc4: 4b20 ldr r3, [pc, #128] @ (8006048 ) + 8005fc6: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8005fc8: b29a uxth r2, r3 + 8005fca: 1dfb adds r3, r7, #7 + 8005fcc: 701a strb r2, [r3, #0] + USART1->ISR &= ~USART_ISR_RXNE; + 8005fce: 4b1e ldr r3, [pc, #120] @ (8006048 ) + 8005fd0: 69da ldr r2, [r3, #28] + 8005fd2: 4b1d ldr r3, [pc, #116] @ (8006048 ) + 8005fd4: 2120 movs r1, #32 + 8005fd6: 438a bics r2, r1 + 8005fd8: 61da str r2, [r3, #28] + //if there are any RX errors reset comms else process data + if (USART1->ISR & 0x000F) { + 8005fda: 4b1b ldr r3, [pc, #108] @ (8006048 ) + 8005fdc: 69db ldr r3, [r3, #28] + 8005fde: 220f movs r2, #15 + 8005fe0: 4013 ands r3, r2 + 8005fe2: d00a beq.n 8005ffa + Comms_Reset(&RX); + 8005fe4: 4b19 ldr r3, [pc, #100] @ (800604c ) + 8005fe6: 0018 movs r0, r3 + 8005fe8: f000 f834 bl 8006054 + USART1->ISR &= ~0x000F; + 8005fec: 4b16 ldr r3, [pc, #88] @ (8006048 ) + 8005fee: 69da ldr r2, [r3, #28] + 8005ff0: 4b15 ldr r3, [pc, #84] @ (8006048 ) + 8005ff2: 210f movs r1, #15 + 8005ff4: 438a bics r2, r1 + 8005ff6: 61da str r2, [r3, #28] + 8005ff8: e004 b.n 8006004 + } else { + Rx_Char(tmp); + 8005ffa: 1dfb adds r3, r7, #7 + 8005ffc: 781b ldrb r3, [r3, #0] + 8005ffe: 0018 movs r0, r3 + 8006000: f000 f846 bl 8006090 + } + } +//transmit interrupt + if (USART1->ISR & USART_ISR_TC) { + 8006004: 4b10 ldr r3, [pc, #64] @ (8006048 ) + 8006006: 69db ldr r3, [r3, #28] + 8006008: 2240 movs r2, #64 @ 0x40 + 800600a: 4013 ands r3, r2 + 800600c: d018 beq.n 8006040 + if (TX.bytes_done < TX.cnt) { + 800600e: 4b10 ldr r3, [pc, #64] @ (8006050 ) + 8006010: 895a ldrh r2, [r3, #10] + 8006012: 4b0f ldr r3, [pc, #60] @ (8006050 ) + 8006014: 891b ldrh r3, [r3, #8] + 8006016: 429a cmp r2, r3 + 8006018: d210 bcs.n 800603c + USART1->TDR = *TX.address; + 800601a: 4b0d ldr r3, [pc, #52] @ (8006050 ) + 800601c: 68db ldr r3, [r3, #12] + 800601e: 781a ldrb r2, [r3, #0] + 8006020: 4b09 ldr r3, [pc, #36] @ (8006048 ) + 8006022: 851a strh r2, [r3, #40] @ 0x28 + TX.address++; + 8006024: 4b0a ldr r3, [pc, #40] @ (8006050 ) + 8006026: 68db ldr r3, [r3, #12] + 8006028: 1c5a adds r2, r3, #1 + 800602a: 4b09 ldr r3, [pc, #36] @ (8006050 ) + 800602c: 60da str r2, [r3, #12] + TX.bytes_done++; + 800602e: 4b08 ldr r3, [pc, #32] @ (8006050 ) + 8006030: 895b ldrh r3, [r3, #10] + 8006032: 3301 adds r3, #1 + 8006034: b29a uxth r2, r3 + 8006036: 4b06 ldr r3, [pc, #24] @ (8006050 ) + 8006038: 815a strh r2, [r3, #10] + } else + TX_Done(); + + } +} + 800603a: e001 b.n 8006040 + TX_Done(); + 800603c: f000 fa66 bl 800650c +} + 8006040: 46c0 nop @ (mov r8, r8) + 8006042: 46bd mov sp, r7 + 8006044: b002 add sp, #8 + 8006046: bd80 pop {r7, pc} + 8006048: 40013800 .word 0x40013800 + 800604c: 20000b34 .word 0x20000b34 + 8006050: 20000c50 .word 0x20000c50 + +08006054 : + +void Comms_Reset(comms_status *CS) { + 8006054: b580 push {r7, lr} + 8006056: b082 sub sp, #8 + 8006058: af00 add r7, sp, #0 + 800605a: 6078 str r0, [r7, #4] + + CS->mode = IDLE; //Mode Idle + 800605c: 687b ldr r3, [r7, #4] + 800605e: 2200 movs r2, #0 + 8006060: 701a strb r2, [r3, #0] + CS->cnt = 0; //Nothing to receive + 8006062: 687b ldr r3, [r7, #4] + 8006064: 2200 movs r2, #0 + 8006066: 811a strh r2, [r3, #8] + CS->bytes_done = 0; //Nothing received + 8006068: 687b ldr r3, [r7, #4] + 800606a: 2200 movs r2, #0 + 800606c: 815a strh r2, [r3, #10] + CS->crc32 = 0; //Reset crc32 + 800606e: 687b ldr r3, [r7, #4] + 8006070: 2200 movs r2, #0 + 8006072: 619a str r2, [r3, #24] + CS->pause_flag = 0; + 8006074: 687b ldr r3, [r7, #4] + 8006076: 2200 movs r2, #0 + 8006078: 759a strb r2, [r3, #22] + CS->address = &CS->cmd; //Point incoming characters to cmd_bufer + 800607a: 687b ldr r3, [r7, #4] + 800607c: 1c5a adds r2, r3, #1 + 800607e: 687b ldr r3, [r7, #4] + 8006080: 60da str r2, [r3, #12] + CS->timeout = 0; + 8006082: 687b ldr r3, [r7, #4] + 8006084: 2200 movs r2, #0 + 8006086: 829a strh r2, [r3, #20] +} + 8006088: 46c0 nop @ (mov r8, r8) + 800608a: 46bd mov sp, r7 + 800608c: b002 add sp, #8 + 800608e: bd80 pop {r7, pc} + +08006090 : + +void Rx_Char(unsigned char data) { + 8006090: b580 push {r7, lr} + 8006092: b082 sub sp, #8 + 8006094: af00 add r7, sp, #0 + 8006096: 0002 movs r2, r0 + 8006098: 1dfb adds r3, r7, #7 + 800609a: 701a strb r2, [r3, #0] + + RX.bytes_done++; + 800609c: 4bc5 ldr r3, [pc, #788] @ (80063b4 ) + 800609e: 895b ldrh r3, [r3, #10] + 80060a0: 3301 adds r3, #1 + 80060a2: b29a uxth r2, r3 + 80060a4: 4bc3 ldr r3, [pc, #780] @ (80063b4 ) + 80060a6: 815a strh r2, [r3, #10] + + if (RX.bytes_done == 1) { + 80060a8: 4bc2 ldr r3, [pc, #776] @ (80063b4 ) + 80060aa: 895b ldrh r3, [r3, #10] + 80060ac: 2b01 cmp r3, #1 + 80060ae: d159 bne.n 8006164 + if (data == 'A') { + 80060b0: 1dfb adds r3, r7, #7 + 80060b2: 781b ldrb r3, [r3, #0] + 80060b4: 2b41 cmp r3, #65 @ 0x41 + 80060b6: d10b bne.n 80060d0 + SCI_flags |= SCI_FLAGS_TX_VARIABLES; + 80060b8: 4bbf ldr r3, [pc, #764] @ (80063b8 ) + 80060ba: 781b ldrb r3, [r3, #0] + 80060bc: 2202 movs r2, #2 + 80060be: 4313 orrs r3, r2 + 80060c0: b2da uxtb r2, r3 + 80060c2: 4bbd ldr r3, [pc, #756] @ (80063b8 ) + 80060c4: 701a strb r2, [r3, #0] + Comms_Reset(&RX); + 80060c6: 4bbb ldr r3, [pc, #748] @ (80063b4 ) + 80060c8: 0018 movs r0, r3 + 80060ca: f7ff ffc3 bl 8006054 + 80060ce: e1a6 b.n 800641e + } else if (data == 'Q') { + 80060d0: 1dfb adds r3, r7, #7 + 80060d2: 781b ldrb r3, [r3, #0] + 80060d4: 2b51 cmp r3, #81 @ 0x51 + 80060d6: d109 bne.n 80060ec + TX_Schedule((unsigned char*) Revision, 20); + 80060d8: 4bb8 ldr r3, [pc, #736] @ (80063bc ) + 80060da: 2114 movs r1, #20 + 80060dc: 0018 movs r0, r3 + 80060de: f000 f9a3 bl 8006428 + Comms_Reset(&RX); + 80060e2: 4bb4 ldr r3, [pc, #720] @ (80063b4 ) + 80060e4: 0018 movs r0, r3 + 80060e6: f7ff ffb5 bl 8006054 + 80060ea: e198 b.n 800641e + } else if (data == 'S') { + 80060ec: 1dfb adds r3, r7, #7 + 80060ee: 781b ldrb r3, [r3, #0] + 80060f0: 2b53 cmp r3, #83 @ 0x53 + 80060f2: d109 bne.n 8006108 + TX_Schedule((unsigned char*) Signature, 20); + 80060f4: 4bb2 ldr r3, [pc, #712] @ (80063c0 ) + 80060f6: 2114 movs r1, #20 + 80060f8: 0018 movs r0, r3 + 80060fa: f000 f995 bl 8006428 + Comms_Reset(&RX); + 80060fe: 4bad ldr r3, [pc, #692] @ (80063b4 ) + 8006100: 0018 movs r0, r3 + 8006102: f7ff ffa7 bl 8006054 + 8006106: e18a b.n 800641e + } else if (data == 'B') { + 8006108: 1dfb adds r3, r7, #7 + 800610a: 781b ldrb r3, [r3, #0] + 800610c: 2b42 cmp r3, #66 @ 0x42 + 800610e: d107 bne.n 8006120 + Store_config(); + 8006110: 4bac ldr r3, [pc, #688] @ (80063c4 ) + 8006112: 681b ldr r3, [r3, #0] + 8006114: 4798 blx r3 + Comms_Reset(&RX); + 8006116: 4ba7 ldr r3, [pc, #668] @ (80063b4 ) + 8006118: 0018 movs r0, r3 + 800611a: f7ff ff9b bl 8006054 + 800611e: e17e b.n 800641e + } else if ((data == 'r') || (data == 'w') || (data == 'k') + 8006120: 1dfb adds r3, r7, #7 + 8006122: 781b ldrb r3, [r3, #0] + 8006124: 2b72 cmp r3, #114 @ 0x72 + 8006126: d00f beq.n 8006148 + 8006128: 1dfb adds r3, r7, #7 + 800612a: 781b ldrb r3, [r3, #0] + 800612c: 2b77 cmp r3, #119 @ 0x77 + 800612e: d00b beq.n 8006148 + 8006130: 1dfb adds r3, r7, #7 + 8006132: 781b ldrb r3, [r3, #0] + 8006134: 2b6b cmp r3, #107 @ 0x6b + 8006136: d007 beq.n 8006148 + || (data == 'b') || (data == 'z')) { + 8006138: 1dfb adds r3, r7, #7 + 800613a: 781b ldrb r3, [r3, #0] + 800613c: 2b62 cmp r3, #98 @ 0x62 + 800613e: d003 beq.n 8006148 + 8006140: 1dfb adds r3, r7, #7 + 8006142: 781b ldrb r3, [r3, #0] + 8006144: 2b7a cmp r3, #122 @ 0x7a + 8006146: d108 bne.n 800615a + RX.timeout = 500; + 8006148: 4b9a ldr r3, [pc, #616] @ (80063b4 ) + 800614a: 22fa movs r2, #250 @ 0xfa + 800614c: 0052 lsls r2, r2, #1 + 800614e: 829a strh r2, [r3, #20] + RX.cmd = data; + 8006150: 4b98 ldr r3, [pc, #608] @ (80063b4 ) + 8006152: 1dfa adds r2, r7, #7 + 8006154: 7812 ldrb r2, [r2, #0] + 8006156: 705a strb r2, [r3, #1] + 8006158: e161 b.n 800641e + } else { + Comms_Reset(&RX); + 800615a: 4b96 ldr r3, [pc, #600] @ (80063b4 ) + 800615c: 0018 movs r0, r3 + 800615e: f7ff ff79 bl 8006054 + return; + 8006162: e15c b.n 800641e + } + + } else if (RX.bytes_done == 2) { + 8006164: 4b93 ldr r3, [pc, #588] @ (80063b4 ) + 8006166: 895b ldrh r3, [r3, #10] + 8006168: 2b02 cmp r3, #2 + 800616a: d104 bne.n 8006176 + RX.CANid = data; + 800616c: 4b91 ldr r3, [pc, #580] @ (80063b4 ) + 800616e: 1dfa adds r2, r7, #7 + 8006170: 7812 ldrb r2, [r2, #0] + 8006172: 709a strb r2, [r3, #2] + 8006174: e153 b.n 800641e + } else if (RX.bytes_done == 3) { + 8006176: 4b8f ldr r3, [pc, #572] @ (80063b4 ) + 8006178: 895b ldrh r3, [r3, #10] + 800617a: 2b03 cmp r3, #3 + 800617c: d110 bne.n 80061a0 + RX.table_index = data; + 800617e: 4b8d ldr r3, [pc, #564] @ (80063b4 ) + 8006180: 1dfa adds r2, r7, #7 + 8006182: 7812 ldrb r2, [r2, #0] + 8006184: 70da strb r2, [r3, #3] + if (RX.cmd == 'b') { + 8006186: 4b8b ldr r3, [pc, #556] @ (80063b4 ) + 8006188: 785b ldrb r3, [r3, #1] + 800618a: 2b62 cmp r3, #98 @ 0x62 + 800618c: d000 beq.n 8006190 + 800618e: e146 b.n 800641e + Store_config(); + 8006190: 4b8c ldr r3, [pc, #560] @ (80063c4 ) + 8006192: 681b ldr r3, [r3, #0] + 8006194: 4798 blx r3 + Comms_Reset(&RX); + 8006196: 4b87 ldr r3, [pc, #540] @ (80063b4 ) + 8006198: 0018 movs r0, r3 + 800619a: f7ff ff5b bl 8006054 + return; + 800619e: e13e b.n 800641e + } + } else if (RX.bytes_done == 4) { + 80061a0: 4b84 ldr r3, [pc, #528] @ (80063b4 ) + 80061a2: 895b ldrh r3, [r3, #10] + 80061a4: 2b04 cmp r3, #4 + 80061a6: d108 bne.n 80061ba + RX.offset = 0x00; + 80061a8: 4b82 ldr r3, [pc, #520] @ (80063b4 ) + 80061aa: 2200 movs r2, #0 + 80061ac: 809a strh r2, [r3, #4] + RX.offset = (unsigned short) data; + 80061ae: 1dfb adds r3, r7, #7 + 80061b0: 781b ldrb r3, [r3, #0] + 80061b2: b29a uxth r2, r3 + 80061b4: 4b7f ldr r3, [pc, #508] @ (80063b4 ) + 80061b6: 809a strh r2, [r3, #4] + 80061b8: e131 b.n 800641e + } else if (RX.bytes_done == 5) { + 80061ba: 4b7e ldr r3, [pc, #504] @ (80063b4 ) + 80061bc: 895b ldrh r3, [r3, #10] + 80061be: 2b05 cmp r3, #5 + 80061c0: d10d bne.n 80061de + RX.offset |= ((unsigned short) data) << 8; + 80061c2: 4b7c ldr r3, [pc, #496] @ (80063b4 ) + 80061c4: 889b ldrh r3, [r3, #4] + 80061c6: b21a sxth r2, r3 + 80061c8: 1dfb adds r3, r7, #7 + 80061ca: 781b ldrb r3, [r3, #0] + 80061cc: b21b sxth r3, r3 + 80061ce: 021b lsls r3, r3, #8 + 80061d0: b21b sxth r3, r3 + 80061d2: 4313 orrs r3, r2 + 80061d4: b21b sxth r3, r3 + 80061d6: b29a uxth r2, r3 + 80061d8: 4b76 ldr r3, [pc, #472] @ (80063b4 ) + 80061da: 809a strh r2, [r3, #4] + 80061dc: e11f b.n 800641e + } else if (RX.bytes_done == 6) { + 80061de: 4b75 ldr r3, [pc, #468] @ (80063b4 ) + 80061e0: 895b ldrh r3, [r3, #10] + 80061e2: 2b06 cmp r3, #6 + 80061e4: d108 bne.n 80061f8 + RX.data_size = 0x00; + 80061e6: 4b73 ldr r3, [pc, #460] @ (80063b4 ) + 80061e8: 2200 movs r2, #0 + 80061ea: 80da strh r2, [r3, #6] + RX.data_size = (unsigned short) data; + 80061ec: 1dfb adds r3, r7, #7 + 80061ee: 781b ldrb r3, [r3, #0] + 80061f0: b29a uxth r2, r3 + 80061f2: 4b70 ldr r3, [pc, #448] @ (80063b4 ) + 80061f4: 80da strh r2, [r3, #6] + 80061f6: e112 b.n 800641e + } else if (RX.bytes_done == 7) { + 80061f8: 4b6e ldr r3, [pc, #440] @ (80063b4 ) + 80061fa: 895b ldrh r3, [r3, #10] + 80061fc: 2b07 cmp r3, #7 + 80061fe: d000 beq.n 8006202 + 8006200: e0ee b.n 80063e0 + RX.data_size += ((unsigned short) data) << 8; + 8006202: 4b6c ldr r3, [pc, #432] @ (80063b4 ) + 8006204: 88da ldrh r2, [r3, #6] + 8006206: 1dfb adds r3, r7, #7 + 8006208: 781b ldrb r3, [r3, #0] + 800620a: b29b uxth r3, r3 + 800620c: 021b lsls r3, r3, #8 + 800620e: b29b uxth r3, r3 + 8006210: 18d3 adds r3, r2, r3 + 8006212: b29a uxth r2, r3 + 8006214: 4b67 ldr r3, [pc, #412] @ (80063b4 ) + 8006216: 80da strh r2, [r3, #6] + + if (RX.CANid == TS_CAN_ID) { + 8006218: 4b66 ldr r3, [pc, #408] @ (80063b4 ) + 800621a: 789b ldrb r3, [r3, #2] + 800621c: 2b00 cmp r3, #0 + 800621e: d000 beq.n 8006222 + 8006220: e0b5 b.n 800638e + + if (RX.cmd == 'k') { + 8006222: 4b64 ldr r3, [pc, #400] @ (80063b4 ) + 8006224: 785b ldrb r3, [r3, #1] + 8006226: 2b6b cmp r3, #107 @ 0x6b + 8006228: d10b bne.n 8006242 + SCI_flags |= SCI_FLAGS_CRC32; + 800622a: 4b63 ldr r3, [pc, #396] @ (80063b8 ) + 800622c: 781b ldrb r3, [r3, #0] + 800622e: 2201 movs r2, #1 + 8006230: 4313 orrs r3, r2 + 8006232: b2da uxtb r2, r3 + 8006234: 4b60 ldr r3, [pc, #384] @ (80063b8 ) + 8006236: 701a strb r2, [r3, #0] + Comms_Reset(&RX); + 8006238: 4b5e ldr r3, [pc, #376] @ (80063b4 ) + 800623a: 0018 movs r0, r3 + 800623c: f7ff ff0a bl 8006054 + return; + 8006240: e0ed b.n 800641e + } else if (RX.cmd == 'z') { + 8006242: 4b5c ldr r3, [pc, #368] @ (80063b4 ) + 8006244: 785b ldrb r3, [r3, #1] + 8006246: 2b7a cmp r3, #122 @ 0x7a + 8006248: d141 bne.n 80062ce + // process command buttons + if (RX.data_size == 0x0100) { + 800624a: 4b5a ldr r3, [pc, #360] @ (80063b4 ) + 800624c: 88da ldrh r2, [r3, #6] + 800624e: 2380 movs r3, #128 @ 0x80 + 8006250: 005b lsls r3, r3, #1 + 8006252: 429a cmp r2, r3 + 8006254: d102 bne.n 800625c + Apply_Sensor_Calibration(); + 8006256: f7fc fef1 bl 800303c + 800625a: e033 b.n 80062c4 + } else if (RX.data_size == 0x0200) { + 800625c: 4b55 ldr r3, [pc, #340] @ (80063b4 ) + 800625e: 88da ldrh r2, [r3, #6] + 8006260: 2380 movs r3, #128 @ 0x80 + 8006262: 009b lsls r3, r3, #2 + 8006264: 429a cmp r2, r3 + 8006266: d10e bne.n 8006286 + DBW_Stop(); + 8006268: f7fd feea bl 8004040 + config->config_bits |= CONFIG_TESTMODE_F; + 800626c: 4b56 ldr r3, [pc, #344] @ (80063c8 ) + 800626e: 681b ldr r3, [r3, #0] + 8006270: 4a56 ldr r2, [pc, #344] @ (80063cc ) + 8006272: 5a9b ldrh r3, [r3, r2] + 8006274: b29a uxth r2, r3 + 8006276: 4b54 ldr r3, [pc, #336] @ (80063c8 ) + 8006278: 681b ldr r3, [r3, #0] + 800627a: 2104 movs r1, #4 + 800627c: 430a orrs r2, r1 + 800627e: b291 uxth r1, r2 + 8006280: 4a52 ldr r2, [pc, #328] @ (80063cc ) + 8006282: 5299 strh r1, [r3, r2] + 8006284: e01e b.n 80062c4 + } else if (RX.data_size == 0x0300) { + 8006286: 4b4b ldr r3, [pc, #300] @ (80063b4 ) + 8006288: 88da ldrh r2, [r3, #6] + 800628a: 23c0 movs r3, #192 @ 0xc0 + 800628c: 009b lsls r3, r3, #2 + 800628e: 429a cmp r2, r3 + 8006290: d10c bne.n 80062ac + config->config_bits &= ~CONFIG_TESTMODE_F; + 8006292: 4b4d ldr r3, [pc, #308] @ (80063c8 ) + 8006294: 681b ldr r3, [r3, #0] + 8006296: 4a4d ldr r2, [pc, #308] @ (80063cc ) + 8006298: 5a9b ldrh r3, [r3, r2] + 800629a: b29a uxth r2, r3 + 800629c: 4b4a ldr r3, [pc, #296] @ (80063c8 ) + 800629e: 681b ldr r3, [r3, #0] + 80062a0: 2104 movs r1, #4 + 80062a2: 438a bics r2, r1 + 80062a4: b291 uxth r1, r2 + 80062a6: 4a49 ldr r2, [pc, #292] @ (80063cc ) + 80062a8: 5299 strh r1, [r3, r2] + 80062aa: e00b b.n 80062c4 + } else if (RX.data_size == 0x0400) { + 80062ac: 4b41 ldr r3, [pc, #260] @ (80063b4 ) + 80062ae: 88da ldrh r2, [r3, #6] + 80062b0: 2380 movs r3, #128 @ 0x80 + 80062b2: 00db lsls r3, r3, #3 + 80062b4: 429a cmp r2, r3 + 80062b6: d105 bne.n 80062c4 + //Start TPS AUTOCAL + ac_timer = 200; + 80062b8: 4b45 ldr r3, [pc, #276] @ (80063d0 ) + 80062ba: 22c8 movs r2, #200 @ 0xc8 + 80062bc: 601a str r2, [r3, #0] + ac_mode = 1; + 80062be: 4b45 ldr r3, [pc, #276] @ (80063d4 ) + 80062c0: 2201 movs r2, #1 + 80062c2: 601a str r2, [r3, #0] + } + Comms_Reset(&RX); + 80062c4: 4b3b ldr r3, [pc, #236] @ (80063b4 ) + 80062c6: 0018 movs r0, r3 + 80062c8: f7ff fec4 bl 8006054 + 80062cc: e0a7 b.n 800641e + } else if (RX.cmd == 'r') { + 80062ce: 4b39 ldr r3, [pc, #228] @ (80063b4 ) + 80062d0: 785b ldrb r3, [r3, #1] + 80062d2: 2b72 cmp r3, #114 @ 0x72 + 80062d4: d139 bne.n 800634a + // Read different tables + if (RX.table_index == 0x01) { + 80062d6: 4b37 ldr r3, [pc, #220] @ (80063b4 ) + 80062d8: 78db ldrb r3, [r3, #3] + 80062da: 2b01 cmp r3, #1 + 80062dc: d10b bne.n 80062f6 + TX_Schedule((unsigned char*) config + RX.offset, + 80062de: 4b3a ldr r3, [pc, #232] @ (80063c8 ) + 80062e0: 681b ldr r3, [r3, #0] + 80062e2: 4a34 ldr r2, [pc, #208] @ (80063b4 ) + 80062e4: 8892 ldrh r2, [r2, #4] + 80062e6: 189a adds r2, r3, r2 + 80062e8: 4b32 ldr r3, [pc, #200] @ (80063b4 ) + 80062ea: 88db ldrh r3, [r3, #6] + 80062ec: 0019 movs r1, r3 + 80062ee: 0010 movs r0, r2 + 80062f0: f000 f89a bl 8006428 + 80062f4: e024 b.n 8006340 + RX.data_size); + } else if (RX.table_index == 0x07) { + 80062f6: 4b2f ldr r3, [pc, #188] @ (80063b4 ) + 80062f8: 78db ldrb r3, [r3, #3] + 80062fa: 2b07 cmp r3, #7 + 80062fc: d10d bne.n 800631a + Copy_Tx_Vars(); + 80062fe: f000 f947 bl 8006590 + TX_Schedule((unsigned char*) &tx_bufer + RX.offset, + 8006302: 4b2c ldr r3, [pc, #176] @ (80063b4 ) + 8006304: 889b ldrh r3, [r3, #4] + 8006306: 001a movs r2, r3 + 8006308: 4b33 ldr r3, [pc, #204] @ (80063d8 ) + 800630a: 18d2 adds r2, r2, r3 + 800630c: 4b29 ldr r3, [pc, #164] @ (80063b4 ) + 800630e: 88db ldrh r3, [r3, #6] + 8006310: 0019 movs r1, r3 + 8006312: 0010 movs r0, r2 + 8006314: f000 f888 bl 8006428 + 8006318: e012 b.n 8006340 + RX.data_size); + } else if (RX.table_index == 0x0e) { + 800631a: 4b26 ldr r3, [pc, #152] @ (80063b4 ) + 800631c: 78db ldrb r3, [r3, #3] + 800631e: 2b0e cmp r3, #14 + 8006320: d105 bne.n 800632e + TX_Schedule((unsigned char*) Signature, 20); + 8006322: 4b27 ldr r3, [pc, #156] @ (80063c0 ) + 8006324: 2114 movs r1, #20 + 8006326: 0018 movs r0, r3 + 8006328: f000 f87e bl 8006428 + 800632c: e008 b.n 8006340 + } else if (RX.table_index == 0x0f) { + 800632e: 4b21 ldr r3, [pc, #132] @ (80063b4 ) + 8006330: 78db ldrb r3, [r3, #3] + 8006332: 2b0f cmp r3, #15 + 8006334: d104 bne.n 8006340 + TX_Schedule((unsigned char*) Revision, 20); + 8006336: 4b21 ldr r3, [pc, #132] @ (80063bc ) + 8006338: 2114 movs r1, #20 + 800633a: 0018 movs r0, r3 + 800633c: f000 f874 bl 8006428 + } + Comms_Reset(&RX); + 8006340: 4b1c ldr r3, [pc, #112] @ (80063b4 ) + 8006342: 0018 movs r0, r3 + 8006344: f7ff fe86 bl 8006054 + return; + 8006348: e069 b.n 800641e + } else { + //Comms are not reset for 'w' command + // setup write pointer + RX.cnt = RX.bytes_done + RX.data_size; + 800634a: 4b1a ldr r3, [pc, #104] @ (80063b4 ) + 800634c: 895a ldrh r2, [r3, #10] + 800634e: 4b19 ldr r3, [pc, #100] @ (80063b4 ) + 8006350: 88db ldrh r3, [r3, #6] + 8006352: 18d3 adds r3, r2, r3 + 8006354: b29a uxth r2, r3 + 8006356: 4b17 ldr r3, [pc, #92] @ (80063b4 ) + 8006358: 811a strh r2, [r3, #8] + if (RX.table_index == 0x01) { + 800635a: 4b16 ldr r3, [pc, #88] @ (80063b4 ) + 800635c: 78db ldrb r3, [r3, #3] + 800635e: 2b01 cmp r3, #1 + 8006360: d107 bne.n 8006372 + RX.address = (unsigned char*) config + RX.offset; + 8006362: 4b19 ldr r3, [pc, #100] @ (80063c8 ) + 8006364: 681b ldr r3, [r3, #0] + 8006366: 4a13 ldr r2, [pc, #76] @ (80063b4 ) + 8006368: 8892 ldrh r2, [r2, #4] + 800636a: 189a adds r2, r3, r2 + 800636c: 4b11 ldr r3, [pc, #68] @ (80063b4 ) + 800636e: 60da str r2, [r3, #12] + // Do not allow more then 256 bytes to be written to CAN buffer + if (RX.data_size > 256) + Comms_Reset(&RX); + } + + return; + 8006370: e054 b.n 800641c + RX.address = (unsigned char*) RX.can_bufer; + 8006372: 4b10 ldr r3, [pc, #64] @ (80063b4 ) + 8006374: 4a19 ldr r2, [pc, #100] @ (80063dc ) + 8006376: 60da str r2, [r3, #12] + if (RX.data_size > 256) + 8006378: 4b0e ldr r3, [pc, #56] @ (80063b4 ) + 800637a: 88da ldrh r2, [r3, #6] + 800637c: 2380 movs r3, #128 @ 0x80 + 800637e: 005b lsls r3, r3, #1 + 8006380: 429a cmp r2, r3 + 8006382: d94b bls.n 800641c + Comms_Reset(&RX); + 8006384: 4b0b ldr r3, [pc, #44] @ (80063b4 ) + 8006386: 0018 movs r0, r3 + 8006388: f7ff fe64 bl 8006054 + return; + 800638c: e046 b.n 800641c + } + + } else { + // if received CANID != TS_CANID + if ((RX.cmd == 'k') || (RX.cmd == 'r')) { + 800638e: 4b09 ldr r3, [pc, #36] @ (80063b4 ) + 8006390: 785b ldrb r3, [r3, #1] + 8006392: 2b6b cmp r3, #107 @ 0x6b + 8006394: d003 beq.n 800639e + 8006396: 4b07 ldr r3, [pc, #28] @ (80063b4 ) + 8006398: 785b ldrb r3, [r3, #1] + 800639a: 2b72 cmp r3, #114 @ 0x72 + 800639c: d104 bne.n 80063a8 + //TODO pass data to CAN device + Comms_Reset(&RX); + 800639e: 4b05 ldr r3, [pc, #20] @ (80063b4 ) + 80063a0: 0018 movs r0, r3 + 80063a2: f7ff fe57 bl 8006054 + return; + 80063a6: e03a b.n 800641e + } + Comms_Reset(&RX); + 80063a8: 4b02 ldr r3, [pc, #8] @ (80063b4 ) + 80063aa: 0018 movs r0, r3 + 80063ac: f7ff fe52 bl 8006054 + return; + 80063b0: e035 b.n 800641e + 80063b2: 46c0 nop @ (mov r8, r8) + 80063b4: 20000b34 .word 0x20000b34 + 80063b8: 20000d6c .word 0x20000d6c + 80063bc: 08008b0c .word 0x08008b0c + 80063c0: 08008af8 .word 0x08008af8 + 80063c4: 20000008 .word 0x20000008 + 80063c8: 200009cc .word 0x200009cc + 80063cc: 0000033a .word 0x0000033a + 80063d0: 20000000 .word 0x20000000 + 80063d4: 200009d0 .word 0x200009d0 + 80063d8: 20000d78 .word 0x20000d78 + 80063dc: 20000b50 .word 0x20000b50 + } + } else { + //receive data TX.bytes_done >7 + *(RX.address) = data; + 80063e0: 4b10 ldr r3, [pc, #64] @ (8006424 ) + 80063e2: 68db ldr r3, [r3, #12] + 80063e4: 1dfa adds r2, r7, #7 + 80063e6: 7812 ldrb r2, [r2, #0] + 80063e8: 701a strb r2, [r3, #0] + RX.address++; + 80063ea: 4b0e ldr r3, [pc, #56] @ (8006424 ) + 80063ec: 68db ldr r3, [r3, #12] + 80063ee: 1c5a adds r2, r3, #1 + 80063f0: 4b0c ldr r3, [pc, #48] @ (8006424 ) + 80063f2: 60da str r2, [r3, #12] + + if (RX.bytes_done >= RX.cnt) { + 80063f4: 4b0b ldr r3, [pc, #44] @ (8006424 ) + 80063f6: 895a ldrh r2, [r3, #10] + 80063f8: 4b0a ldr r3, [pc, #40] @ (8006424 ) + 80063fa: 891b ldrh r3, [r3, #8] + 80063fc: 429a cmp r2, r3 + 80063fe: d30e bcc.n 800641e + if (RX.table_index == 0x0d) { + 8006400: 4b08 ldr r3, [pc, #32] @ (8006424 ) + 8006402: 78db ldrb r3, [r3, #3] + 8006404: 2b0d cmp r3, #13 + 8006406: d104 bne.n 8006412 + //TODO Call command by index + Comms_Reset(&RX); + 8006408: 4b06 ldr r3, [pc, #24] @ (8006424 ) + 800640a: 0018 movs r0, r3 + 800640c: f7ff fe22 bl 8006054 + 8006410: e005 b.n 800641e + } else { + // Expecting here ends data write chain + Comms_Reset(&RX); + 8006412: 4b04 ldr r3, [pc, #16] @ (8006424 ) + 8006414: 0018 movs r0, r3 + 8006416: f7ff fe1d bl 8006054 + 800641a: e000 b.n 800641e + return; + 800641c: 46c0 nop @ (mov r8, r8) + + } + + } + +} // RX Char + 800641e: 46bd mov sp, r7 + 8006420: b002 add sp, #8 + 8006422: bd80 pop {r7, pc} + 8006424: 20000b34 .word 0x20000b34 + +08006428 : + +void TX_Schedule(unsigned char *data, unsigned short count) { + 8006428: b580 push {r7, lr} + 800642a: b082 sub sp, #8 + 800642c: af00 add r7, sp, #0 + 800642e: 6078 str r0, [r7, #4] + 8006430: 000a movs r2, r1 + 8006432: 1cbb adds r3, r7, #2 + 8006434: 801a strh r2, [r3, #0] + //Schedule transmission + TX.mode = TRANSMISSION_IN_PROGRESS; // Set TX mode to transmit + 8006436: 4b16 ldr r3, [pc, #88] @ (8006490 ) + 8006438: 2201 movs r2, #1 + 800643a: 701a strb r2, [r3, #0] + + TX.cnt = count; // Set number of byte to be transmited + 800643c: 4b14 ldr r3, [pc, #80] @ (8006490 ) + 800643e: 1cba adds r2, r7, #2 + 8006440: 8812 ldrh r2, [r2, #0] + 8006442: 811a strh r2, [r3, #8] + TX.bytes_done = 0; // Set number of bytes transmitted + 8006444: 4b12 ldr r3, [pc, #72] @ (8006490 ) + 8006446: 2200 movs r2, #0 + 8006448: 815a strh r2, [r3, #10] + TX.address = data; // Store updated address + 800644a: 4b11 ldr r3, [pc, #68] @ (8006490 ) + 800644c: 687a ldr r2, [r7, #4] + 800644e: 60da str r2, [r3, #12] + + //transmit first data byte + USART1->ICR |= USART_ICR_TCCF; + 8006450: 4b10 ldr r3, [pc, #64] @ (8006494 ) + 8006452: 6a1a ldr r2, [r3, #32] + 8006454: 4b0f ldr r3, [pc, #60] @ (8006494 ) + 8006456: 2140 movs r1, #64 @ 0x40 + 8006458: 430a orrs r2, r1 + 800645a: 621a str r2, [r3, #32] + USART1->TDR = *data; + 800645c: 687b ldr r3, [r7, #4] + 800645e: 781a ldrb r2, [r3, #0] + 8006460: 4b0c ldr r3, [pc, #48] @ (8006494 ) + 8006462: 851a strh r2, [r3, #40] @ 0x28 + USART1->CR1 |= USART_CR1_TCIE; + 8006464: 4b0b ldr r3, [pc, #44] @ (8006494 ) + 8006466: 681a ldr r2, [r3, #0] + 8006468: 4b0a ldr r3, [pc, #40] @ (8006494 ) + 800646a: 2140 movs r1, #64 @ 0x40 + 800646c: 430a orrs r2, r1 + 800646e: 601a str r2, [r3, #0] + + TX.bytes_done++; + 8006470: 4b07 ldr r3, [pc, #28] @ (8006490 ) + 8006472: 895b ldrh r3, [r3, #10] + 8006474: 3301 adds r3, #1 + 8006476: b29a uxth r2, r3 + 8006478: 4b05 ldr r3, [pc, #20] @ (8006490 ) + 800647a: 815a strh r2, [r3, #10] + TX.address++; + 800647c: 4b04 ldr r3, [pc, #16] @ (8006490 ) + 800647e: 68db ldr r3, [r3, #12] + 8006480: 1c5a adds r2, r3, #1 + 8006482: 4b03 ldr r3, [pc, #12] @ (8006490 ) + 8006484: 60da str r2, [r3, #12] +// else{ +// +// +// } + + return; + 8006486: 46c0 nop @ (mov r8, r8) +} + 8006488: 46bd mov sp, r7 + 800648a: b002 add sp, #8 + 800648c: bd80 pop {r7, pc} + 800648e: 46c0 nop @ (mov r8, r8) + 8006490: 20000c50 .word 0x20000c50 + 8006494: 40013800 .word 0x40013800 + +08006498 : + +void Poll_Tx(void) { + 8006498: b580 push {r7, lr} + 800649a: af00 add r7, sp, #0 + + if (TX.mode == TRANSMISSION_IN_PROGRESS) { + 800649c: 4b17 ldr r3, [pc, #92] @ (80064fc ) + 800649e: 781b ldrb r3, [r3, #0] + 80064a0: 2b01 cmp r3, #1 + 80064a2: d029 beq.n 80064f8 + // do nothing because transmitter is busy; + } + // Check if variables should be transmitted + else if (SCI_flags & SCI_FLAGS_TX_VARIABLES) { + 80064a4: 4b16 ldr r3, [pc, #88] @ (8006500 ) + 80064a6: 781b ldrb r3, [r3, #0] + 80064a8: 001a movs r2, r3 + 80064aa: 2302 movs r3, #2 + 80064ac: 4013 ands r3, r2 + 80064ae: d00e beq.n 80064ce + //Copy variables to tx_bufer + Copy_Tx_Vars(); + 80064b0: f000 f86e bl 8006590 + TX_Schedule((unsigned char*) &tx_bufer, sizeof(var_t)); + 80064b4: 4b13 ldr r3, [pc, #76] @ (8006504 ) + 80064b6: 2134 movs r1, #52 @ 0x34 + 80064b8: 0018 movs r0, r3 + 80064ba: f7ff ffb5 bl 8006428 + SCI_flags &= ~SCI_FLAGS_TX_VARIABLES; + 80064be: 4b10 ldr r3, [pc, #64] @ (8006500 ) + 80064c0: 781b ldrb r3, [r3, #0] + 80064c2: 2202 movs r2, #2 + 80064c4: 4393 bics r3, r2 + 80064c6: b2da uxtb r2, r3 + 80064c8: 4b0d ldr r3, [pc, #52] @ (8006500 ) + 80064ca: 701a strb r2, [r3, #0] + return; + 80064cc: e014 b.n 80064f8 + + } else if (SCI_flags & SCI_FLAGS_CRC32) { + 80064ce: 4b0c ldr r3, [pc, #48] @ (8006500 ) + 80064d0: 781b ldrb r3, [r3, #0] + 80064d2: 001a movs r2, r3 + 80064d4: 2301 movs r3, #1 + 80064d6: 4013 ands r3, r2 + 80064d8: d00e beq.n 80064f8 + SCI_flags &= ~SCI_FLAGS_CRC32; + 80064da: 4b09 ldr r3, [pc, #36] @ (8006500 ) + 80064dc: 781b ldrb r3, [r3, #0] + 80064de: 2201 movs r2, #1 + 80064e0: 4393 bics r3, r2 + 80064e2: b2da uxtb r2, r3 + 80064e4: 4b06 ldr r3, [pc, #24] @ (8006500 ) + 80064e6: 701a strb r2, [r3, #0] + CRC32(); + 80064e8: f000 f82a bl 8006540 + TX_Schedule((unsigned char*) &crc32_bufer[0], 4); + 80064ec: 4b06 ldr r3, [pc, #24] @ (8006508 ) + 80064ee: 2104 movs r1, #4 + 80064f0: 0018 movs r0, r3 + 80064f2: f7ff ff99 bl 8006428 + return; + 80064f6: 46c0 nop @ (mov r8, r8) + + } + +} + 80064f8: 46bd mov sp, r7 + 80064fa: bd80 pop {r7, pc} + 80064fc: 20000c50 .word 0x20000c50 + 8006500: 20000d6c .word 0x20000d6c + 8006504: 20000d78 .word 0x20000d78 + 8006508: 20000d70 .word 0x20000d70 + +0800650c : + +void TX_Done(void) { + 800650c: b580 push {r7, lr} + 800650e: af00 add r7, sp, #0 + Comms_Reset(&TX); + 8006510: 4b09 ldr r3, [pc, #36] @ (8006538 ) + 8006512: 0018 movs r0, r3 + 8006514: f7ff fd9e bl 8006054 + //disable TX interrupt + USART1->CR1 &= ~USART_CR1_TCIE; + 8006518: 4b08 ldr r3, [pc, #32] @ (800653c ) + 800651a: 681a ldr r2, [r3, #0] + 800651c: 4b07 ldr r3, [pc, #28] @ (800653c ) + 800651e: 2140 movs r1, #64 @ 0x40 + 8006520: 438a bics r2, r1 + 8006522: 601a str r2, [r3, #0] + USART1->ICR |= USART_ICR_TCCF; + 8006524: 4b05 ldr r3, [pc, #20] @ (800653c ) + 8006526: 6a1a ldr r2, [r3, #32] + 8006528: 4b04 ldr r3, [pc, #16] @ (800653c ) + 800652a: 2140 movs r1, #64 @ 0x40 + 800652c: 430a orrs r2, r1 + 800652e: 621a str r2, [r3, #32] + +} + 8006530: 46c0 nop @ (mov r8, r8) + 8006532: 46bd mov sp, r7 + 8006534: bd80 pop {r7, pc} + 8006536: 46c0 nop @ (mov r8, r8) + 8006538: 20000c50 .word 0x20000c50 + 800653c: 40013800 .word 0x40013800 + +08006540 : + +void CRC32(void) { + 8006540: b580 push {r7, lr} + 8006542: b082 sub sp, #8 + 8006544: af00 add r7, sp, #0 + unsigned int tmp; + + tmp = (unsigned int) crc32((void*) config, sizeof(config_t)); + 8006546: 4b10 ldr r3, [pc, #64] @ (8006588 ) + 8006548: 681b ldr r3, [r3, #0] + 800654a: 22d6 movs r2, #214 @ 0xd6 + 800654c: 0092 lsls r2, r2, #2 + 800654e: 0011 movs r1, r2 + 8006550: 0018 movs r0, r3 + 8006552: f000 f899 bl 8006688 + 8006556: 0003 movs r3, r0 + 8006558: 607b str r3, [r7, #4] + crc32_bufer[0] = (unsigned char) ((tmp >> 24) & 0x000000ff); + 800655a: 687b ldr r3, [r7, #4] + 800655c: 0e1b lsrs r3, r3, #24 + 800655e: b2da uxtb r2, r3 + 8006560: 4b0a ldr r3, [pc, #40] @ (800658c ) + 8006562: 701a strb r2, [r3, #0] + crc32_bufer[1] = (unsigned char) ((tmp >> 16) & 0x000000ff); + 8006564: 687b ldr r3, [r7, #4] + 8006566: 0c1b lsrs r3, r3, #16 + 8006568: b2da uxtb r2, r3 + 800656a: 4b08 ldr r3, [pc, #32] @ (800658c ) + 800656c: 705a strb r2, [r3, #1] + crc32_bufer[2] = (unsigned char) ((tmp >> 8) & 0x000000ff); + 800656e: 687b ldr r3, [r7, #4] + 8006570: 0a1b lsrs r3, r3, #8 + 8006572: b2da uxtb r2, r3 + 8006574: 4b05 ldr r3, [pc, #20] @ (800658c ) + 8006576: 709a strb r2, [r3, #2] + crc32_bufer[3] = (unsigned char) ((tmp) & 0x000000ff); + 8006578: 687b ldr r3, [r7, #4] + 800657a: b2da uxtb r2, r3 + 800657c: 4b03 ldr r3, [pc, #12] @ (800658c ) + 800657e: 70da strb r2, [r3, #3] +} + 8006580: 46c0 nop @ (mov r8, r8) + 8006582: 46bd mov sp, r7 + 8006584: b002 add sp, #8 + 8006586: bd80 pop {r7, pc} + 8006588: 200009cc .word 0x200009cc + 800658c: 20000d70 .word 0x20000d70 + +08006590 : + +void Copy_Tx_Vars(void) { + 8006590: b580 push {r7, lr} + 8006592: af00 add r7, sp, #0 + +//TODO copy all variables from *var to tx_bufer to make sure +// nothing is changed while transmission is in progress +//tx_bufer.a = var->a; + + tx_bufer.clock = var.clock; + 8006594: 4b3a ldr r3, [pc, #232] @ (8006680 ) + 8006596: 681a ldr r2, [r3, #0] + 8006598: 4b3a ldr r3, [pc, #232] @ (8006684 ) + 800659a: 601a str r2, [r3, #0] + tx_bufer.status0 = var.rpm; + 800659c: 4b38 ldr r3, [pc, #224] @ (8006680 ) + 800659e: 8e5b ldrh r3, [r3, #50] @ 0x32 + 80065a0: b29a uxth r2, r3 + 80065a2: 4b38 ldr r3, [pc, #224] @ (8006684 ) + 80065a4: 809a strh r2, [r3, #4] + tx_bufer.status1 = var.status1; + 80065a6: 4b36 ldr r3, [pc, #216] @ (8006680 ) + 80065a8: 88db ldrh r3, [r3, #6] + 80065aa: b29a uxth r2, r3 + 80065ac: 4b35 ldr r3, [pc, #212] @ (8006684 ) + 80065ae: 80da strh r2, [r3, #6] + tx_bufer.status2 = var.status2; + 80065b0: 4b33 ldr r3, [pc, #204] @ (8006680 ) + 80065b2: 891b ldrh r3, [r3, #8] + 80065b4: b29a uxth r2, r3 + 80065b6: 4b33 ldr r3, [pc, #204] @ (8006684 ) + 80065b8: 811a strh r2, [r3, #8] + tx_bufer.status3 = var.status3; + 80065ba: 4b31 ldr r3, [pc, #196] @ (8006680 ) + 80065bc: 895b ldrh r3, [r3, #10] + 80065be: b29a uxth r2, r3 + 80065c0: 4b30 ldr r3, [pc, #192] @ (8006684 ) + 80065c2: 815a strh r2, [r3, #10] + + tx_bufer.pps1_adc = var.pps1_adc; + 80065c4: 4b2e ldr r3, [pc, #184] @ (8006680 ) + 80065c6: 899b ldrh r3, [r3, #12] + 80065c8: b29a uxth r2, r3 + 80065ca: 4b2e ldr r3, [pc, #184] @ (8006684 ) + 80065cc: 819a strh r2, [r3, #12] + tx_bufer.pps2_adc = var.pps2_adc; + 80065ce: 4b2c ldr r3, [pc, #176] @ (8006680 ) + 80065d0: 89db ldrh r3, [r3, #14] + 80065d2: b29a uxth r2, r3 + 80065d4: 4b2b ldr r3, [pc, #172] @ (8006684 ) + 80065d6: 81da strh r2, [r3, #14] + tx_bufer.tps1_adc = var.tps1_adc; + 80065d8: 4b29 ldr r3, [pc, #164] @ (8006680 ) + 80065da: 8a1b ldrh r3, [r3, #16] + 80065dc: b29a uxth r2, r3 + 80065de: 4b29 ldr r3, [pc, #164] @ (8006684 ) + 80065e0: 821a strh r2, [r3, #16] + tx_bufer.tps2_adc = var.tps2_adc; + 80065e2: 4b27 ldr r3, [pc, #156] @ (8006680 ) + 80065e4: 8a5b ldrh r3, [r3, #18] + 80065e6: b29a uxth r2, r3 + 80065e8: 4b26 ldr r3, [pc, #152] @ (8006684 ) + 80065ea: 825a strh r2, [r3, #18] + tx_bufer.motor_current_adc = var.motor_current_adc; + 80065ec: 4b24 ldr r3, [pc, #144] @ (8006680 ) + 80065ee: 8a9b ldrh r3, [r3, #20] + 80065f0: b29a uxth r2, r3 + 80065f2: 4b24 ldr r3, [pc, #144] @ (8006684 ) + 80065f4: 829a strh r2, [r3, #20] + tx_bufer.vbat_adc = var.vbat_adc; + 80065f6: 4b22 ldr r3, [pc, #136] @ (8006680 ) + 80065f8: 8adb ldrh r3, [r3, #22] + 80065fa: b29a uxth r2, r3 + 80065fc: 4b21 ldr r3, [pc, #132] @ (8006684 ) + 80065fe: 82da strh r2, [r3, #22] + + tx_bufer.pps1 = var.pps1; + 8006600: 4b1f ldr r3, [pc, #124] @ (8006680 ) + 8006602: 8b1b ldrh r3, [r3, #24] + 8006604: b21a sxth r2, r3 + 8006606: 4b1f ldr r3, [pc, #124] @ (8006684 ) + 8006608: 831a strh r2, [r3, #24] + tx_bufer.pps2 = var.pps2; + 800660a: 4b1d ldr r3, [pc, #116] @ (8006680 ) + 800660c: 8b5b ldrh r3, [r3, #26] + 800660e: b21a sxth r2, r3 + 8006610: 4b1c ldr r3, [pc, #112] @ (8006684 ) + 8006612: 835a strh r2, [r3, #26] + tx_bufer.tps1 = var.tps1; + 8006614: 4b1a ldr r3, [pc, #104] @ (8006680 ) + 8006616: 8b9b ldrh r3, [r3, #28] + 8006618: b21a sxth r2, r3 + 800661a: 4b1a ldr r3, [pc, #104] @ (8006684 ) + 800661c: 839a strh r2, [r3, #28] + tx_bufer.tps2 = var.tps2; + 800661e: 4b18 ldr r3, [pc, #96] @ (8006680 ) + 8006620: 8bdb ldrh r3, [r3, #30] + 8006622: b21a sxth r2, r3 + 8006624: 4b17 ldr r3, [pc, #92] @ (8006684 ) + 8006626: 83da strh r2, [r3, #30] + tx_bufer.pps = var.pps; + 8006628: 4b15 ldr r3, [pc, #84] @ (8006680 ) + 800662a: 8c1b ldrh r3, [r3, #32] + 800662c: b21a sxth r2, r3 + 800662e: 4b15 ldr r3, [pc, #84] @ (8006684 ) + 8006630: 841a strh r2, [r3, #32] + tx_bufer.tps = var.tps; + 8006632: 4b13 ldr r3, [pc, #76] @ (8006680 ) + 8006634: 8c5b ldrh r3, [r3, #34] @ 0x22 + 8006636: b21a sxth r2, r3 + 8006638: 4b12 ldr r3, [pc, #72] @ (8006684 ) + 800663a: 845a strh r2, [r3, #34] @ 0x22 + tx_bufer.tps_error = var.tps_error; + 800663c: 4b10 ldr r3, [pc, #64] @ (8006680 ) + 800663e: 8c9b ldrh r3, [r3, #36] @ 0x24 + 8006640: b21a sxth r2, r3 + 8006642: 4b10 ldr r3, [pc, #64] @ (8006684 ) + 8006644: 849a strh r2, [r3, #36] @ 0x24 + tx_bufer.motor_pwm = var.motor_pwm; + 8006646: 4b0e ldr r3, [pc, #56] @ (8006680 ) + 8006648: 8cdb ldrh r3, [r3, #38] @ 0x26 + 800664a: b21a sxth r2, r3 + 800664c: 4b0d ldr r3, [pc, #52] @ (8006684 ) + 800664e: 84da strh r2, [r3, #38] @ 0x26 + tx_bufer.idle_dc = var.idle_dc; + 8006650: 4b0b ldr r3, [pc, #44] @ (8006680 ) + 8006652: 8d1b ldrh r3, [r3, #40] @ 0x28 + 8006654: b29a uxth r2, r3 + 8006656: 4b0b ldr r3, [pc, #44] @ (8006684 ) + 8006658: 851a strh r2, [r3, #40] @ 0x28 + tx_bufer.pps_delta = var.pps_delta; + 800665a: 4b09 ldr r3, [pc, #36] @ (8006680 ) + 800665c: 8d5b ldrh r3, [r3, #42] @ 0x2a + 800665e: b21a sxth r2, r3 + 8006660: 4b08 ldr r3, [pc, #32] @ (8006684 ) + 8006662: 855a strh r2, [r3, #42] @ 0x2a + tx_bufer.tps_delta = var.tps_delta; + 8006664: 4b06 ldr r3, [pc, #24] @ (8006680 ) + 8006666: 8d9b ldrh r3, [r3, #44] @ 0x2c + 8006668: b21a sxth r2, r3 + 800666a: 4b06 ldr r3, [pc, #24] @ (8006684 ) + 800666c: 859a strh r2, [r3, #44] @ 0x2c + tx_bufer.tps_target = var.tps_target; + 800666e: 4b04 ldr r3, [pc, #16] @ (8006680 ) + 8006670: 8ddb ldrh r3, [r3, #46] @ 0x2e + 8006672: b21a sxth r2, r3 + 8006674: 4b03 ldr r3, [pc, #12] @ (8006684 ) + 8006676: 85da strh r2, [r3, #46] @ 0x2e +} + 8006678: 46c0 nop @ (mov r8, r8) + 800667a: 46bd mov sp, r7 + 800667c: bd80 pop {r7, pc} + 800667e: 46c0 nop @ (mov r8, r8) + 8006680: 20000998 .word 0x20000998 + 8006684: 20000d78 .word 0x20000d78 + +08006688 : + +/** + * Online CRC calculator: + * http://www.zorc.breitbandkatze.de/crc.html + */ +uint32_t crc32(void *buf, uint32_t size) { + 8006688: b580 push {r7, lr} + 800668a: b082 sub sp, #8 + 800668c: af00 add r7, sp, #0 + 800668e: 6078 str r0, [r7, #4] + 8006690: 6039 str r1, [r7, #0] + return crc32inc(buf, 0, size); + 8006692: 683a ldr r2, [r7, #0] + 8006694: 687b ldr r3, [r7, #4] + 8006696: 2100 movs r1, #0 + 8006698: 0018 movs r0, r3 + 800669a: f000 f805 bl 80066a8 + 800669e: 0003 movs r3, r0 +} + 80066a0: 0018 movs r0, r3 + 80066a2: 46bd mov sp, r7 + 80066a4: b002 add sp, #8 + 80066a6: bd80 pop {r7, pc} + +080066a8 : + +uint32_t crc32inc(void *buf, uint32_t crc, uint32_t size) { + 80066a8: b580 push {r7, lr} + 80066aa: b086 sub sp, #24 + 80066ac: af00 add r7, sp, #0 + 80066ae: 60f8 str r0, [r7, #12] + 80066b0: 60b9 str r1, [r7, #8] + 80066b2: 607a str r2, [r7, #4] + uint8_t *p; + + p = (uint8_t*) buf; + 80066b4: 68fb ldr r3, [r7, #12] + 80066b6: 617b str r3, [r7, #20] + crc = crc ^ 0xFFFFFFFF; + 80066b8: 68bb ldr r3, [r7, #8] + 80066ba: 43db mvns r3, r3 + 80066bc: 60bb str r3, [r7, #8] + + while (size--) { + 80066be: e00f b.n 80066e0 + crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + 80066c0: 697b ldr r3, [r7, #20] + 80066c2: 1c5a adds r2, r3, #1 + 80066c4: 617a str r2, [r7, #20] + 80066c6: 781b ldrb r3, [r3, #0] + 80066c8: 001a movs r2, r3 + 80066ca: 68bb ldr r3, [r7, #8] + 80066cc: 4053 eors r3, r2 + 80066ce: 22ff movs r2, #255 @ 0xff + 80066d0: 401a ands r2, r3 + 80066d2: 4b09 ldr r3, [pc, #36] @ (80066f8 ) + 80066d4: 0092 lsls r2, r2, #2 + 80066d6: 58d2 ldr r2, [r2, r3] + 80066d8: 68bb ldr r3, [r7, #8] + 80066da: 0a1b lsrs r3, r3, #8 + 80066dc: 4053 eors r3, r2 + 80066de: 60bb str r3, [r7, #8] + while (size--) { + 80066e0: 687b ldr r3, [r7, #4] + 80066e2: 1e5a subs r2, r3, #1 + 80066e4: 607a str r2, [r7, #4] + 80066e6: 2b00 cmp r3, #0 + 80066e8: d1ea bne.n 80066c0 + } + + return crc ^ 0xFFFFFFFF; + 80066ea: 68bb ldr r3, [r7, #8] + 80066ec: 43db mvns r3, r3 +} + 80066ee: 0018 movs r0, r3 + 80066f0: 46bd mov sp, r7 + 80066f2: b006 add sp, #24 + 80066f4: bd80 pop {r7, pc} + 80066f6: 46c0 nop @ (mov r8, r8) + 80066f8: 2000000c .word 0x2000000c + +080066fc : + +void Write_Config(void) { + 80066fc: b5b0 push {r4, r5, r7, lr} + 80066fe: b088 sub sp, #32 + 8006700: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 8006702: b672 cpsid i +} + 8006704: 46c0 nop @ (mov r8, r8) + __disable_irq(); + uint32_t error; + FLASH_EraseInitTypeDef erase_pages; + erase_pages.NbPages = 2; + 8006706: 003b movs r3, r7 + 8006708: 2202 movs r2, #2 + 800670a: 609a str r2, [r3, #8] + erase_pages.TypeErase = TYPEERASE_PAGES; + 800670c: 003b movs r3, r7 + 800670e: 2200 movs r2, #0 + 8006710: 601a str r2, [r3, #0] + erase_pages.PageAddress = (uint32_t) &config_flash; + 8006712: 4a23 ldr r2, [pc, #140] @ (80067a0 ) + 8006714: 003b movs r3, r7 + 8006716: 605a str r2, [r3, #4] + HAL_FLASH_Unlock(); + 8006718: f000 fc8a bl 8007030 + HAL_FLASHEx_Erase(&erase_pages, &error); + 800671c: 230c movs r3, #12 + 800671e: 18fa adds r2, r7, r3 + 8006720: 003b movs r3, r7 + 8006722: 0011 movs r1, r2 + 8006724: 0018 movs r0, r3 + 8006726: f000 fd43 bl 80071b0 + HAL_FLASH_Lock(); + 800672a: f000 fca7 bl 800707c + + uint16_t num_wrt; + if (sizeof(config_t) & 0x0001) + num_wrt = (sizeof(config_t) << 1) + 1; + else + num_wrt = sizeof(config_t) << 1; + 800672e: 2112 movs r1, #18 + 8006730: 187b adds r3, r7, r1 + 8006732: 22d6 movs r2, #214 @ 0xd6 + 8006734: 00d2 lsls r2, r2, #3 + 8006736: 801a strh r2, [r3, #0] + if (num_wrt > 2048) + 8006738: 187b adds r3, r7, r1 + 800673a: 881a ldrh r2, [r3, #0] + 800673c: 2380 movs r3, #128 @ 0x80 + 800673e: 011b lsls r3, r3, #4 + 8006740: 429a cmp r2, r3 + 8006742: d901 bls.n 8006748 + Error_Handler(); + 8006744: f7fe faec bl 8004d20 + + HAL_FLASH_Unlock(); + 8006748: f000 fc72 bl 8007030 + uint16_t *data, *flash_address; + data = (uint16_t*) &config_ram; + 800674c: 4b15 ldr r3, [pc, #84] @ (80067a4 ) + 800674e: 61fb str r3, [r7, #28] + flash_address = (uint16_t*) &config_flash; + 8006750: 4b13 ldr r3, [pc, #76] @ (80067a0 ) + 8006752: 61bb str r3, [r7, #24] + for (int i = 0; i < num_wrt; i++) { + 8006754: 2300 movs r3, #0 + 8006756: 617b str r3, [r7, #20] + 8006758: e013 b.n 8006782 + HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, (uint32_t) flash_address, + 800675a: 69b9 ldr r1, [r7, #24] + *data); + 800675c: 69fb ldr r3, [r7, #28] + 800675e: 881b ldrh r3, [r3, #0] + HAL_FLASH_Program(TYPEPROGRAM_HALFWORD, (uint32_t) flash_address, + 8006760: 001c movs r4, r3 + 8006762: 2300 movs r3, #0 + 8006764: 001d movs r5, r3 + 8006766: 0022 movs r2, r4 + 8006768: 002b movs r3, r5 + 800676a: 2001 movs r0, #1 + 800676c: f000 fbca bl 8006f04 + data++; + 8006770: 69fb ldr r3, [r7, #28] + 8006772: 3302 adds r3, #2 + 8006774: 61fb str r3, [r7, #28] + flash_address++; + 8006776: 69bb ldr r3, [r7, #24] + 8006778: 3302 adds r3, #2 + 800677a: 61bb str r3, [r7, #24] + for (int i = 0; i < num_wrt; i++) { + 800677c: 697b ldr r3, [r7, #20] + 800677e: 3301 adds r3, #1 + 8006780: 617b str r3, [r7, #20] + 8006782: 2312 movs r3, #18 + 8006784: 18fb adds r3, r7, r3 + 8006786: 881b ldrh r3, [r3, #0] + 8006788: 697a ldr r2, [r7, #20] + 800678a: 429a cmp r2, r3 + 800678c: dbe5 blt.n 800675a + } + HAL_FLASH_Lock(); + 800678e: f000 fc75 bl 800707c + __ASM volatile ("cpsie i" : : : "memory"); + 8006792: b662 cpsie i +} + 8006794: 46c0 nop @ (mov r8, r8) + __enable_irq(); +} + 8006796: 46c0 nop @ (mov r8, r8) + 8006798: 46bd mov sp, r7 + 800679a: b008 add sp, #32 + 800679c: bdb0 pop {r4, r5, r7, pc} + 800679e: 46c0 nop @ (mov r8, r8) + 80067a0: 0800f000 .word 0x0800f000 + 80067a4: 20000640 .word 0x20000640 + +080067a8 : + +void TS_Comms_RX_Timeout(void) { + 80067a8: b580 push {r7, lr} + 80067aa: af00 add r7, sp, #0 + if (RX.mode != IDLE) { + 80067ac: 4b0c ldr r3, [pc, #48] @ (80067e0 ) + 80067ae: 781b ldrb r3, [r3, #0] + 80067b0: 2b00 cmp r3, #0 + 80067b2: d011 beq.n 80067d8 + if (RX.timeout) { + 80067b4: 4b0a ldr r3, [pc, #40] @ (80067e0 ) + 80067b6: 8a9b ldrh r3, [r3, #20] + 80067b8: 2b00 cmp r3, #0 + 80067ba: d00d beq.n 80067d8 + RX.timeout--; + 80067bc: 4b08 ldr r3, [pc, #32] @ (80067e0 ) + 80067be: 8a9b ldrh r3, [r3, #20] + 80067c0: 3b01 subs r3, #1 + 80067c2: b29a uxth r2, r3 + 80067c4: 4b06 ldr r3, [pc, #24] @ (80067e0 ) + 80067c6: 829a strh r2, [r3, #20] + if (RX.timeout == 0) { + 80067c8: 4b05 ldr r3, [pc, #20] @ (80067e0 ) + 80067ca: 8a9b ldrh r3, [r3, #20] + 80067cc: 2b00 cmp r3, #0 + 80067ce: d103 bne.n 80067d8 + Comms_Reset(&RX); + 80067d0: 4b03 ldr r3, [pc, #12] @ (80067e0 ) + 80067d2: 0018 movs r0, r3 + 80067d4: f7ff fc3e bl 8006054 + } + } + } +} + 80067d8: 46c0 nop @ (mov r8, r8) + 80067da: 46bd mov sp, r7 + 80067dc: bd80 pop {r7, pc} + 80067de: 46c0 nop @ (mov r8, r8) + 80067e0: 20000b34 .word 0x20000b34 + +080067e4 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 80067e4: 480d ldr r0, [pc, #52] @ (800681c ) + mov sp, r0 /* set stack pointer */ + 80067e6: 4685 mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80067e8: 480d ldr r0, [pc, #52] @ (8006820 ) + ldr r1, =_edata + 80067ea: 490e ldr r1, [pc, #56] @ (8006824 ) + ldr r2, =_sidata + 80067ec: 4a0e ldr r2, [pc, #56] @ (8006828 ) + movs r3, #0 + 80067ee: 2300 movs r3, #0 + b LoopCopyDataInit + 80067f0: e002 b.n 80067f8 + +080067f2 : + +CopyDataInit: + ldr r4, [r2, r3] + 80067f2: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80067f4: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80067f6: 3304 adds r3, #4 + +080067f8 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80067f8: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80067fa: 428c cmp r4, r1 + bcc CopyDataInit + 80067fc: d3f9 bcc.n 80067f2 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80067fe: 4a0b ldr r2, [pc, #44] @ (800682c ) + ldr r4, =_ebss + 8006800: 4c0b ldr r4, [pc, #44] @ (8006830 ) + movs r3, #0 + 8006802: 2300 movs r3, #0 + b LoopFillZerobss + 8006804: e001 b.n 800680a + +08006806 : + +FillZerobss: + str r3, [r2] + 8006806: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8006808: 3204 adds r2, #4 + +0800680a : + +LoopFillZerobss: + cmp r2, r4 + 800680a: 42a2 cmp r2, r4 + bcc FillZerobss + 800680c: d3fb bcc.n 8006806 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 800680e: f7ff fbab bl 8005f68 +/* Call static constructors */ + bl __libc_init_array + 8006812: f002 f885 bl 8008920 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8006816: f7fd ffe7 bl 80047e8
+ +0800681a : + +LoopForever: + b LoopForever + 800681a: e7fe b.n 800681a + ldr r0, =_estack + 800681c: 20004000 .word 0x20004000 + ldr r0, =_sdata + 8006820: 20000000 .word 0x20000000 + ldr r1, =_edata + 8006824: 20000414 .word 0x20000414 + ldr r2, =_sidata + 8006828: 08008b28 .word 0x08008b28 + ldr r2, =_sbss + 800682c: 20000418 .word 0x20000418 + ldr r4, =_ebss + 8006830: 20000dd0 .word 0x20000dd0 + +08006834 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8006834: e7fe b.n 8006834 + ... + +08006838 : + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8006838: b580 push {r7, lr} + 800683a: af00 add r7, sp, #0 + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 800683c: 4b07 ldr r3, [pc, #28] @ (800685c ) + 800683e: 681a ldr r2, [r3, #0] + 8006840: 4b06 ldr r3, [pc, #24] @ (800685c ) + 8006842: 2110 movs r1, #16 + 8006844: 430a orrs r2, r1 + 8006846: 601a str r2, [r3, #0] +#endif /* PREFETCH_ENABLE */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + + HAL_InitTick(TICK_INT_PRIORITY); + 8006848: 2000 movs r0, #0 + 800684a: f000 f809 bl 8006860 + + /* Init the low level hardware */ + HAL_MspInit(); + 800684e: f7ff fa81 bl 8005d54 + + /* Return function status */ + return HAL_OK; + 8006852: 2300 movs r3, #0 +} + 8006854: 0018 movs r0, r3 + 8006856: 46bd mov sp, r7 + 8006858: bd80 pop {r7, pc} + 800685a: 46c0 nop @ (mov r8, r8) + 800685c: 40022000 .word 0x40022000 + +08006860 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8006860: b590 push {r4, r7, lr} + 8006862: b083 sub sp, #12 + 8006864: af00 add r7, sp, #0 + 8006866: 6078 str r0, [r7, #4] + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8006868: 4b14 ldr r3, [pc, #80] @ (80068bc ) + 800686a: 681c ldr r4, [r3, #0] + 800686c: 4b14 ldr r3, [pc, #80] @ (80068c0 ) + 800686e: 781b ldrb r3, [r3, #0] + 8006870: 0019 movs r1, r3 + 8006872: 23fa movs r3, #250 @ 0xfa + 8006874: 0098 lsls r0, r3, #2 + 8006876: f7f9 fc47 bl 8000108 <__udivsi3> + 800687a: 0003 movs r3, r0 + 800687c: 0019 movs r1, r3 + 800687e: 0020 movs r0, r4 + 8006880: f7f9 fc42 bl 8000108 <__udivsi3> + 8006884: 0003 movs r3, r0 + 8006886: 0018 movs r0, r3 + 8006888: f000 fb2f bl 8006eea + 800688c: 1e03 subs r3, r0, #0 + 800688e: d001 beq.n 8006894 + { + return HAL_ERROR; + 8006890: 2301 movs r3, #1 + 8006892: e00f b.n 80068b4 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8006894: 687b ldr r3, [r7, #4] + 8006896: 2b03 cmp r3, #3 + 8006898: d80b bhi.n 80068b2 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 800689a: 6879 ldr r1, [r7, #4] + 800689c: 2301 movs r3, #1 + 800689e: 425b negs r3, r3 + 80068a0: 2200 movs r2, #0 + 80068a2: 0018 movs r0, r3 + 80068a4: f000 fb0c bl 8006ec0 + uwTickPrio = TickPriority; + 80068a8: 4b06 ldr r3, [pc, #24] @ (80068c4 ) + 80068aa: 687a ldr r2, [r7, #4] + 80068ac: 601a str r2, [r3, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 80068ae: 2300 movs r3, #0 + 80068b0: e000 b.n 80068b4 + return HAL_ERROR; + 80068b2: 2301 movs r3, #1 +} + 80068b4: 0018 movs r0, r3 + 80068b6: 46bd mov sp, r7 + 80068b8: b003 add sp, #12 + 80068ba: bd90 pop {r4, r7, pc} + 80068bc: 20000004 .word 0x20000004 + 80068c0: 20000410 .word 0x20000410 + 80068c4: 2000040c .word 0x2000040c + +080068c8 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 80068c8: b580 push {r7, lr} + 80068ca: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 80068cc: 4b05 ldr r3, [pc, #20] @ (80068e4 ) + 80068ce: 781b ldrb r3, [r3, #0] + 80068d0: 001a movs r2, r3 + 80068d2: 4b05 ldr r3, [pc, #20] @ (80068e8 ) + 80068d4: 681b ldr r3, [r3, #0] + 80068d6: 18d2 adds r2, r2, r3 + 80068d8: 4b03 ldr r3, [pc, #12] @ (80068e8 ) + 80068da: 601a str r2, [r3, #0] +} + 80068dc: 46c0 nop @ (mov r8, r8) + 80068de: 46bd mov sp, r7 + 80068e0: bd80 pop {r7, pc} + 80068e2: 46c0 nop @ (mov r8, r8) + 80068e4: 20000410 .word 0x20000410 + 80068e8: 20000dac .word 0x20000dac + +080068ec : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80068ec: b580 push {r7, lr} + 80068ee: af00 add r7, sp, #0 + return uwTick; + 80068f0: 4b02 ldr r3, [pc, #8] @ (80068fc ) + 80068f2: 681b ldr r3, [r3, #0] +} + 80068f4: 0018 movs r0, r3 + 80068f6: 46bd mov sp, r7 + 80068f8: bd80 pop {r7, pc} + 80068fa: 46c0 nop @ (mov r8, r8) + 80068fc: 20000dac .word 0x20000dac + +08006900 : + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + 8006900: b580 push {r7, lr} + 8006902: b084 sub sp, #16 + 8006904: af00 add r7, sp, #0 + 8006906: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 8006908: 230f movs r3, #15 + 800690a: 18fb adds r3, r7, r3 + 800690c: 2200 movs r2, #0 + 800690e: 701a strb r2, [r3, #0] + uint32_t tmpCFGR1 = 0U; + 8006910: 2300 movs r3, #0 + 8006912: 60bb str r3, [r7, #8] + + /* Check ADC handle */ + if(hadc == NULL) + 8006914: 687b ldr r3, [r7, #4] + 8006916: 2b00 cmp r3, #0 + 8006918: d101 bne.n 800691e + { + return HAL_ERROR; + 800691a: 2301 movs r3, #1 + 800691c: e125 b.n 8006b6a + /* Refer to header of this file for more details on clock enabling procedure*/ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + /* - ADC voltage regulator enable */ + if (hadc->State == HAL_ADC_STATE_RESET) + 800691e: 687b ldr r3, [r7, #4] + 8006920: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006922: 2b00 cmp r3, #0 + 8006924: d10a bne.n 800693c + { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 8006926: 687b ldr r3, [r7, #4] + 8006928: 2200 movs r2, #0 + 800692a: 63da str r2, [r3, #60] @ 0x3c + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + 800692c: 687b ldr r3, [r7, #4] + 800692e: 2234 movs r2, #52 @ 0x34 + 8006930: 2100 movs r1, #0 + 8006932: 5499 strb r1, [r3, r2] + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 8006934: 687b ldr r3, [r7, #4] + 8006936: 0018 movs r0, r3 + 8006938: f7ff fa30 bl 8005d9c + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + /* and if there is no conversion on going on regular group (ADC can be */ + /* enabled anyway, in case of call of this function to update a parameter */ + /* on the fly). */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && + 800693c: 687b ldr r3, [r7, #4] + 800693e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006940: 2210 movs r2, #16 + 8006942: 4013 ands r3, r2 + 8006944: d000 beq.n 8006948 + 8006946: e103 b.n 8006b50 + 8006948: 230f movs r3, #15 + 800694a: 18fb adds r3, r7, r3 + 800694c: 781b ldrb r3, [r3, #0] + 800694e: 2b00 cmp r3, #0 + 8006950: d000 beq.n 8006954 + 8006952: e0fd b.n 8006b50 + (tmp_hal_status == HAL_OK) && + (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + 8006954: 687b ldr r3, [r7, #4] + 8006956: 681b ldr r3, [r3, #0] + 8006958: 689b ldr r3, [r3, #8] + 800695a: 2204 movs r2, #4 + 800695c: 4013 ands r3, r2 + (tmp_hal_status == HAL_OK) && + 800695e: d000 beq.n 8006962 + 8006960: e0f6 b.n 8006b50 + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8006962: 687b ldr r3, [r7, #4] + 8006964: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006966: 4a83 ldr r2, [pc, #524] @ (8006b74 ) + 8006968: 4013 ands r3, r2 + 800696a: 2202 movs r2, #2 + 800696c: 431a orrs r2, r3 + 800696e: 687b ldr r3, [r7, #4] + 8006970: 639a str r2, [r3, #56] @ 0x38 + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - ADC clock mode */ + /* - ADC clock prescaler */ + /* - ADC resolution */ + if (ADC_IS_ENABLE(hadc) == RESET) + 8006972: 687b ldr r3, [r7, #4] + 8006974: 681b ldr r3, [r3, #0] + 8006976: 689b ldr r3, [r3, #8] + 8006978: 2203 movs r2, #3 + 800697a: 4013 ands r3, r2 + 800697c: 2b01 cmp r3, #1 + 800697e: d112 bne.n 80069a6 + 8006980: 687b ldr r3, [r7, #4] + 8006982: 681b ldr r3, [r3, #0] + 8006984: 681b ldr r3, [r3, #0] + 8006986: 2201 movs r2, #1 + 8006988: 4013 ands r3, r2 + 800698a: 2b01 cmp r3, #1 + 800698c: d009 beq.n 80069a2 + 800698e: 687b ldr r3, [r7, #4] + 8006990: 681b ldr r3, [r3, #0] + 8006992: 68da ldr r2, [r3, #12] + 8006994: 2380 movs r3, #128 @ 0x80 + 8006996: 021b lsls r3, r3, #8 + 8006998: 401a ands r2, r3 + 800699a: 2380 movs r3, #128 @ 0x80 + 800699c: 021b lsls r3, r3, #8 + 800699e: 429a cmp r2, r3 + 80069a0: d101 bne.n 80069a6 + 80069a2: 2301 movs r3, #1 + 80069a4: e000 b.n 80069a8 + 80069a6: 2300 movs r3, #0 + 80069a8: 2b00 cmp r3, #0 + 80069aa: d116 bne.n 80069da + /* parameters): */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + 80069ac: 687b ldr r3, [r7, #4] + 80069ae: 681b ldr r3, [r3, #0] + 80069b0: 68db ldr r3, [r3, #12] + 80069b2: 2218 movs r2, #24 + 80069b4: 4393 bics r3, r2 + 80069b6: 0019 movs r1, r3 + 80069b8: 687b ldr r3, [r7, #4] + 80069ba: 689a ldr r2, [r3, #8] + 80069bc: 687b ldr r3, [r7, #4] + 80069be: 681b ldr r3, [r3, #0] + 80069c0: 430a orrs r2, r1 + 80069c2: 60da str r2, [r3, #12] + ADC_CFGR1_RES , + hadc->Init.Resolution ); + + /* Configuration of ADC clock mode: clock source AHB or HSI with */ + /* selectable prescaler */ + MODIFY_REG(hadc->Instance->CFGR2 , + 80069c4: 687b ldr r3, [r7, #4] + 80069c6: 681b ldr r3, [r3, #0] + 80069c8: 691b ldr r3, [r3, #16] + 80069ca: 009b lsls r3, r3, #2 + 80069cc: 0899 lsrs r1, r3, #2 + 80069ce: 687b ldr r3, [r7, #4] + 80069d0: 685a ldr r2, [r3, #4] + 80069d2: 687b ldr r3, [r7, #4] + 80069d4: 681b ldr r3, [r3, #0] + 80069d6: 430a orrs r2, r1 + 80069d8: 611a str r2, [r3, #16] + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | + 80069da: 687b ldr r3, [r7, #4] + 80069dc: 681b ldr r3, [r3, #0] + 80069de: 68da ldr r2, [r3, #12] + 80069e0: 687b ldr r3, [r7, #4] + 80069e2: 681b ldr r3, [r3, #0] + 80069e4: 4964 ldr r1, [pc, #400] @ (8006b78 ) + 80069e6: 400a ands r2, r1 + 80069e8: 60da str r2, [r3, #12] + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG ); + + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + 80069ea: 687b ldr r3, [r7, #4] + 80069ec: 7e1b ldrb r3, [r3, #24] + 80069ee: 039a lsls r2, r3, #14 + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + 80069f0: 687b ldr r3, [r7, #4] + 80069f2: 7e5b ldrb r3, [r3, #25] + 80069f4: 03db lsls r3, r3, #15 + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + 80069f6: 431a orrs r2, r3 + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 80069f8: 687b ldr r3, [r7, #4] + 80069fa: 7e9b ldrb r3, [r3, #26] + 80069fc: 035b lsls r3, r3, #13 + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + 80069fe: 431a orrs r2, r3 + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + 8006a00: 687b ldr r3, [r7, #4] + 8006a02: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006a04: 2b01 cmp r3, #1 + 8006a06: d002 beq.n 8006a0e + 8006a08: 2380 movs r3, #128 @ 0x80 + 8006a0a: 015b lsls r3, r3, #5 + 8006a0c: e000 b.n 8006a10 + 8006a0e: 2300 movs r3, #0 + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 8006a10: 431a orrs r2, r3 + hadc->Init.DataAlign | + 8006a12: 687b ldr r3, [r7, #4] + 8006a14: 68db ldr r3, [r3, #12] + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + 8006a16: 431a orrs r2, r3 + ADC_SCANDIR(hadc->Init.ScanConvMode) | + 8006a18: 687b ldr r3, [r7, #4] + 8006a1a: 691b ldr r3, [r3, #16] + 8006a1c: 2b02 cmp r3, #2 + 8006a1e: d101 bne.n 8006a24 + 8006a20: 2304 movs r3, #4 + 8006a22: e000 b.n 8006a26 + 8006a24: 2300 movs r3, #0 + hadc->Init.DataAlign | + 8006a26: 431a orrs r2, r3 + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); + 8006a28: 687b ldr r3, [r7, #4] + 8006a2a: 2124 movs r1, #36 @ 0x24 + 8006a2c: 5c5b ldrb r3, [r3, r1] + 8006a2e: 005b lsls r3, r3, #1 + ADC_SCANDIR(hadc->Init.ScanConvMode) | + 8006a30: 4313 orrs r3, r2 + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + 8006a32: 68ba ldr r2, [r7, #8] + 8006a34: 4313 orrs r3, r2 + 8006a36: 60bb str r3, [r7, #8] + + /* Enable discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + 8006a38: 687b ldr r3, [r7, #4] + 8006a3a: 7edb ldrb r3, [r3, #27] + 8006a3c: 2b01 cmp r3, #1 + 8006a3e: d115 bne.n 8006a6c + { + if (hadc->Init.ContinuousConvMode == DISABLE) + 8006a40: 687b ldr r3, [r7, #4] + 8006a42: 7e9b ldrb r3, [r3, #26] + 8006a44: 2b00 cmp r3, #0 + 8006a46: d105 bne.n 8006a54 + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + 8006a48: 68bb ldr r3, [r7, #8] + 8006a4a: 2280 movs r2, #128 @ 0x80 + 8006a4c: 0252 lsls r2, r2, #9 + 8006a4e: 4313 orrs r3, r2 + 8006a50: 60bb str r3, [r7, #8] + 8006a52: e00b b.n 8006a6c + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 8006a54: 687b ldr r3, [r7, #4] + 8006a56: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006a58: 2220 movs r2, #32 + 8006a5a: 431a orrs r2, r3 + 8006a5c: 687b ldr r3, [r7, #4] + 8006a5e: 639a str r2, [r3, #56] @ 0x38 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 8006a60: 687b ldr r3, [r7, #4] + 8006a62: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006a64: 2201 movs r2, #1 + 8006a66: 431a orrs r2, r3 + 8006a68: 687b ldr r3, [r7, #4] + 8006a6a: 63da str r2, [r3, #60] @ 0x3c + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 8006a6c: 687b ldr r3, [r7, #4] + 8006a6e: 69da ldr r2, [r3, #28] + 8006a70: 23c2 movs r3, #194 @ 0xc2 + 8006a72: 33ff adds r3, #255 @ 0xff + 8006a74: 429a cmp r2, r3 + 8006a76: d007 beq.n 8006a88 + { + tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | + 8006a78: 687b ldr r3, [r7, #4] + 8006a7a: 69da ldr r2, [r3, #28] + hadc->Init.ExternalTrigConvEdge ); + 8006a7c: 687b ldr r3, [r7, #4] + 8006a7e: 6a1b ldr r3, [r3, #32] + tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | + 8006a80: 4313 orrs r3, r2 + 8006a82: 68ba ldr r2, [r7, #8] + 8006a84: 4313 orrs r3, r2 + 8006a86: 60bb str r3, [r7, #8] + } + + /* Update ADC configuration register with previous settings */ + hadc->Instance->CFGR1 |= tmpCFGR1; + 8006a88: 687b ldr r3, [r7, #4] + 8006a8a: 681b ldr r3, [r3, #0] + 8006a8c: 68d9 ldr r1, [r3, #12] + 8006a8e: 687b ldr r3, [r7, #4] + 8006a90: 681b ldr r3, [r3, #0] + 8006a92: 68ba ldr r2, [r7, #8] + 8006a94: 430a orrs r2, r1 + 8006a96: 60da str r2, [r3, #12] + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function if parameter */ + /* "SamplingTimeCommon" has been set to a valid sampling time. */ + /* Otherwise, sampling time is set into ADC channel initialization */ + /* structure with parameter "SamplingTime" (obsolete). */ + if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + 8006a98: 687b ldr r3, [r7, #4] + 8006a9a: 6ada ldr r2, [r3, #44] @ 0x2c + 8006a9c: 2380 movs r3, #128 @ 0x80 + 8006a9e: 055b lsls r3, r3, #21 + 8006aa0: 429a cmp r2, r3 + 8006aa2: d01b beq.n 8006adc + 8006aa4: 687b ldr r3, [r7, #4] + 8006aa6: 6adb ldr r3, [r3, #44] @ 0x2c + 8006aa8: 2b01 cmp r3, #1 + 8006aaa: d017 beq.n 8006adc + 8006aac: 687b ldr r3, [r7, #4] + 8006aae: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ab0: 2b02 cmp r3, #2 + 8006ab2: d013 beq.n 8006adc + 8006ab4: 687b ldr r3, [r7, #4] + 8006ab6: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ab8: 2b03 cmp r3, #3 + 8006aba: d00f beq.n 8006adc + 8006abc: 687b ldr r3, [r7, #4] + 8006abe: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ac0: 2b04 cmp r3, #4 + 8006ac2: d00b beq.n 8006adc + 8006ac4: 687b ldr r3, [r7, #4] + 8006ac6: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ac8: 2b05 cmp r3, #5 + 8006aca: d007 beq.n 8006adc + 8006acc: 687b ldr r3, [r7, #4] + 8006ace: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ad0: 2b06 cmp r3, #6 + 8006ad2: d003 beq.n 8006adc + 8006ad4: 687b ldr r3, [r7, #4] + 8006ad6: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ad8: 2b07 cmp r3, #7 + 8006ada: d112 bne.n 8006b02 + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + 8006adc: 687b ldr r3, [r7, #4] + 8006ade: 681b ldr r3, [r3, #0] + 8006ae0: 695a ldr r2, [r3, #20] + 8006ae2: 687b ldr r3, [r7, #4] + 8006ae4: 681b ldr r3, [r3, #0] + 8006ae6: 2107 movs r1, #7 + 8006ae8: 438a bics r2, r1 + 8006aea: 615a str r2, [r3, #20] + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); + 8006aec: 687b ldr r3, [r7, #4] + 8006aee: 681b ldr r3, [r3, #0] + 8006af0: 6959 ldr r1, [r3, #20] + 8006af2: 687b ldr r3, [r7, #4] + 8006af4: 6adb ldr r3, [r3, #44] @ 0x2c + 8006af6: 2207 movs r2, #7 + 8006af8: 401a ands r2, r3 + 8006afa: 687b ldr r3, [r7, #4] + 8006afc: 681b ldr r3, [r3, #0] + 8006afe: 430a orrs r2, r1 + 8006b00: 615a str r2, [r3, #20] + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmpCFGR1'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) + 8006b02: 687b ldr r3, [r7, #4] + 8006b04: 681b ldr r3, [r3, #0] + 8006b06: 68db ldr r3, [r3, #12] + 8006b08: 4a1c ldr r2, [pc, #112] @ (8006b7c ) + 8006b0a: 4013 ands r3, r2 + 8006b0c: 68ba ldr r2, [r7, #8] + 8006b0e: 429a cmp r2, r3 + 8006b10: d10b bne.n 8006b2a + == tmpCFGR1) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 8006b12: 687b ldr r3, [r7, #4] + 8006b14: 2200 movs r2, #0 + 8006b16: 63da str r2, [r3, #60] @ 0x3c + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8006b18: 687b ldr r3, [r7, #4] + 8006b1a: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006b1c: 2203 movs r2, #3 + 8006b1e: 4393 bics r3, r2 + 8006b20: 2201 movs r2, #1 + 8006b22: 431a orrs r2, r3 + 8006b24: 687b ldr r3, [r7, #4] + 8006b26: 639a str r2, [r3, #56] @ 0x38 + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) + 8006b28: e01c b.n 8006b64 + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + 8006b2a: 687b ldr r3, [r7, #4] + 8006b2c: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006b2e: 2212 movs r2, #18 + 8006b30: 4393 bics r3, r2 + 8006b32: 2210 movs r2, #16 + 8006b34: 431a orrs r2, r3 + 8006b36: 687b ldr r3, [r7, #4] + 8006b38: 639a str r2, [r3, #56] @ 0x38 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 8006b3a: 687b ldr r3, [r7, #4] + 8006b3c: 6bdb ldr r3, [r3, #60] @ 0x3c + 8006b3e: 2201 movs r2, #1 + 8006b40: 431a orrs r2, r3 + 8006b42: 687b ldr r3, [r7, #4] + 8006b44: 63da str r2, [r3, #60] @ 0x3c + + tmp_hal_status = HAL_ERROR; + 8006b46: 230f movs r3, #15 + 8006b48: 18fb adds r3, r7, r3 + 8006b4a: 2201 movs r2, #1 + 8006b4c: 701a strb r2, [r3, #0] + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) + 8006b4e: e009 b.n 8006b64 + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 8006b50: 687b ldr r3, [r7, #4] + 8006b52: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006b54: 2210 movs r2, #16 + 8006b56: 431a orrs r2, r3 + 8006b58: 687b ldr r3, [r7, #4] + 8006b5a: 639a str r2, [r3, #56] @ 0x38 + + tmp_hal_status = HAL_ERROR; + 8006b5c: 230f movs r3, #15 + 8006b5e: 18fb adds r3, r7, r3 + 8006b60: 2201 movs r2, #1 + 8006b62: 701a strb r2, [r3, #0] + } + + /* Return function status */ + return tmp_hal_status; + 8006b64: 230f movs r3, #15 + 8006b66: 18fb adds r3, r7, r3 + 8006b68: 781b ldrb r3, [r3, #0] +} + 8006b6a: 0018 movs r0, r3 + 8006b6c: 46bd mov sp, r7 + 8006b6e: b004 add sp, #16 + 8006b70: bd80 pop {r7, pc} + 8006b72: 46c0 nop @ (mov r8, r8) + 8006b74: fffffefd .word 0xfffffefd + 8006b78: fffe0219 .word 0xfffe0219 + 8006b7c: 833fffe7 .word 0x833fffe7 + +08006b80 : + * @param hadc ADC handle + * @param sConfig Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + 8006b80: b580 push {r7, lr} + 8006b82: b084 sub sp, #16 + 8006b84: af00 add r7, sp, #0 + 8006b86: 6078 str r0, [r7, #4] + 8006b88: 6039 str r1, [r7, #0] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 8006b8a: 230f movs r3, #15 + 8006b8c: 18fb adds r3, r7, r3 + 8006b8e: 2200 movs r2, #0 + 8006b90: 701a strb r2, [r3, #0] + __IO uint32_t wait_loop_index = 0U; + 8006b92: 2300 movs r3, #0 + 8006b94: 60bb str r3, [r7, #8] + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_RANK(sConfig->Rank)); + + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + 8006b96: 687b ldr r3, [r7, #4] + 8006b98: 6ada ldr r2, [r3, #44] @ 0x2c + 8006b9a: 2380 movs r3, #128 @ 0x80 + 8006b9c: 055b lsls r3, r3, #21 + 8006b9e: 429a cmp r2, r3 + 8006ba0: d011 beq.n 8006bc6 + 8006ba2: 687b ldr r3, [r7, #4] + 8006ba4: 6adb ldr r3, [r3, #44] @ 0x2c + 8006ba6: 2b01 cmp r3, #1 + 8006ba8: d00d beq.n 8006bc6 + 8006baa: 687b ldr r3, [r7, #4] + 8006bac: 6adb ldr r3, [r3, #44] @ 0x2c + 8006bae: 2b02 cmp r3, #2 + 8006bb0: d009 beq.n 8006bc6 + 8006bb2: 687b ldr r3, [r7, #4] + 8006bb4: 6adb ldr r3, [r3, #44] @ 0x2c + 8006bb6: 2b03 cmp r3, #3 + 8006bb8: d005 beq.n 8006bc6 + 8006bba: 687b ldr r3, [r7, #4] + 8006bbc: 6adb ldr r3, [r3, #44] @ 0x2c + 8006bbe: 2b04 cmp r3, #4 + 8006bc0: d001 beq.n 8006bc6 + 8006bc2: 687b ldr r3, [r7, #4] + 8006bc4: 6adb ldr r3, [r3, #44] @ 0x2c + { + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + 8006bc6: 687b ldr r3, [r7, #4] + 8006bc8: 2234 movs r2, #52 @ 0x34 + 8006bca: 5c9b ldrb r3, [r3, r2] + 8006bcc: 2b01 cmp r3, #1 + 8006bce: d101 bne.n 8006bd4 + 8006bd0: 2302 movs r3, #2 + 8006bd2: e0d0 b.n 8006d76 + 8006bd4: 687b ldr r3, [r7, #4] + 8006bd6: 2234 movs r2, #52 @ 0x34 + 8006bd8: 2101 movs r1, #1 + 8006bda: 5499 strb r1, [r3, r2] + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + 8006bdc: 687b ldr r3, [r7, #4] + 8006bde: 681b ldr r3, [r3, #0] + 8006be0: 689b ldr r3, [r3, #8] + 8006be2: 2204 movs r2, #4 + 8006be4: 4013 ands r3, r2 + 8006be6: d000 beq.n 8006bea + 8006be8: e0b4 b.n 8006d54 + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC conversion sequencer. */ + if (sConfig->Rank != ADC_RANK_NONE) + 8006bea: 683b ldr r3, [r7, #0] + 8006bec: 685b ldr r3, [r3, #4] + 8006bee: 4a64 ldr r2, [pc, #400] @ (8006d80 ) + 8006bf0: 4293 cmp r3, r2 + 8006bf2: d100 bne.n 8006bf6 + 8006bf4: e082 b.n 8006cfc + { + /* Regular sequence configuration */ + /* Set the channel selection register from the selected channel */ + hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); + 8006bf6: 687b ldr r3, [r7, #4] + 8006bf8: 681b ldr r3, [r3, #0] + 8006bfa: 6a99 ldr r1, [r3, #40] @ 0x28 + 8006bfc: 683b ldr r3, [r7, #0] + 8006bfe: 681b ldr r3, [r3, #0] + 8006c00: 2201 movs r2, #1 + 8006c02: 409a lsls r2, r3 + 8006c04: 687b ldr r3, [r7, #4] + 8006c06: 681b ldr r3, [r3, #0] + 8006c08: 430a orrs r2, r1 + 8006c0a: 629a str r2, [r3, #40] @ 0x28 + /* Channel sampling time configuration */ + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function with */ + /* parameter "SamplingTime" (obsolete) only if not already set into */ + /* ADC initialization structure with parameter "SamplingTimeCommon". */ + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + 8006c0c: 687b ldr r3, [r7, #4] + 8006c0e: 6ada ldr r2, [r3, #44] @ 0x2c + 8006c10: 2380 movs r3, #128 @ 0x80 + 8006c12: 055b lsls r3, r3, #21 + 8006c14: 429a cmp r2, r3 + 8006c16: d037 beq.n 8006c88 + 8006c18: 687b ldr r3, [r7, #4] + 8006c1a: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c1c: 2b01 cmp r3, #1 + 8006c1e: d033 beq.n 8006c88 + 8006c20: 687b ldr r3, [r7, #4] + 8006c22: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c24: 2b02 cmp r3, #2 + 8006c26: d02f beq.n 8006c88 + 8006c28: 687b ldr r3, [r7, #4] + 8006c2a: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c2c: 2b03 cmp r3, #3 + 8006c2e: d02b beq.n 8006c88 + 8006c30: 687b ldr r3, [r7, #4] + 8006c32: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c34: 2b04 cmp r3, #4 + 8006c36: d027 beq.n 8006c88 + 8006c38: 687b ldr r3, [r7, #4] + 8006c3a: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c3c: 2b05 cmp r3, #5 + 8006c3e: d023 beq.n 8006c88 + 8006c40: 687b ldr r3, [r7, #4] + 8006c42: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c44: 2b06 cmp r3, #6 + 8006c46: d01f beq.n 8006c88 + 8006c48: 687b ldr r3, [r7, #4] + 8006c4a: 6adb ldr r3, [r3, #44] @ 0x2c + 8006c4c: 2b07 cmp r3, #7 + 8006c4e: d01b beq.n 8006c88 + { + /* Modify sampling time if needed (not needed in case of reoccurrence */ + /* for several channels programmed consecutively into the sequencer) */ + if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) + 8006c50: 683b ldr r3, [r7, #0] + 8006c52: 689a ldr r2, [r3, #8] + 8006c54: 687b ldr r3, [r7, #4] + 8006c56: 681b ldr r3, [r3, #0] + 8006c58: 695b ldr r3, [r3, #20] + 8006c5a: 2107 movs r1, #7 + 8006c5c: 400b ands r3, r1 + 8006c5e: 429a cmp r2, r3 + 8006c60: d012 beq.n 8006c88 + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + 8006c62: 687b ldr r3, [r7, #4] + 8006c64: 681b ldr r3, [r3, #0] + 8006c66: 695a ldr r2, [r3, #20] + 8006c68: 687b ldr r3, [r7, #4] + 8006c6a: 681b ldr r3, [r3, #0] + 8006c6c: 2107 movs r1, #7 + 8006c6e: 438a bics r2, r1 + 8006c70: 615a str r2, [r3, #20] + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); + 8006c72: 687b ldr r3, [r7, #4] + 8006c74: 681b ldr r3, [r3, #0] + 8006c76: 6959 ldr r1, [r3, #20] + 8006c78: 683b ldr r3, [r7, #0] + 8006c7a: 689b ldr r3, [r3, #8] + 8006c7c: 2207 movs r2, #7 + 8006c7e: 401a ands r2, r3 + 8006c80: 687b ldr r3, [r7, #4] + 8006c82: 681b ldr r3, [r3, #0] + 8006c84: 430a orrs r2, r1 + 8006c86: 615a str r2, [r3, #20] + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + 8006c88: 683b ldr r3, [r7, #0] + 8006c8a: 681b ldr r3, [r3, #0] + 8006c8c: 2b10 cmp r3, #16 + 8006c8e: d007 beq.n 8006ca0 + 8006c90: 683b ldr r3, [r7, #0] + 8006c92: 681b ldr r3, [r3, #0] + 8006c94: 2b11 cmp r3, #17 + 8006c96: d003 beq.n 8006ca0 + 8006c98: 683b ldr r3, [r7, #0] + 8006c9a: 681b ldr r3, [r3, #0] + 8006c9c: 2b12 cmp r3, #18 + 8006c9e: d163 bne.n 8006d68 + { + /* If Channel_16 is selected, enable Temp. sensor measurement path. */ + /* If Channel_17 is selected, enable VREFINT measurement path. */ + /* If Channel_18 is selected, enable VBAT measurement path. */ + ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); + 8006ca0: 4b38 ldr r3, [pc, #224] @ (8006d84 ) + 8006ca2: 6819 ldr r1, [r3, #0] + 8006ca4: 683b ldr r3, [r7, #0] + 8006ca6: 681b ldr r3, [r3, #0] + 8006ca8: 2b10 cmp r3, #16 + 8006caa: d009 beq.n 8006cc0 + 8006cac: 683b ldr r3, [r7, #0] + 8006cae: 681b ldr r3, [r3, #0] + 8006cb0: 2b11 cmp r3, #17 + 8006cb2: d102 bne.n 8006cba + 8006cb4: 2380 movs r3, #128 @ 0x80 + 8006cb6: 03db lsls r3, r3, #15 + 8006cb8: e004 b.n 8006cc4 + 8006cba: 2380 movs r3, #128 @ 0x80 + 8006cbc: 045b lsls r3, r3, #17 + 8006cbe: e001 b.n 8006cc4 + 8006cc0: 2380 movs r3, #128 @ 0x80 + 8006cc2: 041b lsls r3, r3, #16 + 8006cc4: 4a2f ldr r2, [pc, #188] @ (8006d84 ) + 8006cc6: 430b orrs r3, r1 + 8006cc8: 6013 str r3, [r2, #0] + + /* If Temp. sensor is selected, wait for stabilization delay */ + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 8006cca: 683b ldr r3, [r7, #0] + 8006ccc: 681b ldr r3, [r3, #0] + 8006cce: 2b10 cmp r3, #16 + 8006cd0: d14a bne.n 8006d68 + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + 8006cd2: 4b2d ldr r3, [pc, #180] @ (8006d88 ) + 8006cd4: 681b ldr r3, [r3, #0] + 8006cd6: 492d ldr r1, [pc, #180] @ (8006d8c ) + 8006cd8: 0018 movs r0, r3 + 8006cda: f7f9 fa15 bl 8000108 <__udivsi3> + 8006cde: 0003 movs r3, r0 + 8006ce0: 001a movs r2, r3 + 8006ce2: 0013 movs r3, r2 + 8006ce4: 009b lsls r3, r3, #2 + 8006ce6: 189b adds r3, r3, r2 + 8006ce8: 005b lsls r3, r3, #1 + 8006cea: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 8006cec: e002 b.n 8006cf4 + { + wait_loop_index--; + 8006cee: 68bb ldr r3, [r7, #8] + 8006cf0: 3b01 subs r3, #1 + 8006cf2: 60bb str r3, [r7, #8] + while(wait_loop_index != 0U) + 8006cf4: 68bb ldr r3, [r7, #8] + 8006cf6: 2b00 cmp r3, #0 + 8006cf8: d1f9 bne.n 8006cee + 8006cfa: e035 b.n 8006d68 + } + else + { + /* Regular sequence configuration */ + /* Reset the channel selection register from the selected channel */ + hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); + 8006cfc: 687b ldr r3, [r7, #4] + 8006cfe: 681b ldr r3, [r3, #0] + 8006d00: 6a9a ldr r2, [r3, #40] @ 0x28 + 8006d02: 683b ldr r3, [r7, #0] + 8006d04: 681b ldr r3, [r3, #0] + 8006d06: 2101 movs r1, #1 + 8006d08: 4099 lsls r1, r3 + 8006d0a: 000b movs r3, r1 + 8006d0c: 43d9 mvns r1, r3 + 8006d0e: 687b ldr r3, [r7, #4] + 8006d10: 681b ldr r3, [r3, #0] + 8006d12: 400a ands r2, r1 + 8006d14: 629a str r2, [r3, #40] @ 0x28 + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths disable: If internal channel selected, */ + /* disable dedicated internal buffers and path. */ + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + 8006d16: 683b ldr r3, [r7, #0] + 8006d18: 681b ldr r3, [r3, #0] + 8006d1a: 2b10 cmp r3, #16 + 8006d1c: d007 beq.n 8006d2e + 8006d1e: 683b ldr r3, [r7, #0] + 8006d20: 681b ldr r3, [r3, #0] + 8006d22: 2b11 cmp r3, #17 + 8006d24: d003 beq.n 8006d2e + 8006d26: 683b ldr r3, [r7, #0] + 8006d28: 681b ldr r3, [r3, #0] + 8006d2a: 2b12 cmp r3, #18 + 8006d2c: d11c bne.n 8006d68 + { + /* If Channel_16 is selected, disable Temp. sensor measurement path. */ + /* If Channel_17 is selected, disable VREFINT measurement path. */ + /* If Channel_18 is selected, disable VBAT measurement path. */ + ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); + 8006d2e: 4b15 ldr r3, [pc, #84] @ (8006d84 ) + 8006d30: 6819 ldr r1, [r3, #0] + 8006d32: 683b ldr r3, [r7, #0] + 8006d34: 681b ldr r3, [r3, #0] + 8006d36: 2b10 cmp r3, #16 + 8006d38: d007 beq.n 8006d4a + 8006d3a: 683b ldr r3, [r7, #0] + 8006d3c: 681b ldr r3, [r3, #0] + 8006d3e: 2b11 cmp r3, #17 + 8006d40: d101 bne.n 8006d46 + 8006d42: 4b13 ldr r3, [pc, #76] @ (8006d90 ) + 8006d44: e002 b.n 8006d4c + 8006d46: 4b13 ldr r3, [pc, #76] @ (8006d94 ) + 8006d48: e000 b.n 8006d4c + 8006d4a: 4b13 ldr r3, [pc, #76] @ (8006d98 ) + 8006d4c: 4a0d ldr r2, [pc, #52] @ (8006d84 ) + 8006d4e: 400b ands r3, r1 + 8006d50: 6013 str r3, [r2, #0] + 8006d52: e009 b.n 8006d68 + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 8006d54: 687b ldr r3, [r7, #4] + 8006d56: 6b9b ldr r3, [r3, #56] @ 0x38 + 8006d58: 2220 movs r2, #32 + 8006d5a: 431a orrs r2, r3 + 8006d5c: 687b ldr r3, [r7, #4] + 8006d5e: 639a str r2, [r3, #56] @ 0x38 + + tmp_hal_status = HAL_ERROR; + 8006d60: 230f movs r3, #15 + 8006d62: 18fb adds r3, r7, r3 + 8006d64: 2201 movs r2, #1 + 8006d66: 701a strb r2, [r3, #0] + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8006d68: 687b ldr r3, [r7, #4] + 8006d6a: 2234 movs r2, #52 @ 0x34 + 8006d6c: 2100 movs r1, #0 + 8006d6e: 5499 strb r1, [r3, r2] + + /* Return function status */ + return tmp_hal_status; + 8006d70: 230f movs r3, #15 + 8006d72: 18fb adds r3, r7, r3 + 8006d74: 781b ldrb r3, [r3, #0] +} + 8006d76: 0018 movs r0, r3 + 8006d78: 46bd mov sp, r7 + 8006d7a: b004 add sp, #16 + 8006d7c: bd80 pop {r7, pc} + 8006d7e: 46c0 nop @ (mov r8, r8) + 8006d80: 00001001 .word 0x00001001 + 8006d84: 40012708 .word 0x40012708 + 8006d88: 20000004 .word 0x20000004 + 8006d8c: 000f4240 .word 0x000f4240 + 8006d90: ffbfffff .word 0xffbfffff + 8006d94: feffffff .word 0xfeffffff + 8006d98: ff7fffff .word 0xff7fffff + +08006d9c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8006d9c: b590 push {r4, r7, lr} + 8006d9e: b083 sub sp, #12 + 8006da0: af00 add r7, sp, #0 + 8006da2: 0002 movs r2, r0 + 8006da4: 6039 str r1, [r7, #0] + 8006da6: 1dfb adds r3, r7, #7 + 8006da8: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) >= 0) + 8006daa: 1dfb adds r3, r7, #7 + 8006dac: 781b ldrb r3, [r3, #0] + 8006dae: 2b7f cmp r3, #127 @ 0x7f + 8006db0: d828 bhi.n 8006e04 <__NVIC_SetPriority+0x68> + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8006db2: 4a2f ldr r2, [pc, #188] @ (8006e70 <__NVIC_SetPriority+0xd4>) + 8006db4: 1dfb adds r3, r7, #7 + 8006db6: 781b ldrb r3, [r3, #0] + 8006db8: b25b sxtb r3, r3 + 8006dba: 089b lsrs r3, r3, #2 + 8006dbc: 33c0 adds r3, #192 @ 0xc0 + 8006dbe: 009b lsls r3, r3, #2 + 8006dc0: 589b ldr r3, [r3, r2] + 8006dc2: 1dfa adds r2, r7, #7 + 8006dc4: 7812 ldrb r2, [r2, #0] + 8006dc6: 0011 movs r1, r2 + 8006dc8: 2203 movs r2, #3 + 8006dca: 400a ands r2, r1 + 8006dcc: 00d2 lsls r2, r2, #3 + 8006dce: 21ff movs r1, #255 @ 0xff + 8006dd0: 4091 lsls r1, r2 + 8006dd2: 000a movs r2, r1 + 8006dd4: 43d2 mvns r2, r2 + 8006dd6: 401a ands r2, r3 + 8006dd8: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8006dda: 683b ldr r3, [r7, #0] + 8006ddc: 019b lsls r3, r3, #6 + 8006dde: 22ff movs r2, #255 @ 0xff + 8006de0: 401a ands r2, r3 + 8006de2: 1dfb adds r3, r7, #7 + 8006de4: 781b ldrb r3, [r3, #0] + 8006de6: 0018 movs r0, r3 + 8006de8: 2303 movs r3, #3 + 8006dea: 4003 ands r3, r0 + 8006dec: 00db lsls r3, r3, #3 + 8006dee: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8006df0: 481f ldr r0, [pc, #124] @ (8006e70 <__NVIC_SetPriority+0xd4>) + 8006df2: 1dfb adds r3, r7, #7 + 8006df4: 781b ldrb r3, [r3, #0] + 8006df6: b25b sxtb r3, r3 + 8006df8: 089b lsrs r3, r3, #2 + 8006dfa: 430a orrs r2, r1 + 8006dfc: 33c0 adds r3, #192 @ 0xc0 + 8006dfe: 009b lsls r3, r3, #2 + 8006e00: 501a str r2, [r3, r0] + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + 8006e02: e031 b.n 8006e68 <__NVIC_SetPriority+0xcc> + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8006e04: 4a1b ldr r2, [pc, #108] @ (8006e74 <__NVIC_SetPriority+0xd8>) + 8006e06: 1dfb adds r3, r7, #7 + 8006e08: 781b ldrb r3, [r3, #0] + 8006e0a: 0019 movs r1, r3 + 8006e0c: 230f movs r3, #15 + 8006e0e: 400b ands r3, r1 + 8006e10: 3b08 subs r3, #8 + 8006e12: 089b lsrs r3, r3, #2 + 8006e14: 3306 adds r3, #6 + 8006e16: 009b lsls r3, r3, #2 + 8006e18: 18d3 adds r3, r2, r3 + 8006e1a: 3304 adds r3, #4 + 8006e1c: 681b ldr r3, [r3, #0] + 8006e1e: 1dfa adds r2, r7, #7 + 8006e20: 7812 ldrb r2, [r2, #0] + 8006e22: 0011 movs r1, r2 + 8006e24: 2203 movs r2, #3 + 8006e26: 400a ands r2, r1 + 8006e28: 00d2 lsls r2, r2, #3 + 8006e2a: 21ff movs r1, #255 @ 0xff + 8006e2c: 4091 lsls r1, r2 + 8006e2e: 000a movs r2, r1 + 8006e30: 43d2 mvns r2, r2 + 8006e32: 401a ands r2, r3 + 8006e34: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8006e36: 683b ldr r3, [r7, #0] + 8006e38: 019b lsls r3, r3, #6 + 8006e3a: 22ff movs r2, #255 @ 0xff + 8006e3c: 401a ands r2, r3 + 8006e3e: 1dfb adds r3, r7, #7 + 8006e40: 781b ldrb r3, [r3, #0] + 8006e42: 0018 movs r0, r3 + 8006e44: 2303 movs r3, #3 + 8006e46: 4003 ands r3, r0 + 8006e48: 00db lsls r3, r3, #3 + 8006e4a: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8006e4c: 4809 ldr r0, [pc, #36] @ (8006e74 <__NVIC_SetPriority+0xd8>) + 8006e4e: 1dfb adds r3, r7, #7 + 8006e50: 781b ldrb r3, [r3, #0] + 8006e52: 001c movs r4, r3 + 8006e54: 230f movs r3, #15 + 8006e56: 4023 ands r3, r4 + 8006e58: 3b08 subs r3, #8 + 8006e5a: 089b lsrs r3, r3, #2 + 8006e5c: 430a orrs r2, r1 + 8006e5e: 3306 adds r3, #6 + 8006e60: 009b lsls r3, r3, #2 + 8006e62: 18c3 adds r3, r0, r3 + 8006e64: 3304 adds r3, #4 + 8006e66: 601a str r2, [r3, #0] +} + 8006e68: 46c0 nop @ (mov r8, r8) + 8006e6a: 46bd mov sp, r7 + 8006e6c: b003 add sp, #12 + 8006e6e: bd90 pop {r4, r7, pc} + 8006e70: e000e100 .word 0xe000e100 + 8006e74: e000ed00 .word 0xe000ed00 + +08006e78 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8006e78: b580 push {r7, lr} + 8006e7a: b082 sub sp, #8 + 8006e7c: af00 add r7, sp, #0 + 8006e7e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8006e80: 687b ldr r3, [r7, #4] + 8006e82: 1e5a subs r2, r3, #1 + 8006e84: 2380 movs r3, #128 @ 0x80 + 8006e86: 045b lsls r3, r3, #17 + 8006e88: 429a cmp r2, r3 + 8006e8a: d301 bcc.n 8006e90 + { + return (1UL); /* Reload value impossible */ + 8006e8c: 2301 movs r3, #1 + 8006e8e: e010 b.n 8006eb2 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8006e90: 4b0a ldr r3, [pc, #40] @ (8006ebc ) + 8006e92: 687a ldr r2, [r7, #4] + 8006e94: 3a01 subs r2, #1 + 8006e96: 605a str r2, [r3, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8006e98: 2301 movs r3, #1 + 8006e9a: 425b negs r3, r3 + 8006e9c: 2103 movs r1, #3 + 8006e9e: 0018 movs r0, r3 + 8006ea0: f7ff ff7c bl 8006d9c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8006ea4: 4b05 ldr r3, [pc, #20] @ (8006ebc ) + 8006ea6: 2200 movs r2, #0 + 8006ea8: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8006eaa: 4b04 ldr r3, [pc, #16] @ (8006ebc ) + 8006eac: 2207 movs r2, #7 + 8006eae: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8006eb0: 2300 movs r3, #0 +} + 8006eb2: 0018 movs r0, r3 + 8006eb4: 46bd mov sp, r7 + 8006eb6: b002 add sp, #8 + 8006eb8: bd80 pop {r7, pc} + 8006eba: 46c0 nop @ (mov r8, r8) + 8006ebc: e000e010 .word 0xe000e010 + +08006ec0 : + * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0 based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8006ec0: b580 push {r7, lr} + 8006ec2: b084 sub sp, #16 + 8006ec4: af00 add r7, sp, #0 + 8006ec6: 60b9 str r1, [r7, #8] + 8006ec8: 607a str r2, [r7, #4] + 8006eca: 210f movs r1, #15 + 8006ecc: 187b adds r3, r7, r1 + 8006ece: 1c02 adds r2, r0, #0 + 8006ed0: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); + 8006ed2: 68ba ldr r2, [r7, #8] + 8006ed4: 187b adds r3, r7, r1 + 8006ed6: 781b ldrb r3, [r3, #0] + 8006ed8: b25b sxtb r3, r3 + 8006eda: 0011 movs r1, r2 + 8006edc: 0018 movs r0, r3 + 8006ede: f7ff ff5d bl 8006d9c <__NVIC_SetPriority> +} + 8006ee2: 46c0 nop @ (mov r8, r8) + 8006ee4: 46bd mov sp, r7 + 8006ee6: b004 add sp, #16 + 8006ee8: bd80 pop {r7, pc} + +08006eea : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8006eea: b580 push {r7, lr} + 8006eec: b082 sub sp, #8 + 8006eee: af00 add r7, sp, #0 + 8006ef0: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8006ef2: 687b ldr r3, [r7, #4] + 8006ef4: 0018 movs r0, r3 + 8006ef6: f7ff ffbf bl 8006e78 + 8006efa: 0003 movs r3, r0 +} + 8006efc: 0018 movs r0, r3 + 8006efe: 46bd mov sp, r7 + 8006f00: b002 add sp, #8 + 8006f02: bd80 pop {r7, pc} + +08006f04 : + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + 8006f04: b5f0 push {r4, r5, r6, r7, lr} + 8006f06: b087 sub sp, #28 + 8006f08: af00 add r7, sp, #0 + 8006f0a: 60f8 str r0, [r7, #12] + 8006f0c: 60b9 str r1, [r7, #8] + 8006f0e: 603a str r2, [r7, #0] + 8006f10: 607b str r3, [r7, #4] + HAL_StatusTypeDef status = HAL_ERROR; + 8006f12: 2317 movs r3, #23 + 8006f14: 18fb adds r3, r7, r3 + 8006f16: 2201 movs r2, #1 + 8006f18: 701a strb r2, [r3, #0] + uint8_t index = 0U; + 8006f1a: 2316 movs r3, #22 + 8006f1c: 18fb adds r3, r7, r3 + 8006f1e: 2200 movs r2, #0 + 8006f20: 701a strb r2, [r3, #0] + uint8_t nbiterations = 0U; + 8006f22: 2315 movs r3, #21 + 8006f24: 18fb adds r3, r7, r3 + 8006f26: 2200 movs r2, #0 + 8006f28: 701a strb r2, [r3, #0] + + /* Process Locked */ + __HAL_LOCK(&pFlash); + 8006f2a: 4b3e ldr r3, [pc, #248] @ (8007024 ) + 8006f2c: 7e1b ldrb r3, [r3, #24] + 8006f2e: 2b01 cmp r3, #1 + 8006f30: d101 bne.n 8006f36 + 8006f32: 2302 movs r3, #2 + 8006f34: e072 b.n 800701c + 8006f36: 4b3b ldr r3, [pc, #236] @ (8007024 ) + 8006f38: 2201 movs r2, #1 + 8006f3a: 761a strb r2, [r3, #24] + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 8006f3c: 2317 movs r3, #23 + 8006f3e: 18fe adds r6, r7, r3 + 8006f40: 4b39 ldr r3, [pc, #228] @ (8007028 ) + 8006f42: 0018 movs r0, r3 + 8006f44: f000 f8c4 bl 80070d0 + 8006f48: 0003 movs r3, r0 + 8006f4a: 7033 strb r3, [r6, #0] + + if(status == HAL_OK) + 8006f4c: 2317 movs r3, #23 + 8006f4e: 18fb adds r3, r7, r3 + 8006f50: 781b ldrb r3, [r3, #0] + 8006f52: 2b00 cmp r3, #0 + 8006f54: d15c bne.n 8007010 + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + 8006f56: 68fb ldr r3, [r7, #12] + 8006f58: 2b01 cmp r3, #1 + 8006f5a: d104 bne.n 8006f66 + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + 8006f5c: 2315 movs r3, #21 + 8006f5e: 18fb adds r3, r7, r3 + 8006f60: 2201 movs r2, #1 + 8006f62: 701a strb r2, [r3, #0] + 8006f64: e00b b.n 8006f7e + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 8006f66: 68fb ldr r3, [r7, #12] + 8006f68: 2b02 cmp r3, #2 + 8006f6a: d104 bne.n 8006f76 + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + 8006f6c: 2315 movs r3, #21 + 8006f6e: 18fb adds r3, r7, r3 + 8006f70: 2202 movs r2, #2 + 8006f72: 701a strb r2, [r3, #0] + 8006f74: e003 b.n 8006f7e + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + 8006f76: 2315 movs r3, #21 + 8006f78: 18fb adds r3, r7, r3 + 8006f7a: 2204 movs r2, #4 + 8006f7c: 701a strb r2, [r3, #0] + } + + for (index = 0U; index < nbiterations; index++) + 8006f7e: 2316 movs r3, #22 + 8006f80: 18fb adds r3, r7, r3 + 8006f82: 2200 movs r2, #0 + 8006f84: 701a strb r2, [r3, #0] + 8006f86: e039 b.n 8006ffc + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + 8006f88: 2116 movs r1, #22 + 8006f8a: 187b adds r3, r7, r1 + 8006f8c: 781b ldrb r3, [r3, #0] + 8006f8e: 005a lsls r2, r3, #1 + 8006f90: 68bb ldr r3, [r7, #8] + 8006f92: 18d0 adds r0, r2, r3 + 8006f94: 187b adds r3, r7, r1 + 8006f96: 781b ldrb r3, [r3, #0] + 8006f98: 011b lsls r3, r3, #4 + 8006f9a: 001a movs r2, r3 + 8006f9c: 3a20 subs r2, #32 + 8006f9e: 2a00 cmp r2, #0 + 8006fa0: db03 blt.n 8006faa + 8006fa2: 6879 ldr r1, [r7, #4] + 8006fa4: 40d1 lsrs r1, r2 + 8006fa6: 000c movs r4, r1 + 8006fa8: e008 b.n 8006fbc + 8006faa: 2220 movs r2, #32 + 8006fac: 1ad2 subs r2, r2, r3 + 8006fae: 6879 ldr r1, [r7, #4] + 8006fb0: 4091 lsls r1, r2 + 8006fb2: 000a movs r2, r1 + 8006fb4: 6839 ldr r1, [r7, #0] + 8006fb6: 40d9 lsrs r1, r3 + 8006fb8: 000c movs r4, r1 + 8006fba: 4314 orrs r4, r2 + 8006fbc: 687a ldr r2, [r7, #4] + 8006fbe: 40da lsrs r2, r3 + 8006fc0: 0015 movs r5, r2 + 8006fc2: b2a3 uxth r3, r4 + 8006fc4: 0019 movs r1, r3 + 8006fc6: f000 f867 bl 8007098 + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 8006fca: 2317 movs r3, #23 + 8006fcc: 18fe adds r6, r7, r3 + 8006fce: 4b16 ldr r3, [pc, #88] @ (8007028 ) + 8006fd0: 0018 movs r0, r3 + 8006fd2: f000 f87d bl 80070d0 + 8006fd6: 0003 movs r3, r0 + 8006fd8: 7033 strb r3, [r6, #0] + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + 8006fda: 4b14 ldr r3, [pc, #80] @ (800702c ) + 8006fdc: 691a ldr r2, [r3, #16] + 8006fde: 4b13 ldr r3, [pc, #76] @ (800702c ) + 8006fe0: 2101 movs r1, #1 + 8006fe2: 438a bics r2, r1 + 8006fe4: 611a str r2, [r3, #16] + /* In case of error, stop programming procedure */ + if (status != HAL_OK) + 8006fe6: 2317 movs r3, #23 + 8006fe8: 18fb adds r3, r7, r3 + 8006fea: 781b ldrb r3, [r3, #0] + 8006fec: 2b00 cmp r3, #0 + 8006fee: d10e bne.n 800700e + for (index = 0U; index < nbiterations; index++) + 8006ff0: 2116 movs r1, #22 + 8006ff2: 187b adds r3, r7, r1 + 8006ff4: 781a ldrb r2, [r3, #0] + 8006ff6: 187b adds r3, r7, r1 + 8006ff8: 3201 adds r2, #1 + 8006ffa: 701a strb r2, [r3, #0] + 8006ffc: 2316 movs r3, #22 + 8006ffe: 18fa adds r2, r7, r3 + 8007000: 2315 movs r3, #21 + 8007002: 18fb adds r3, r7, r3 + 8007004: 7812 ldrb r2, [r2, #0] + 8007006: 781b ldrb r3, [r3, #0] + 8007008: 429a cmp r2, r3 + 800700a: d3bd bcc.n 8006f88 + 800700c: e000 b.n 8007010 + { + break; + 800700e: 46c0 nop @ (mov r8, r8) + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + 8007010: 4b04 ldr r3, [pc, #16] @ (8007024 ) + 8007012: 2200 movs r2, #0 + 8007014: 761a strb r2, [r3, #24] + + return status; + 8007016: 2317 movs r3, #23 + 8007018: 18fb adds r3, r7, r3 + 800701a: 781b ldrb r3, [r3, #0] +} + 800701c: 0018 movs r0, r3 + 800701e: 46bd mov sp, r7 + 8007020: b007 add sp, #28 + 8007022: bdf0 pop {r4, r5, r6, r7, pc} + 8007024: 20000db0 .word 0x20000db0 + 8007028: 0000c350 .word 0x0000c350 + 800702c: 40022000 .word 0x40022000 + +08007030 : +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + 8007030: b580 push {r7, lr} + 8007032: b082 sub sp, #8 + 8007034: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8007036: 1dfb adds r3, r7, #7 + 8007038: 2200 movs r2, #0 + 800703a: 701a strb r2, [r3, #0] + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 800703c: 4b0c ldr r3, [pc, #48] @ (8007070 ) + 800703e: 691b ldr r3, [r3, #16] + 8007040: 2280 movs r2, #128 @ 0x80 + 8007042: 4013 ands r3, r2 + 8007044: d00d beq.n 8007062 + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + 8007046: 4b0a ldr r3, [pc, #40] @ (8007070 ) + 8007048: 4a0a ldr r2, [pc, #40] @ (8007074 ) + 800704a: 605a str r2, [r3, #4] + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 800704c: 4b08 ldr r3, [pc, #32] @ (8007070 ) + 800704e: 4a0a ldr r2, [pc, #40] @ (8007078 ) + 8007050: 605a str r2, [r3, #4] + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 8007052: 4b07 ldr r3, [pc, #28] @ (8007070 ) + 8007054: 691b ldr r3, [r3, #16] + 8007056: 2280 movs r2, #128 @ 0x80 + 8007058: 4013 ands r3, r2 + 800705a: d002 beq.n 8007062 + { + status = HAL_ERROR; + 800705c: 1dfb adds r3, r7, #7 + 800705e: 2201 movs r2, #1 + 8007060: 701a strb r2, [r3, #0] + } + } + + return status; + 8007062: 1dfb adds r3, r7, #7 + 8007064: 781b ldrb r3, [r3, #0] +} + 8007066: 0018 movs r0, r3 + 8007068: 46bd mov sp, r7 + 800706a: b002 add sp, #8 + 800706c: bd80 pop {r7, pc} + 800706e: 46c0 nop @ (mov r8, r8) + 8007070: 40022000 .word 0x40022000 + 8007074: 45670123 .word 0x45670123 + 8007078: cdef89ab .word 0xcdef89ab + +0800707c : +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + 800707c: b580 push {r7, lr} + 800707e: af00 add r7, sp, #0 + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + 8007080: 4b04 ldr r3, [pc, #16] @ (8007094 ) + 8007082: 691a ldr r2, [r3, #16] + 8007084: 4b03 ldr r3, [pc, #12] @ (8007094 ) + 8007086: 2180 movs r1, #128 @ 0x80 + 8007088: 430a orrs r2, r1 + 800708a: 611a str r2, [r3, #16] + + return HAL_OK; + 800708c: 2300 movs r3, #0 +} + 800708e: 0018 movs r0, r3 + 8007090: 46bd mov sp, r7 + 8007092: bd80 pop {r7, pc} + 8007094: 40022000 .word 0x40022000 + +08007098 : + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + 8007098: b580 push {r7, lr} + 800709a: b082 sub sp, #8 + 800709c: af00 add r7, sp, #0 + 800709e: 6078 str r0, [r7, #4] + 80070a0: 000a movs r2, r1 + 80070a2: 1cbb adds r3, r7, #2 + 80070a4: 801a strh r2, [r3, #0] + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 80070a6: 4b08 ldr r3, [pc, #32] @ (80070c8 ) + 80070a8: 2200 movs r2, #0 + 80070aa: 61da str r2, [r3, #28] + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + 80070ac: 4b07 ldr r3, [pc, #28] @ (80070cc ) + 80070ae: 691a ldr r2, [r3, #16] + 80070b0: 4b06 ldr r3, [pc, #24] @ (80070cc ) + 80070b2: 2101 movs r1, #1 + 80070b4: 430a orrs r2, r1 + 80070b6: 611a str r2, [r3, #16] + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; + 80070b8: 687b ldr r3, [r7, #4] + 80070ba: 1cba adds r2, r7, #2 + 80070bc: 8812 ldrh r2, [r2, #0] + 80070be: 801a strh r2, [r3, #0] +} + 80070c0: 46c0 nop @ (mov r8, r8) + 80070c2: 46bd mov sp, r7 + 80070c4: b002 add sp, #8 + 80070c6: bd80 pop {r7, pc} + 80070c8: 20000db0 .word 0x20000db0 + 80070cc: 40022000 .word 0x40022000 + +080070d0 : + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + 80070d0: b580 push {r7, lr} + 80070d2: b084 sub sp, #16 + 80070d4: af00 add r7, sp, #0 + 80070d6: 6078 str r0, [r7, #4] + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + 80070d8: f7ff fc08 bl 80068ec + 80070dc: 0003 movs r3, r0 + 80070de: 60fb str r3, [r7, #12] + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + 80070e0: e00f b.n 8007102 + { + if (Timeout != HAL_MAX_DELAY) + 80070e2: 687b ldr r3, [r7, #4] + 80070e4: 3301 adds r3, #1 + 80070e6: d00c beq.n 8007102 + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 80070e8: 687b ldr r3, [r7, #4] + 80070ea: 2b00 cmp r3, #0 + 80070ec: d007 beq.n 80070fe + 80070ee: f7ff fbfd bl 80068ec + 80070f2: 0002 movs r2, r0 + 80070f4: 68fb ldr r3, [r7, #12] + 80070f6: 1ad3 subs r3, r2, r3 + 80070f8: 687a ldr r2, [r7, #4] + 80070fa: 429a cmp r2, r3 + 80070fc: d201 bcs.n 8007102 + { + return HAL_TIMEOUT; + 80070fe: 2303 movs r3, #3 + 8007100: e01f b.n 8007142 + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + 8007102: 4b12 ldr r3, [pc, #72] @ (800714c ) + 8007104: 68db ldr r3, [r3, #12] + 8007106: 2201 movs r2, #1 + 8007108: 4013 ands r3, r2 + 800710a: 2b01 cmp r3, #1 + 800710c: d0e9 beq.n 80070e2 + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 800710e: 4b0f ldr r3, [pc, #60] @ (800714c ) + 8007110: 68db ldr r3, [r3, #12] + 8007112: 2220 movs r2, #32 + 8007114: 4013 ands r3, r2 + 8007116: 2b20 cmp r3, #32 + 8007118: d102 bne.n 8007120 + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 800711a: 4b0c ldr r3, [pc, #48] @ (800714c ) + 800711c: 2220 movs r2, #32 + 800711e: 60da str r2, [r3, #12] + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 8007120: 4b0a ldr r3, [pc, #40] @ (800714c ) + 8007122: 68db ldr r3, [r3, #12] + 8007124: 2210 movs r2, #16 + 8007126: 4013 ands r3, r2 + 8007128: 2b10 cmp r3, #16 + 800712a: d005 beq.n 8007138 + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 800712c: 4b07 ldr r3, [pc, #28] @ (800714c ) + 800712e: 68db ldr r3, [r3, #12] + 8007130: 2204 movs r2, #4 + 8007132: 4013 ands r3, r2 + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 8007134: 2b04 cmp r3, #4 + 8007136: d103 bne.n 8007140 + { + /*Save the error code*/ + FLASH_SetErrorCode(); + 8007138: f000 f80a bl 8007150 + return HAL_ERROR; + 800713c: 2301 movs r3, #1 + 800713e: e000 b.n 8007142 + } + + /* There is no error flag set */ + return HAL_OK; + 8007140: 2300 movs r3, #0 +} + 8007142: 0018 movs r0, r3 + 8007144: 46bd mov sp, r7 + 8007146: b004 add sp, #16 + 8007148: bd80 pop {r7, pc} + 800714a: 46c0 nop @ (mov r8, r8) + 800714c: 40022000 .word 0x40022000 + +08007150 : +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + 8007150: b580 push {r7, lr} + 8007152: b082 sub sp, #8 + 8007154: af00 add r7, sp, #0 + uint32_t flags = 0U; + 8007156: 2300 movs r3, #0 + 8007158: 607b str r3, [r7, #4] + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + 800715a: 4b13 ldr r3, [pc, #76] @ (80071a8 ) + 800715c: 68db ldr r3, [r3, #12] + 800715e: 2210 movs r2, #16 + 8007160: 4013 ands r3, r2 + 8007162: 2b10 cmp r3, #16 + 8007164: d109 bne.n 800717a + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 8007166: 4b11 ldr r3, [pc, #68] @ (80071ac ) + 8007168: 69db ldr r3, [r3, #28] + 800716a: 2202 movs r2, #2 + 800716c: 431a orrs r2, r3 + 800716e: 4b0f ldr r3, [pc, #60] @ (80071ac ) + 8007170: 61da str r2, [r3, #28] + flags |= FLASH_FLAG_WRPERR; + 8007172: 687b ldr r3, [r7, #4] + 8007174: 2210 movs r2, #16 + 8007176: 4313 orrs r3, r2 + 8007178: 607b str r3, [r7, #4] + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 800717a: 4b0b ldr r3, [pc, #44] @ (80071a8 ) + 800717c: 68db ldr r3, [r3, #12] + 800717e: 2204 movs r2, #4 + 8007180: 4013 ands r3, r2 + 8007182: 2b04 cmp r3, #4 + 8007184: d109 bne.n 800719a + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + 8007186: 4b09 ldr r3, [pc, #36] @ (80071ac ) + 8007188: 69db ldr r3, [r3, #28] + 800718a: 2201 movs r2, #1 + 800718c: 431a orrs r2, r3 + 800718e: 4b07 ldr r3, [pc, #28] @ (80071ac ) + 8007190: 61da str r2, [r3, #28] + flags |= FLASH_FLAG_PGERR; + 8007192: 687b ldr r3, [r7, #4] + 8007194: 2204 movs r2, #4 + 8007196: 4313 orrs r3, r2 + 8007198: 607b str r3, [r7, #4] + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); + 800719a: 4b03 ldr r3, [pc, #12] @ (80071a8 ) + 800719c: 687a ldr r2, [r7, #4] + 800719e: 60da str r2, [r3, #12] +} + 80071a0: 46c0 nop @ (mov r8, r8) + 80071a2: 46bd mov sp, r7 + 80071a4: b002 add sp, #8 + 80071a6: bd80 pop {r7, pc} + 80071a8: 40022000 .word 0x40022000 + 80071ac: 20000db0 .word 0x20000db0 + +080071b0 : + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + 80071b0: b5b0 push {r4, r5, r7, lr} + 80071b2: b084 sub sp, #16 + 80071b4: af00 add r7, sp, #0 + 80071b6: 6078 str r0, [r7, #4] + 80071b8: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_ERROR; + 80071ba: 230f movs r3, #15 + 80071bc: 18fb adds r3, r7, r3 + 80071be: 2201 movs r2, #1 + 80071c0: 701a strb r2, [r3, #0] + uint32_t address = 0U; + 80071c2: 2300 movs r3, #0 + 80071c4: 60bb str r3, [r7, #8] + + /* Process Locked */ + __HAL_LOCK(&pFlash); + 80071c6: 4b32 ldr r3, [pc, #200] @ (8007290 ) + 80071c8: 7e1b ldrb r3, [r3, #24] + 80071ca: 2b01 cmp r3, #1 + 80071cc: d101 bne.n 80071d2 + 80071ce: 2302 movs r3, #2 + 80071d0: e05a b.n 8007288 + 80071d2: 4b2f ldr r3, [pc, #188] @ (8007290 ) + 80071d4: 2201 movs r2, #1 + 80071d6: 761a strb r2, [r3, #24] + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 80071d8: 687b ldr r3, [r7, #4] + 80071da: 681b ldr r3, [r3, #0] + 80071dc: 2b01 cmp r3, #1 + 80071de: d116 bne.n 800720e + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 80071e0: 4b2c ldr r3, [pc, #176] @ (8007294 ) + 80071e2: 0018 movs r0, r3 + 80071e4: f7ff ff74 bl 80070d0 + 80071e8: 1e03 subs r3, r0, #0 + 80071ea: d147 bne.n 800727c + { + /*Mass erase to be done*/ + FLASH_MassErase(); + 80071ec: f000 f856 bl 800729c + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 80071f0: 230f movs r3, #15 + 80071f2: 18fc adds r4, r7, r3 + 80071f4: 4b27 ldr r3, [pc, #156] @ (8007294 ) + 80071f6: 0018 movs r0, r3 + 80071f8: f7ff ff6a bl 80070d0 + 80071fc: 0003 movs r3, r0 + 80071fe: 7023 strb r3, [r4, #0] + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + 8007200: 4b25 ldr r3, [pc, #148] @ (8007298 ) + 8007202: 691a ldr r2, [r3, #16] + 8007204: 4b24 ldr r3, [pc, #144] @ (8007298 ) + 8007206: 2104 movs r1, #4 + 8007208: 438a bics r2, r1 + 800720a: 611a str r2, [r3, #16] + 800720c: e036 b.n 800727c + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 800720e: 4b21 ldr r3, [pc, #132] @ (8007294 ) + 8007210: 0018 movs r0, r3 + 8007212: f7ff ff5d bl 80070d0 + 8007216: 1e03 subs r3, r0, #0 + 8007218: d130 bne.n 800727c + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + 800721a: 683b ldr r3, [r7, #0] + 800721c: 2201 movs r2, #1 + 800721e: 4252 negs r2, r2 + 8007220: 601a str r2, [r3, #0] + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + 8007222: 687b ldr r3, [r7, #4] + 8007224: 685b ldr r3, [r3, #4] + 8007226: 60bb str r3, [r7, #8] + 8007228: e01f b.n 800726a + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + 800722a: 68bb ldr r3, [r7, #8] + 800722c: 0018 movs r0, r3 + 800722e: f000 f84d bl 80072cc + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 8007232: 250f movs r5, #15 + 8007234: 197c adds r4, r7, r5 + 8007236: 4b17 ldr r3, [pc, #92] @ (8007294 ) + 8007238: 0018 movs r0, r3 + 800723a: f7ff ff49 bl 80070d0 + 800723e: 0003 movs r3, r0 + 8007240: 7023 strb r3, [r4, #0] + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 8007242: 4b15 ldr r3, [pc, #84] @ (8007298 ) + 8007244: 691a ldr r2, [r3, #16] + 8007246: 4b14 ldr r3, [pc, #80] @ (8007298 ) + 8007248: 2102 movs r1, #2 + 800724a: 438a bics r2, r1 + 800724c: 611a str r2, [r3, #16] + + if (status != HAL_OK) + 800724e: 197b adds r3, r7, r5 + 8007250: 781b ldrb r3, [r3, #0] + 8007252: 2b00 cmp r3, #0 + 8007254: d003 beq.n 800725e + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + 8007256: 683b ldr r3, [r7, #0] + 8007258: 68ba ldr r2, [r7, #8] + 800725a: 601a str r2, [r3, #0] + break; + 800725c: e00e b.n 800727c + address += FLASH_PAGE_SIZE) + 800725e: 68bb ldr r3, [r7, #8] + 8007260: 2280 movs r2, #128 @ 0x80 + 8007262: 0112 lsls r2, r2, #4 + 8007264: 4694 mov ip, r2 + 8007266: 4463 add r3, ip + 8007268: 60bb str r3, [r7, #8] + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 800726a: 687b ldr r3, [r7, #4] + 800726c: 689b ldr r3, [r3, #8] + 800726e: 02da lsls r2, r3, #11 + 8007270: 687b ldr r3, [r7, #4] + 8007272: 685b ldr r3, [r3, #4] + 8007274: 18d3 adds r3, r2, r3 + 8007276: 68ba ldr r2, [r7, #8] + 8007278: 429a cmp r2, r3 + 800727a: d3d6 bcc.n 800722a + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + 800727c: 4b04 ldr r3, [pc, #16] @ (8007290 ) + 800727e: 2200 movs r2, #0 + 8007280: 761a strb r2, [r3, #24] + + return status; + 8007282: 230f movs r3, #15 + 8007284: 18fb adds r3, r7, r3 + 8007286: 781b ldrb r3, [r3, #0] +} + 8007288: 0018 movs r0, r3 + 800728a: 46bd mov sp, r7 + 800728c: b004 add sp, #16 + 800728e: bdb0 pop {r4, r5, r7, pc} + 8007290: 20000db0 .word 0x20000db0 + 8007294: 0000c350 .word 0x0000c350 + 8007298: 40022000 .word 0x40022000 + +0800729c : + * @brief Full erase of FLASH memory Bank + * + * @retval None + */ +static void FLASH_MassErase(void) +{ + 800729c: b580 push {r7, lr} + 800729e: af00 add r7, sp, #0 + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 80072a0: 4b08 ldr r3, [pc, #32] @ (80072c4 ) + 80072a2: 2200 movs r2, #0 + 80072a4: 61da str r2, [r3, #28] + + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + 80072a6: 4b08 ldr r3, [pc, #32] @ (80072c8 ) + 80072a8: 691a ldr r2, [r3, #16] + 80072aa: 4b07 ldr r3, [pc, #28] @ (80072c8 ) + 80072ac: 2104 movs r1, #4 + 80072ae: 430a orrs r2, r1 + 80072b0: 611a str r2, [r3, #16] + SET_BIT(FLASH->CR, FLASH_CR_STRT); + 80072b2: 4b05 ldr r3, [pc, #20] @ (80072c8 ) + 80072b4: 691a ldr r2, [r3, #16] + 80072b6: 4b04 ldr r3, [pc, #16] @ (80072c8 ) + 80072b8: 2140 movs r1, #64 @ 0x40 + 80072ba: 430a orrs r2, r1 + 80072bc: 611a str r2, [r3, #16] +} + 80072be: 46c0 nop @ (mov r8, r8) + 80072c0: 46bd mov sp, r7 + 80072c2: bd80 pop {r7, pc} + 80072c4: 20000db0 .word 0x20000db0 + 80072c8: 40022000 .word 0x40022000 + +080072cc : + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + 80072cc: b580 push {r7, lr} + 80072ce: b082 sub sp, #8 + 80072d0: af00 add r7, sp, #0 + 80072d2: 6078 str r0, [r7, #4] + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 80072d4: 4b0a ldr r3, [pc, #40] @ (8007300 ) + 80072d6: 2200 movs r2, #0 + 80072d8: 61da str r2, [r3, #28] + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + 80072da: 4b0a ldr r3, [pc, #40] @ (8007304 ) + 80072dc: 691a ldr r2, [r3, #16] + 80072de: 4b09 ldr r3, [pc, #36] @ (8007304 ) + 80072e0: 2102 movs r1, #2 + 80072e2: 430a orrs r2, r1 + 80072e4: 611a str r2, [r3, #16] + WRITE_REG(FLASH->AR, PageAddress); + 80072e6: 4b07 ldr r3, [pc, #28] @ (8007304 ) + 80072e8: 687a ldr r2, [r7, #4] + 80072ea: 615a str r2, [r3, #20] + SET_BIT(FLASH->CR, FLASH_CR_STRT); + 80072ec: 4b05 ldr r3, [pc, #20] @ (8007304 ) + 80072ee: 691a ldr r2, [r3, #16] + 80072f0: 4b04 ldr r3, [pc, #16] @ (8007304 ) + 80072f2: 2140 movs r1, #64 @ 0x40 + 80072f4: 430a orrs r2, r1 + 80072f6: 611a str r2, [r3, #16] +} + 80072f8: 46c0 nop @ (mov r8, r8) + 80072fa: 46bd mov sp, r7 + 80072fc: b002 add sp, #8 + 80072fe: bd80 pop {r7, pc} + 8007300: 20000db0 .word 0x20000db0 + 8007304: 40022000 .word 0x40022000 + +08007308 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8007308: b580 push {r7, lr} + 800730a: b086 sub sp, #24 + 800730c: af00 add r7, sp, #0 + 800730e: 6078 str r0, [r7, #4] + 8007310: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8007312: 2300 movs r3, #0 + 8007314: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8007316: e155 b.n 80075c4 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8007318: 683b ldr r3, [r7, #0] + 800731a: 681b ldr r3, [r3, #0] + 800731c: 2101 movs r1, #1 + 800731e: 697a ldr r2, [r7, #20] + 8007320: 4091 lsls r1, r2 + 8007322: 000a movs r2, r1 + 8007324: 4013 ands r3, r2 + 8007326: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8007328: 68fb ldr r3, [r7, #12] + 800732a: 2b00 cmp r3, #0 + 800732c: d100 bne.n 8007330 + 800732e: e146 b.n 80075be + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8007330: 683b ldr r3, [r7, #0] + 8007332: 685b ldr r3, [r3, #4] + 8007334: 2b01 cmp r3, #1 + 8007336: d00b beq.n 8007350 + 8007338: 683b ldr r3, [r7, #0] + 800733a: 685b ldr r3, [r3, #4] + 800733c: 2b02 cmp r3, #2 + 800733e: d007 beq.n 8007350 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8007340: 683b ldr r3, [r7, #0] + 8007342: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8007344: 2b11 cmp r3, #17 + 8007346: d003 beq.n 8007350 + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8007348: 683b ldr r3, [r7, #0] + 800734a: 685b ldr r3, [r3, #4] + 800734c: 2b12 cmp r3, #18 + 800734e: d130 bne.n 80073b2 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8007350: 687b ldr r3, [r7, #4] + 8007352: 689b ldr r3, [r3, #8] + 8007354: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 8007356: 697b ldr r3, [r7, #20] + 8007358: 005b lsls r3, r3, #1 + 800735a: 2203 movs r2, #3 + 800735c: 409a lsls r2, r3 + 800735e: 0013 movs r3, r2 + 8007360: 43da mvns r2, r3 + 8007362: 693b ldr r3, [r7, #16] + 8007364: 4013 ands r3, r2 + 8007366: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2u)); + 8007368: 683b ldr r3, [r7, #0] + 800736a: 68da ldr r2, [r3, #12] + 800736c: 697b ldr r3, [r7, #20] + 800736e: 005b lsls r3, r3, #1 + 8007370: 409a lsls r2, r3 + 8007372: 0013 movs r3, r2 + 8007374: 693a ldr r2, [r7, #16] + 8007376: 4313 orrs r3, r2 + 8007378: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 800737a: 687b ldr r3, [r7, #4] + 800737c: 693a ldr r2, [r7, #16] + 800737e: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8007380: 687b ldr r3, [r7, #4] + 8007382: 685b ldr r3, [r3, #4] + 8007384: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8007386: 2201 movs r2, #1 + 8007388: 697b ldr r3, [r7, #20] + 800738a: 409a lsls r2, r3 + 800738c: 0013 movs r3, r2 + 800738e: 43da mvns r2, r3 + 8007390: 693b ldr r3, [r7, #16] + 8007392: 4013 ands r3, r2 + 8007394: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); + 8007396: 683b ldr r3, [r7, #0] + 8007398: 685b ldr r3, [r3, #4] + 800739a: 091b lsrs r3, r3, #4 + 800739c: 2201 movs r2, #1 + 800739e: 401a ands r2, r3 + 80073a0: 697b ldr r3, [r7, #20] + 80073a2: 409a lsls r2, r3 + 80073a4: 0013 movs r3, r2 + 80073a6: 693a ldr r2, [r7, #16] + 80073a8: 4313 orrs r3, r2 + 80073aa: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80073ac: 687b ldr r3, [r7, #4] + 80073ae: 693a ldr r2, [r7, #16] + 80073b0: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80073b2: 687b ldr r3, [r7, #4] + 80073b4: 68db ldr r3, [r3, #12] + 80073b6: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 80073b8: 697b ldr r3, [r7, #20] + 80073ba: 005b lsls r3, r3, #1 + 80073bc: 2203 movs r2, #3 + 80073be: 409a lsls r2, r3 + 80073c0: 0013 movs r3, r2 + 80073c2: 43da mvns r2, r3 + 80073c4: 693b ldr r3, [r7, #16] + 80073c6: 4013 ands r3, r2 + 80073c8: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2u)); + 80073ca: 683b ldr r3, [r7, #0] + 80073cc: 689a ldr r2, [r3, #8] + 80073ce: 697b ldr r3, [r7, #20] + 80073d0: 005b lsls r3, r3, #1 + 80073d2: 409a lsls r2, r3 + 80073d4: 0013 movs r3, r2 + 80073d6: 693a ldr r2, [r7, #16] + 80073d8: 4313 orrs r3, r2 + 80073da: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80073dc: 687b ldr r3, [r7, #4] + 80073de: 693a ldr r2, [r7, #16] + 80073e0: 60da str r2, [r3, #12] + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80073e2: 683b ldr r3, [r7, #0] + 80073e4: 685b ldr r3, [r3, #4] + 80073e6: 2b02 cmp r3, #2 + 80073e8: d003 beq.n 80073f2 + 80073ea: 683b ldr r3, [r7, #0] + 80073ec: 685b ldr r3, [r3, #4] + 80073ee: 2b12 cmp r3, #18 + 80073f0: d123 bne.n 800743a + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + 80073f2: 697b ldr r3, [r7, #20] + 80073f4: 08da lsrs r2, r3, #3 + 80073f6: 687b ldr r3, [r7, #4] + 80073f8: 3208 adds r2, #8 + 80073fa: 0092 lsls r2, r2, #2 + 80073fc: 58d3 ldr r3, [r2, r3] + 80073fe: 613b str r3, [r7, #16] + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 8007400: 697b ldr r3, [r7, #20] + 8007402: 2207 movs r2, #7 + 8007404: 4013 ands r3, r2 + 8007406: 009b lsls r3, r3, #2 + 8007408: 220f movs r2, #15 + 800740a: 409a lsls r2, r3 + 800740c: 0013 movs r3, r2 + 800740e: 43da mvns r2, r3 + 8007410: 693b ldr r3, [r7, #16] + 8007412: 4013 ands r3, r2 + 8007414: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 8007416: 683b ldr r3, [r7, #0] + 8007418: 691a ldr r2, [r3, #16] + 800741a: 697b ldr r3, [r7, #20] + 800741c: 2107 movs r1, #7 + 800741e: 400b ands r3, r1 + 8007420: 009b lsls r3, r3, #2 + 8007422: 409a lsls r2, r3 + 8007424: 0013 movs r3, r2 + 8007426: 693a ldr r2, [r7, #16] + 8007428: 4313 orrs r3, r2 + 800742a: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 800742c: 697b ldr r3, [r7, #20] + 800742e: 08da lsrs r2, r3, #3 + 8007430: 687b ldr r3, [r7, #4] + 8007432: 3208 adds r2, #8 + 8007434: 0092 lsls r2, r2, #2 + 8007436: 6939 ldr r1, [r7, #16] + 8007438: 50d1 str r1, [r2, r3] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800743a: 687b ldr r3, [r7, #4] + 800743c: 681b ldr r3, [r3, #0] + 800743e: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 8007440: 697b ldr r3, [r7, #20] + 8007442: 005b lsls r3, r3, #1 + 8007444: 2203 movs r2, #3 + 8007446: 409a lsls r2, r3 + 8007448: 0013 movs r3, r2 + 800744a: 43da mvns r2, r3 + 800744c: 693b ldr r3, [r7, #16] + 800744e: 4013 ands r3, r2 + 8007450: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 8007452: 683b ldr r3, [r7, #0] + 8007454: 685b ldr r3, [r3, #4] + 8007456: 2203 movs r2, #3 + 8007458: 401a ands r2, r3 + 800745a: 697b ldr r3, [r7, #20] + 800745c: 005b lsls r3, r3, #1 + 800745e: 409a lsls r2, r3 + 8007460: 0013 movs r3, r2 + 8007462: 693a ldr r2, [r7, #16] + 8007464: 4313 orrs r3, r2 + 8007466: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8007468: 687b ldr r3, [r7, #4] + 800746a: 693a ldr r2, [r7, #16] + 800746c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 800746e: 683b ldr r3, [r7, #0] + 8007470: 685a ldr r2, [r3, #4] + 8007472: 2380 movs r3, #128 @ 0x80 + 8007474: 055b lsls r3, r3, #21 + 8007476: 4013 ands r3, r2 + 8007478: d100 bne.n 800747c + 800747a: e0a0 b.n 80075be + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800747c: 4b57 ldr r3, [pc, #348] @ (80075dc ) + 800747e: 699a ldr r2, [r3, #24] + 8007480: 4b56 ldr r3, [pc, #344] @ (80075dc ) + 8007482: 2101 movs r1, #1 + 8007484: 430a orrs r2, r1 + 8007486: 619a str r2, [r3, #24] + 8007488: 4b54 ldr r3, [pc, #336] @ (80075dc ) + 800748a: 699b ldr r3, [r3, #24] + 800748c: 2201 movs r2, #1 + 800748e: 4013 ands r3, r2 + 8007490: 60bb str r3, [r7, #8] + 8007492: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2u]; + 8007494: 4a52 ldr r2, [pc, #328] @ (80075e0 ) + 8007496: 697b ldr r3, [r7, #20] + 8007498: 089b lsrs r3, r3, #2 + 800749a: 3302 adds r3, #2 + 800749c: 009b lsls r3, r3, #2 + 800749e: 589b ldr r3, [r3, r2] + 80074a0: 613b str r3, [r7, #16] + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 80074a2: 697b ldr r3, [r7, #20] + 80074a4: 2203 movs r2, #3 + 80074a6: 4013 ands r3, r2 + 80074a8: 009b lsls r3, r3, #2 + 80074aa: 220f movs r2, #15 + 80074ac: 409a lsls r2, r3 + 80074ae: 0013 movs r3, r2 + 80074b0: 43da mvns r2, r3 + 80074b2: 693b ldr r3, [r7, #16] + 80074b4: 4013 ands r3, r2 + 80074b6: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 80074b8: 687a ldr r2, [r7, #4] + 80074ba: 2390 movs r3, #144 @ 0x90 + 80074bc: 05db lsls r3, r3, #23 + 80074be: 429a cmp r2, r3 + 80074c0: d019 beq.n 80074f6 + 80074c2: 687b ldr r3, [r7, #4] + 80074c4: 4a47 ldr r2, [pc, #284] @ (80075e4 ) + 80074c6: 4293 cmp r3, r2 + 80074c8: d013 beq.n 80074f2 + 80074ca: 687b ldr r3, [r7, #4] + 80074cc: 4a46 ldr r2, [pc, #280] @ (80075e8 ) + 80074ce: 4293 cmp r3, r2 + 80074d0: d00d beq.n 80074ee + 80074d2: 687b ldr r3, [r7, #4] + 80074d4: 4a45 ldr r2, [pc, #276] @ (80075ec ) + 80074d6: 4293 cmp r3, r2 + 80074d8: d007 beq.n 80074ea + 80074da: 687b ldr r3, [r7, #4] + 80074dc: 4a44 ldr r2, [pc, #272] @ (80075f0 ) + 80074de: 4293 cmp r3, r2 + 80074e0: d101 bne.n 80074e6 + 80074e2: 2304 movs r3, #4 + 80074e4: e008 b.n 80074f8 + 80074e6: 2305 movs r3, #5 + 80074e8: e006 b.n 80074f8 + 80074ea: 2303 movs r3, #3 + 80074ec: e004 b.n 80074f8 + 80074ee: 2302 movs r3, #2 + 80074f0: e002 b.n 80074f8 + 80074f2: 2301 movs r3, #1 + 80074f4: e000 b.n 80074f8 + 80074f6: 2300 movs r3, #0 + 80074f8: 697a ldr r2, [r7, #20] + 80074fa: 2103 movs r1, #3 + 80074fc: 400a ands r2, r1 + 80074fe: 0092 lsls r2, r2, #2 + 8007500: 4093 lsls r3, r2 + 8007502: 693a ldr r2, [r7, #16] + 8007504: 4313 orrs r3, r2 + 8007506: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 8007508: 4935 ldr r1, [pc, #212] @ (80075e0 ) + 800750a: 697b ldr r3, [r7, #20] + 800750c: 089b lsrs r3, r3, #2 + 800750e: 3302 adds r3, #2 + 8007510: 009b lsls r3, r3, #2 + 8007512: 693a ldr r2, [r7, #16] + 8007514: 505a str r2, [r3, r1] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8007516: 4b37 ldr r3, [pc, #220] @ (80075f4 ) + 8007518: 681b ldr r3, [r3, #0] + 800751a: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 800751c: 68fb ldr r3, [r7, #12] + 800751e: 43da mvns r2, r3 + 8007520: 693b ldr r3, [r7, #16] + 8007522: 4013 ands r3, r2 + 8007524: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 8007526: 683b ldr r3, [r7, #0] + 8007528: 685a ldr r2, [r3, #4] + 800752a: 2380 movs r3, #128 @ 0x80 + 800752c: 025b lsls r3, r3, #9 + 800752e: 4013 ands r3, r2 + 8007530: d003 beq.n 800753a + { + temp |= iocurrent; + 8007532: 693a ldr r2, [r7, #16] + 8007534: 68fb ldr r3, [r7, #12] + 8007536: 4313 orrs r3, r2 + 8007538: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 800753a: 4b2e ldr r3, [pc, #184] @ (80075f4 ) + 800753c: 693a ldr r2, [r7, #16] + 800753e: 601a str r2, [r3, #0] + + temp = EXTI->EMR; + 8007540: 4b2c ldr r3, [pc, #176] @ (80075f4 ) + 8007542: 685b ldr r3, [r3, #4] + 8007544: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8007546: 68fb ldr r3, [r7, #12] + 8007548: 43da mvns r2, r3 + 800754a: 693b ldr r3, [r7, #16] + 800754c: 4013 ands r3, r2 + 800754e: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 8007550: 683b ldr r3, [r7, #0] + 8007552: 685a ldr r2, [r3, #4] + 8007554: 2380 movs r3, #128 @ 0x80 + 8007556: 029b lsls r3, r3, #10 + 8007558: 4013 ands r3, r2 + 800755a: d003 beq.n 8007564 + { + temp |= iocurrent; + 800755c: 693a ldr r2, [r7, #16] + 800755e: 68fb ldr r3, [r7, #12] + 8007560: 4313 orrs r3, r2 + 8007562: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8007564: 4b23 ldr r3, [pc, #140] @ (80075f4 ) + 8007566: 693a ldr r2, [r7, #16] + 8007568: 605a str r2, [r3, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 800756a: 4b22 ldr r3, [pc, #136] @ (80075f4 ) + 800756c: 689b ldr r3, [r3, #8] + 800756e: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8007570: 68fb ldr r3, [r7, #12] + 8007572: 43da mvns r2, r3 + 8007574: 693b ldr r3, [r7, #16] + 8007576: 4013 ands r3, r2 + 8007578: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 800757a: 683b ldr r3, [r7, #0] + 800757c: 685a ldr r2, [r3, #4] + 800757e: 2380 movs r3, #128 @ 0x80 + 8007580: 035b lsls r3, r3, #13 + 8007582: 4013 ands r3, r2 + 8007584: d003 beq.n 800758e + { + temp |= iocurrent; + 8007586: 693a ldr r2, [r7, #16] + 8007588: 68fb ldr r3, [r7, #12] + 800758a: 4313 orrs r3, r2 + 800758c: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 800758e: 4b19 ldr r3, [pc, #100] @ (80075f4 ) + 8007590: 693a ldr r2, [r7, #16] + 8007592: 609a str r2, [r3, #8] + + temp = EXTI->FTSR; + 8007594: 4b17 ldr r3, [pc, #92] @ (80075f4 ) + 8007596: 68db ldr r3, [r3, #12] + 8007598: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 800759a: 68fb ldr r3, [r7, #12] + 800759c: 43da mvns r2, r3 + 800759e: 693b ldr r3, [r7, #16] + 80075a0: 4013 ands r3, r2 + 80075a2: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 80075a4: 683b ldr r3, [r7, #0] + 80075a6: 685a ldr r2, [r3, #4] + 80075a8: 2380 movs r3, #128 @ 0x80 + 80075aa: 039b lsls r3, r3, #14 + 80075ac: 4013 ands r3, r2 + 80075ae: d003 beq.n 80075b8 + { + temp |= iocurrent; + 80075b0: 693a ldr r2, [r7, #16] + 80075b2: 68fb ldr r3, [r7, #12] + 80075b4: 4313 orrs r3, r2 + 80075b6: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 80075b8: 4b0e ldr r3, [pc, #56] @ (80075f4 ) + 80075ba: 693a ldr r2, [r7, #16] + 80075bc: 60da str r2, [r3, #12] + } + } + + position++; + 80075be: 697b ldr r3, [r7, #20] + 80075c0: 3301 adds r3, #1 + 80075c2: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80075c4: 683b ldr r3, [r7, #0] + 80075c6: 681a ldr r2, [r3, #0] + 80075c8: 697b ldr r3, [r7, #20] + 80075ca: 40da lsrs r2, r3 + 80075cc: 1e13 subs r3, r2, #0 + 80075ce: d000 beq.n 80075d2 + 80075d0: e6a2 b.n 8007318 + } +} + 80075d2: 46c0 nop @ (mov r8, r8) + 80075d4: 46c0 nop @ (mov r8, r8) + 80075d6: 46bd mov sp, r7 + 80075d8: b006 add sp, #24 + 80075da: bd80 pop {r7, pc} + 80075dc: 40021000 .word 0x40021000 + 80075e0: 40010000 .word 0x40010000 + 80075e4: 48000400 .word 0x48000400 + 80075e8: 48000800 .word 0x48000800 + 80075ec: 48000c00 .word 0x48000c00 + 80075f0: 48001000 .word 0x48001000 + 80075f4: 40010400 .word 0x40010400 + +080075f8 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80075f8: b580 push {r7, lr} + 80075fa: b082 sub sp, #8 + 80075fc: af00 add r7, sp, #0 + 80075fe: 6078 str r0, [r7, #4] + 8007600: 0008 movs r0, r1 + 8007602: 0011 movs r1, r2 + 8007604: 1cbb adds r3, r7, #2 + 8007606: 1c02 adds r2, r0, #0 + 8007608: 801a strh r2, [r3, #0] + 800760a: 1c7b adds r3, r7, #1 + 800760c: 1c0a adds r2, r1, #0 + 800760e: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8007610: 1c7b adds r3, r7, #1 + 8007612: 781b ldrb r3, [r3, #0] + 8007614: 2b00 cmp r3, #0 + 8007616: d004 beq.n 8007622 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8007618: 1cbb adds r3, r7, #2 + 800761a: 881a ldrh r2, [r3, #0] + 800761c: 687b ldr r3, [r7, #4] + 800761e: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 8007620: e003 b.n 800762a + GPIOx->BRR = (uint32_t)GPIO_Pin; + 8007622: 1cbb adds r3, r7, #2 + 8007624: 881a ldrh r2, [r3, #0] + 8007626: 687b ldr r3, [r7, #4] + 8007628: 629a str r2, [r3, #40] @ 0x28 +} + 800762a: 46c0 nop @ (mov r8, r8) + 800762c: 46bd mov sp, r7 + 800762e: b002 add sp, #8 + 8007630: bd80 pop {r7, pc} + +08007632 : + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + 8007632: b580 push {r7, lr} + 8007634: b084 sub sp, #16 + 8007636: af00 add r7, sp, #0 + 8007638: 6078 str r0, [r7, #4] + 800763a: 000a movs r2, r1 + 800763c: 1cbb adds r3, r7, #2 + 800763e: 801a strh r2, [r3, #0] + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + 8007640: 687b ldr r3, [r7, #4] + 8007642: 695b ldr r3, [r3, #20] + 8007644: 60fb str r3, [r7, #12] + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 8007646: 1cbb adds r3, r7, #2 + 8007648: 881b ldrh r3, [r3, #0] + 800764a: 68fa ldr r2, [r7, #12] + 800764c: 4013 ands r3, r2 + 800764e: 041a lsls r2, r3, #16 + 8007650: 68fb ldr r3, [r7, #12] + 8007652: 43db mvns r3, r3 + 8007654: 1cb9 adds r1, r7, #2 + 8007656: 8809 ldrh r1, [r1, #0] + 8007658: 400b ands r3, r1 + 800765a: 431a orrs r2, r3 + 800765c: 687b ldr r3, [r7, #4] + 800765e: 619a str r2, [r3, #24] +} + 8007660: 46c0 nop @ (mov r8, r8) + 8007662: 46bd mov sp, r7 + 8007664: b004 add sp, #16 + 8007666: bd80 pop {r7, pc} + +08007668 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8007668: b580 push {r7, lr} + 800766a: b088 sub sp, #32 + 800766c: af00 add r7, sp, #0 + 800766e: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + uint32_t pll_config2; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 8007670: 687b ldr r3, [r7, #4] + 8007672: 2b00 cmp r3, #0 + 8007674: d102 bne.n 800767c + { + return HAL_ERROR; + 8007676: 2301 movs r3, #1 + 8007678: f000 fb76 bl 8007d68 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 800767c: 687b ldr r3, [r7, #4] + 800767e: 681b ldr r3, [r3, #0] + 8007680: 2201 movs r2, #1 + 8007682: 4013 ands r3, r2 + 8007684: d100 bne.n 8007688 + 8007686: e08e b.n 80077a6 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 8007688: 4bc5 ldr r3, [pc, #788] @ (80079a0 ) + 800768a: 685b ldr r3, [r3, #4] + 800768c: 220c movs r2, #12 + 800768e: 4013 ands r3, r2 + 8007690: 2b04 cmp r3, #4 + 8007692: d00e beq.n 80076b2 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + 8007694: 4bc2 ldr r3, [pc, #776] @ (80079a0 ) + 8007696: 685b ldr r3, [r3, #4] + 8007698: 220c movs r2, #12 + 800769a: 4013 ands r3, r2 + 800769c: 2b08 cmp r3, #8 + 800769e: d117 bne.n 80076d0 + 80076a0: 4bbf ldr r3, [pc, #764] @ (80079a0 ) + 80076a2: 685a ldr r2, [r3, #4] + 80076a4: 23c0 movs r3, #192 @ 0xc0 + 80076a6: 025b lsls r3, r3, #9 + 80076a8: 401a ands r2, r3 + 80076aa: 2380 movs r3, #128 @ 0x80 + 80076ac: 025b lsls r3, r3, #9 + 80076ae: 429a cmp r2, r3 + 80076b0: d10e bne.n 80076d0 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80076b2: 4bbb ldr r3, [pc, #748] @ (80079a0 ) + 80076b4: 681a ldr r2, [r3, #0] + 80076b6: 2380 movs r3, #128 @ 0x80 + 80076b8: 029b lsls r3, r3, #10 + 80076ba: 4013 ands r3, r2 + 80076bc: d100 bne.n 80076c0 + 80076be: e071 b.n 80077a4 + 80076c0: 687b ldr r3, [r7, #4] + 80076c2: 685b ldr r3, [r3, #4] + 80076c4: 2b00 cmp r3, #0 + 80076c6: d000 beq.n 80076ca + 80076c8: e06c b.n 80077a4 + { + return HAL_ERROR; + 80076ca: 2301 movs r3, #1 + 80076cc: f000 fb4c bl 8007d68 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80076d0: 687b ldr r3, [r7, #4] + 80076d2: 685b ldr r3, [r3, #4] + 80076d4: 2b01 cmp r3, #1 + 80076d6: d107 bne.n 80076e8 + 80076d8: 4bb1 ldr r3, [pc, #708] @ (80079a0 ) + 80076da: 681a ldr r2, [r3, #0] + 80076dc: 4bb0 ldr r3, [pc, #704] @ (80079a0 ) + 80076de: 2180 movs r1, #128 @ 0x80 + 80076e0: 0249 lsls r1, r1, #9 + 80076e2: 430a orrs r2, r1 + 80076e4: 601a str r2, [r3, #0] + 80076e6: e02f b.n 8007748 + 80076e8: 687b ldr r3, [r7, #4] + 80076ea: 685b ldr r3, [r3, #4] + 80076ec: 2b00 cmp r3, #0 + 80076ee: d10c bne.n 800770a + 80076f0: 4bab ldr r3, [pc, #684] @ (80079a0 ) + 80076f2: 681a ldr r2, [r3, #0] + 80076f4: 4baa ldr r3, [pc, #680] @ (80079a0 ) + 80076f6: 49ab ldr r1, [pc, #684] @ (80079a4 ) + 80076f8: 400a ands r2, r1 + 80076fa: 601a str r2, [r3, #0] + 80076fc: 4ba8 ldr r3, [pc, #672] @ (80079a0 ) + 80076fe: 681a ldr r2, [r3, #0] + 8007700: 4ba7 ldr r3, [pc, #668] @ (80079a0 ) + 8007702: 49a9 ldr r1, [pc, #676] @ (80079a8 ) + 8007704: 400a ands r2, r1 + 8007706: 601a str r2, [r3, #0] + 8007708: e01e b.n 8007748 + 800770a: 687b ldr r3, [r7, #4] + 800770c: 685b ldr r3, [r3, #4] + 800770e: 2b05 cmp r3, #5 + 8007710: d10e bne.n 8007730 + 8007712: 4ba3 ldr r3, [pc, #652] @ (80079a0 ) + 8007714: 681a ldr r2, [r3, #0] + 8007716: 4ba2 ldr r3, [pc, #648] @ (80079a0 ) + 8007718: 2180 movs r1, #128 @ 0x80 + 800771a: 02c9 lsls r1, r1, #11 + 800771c: 430a orrs r2, r1 + 800771e: 601a str r2, [r3, #0] + 8007720: 4b9f ldr r3, [pc, #636] @ (80079a0 ) + 8007722: 681a ldr r2, [r3, #0] + 8007724: 4b9e ldr r3, [pc, #632] @ (80079a0 ) + 8007726: 2180 movs r1, #128 @ 0x80 + 8007728: 0249 lsls r1, r1, #9 + 800772a: 430a orrs r2, r1 + 800772c: 601a str r2, [r3, #0] + 800772e: e00b b.n 8007748 + 8007730: 4b9b ldr r3, [pc, #620] @ (80079a0 ) + 8007732: 681a ldr r2, [r3, #0] + 8007734: 4b9a ldr r3, [pc, #616] @ (80079a0 ) + 8007736: 499b ldr r1, [pc, #620] @ (80079a4 ) + 8007738: 400a ands r2, r1 + 800773a: 601a str r2, [r3, #0] + 800773c: 4b98 ldr r3, [pc, #608] @ (80079a0 ) + 800773e: 681a ldr r2, [r3, #0] + 8007740: 4b97 ldr r3, [pc, #604] @ (80079a0 ) + 8007742: 4999 ldr r1, [pc, #612] @ (80079a8 ) + 8007744: 400a ands r2, r1 + 8007746: 601a str r2, [r3, #0] + + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8007748: 687b ldr r3, [r7, #4] + 800774a: 685b ldr r3, [r3, #4] + 800774c: 2b00 cmp r3, #0 + 800774e: d014 beq.n 800777a + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007750: f7ff f8cc bl 80068ec + 8007754: 0003 movs r3, r0 + 8007756: 61bb str r3, [r7, #24] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8007758: e008 b.n 800776c + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800775a: f7ff f8c7 bl 80068ec + 800775e: 0002 movs r2, r0 + 8007760: 69bb ldr r3, [r7, #24] + 8007762: 1ad3 subs r3, r2, r3 + 8007764: 2b64 cmp r3, #100 @ 0x64 + 8007766: d901 bls.n 800776c + { + return HAL_TIMEOUT; + 8007768: 2303 movs r3, #3 + 800776a: e2fd b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800776c: 4b8c ldr r3, [pc, #560] @ (80079a0 ) + 800776e: 681a ldr r2, [r3, #0] + 8007770: 2380 movs r3, #128 @ 0x80 + 8007772: 029b lsls r3, r3, #10 + 8007774: 4013 ands r3, r2 + 8007776: d0f0 beq.n 800775a + 8007778: e015 b.n 80077a6 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800777a: f7ff f8b7 bl 80068ec + 800777e: 0003 movs r3, r0 + 8007780: 61bb str r3, [r7, #24] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8007782: e008 b.n 8007796 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8007784: f7ff f8b2 bl 80068ec + 8007788: 0002 movs r2, r0 + 800778a: 69bb ldr r3, [r7, #24] + 800778c: 1ad3 subs r3, r2, r3 + 800778e: 2b64 cmp r3, #100 @ 0x64 + 8007790: d901 bls.n 8007796 + { + return HAL_TIMEOUT; + 8007792: 2303 movs r3, #3 + 8007794: e2e8 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 8007796: 4b82 ldr r3, [pc, #520] @ (80079a0 ) + 8007798: 681a ldr r2, [r3, #0] + 800779a: 2380 movs r3, #128 @ 0x80 + 800779c: 029b lsls r3, r3, #10 + 800779e: 4013 ands r3, r2 + 80077a0: d1f0 bne.n 8007784 + 80077a2: e000 b.n 80077a6 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80077a4: 46c0 nop @ (mov r8, r8) + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80077a6: 687b ldr r3, [r7, #4] + 80077a8: 681b ldr r3, [r3, #0] + 80077aa: 2202 movs r2, #2 + 80077ac: 4013 ands r3, r2 + 80077ae: d100 bne.n 80077b2 + 80077b0: e06c b.n 800788c + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 80077b2: 4b7b ldr r3, [pc, #492] @ (80079a0 ) + 80077b4: 685b ldr r3, [r3, #4] + 80077b6: 220c movs r2, #12 + 80077b8: 4013 ands r3, r2 + 80077ba: d00e beq.n 80077da + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + 80077bc: 4b78 ldr r3, [pc, #480] @ (80079a0 ) + 80077be: 685b ldr r3, [r3, #4] + 80077c0: 220c movs r2, #12 + 80077c2: 4013 ands r3, r2 + 80077c4: 2b08 cmp r3, #8 + 80077c6: d11f bne.n 8007808 + 80077c8: 4b75 ldr r3, [pc, #468] @ (80079a0 ) + 80077ca: 685a ldr r2, [r3, #4] + 80077cc: 23c0 movs r3, #192 @ 0xc0 + 80077ce: 025b lsls r3, r3, #9 + 80077d0: 401a ands r2, r3 + 80077d2: 2380 movs r3, #128 @ 0x80 + 80077d4: 021b lsls r3, r3, #8 + 80077d6: 429a cmp r2, r3 + 80077d8: d116 bne.n 8007808 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80077da: 4b71 ldr r3, [pc, #452] @ (80079a0 ) + 80077dc: 681b ldr r3, [r3, #0] + 80077de: 2202 movs r2, #2 + 80077e0: 4013 ands r3, r2 + 80077e2: d005 beq.n 80077f0 + 80077e4: 687b ldr r3, [r7, #4] + 80077e6: 68db ldr r3, [r3, #12] + 80077e8: 2b01 cmp r3, #1 + 80077ea: d001 beq.n 80077f0 + { + return HAL_ERROR; + 80077ec: 2301 movs r3, #1 + 80077ee: e2bb b.n 8007d68 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80077f0: 4b6b ldr r3, [pc, #428] @ (80079a0 ) + 80077f2: 681b ldr r3, [r3, #0] + 80077f4: 22f8 movs r2, #248 @ 0xf8 + 80077f6: 4393 bics r3, r2 + 80077f8: 0019 movs r1, r3 + 80077fa: 687b ldr r3, [r7, #4] + 80077fc: 691b ldr r3, [r3, #16] + 80077fe: 00da lsls r2, r3, #3 + 8007800: 4b67 ldr r3, [pc, #412] @ (80079a0 ) + 8007802: 430a orrs r2, r1 + 8007804: 601a str r2, [r3, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8007806: e041 b.n 800788c + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8007808: 687b ldr r3, [r7, #4] + 800780a: 68db ldr r3, [r3, #12] + 800780c: 2b00 cmp r3, #0 + 800780e: d024 beq.n 800785a + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8007810: 4b63 ldr r3, [pc, #396] @ (80079a0 ) + 8007812: 681a ldr r2, [r3, #0] + 8007814: 4b62 ldr r3, [pc, #392] @ (80079a0 ) + 8007816: 2101 movs r1, #1 + 8007818: 430a orrs r2, r1 + 800781a: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800781c: f7ff f866 bl 80068ec + 8007820: 0003 movs r3, r0 + 8007822: 61bb str r3, [r7, #24] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007824: e008 b.n 8007838 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8007826: f7ff f861 bl 80068ec + 800782a: 0002 movs r2, r0 + 800782c: 69bb ldr r3, [r7, #24] + 800782e: 1ad3 subs r3, r2, r3 + 8007830: 2b02 cmp r3, #2 + 8007832: d901 bls.n 8007838 + { + return HAL_TIMEOUT; + 8007834: 2303 movs r3, #3 + 8007836: e297 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007838: 4b59 ldr r3, [pc, #356] @ (80079a0 ) + 800783a: 681b ldr r3, [r3, #0] + 800783c: 2202 movs r2, #2 + 800783e: 4013 ands r3, r2 + 8007840: d0f1 beq.n 8007826 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8007842: 4b57 ldr r3, [pc, #348] @ (80079a0 ) + 8007844: 681b ldr r3, [r3, #0] + 8007846: 22f8 movs r2, #248 @ 0xf8 + 8007848: 4393 bics r3, r2 + 800784a: 0019 movs r1, r3 + 800784c: 687b ldr r3, [r7, #4] + 800784e: 691b ldr r3, [r3, #16] + 8007850: 00da lsls r2, r3, #3 + 8007852: 4b53 ldr r3, [pc, #332] @ (80079a0 ) + 8007854: 430a orrs r2, r1 + 8007856: 601a str r2, [r3, #0] + 8007858: e018 b.n 800788c + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800785a: 4b51 ldr r3, [pc, #324] @ (80079a0 ) + 800785c: 681a ldr r2, [r3, #0] + 800785e: 4b50 ldr r3, [pc, #320] @ (80079a0 ) + 8007860: 2101 movs r1, #1 + 8007862: 438a bics r2, r1 + 8007864: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007866: f7ff f841 bl 80068ec + 800786a: 0003 movs r3, r0 + 800786c: 61bb str r3, [r7, #24] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 800786e: e008 b.n 8007882 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8007870: f7ff f83c bl 80068ec + 8007874: 0002 movs r2, r0 + 8007876: 69bb ldr r3, [r7, #24] + 8007878: 1ad3 subs r3, r2, r3 + 800787a: 2b02 cmp r3, #2 + 800787c: d901 bls.n 8007882 + { + return HAL_TIMEOUT; + 800787e: 2303 movs r3, #3 + 8007880: e272 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8007882: 4b47 ldr r3, [pc, #284] @ (80079a0 ) + 8007884: 681b ldr r3, [r3, #0] + 8007886: 2202 movs r2, #2 + 8007888: 4013 ands r3, r2 + 800788a: d1f1 bne.n 8007870 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 800788c: 687b ldr r3, [r7, #4] + 800788e: 681b ldr r3, [r3, #0] + 8007890: 2208 movs r2, #8 + 8007892: 4013 ands r3, r2 + 8007894: d036 beq.n 8007904 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8007896: 687b ldr r3, [r7, #4] + 8007898: 69db ldr r3, [r3, #28] + 800789a: 2b00 cmp r3, #0 + 800789c: d019 beq.n 80078d2 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800789e: 4b40 ldr r3, [pc, #256] @ (80079a0 ) + 80078a0: 6a5a ldr r2, [r3, #36] @ 0x24 + 80078a2: 4b3f ldr r3, [pc, #252] @ (80079a0 ) + 80078a4: 2101 movs r1, #1 + 80078a6: 430a orrs r2, r1 + 80078a8: 625a str r2, [r3, #36] @ 0x24 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80078aa: f7ff f81f bl 80068ec + 80078ae: 0003 movs r3, r0 + 80078b0: 61bb str r3, [r7, #24] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 80078b2: e008 b.n 80078c6 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 80078b4: f7ff f81a bl 80068ec + 80078b8: 0002 movs r2, r0 + 80078ba: 69bb ldr r3, [r7, #24] + 80078bc: 1ad3 subs r3, r2, r3 + 80078be: 2b02 cmp r3, #2 + 80078c0: d901 bls.n 80078c6 + { + return HAL_TIMEOUT; + 80078c2: 2303 movs r3, #3 + 80078c4: e250 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 80078c6: 4b36 ldr r3, [pc, #216] @ (80079a0 ) + 80078c8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80078ca: 2202 movs r2, #2 + 80078cc: 4013 ands r3, r2 + 80078ce: d0f1 beq.n 80078b4 + 80078d0: e018 b.n 8007904 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80078d2: 4b33 ldr r3, [pc, #204] @ (80079a0 ) + 80078d4: 6a5a ldr r2, [r3, #36] @ 0x24 + 80078d6: 4b32 ldr r3, [pc, #200] @ (80079a0 ) + 80078d8: 2101 movs r1, #1 + 80078da: 438a bics r2, r1 + 80078dc: 625a str r2, [r3, #36] @ 0x24 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80078de: f7ff f805 bl 80068ec + 80078e2: 0003 movs r3, r0 + 80078e4: 61bb str r3, [r7, #24] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 80078e6: e008 b.n 80078fa + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 80078e8: f7ff f800 bl 80068ec + 80078ec: 0002 movs r2, r0 + 80078ee: 69bb ldr r3, [r7, #24] + 80078f0: 1ad3 subs r3, r2, r3 + 80078f2: 2b02 cmp r3, #2 + 80078f4: d901 bls.n 80078fa + { + return HAL_TIMEOUT; + 80078f6: 2303 movs r3, #3 + 80078f8: e236 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 80078fa: 4b29 ldr r3, [pc, #164] @ (80079a0 ) + 80078fc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80078fe: 2202 movs r2, #2 + 8007900: 4013 ands r3, r2 + 8007902: d1f1 bne.n 80078e8 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8007904: 687b ldr r3, [r7, #4] + 8007906: 681b ldr r3, [r3, #0] + 8007908: 2204 movs r2, #4 + 800790a: 4013 ands r3, r2 + 800790c: d100 bne.n 8007910 + 800790e: e0b5 b.n 8007a7c + { + FlagStatus pwrclkchanged = RESET; + 8007910: 201f movs r0, #31 + 8007912: 183b adds r3, r7, r0 + 8007914: 2200 movs r2, #0 + 8007916: 701a strb r2, [r3, #0] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8007918: 4b21 ldr r3, [pc, #132] @ (80079a0 ) + 800791a: 69da ldr r2, [r3, #28] + 800791c: 2380 movs r3, #128 @ 0x80 + 800791e: 055b lsls r3, r3, #21 + 8007920: 4013 ands r3, r2 + 8007922: d110 bne.n 8007946 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8007924: 4b1e ldr r3, [pc, #120] @ (80079a0 ) + 8007926: 69da ldr r2, [r3, #28] + 8007928: 4b1d ldr r3, [pc, #116] @ (80079a0 ) + 800792a: 2180 movs r1, #128 @ 0x80 + 800792c: 0549 lsls r1, r1, #21 + 800792e: 430a orrs r2, r1 + 8007930: 61da str r2, [r3, #28] + 8007932: 4b1b ldr r3, [pc, #108] @ (80079a0 ) + 8007934: 69da ldr r2, [r3, #28] + 8007936: 2380 movs r3, #128 @ 0x80 + 8007938: 055b lsls r3, r3, #21 + 800793a: 4013 ands r3, r2 + 800793c: 60fb str r3, [r7, #12] + 800793e: 68fb ldr r3, [r7, #12] + pwrclkchanged = SET; + 8007940: 183b adds r3, r7, r0 + 8007942: 2201 movs r2, #1 + 8007944: 701a strb r2, [r3, #0] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8007946: 4b19 ldr r3, [pc, #100] @ (80079ac ) + 8007948: 681a ldr r2, [r3, #0] + 800794a: 2380 movs r3, #128 @ 0x80 + 800794c: 005b lsls r3, r3, #1 + 800794e: 4013 ands r3, r2 + 8007950: d11a bne.n 8007988 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8007952: 4b16 ldr r3, [pc, #88] @ (80079ac ) + 8007954: 681a ldr r2, [r3, #0] + 8007956: 4b15 ldr r3, [pc, #84] @ (80079ac ) + 8007958: 2180 movs r1, #128 @ 0x80 + 800795a: 0049 lsls r1, r1, #1 + 800795c: 430a orrs r2, r1 + 800795e: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8007960: f7fe ffc4 bl 80068ec + 8007964: 0003 movs r3, r0 + 8007966: 61bb str r3, [r7, #24] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8007968: e008 b.n 800797c + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 800796a: f7fe ffbf bl 80068ec + 800796e: 0002 movs r2, r0 + 8007970: 69bb ldr r3, [r7, #24] + 8007972: 1ad3 subs r3, r2, r3 + 8007974: 2b64 cmp r3, #100 @ 0x64 + 8007976: d901 bls.n 800797c + { + return HAL_TIMEOUT; + 8007978: 2303 movs r3, #3 + 800797a: e1f5 b.n 8007d68 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800797c: 4b0b ldr r3, [pc, #44] @ (80079ac ) + 800797e: 681a ldr r2, [r3, #0] + 8007980: 2380 movs r3, #128 @ 0x80 + 8007982: 005b lsls r3, r3, #1 + 8007984: 4013 ands r3, r2 + 8007986: d0f0 beq.n 800796a + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8007988: 687b ldr r3, [r7, #4] + 800798a: 689b ldr r3, [r3, #8] + 800798c: 2b01 cmp r3, #1 + 800798e: d10f bne.n 80079b0 + 8007990: 4b03 ldr r3, [pc, #12] @ (80079a0 ) + 8007992: 6a1a ldr r2, [r3, #32] + 8007994: 4b02 ldr r3, [pc, #8] @ (80079a0 ) + 8007996: 2101 movs r1, #1 + 8007998: 430a orrs r2, r1 + 800799a: 621a str r2, [r3, #32] + 800799c: e036 b.n 8007a0c + 800799e: 46c0 nop @ (mov r8, r8) + 80079a0: 40021000 .word 0x40021000 + 80079a4: fffeffff .word 0xfffeffff + 80079a8: fffbffff .word 0xfffbffff + 80079ac: 40007000 .word 0x40007000 + 80079b0: 687b ldr r3, [r7, #4] + 80079b2: 689b ldr r3, [r3, #8] + 80079b4: 2b00 cmp r3, #0 + 80079b6: d10c bne.n 80079d2 + 80079b8: 4bca ldr r3, [pc, #808] @ (8007ce4 ) + 80079ba: 6a1a ldr r2, [r3, #32] + 80079bc: 4bc9 ldr r3, [pc, #804] @ (8007ce4 ) + 80079be: 2101 movs r1, #1 + 80079c0: 438a bics r2, r1 + 80079c2: 621a str r2, [r3, #32] + 80079c4: 4bc7 ldr r3, [pc, #796] @ (8007ce4 ) + 80079c6: 6a1a ldr r2, [r3, #32] + 80079c8: 4bc6 ldr r3, [pc, #792] @ (8007ce4 ) + 80079ca: 2104 movs r1, #4 + 80079cc: 438a bics r2, r1 + 80079ce: 621a str r2, [r3, #32] + 80079d0: e01c b.n 8007a0c + 80079d2: 687b ldr r3, [r7, #4] + 80079d4: 689b ldr r3, [r3, #8] + 80079d6: 2b05 cmp r3, #5 + 80079d8: d10c bne.n 80079f4 + 80079da: 4bc2 ldr r3, [pc, #776] @ (8007ce4 ) + 80079dc: 6a1a ldr r2, [r3, #32] + 80079de: 4bc1 ldr r3, [pc, #772] @ (8007ce4 ) + 80079e0: 2104 movs r1, #4 + 80079e2: 430a orrs r2, r1 + 80079e4: 621a str r2, [r3, #32] + 80079e6: 4bbf ldr r3, [pc, #764] @ (8007ce4 ) + 80079e8: 6a1a ldr r2, [r3, #32] + 80079ea: 4bbe ldr r3, [pc, #760] @ (8007ce4 ) + 80079ec: 2101 movs r1, #1 + 80079ee: 430a orrs r2, r1 + 80079f0: 621a str r2, [r3, #32] + 80079f2: e00b b.n 8007a0c + 80079f4: 4bbb ldr r3, [pc, #748] @ (8007ce4 ) + 80079f6: 6a1a ldr r2, [r3, #32] + 80079f8: 4bba ldr r3, [pc, #744] @ (8007ce4 ) + 80079fa: 2101 movs r1, #1 + 80079fc: 438a bics r2, r1 + 80079fe: 621a str r2, [r3, #32] + 8007a00: 4bb8 ldr r3, [pc, #736] @ (8007ce4 ) + 8007a02: 6a1a ldr r2, [r3, #32] + 8007a04: 4bb7 ldr r3, [pc, #732] @ (8007ce4 ) + 8007a06: 2104 movs r1, #4 + 8007a08: 438a bics r2, r1 + 8007a0a: 621a str r2, [r3, #32] + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8007a0c: 687b ldr r3, [r7, #4] + 8007a0e: 689b ldr r3, [r3, #8] + 8007a10: 2b00 cmp r3, #0 + 8007a12: d014 beq.n 8007a3e + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007a14: f7fe ff6a bl 80068ec + 8007a18: 0003 movs r3, r0 + 8007a1a: 61bb str r3, [r7, #24] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007a1c: e009 b.n 8007a32 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8007a1e: f7fe ff65 bl 80068ec + 8007a22: 0002 movs r2, r0 + 8007a24: 69bb ldr r3, [r7, #24] + 8007a26: 1ad3 subs r3, r2, r3 + 8007a28: 4aaf ldr r2, [pc, #700] @ (8007ce8 ) + 8007a2a: 4293 cmp r3, r2 + 8007a2c: d901 bls.n 8007a32 + { + return HAL_TIMEOUT; + 8007a2e: 2303 movs r3, #3 + 8007a30: e19a b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007a32: 4bac ldr r3, [pc, #688] @ (8007ce4 ) + 8007a34: 6a1b ldr r3, [r3, #32] + 8007a36: 2202 movs r2, #2 + 8007a38: 4013 ands r3, r2 + 8007a3a: d0f0 beq.n 8007a1e + 8007a3c: e013 b.n 8007a66 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007a3e: f7fe ff55 bl 80068ec + 8007a42: 0003 movs r3, r0 + 8007a44: 61bb str r3, [r7, #24] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8007a46: e009 b.n 8007a5c + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8007a48: f7fe ff50 bl 80068ec + 8007a4c: 0002 movs r2, r0 + 8007a4e: 69bb ldr r3, [r7, #24] + 8007a50: 1ad3 subs r3, r2, r3 + 8007a52: 4aa5 ldr r2, [pc, #660] @ (8007ce8 ) + 8007a54: 4293 cmp r3, r2 + 8007a56: d901 bls.n 8007a5c + { + return HAL_TIMEOUT; + 8007a58: 2303 movs r3, #3 + 8007a5a: e185 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8007a5c: 4ba1 ldr r3, [pc, #644] @ (8007ce4 ) + 8007a5e: 6a1b ldr r3, [r3, #32] + 8007a60: 2202 movs r2, #2 + 8007a62: 4013 ands r3, r2 + 8007a64: d1f0 bne.n 8007a48 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 8007a66: 231f movs r3, #31 + 8007a68: 18fb adds r3, r7, r3 + 8007a6a: 781b ldrb r3, [r3, #0] + 8007a6c: 2b01 cmp r3, #1 + 8007a6e: d105 bne.n 8007a7c + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8007a70: 4b9c ldr r3, [pc, #624] @ (8007ce4 ) + 8007a72: 69da ldr r2, [r3, #28] + 8007a74: 4b9b ldr r3, [pc, #620] @ (8007ce4 ) + 8007a76: 499d ldr r1, [pc, #628] @ (8007cec ) + 8007a78: 400a ands r2, r1 + 8007a7a: 61da str r2, [r3, #28] + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + 8007a7c: 687b ldr r3, [r7, #4] + 8007a7e: 681b ldr r3, [r3, #0] + 8007a80: 2210 movs r2, #16 + 8007a82: 4013 ands r3, r2 + 8007a84: d063 beq.n 8007b4e + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + 8007a86: 687b ldr r3, [r7, #4] + 8007a88: 695b ldr r3, [r3, #20] + 8007a8a: 2b01 cmp r3, #1 + 8007a8c: d12a bne.n 8007ae4 + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + 8007a8e: 4b95 ldr r3, [pc, #596] @ (8007ce4 ) + 8007a90: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007a92: 4b94 ldr r3, [pc, #592] @ (8007ce4 ) + 8007a94: 2104 movs r1, #4 + 8007a96: 430a orrs r2, r1 + 8007a98: 635a str r2, [r3, #52] @ 0x34 + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + 8007a9a: 4b92 ldr r3, [pc, #584] @ (8007ce4 ) + 8007a9c: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007a9e: 4b91 ldr r3, [pc, #580] @ (8007ce4 ) + 8007aa0: 2101 movs r1, #1 + 8007aa2: 430a orrs r2, r1 + 8007aa4: 635a str r2, [r3, #52] @ 0x34 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007aa6: f7fe ff21 bl 80068ec + 8007aaa: 0003 movs r3, r0 + 8007aac: 61bb str r3, [r7, #24] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + 8007aae: e008 b.n 8007ac2 + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + 8007ab0: f7fe ff1c bl 80068ec + 8007ab4: 0002 movs r2, r0 + 8007ab6: 69bb ldr r3, [r7, #24] + 8007ab8: 1ad3 subs r3, r2, r3 + 8007aba: 2b02 cmp r3, #2 + 8007abc: d901 bls.n 8007ac2 + { + return HAL_TIMEOUT; + 8007abe: 2303 movs r3, #3 + 8007ac0: e152 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + 8007ac2: 4b88 ldr r3, [pc, #544] @ (8007ce4 ) + 8007ac4: 6b5b ldr r3, [r3, #52] @ 0x34 + 8007ac6: 2202 movs r2, #2 + 8007ac8: 4013 ands r3, r2 + 8007aca: d0f1 beq.n 8007ab0 + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + 8007acc: 4b85 ldr r3, [pc, #532] @ (8007ce4 ) + 8007ace: 6b5b ldr r3, [r3, #52] @ 0x34 + 8007ad0: 22f8 movs r2, #248 @ 0xf8 + 8007ad2: 4393 bics r3, r2 + 8007ad4: 0019 movs r1, r3 + 8007ad6: 687b ldr r3, [r7, #4] + 8007ad8: 699b ldr r3, [r3, #24] + 8007ada: 00da lsls r2, r3, #3 + 8007adc: 4b81 ldr r3, [pc, #516] @ (8007ce4 ) + 8007ade: 430a orrs r2, r1 + 8007ae0: 635a str r2, [r3, #52] @ 0x34 + 8007ae2: e034 b.n 8007b4e + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + 8007ae4: 687b ldr r3, [r7, #4] + 8007ae6: 695b ldr r3, [r3, #20] + 8007ae8: 3305 adds r3, #5 + 8007aea: d111 bne.n 8007b10 + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + 8007aec: 4b7d ldr r3, [pc, #500] @ (8007ce4 ) + 8007aee: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007af0: 4b7c ldr r3, [pc, #496] @ (8007ce4 ) + 8007af2: 2104 movs r1, #4 + 8007af4: 438a bics r2, r1 + 8007af6: 635a str r2, [r3, #52] @ 0x34 + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + 8007af8: 4b7a ldr r3, [pc, #488] @ (8007ce4 ) + 8007afa: 6b5b ldr r3, [r3, #52] @ 0x34 + 8007afc: 22f8 movs r2, #248 @ 0xf8 + 8007afe: 4393 bics r3, r2 + 8007b00: 0019 movs r1, r3 + 8007b02: 687b ldr r3, [r7, #4] + 8007b04: 699b ldr r3, [r3, #24] + 8007b06: 00da lsls r2, r3, #3 + 8007b08: 4b76 ldr r3, [pc, #472] @ (8007ce4 ) + 8007b0a: 430a orrs r2, r1 + 8007b0c: 635a str r2, [r3, #52] @ 0x34 + 8007b0e: e01e b.n 8007b4e + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + 8007b10: 4b74 ldr r3, [pc, #464] @ (8007ce4 ) + 8007b12: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007b14: 4b73 ldr r3, [pc, #460] @ (8007ce4 ) + 8007b16: 2104 movs r1, #4 + 8007b18: 430a orrs r2, r1 + 8007b1a: 635a str r2, [r3, #52] @ 0x34 + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + 8007b1c: 4b71 ldr r3, [pc, #452] @ (8007ce4 ) + 8007b1e: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007b20: 4b70 ldr r3, [pc, #448] @ (8007ce4 ) + 8007b22: 2101 movs r1, #1 + 8007b24: 438a bics r2, r1 + 8007b26: 635a str r2, [r3, #52] @ 0x34 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007b28: f7fe fee0 bl 80068ec + 8007b2c: 0003 movs r3, r0 + 8007b2e: 61bb str r3, [r7, #24] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + 8007b30: e008 b.n 8007b44 + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + 8007b32: f7fe fedb bl 80068ec + 8007b36: 0002 movs r2, r0 + 8007b38: 69bb ldr r3, [r7, #24] + 8007b3a: 1ad3 subs r3, r2, r3 + 8007b3c: 2b02 cmp r3, #2 + 8007b3e: d901 bls.n 8007b44 + { + return HAL_TIMEOUT; + 8007b40: 2303 movs r3, #3 + 8007b42: e111 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + 8007b44: 4b67 ldr r3, [pc, #412] @ (8007ce4 ) + 8007b46: 6b5b ldr r3, [r3, #52] @ 0x34 + 8007b48: 2202 movs r2, #2 + 8007b4a: 4013 ands r3, r2 + 8007b4c: d1f1 bne.n 8007b32 + } + } + +#if defined(RCC_HSI48_SUPPORT) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 8007b4e: 687b ldr r3, [r7, #4] + 8007b50: 681b ldr r3, [r3, #0] + 8007b52: 2220 movs r2, #32 + 8007b54: 4013 ands r3, r2 + 8007b56: d05c beq.n 8007c12 + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + 8007b58: 4b62 ldr r3, [pc, #392] @ (8007ce4 ) + 8007b5a: 685b ldr r3, [r3, #4] + 8007b5c: 220c movs r2, #12 + 8007b5e: 4013 ands r3, r2 + 8007b60: 2b0c cmp r3, #12 + 8007b62: d00e beq.n 8007b82 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + 8007b64: 4b5f ldr r3, [pc, #380] @ (8007ce4 ) + 8007b66: 685b ldr r3, [r3, #4] + 8007b68: 220c movs r2, #12 + 8007b6a: 4013 ands r3, r2 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + 8007b6c: 2b08 cmp r3, #8 + 8007b6e: d114 bne.n 8007b9a + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + 8007b70: 4b5c ldr r3, [pc, #368] @ (8007ce4 ) + 8007b72: 685a ldr r2, [r3, #4] + 8007b74: 23c0 movs r3, #192 @ 0xc0 + 8007b76: 025b lsls r3, r3, #9 + 8007b78: 401a ands r2, r3 + 8007b7a: 23c0 movs r3, #192 @ 0xc0 + 8007b7c: 025b lsls r3, r3, #9 + 8007b7e: 429a cmp r2, r3 + 8007b80: d10b bne.n 8007b9a + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + 8007b82: 4b58 ldr r3, [pc, #352] @ (8007ce4 ) + 8007b84: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007b86: 2380 movs r3, #128 @ 0x80 + 8007b88: 025b lsls r3, r3, #9 + 8007b8a: 4013 ands r3, r2 + 8007b8c: d040 beq.n 8007c10 + 8007b8e: 687b ldr r3, [r7, #4] + 8007b90: 6a1b ldr r3, [r3, #32] + 8007b92: 2b01 cmp r3, #1 + 8007b94: d03c beq.n 8007c10 + { + return HAL_ERROR; + 8007b96: 2301 movs r3, #1 + 8007b98: e0e6 b.n 8007d68 + } + } + else + { + /* Check the HSI48 State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 8007b9a: 687b ldr r3, [r7, #4] + 8007b9c: 6a1b ldr r3, [r3, #32] + 8007b9e: 2b00 cmp r3, #0 + 8007ba0: d01b beq.n 8007bda + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 8007ba2: 4b50 ldr r3, [pc, #320] @ (8007ce4 ) + 8007ba4: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007ba6: 4b4f ldr r3, [pc, #316] @ (8007ce4 ) + 8007ba8: 2180 movs r1, #128 @ 0x80 + 8007baa: 0249 lsls r1, r1, #9 + 8007bac: 430a orrs r2, r1 + 8007bae: 635a str r2, [r3, #52] @ 0x34 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007bb0: f7fe fe9c bl 80068ec + 8007bb4: 0003 movs r3, r0 + 8007bb6: 61bb str r3, [r7, #24] + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + 8007bb8: e008 b.n 8007bcc + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8007bba: f7fe fe97 bl 80068ec + 8007bbe: 0002 movs r2, r0 + 8007bc0: 69bb ldr r3, [r7, #24] + 8007bc2: 1ad3 subs r3, r2, r3 + 8007bc4: 2b02 cmp r3, #2 + 8007bc6: d901 bls.n 8007bcc + { + return HAL_TIMEOUT; + 8007bc8: 2303 movs r3, #3 + 8007bca: e0cd b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + 8007bcc: 4b45 ldr r3, [pc, #276] @ (8007ce4 ) + 8007bce: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007bd0: 2380 movs r3, #128 @ 0x80 + 8007bd2: 025b lsls r3, r3, #9 + 8007bd4: 4013 ands r3, r2 + 8007bd6: d0f0 beq.n 8007bba + 8007bd8: e01b b.n 8007c12 + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 8007bda: 4b42 ldr r3, [pc, #264] @ (8007ce4 ) + 8007bdc: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007bde: 4b41 ldr r3, [pc, #260] @ (8007ce4 ) + 8007be0: 4943 ldr r1, [pc, #268] @ (8007cf0 ) + 8007be2: 400a ands r2, r1 + 8007be4: 635a str r2, [r3, #52] @ 0x34 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007be6: f7fe fe81 bl 80068ec + 8007bea: 0003 movs r3, r0 + 8007bec: 61bb str r3, [r7, #24] + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + 8007bee: e008 b.n 8007c02 + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8007bf0: f7fe fe7c bl 80068ec + 8007bf4: 0002 movs r2, r0 + 8007bf6: 69bb ldr r3, [r7, #24] + 8007bf8: 1ad3 subs r3, r2, r3 + 8007bfa: 2b02 cmp r3, #2 + 8007bfc: d901 bls.n 8007c02 + { + return HAL_TIMEOUT; + 8007bfe: 2303 movs r3, #3 + 8007c00: e0b2 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + 8007c02: 4b38 ldr r3, [pc, #224] @ (8007ce4 ) + 8007c04: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007c06: 2380 movs r3, #128 @ 0x80 + 8007c08: 025b lsls r3, r3, #9 + 8007c0a: 4013 ands r3, r2 + 8007c0c: d1f0 bne.n 8007bf0 + 8007c0e: e000 b.n 8007c12 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + 8007c10: 46c0 nop @ (mov r8, r8) +#endif /* RCC_HSI48_SUPPORT */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8007c12: 687b ldr r3, [r7, #4] + 8007c14: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007c16: 2b00 cmp r3, #0 + 8007c18: d100 bne.n 8007c1c + 8007c1a: e0a4 b.n 8007d66 + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8007c1c: 4b31 ldr r3, [pc, #196] @ (8007ce4 ) + 8007c1e: 685b ldr r3, [r3, #4] + 8007c20: 220c movs r2, #12 + 8007c22: 4013 ands r3, r2 + 8007c24: 2b08 cmp r3, #8 + 8007c26: d100 bne.n 8007c2a + 8007c28: e078 b.n 8007d1c + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8007c2a: 687b ldr r3, [r7, #4] + 8007c2c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007c2e: 2b02 cmp r3, #2 + 8007c30: d14c bne.n 8007ccc + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8007c32: 4b2c ldr r3, [pc, #176] @ (8007ce4 ) + 8007c34: 681a ldr r2, [r3, #0] + 8007c36: 4b2b ldr r3, [pc, #172] @ (8007ce4 ) + 8007c38: 492e ldr r1, [pc, #184] @ (8007cf4 ) + 8007c3a: 400a ands r2, r1 + 8007c3c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007c3e: f7fe fe55 bl 80068ec + 8007c42: 0003 movs r3, r0 + 8007c44: 61bb str r3, [r7, #24] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007c46: e008 b.n 8007c5a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8007c48: f7fe fe50 bl 80068ec + 8007c4c: 0002 movs r2, r0 + 8007c4e: 69bb ldr r3, [r7, #24] + 8007c50: 1ad3 subs r3, r2, r3 + 8007c52: 2b02 cmp r3, #2 + 8007c54: d901 bls.n 8007c5a + { + return HAL_TIMEOUT; + 8007c56: 2303 movs r3, #3 + 8007c58: e086 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007c5a: 4b22 ldr r3, [pc, #136] @ (8007ce4 ) + 8007c5c: 681a ldr r2, [r3, #0] + 8007c5e: 2380 movs r3, #128 @ 0x80 + 8007c60: 049b lsls r3, r3, #18 + 8007c62: 4013 ands r3, r2 + 8007c64: d1f0 bne.n 8007c48 + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8007c66: 4b1f ldr r3, [pc, #124] @ (8007ce4 ) + 8007c68: 6adb ldr r3, [r3, #44] @ 0x2c + 8007c6a: 220f movs r2, #15 + 8007c6c: 4393 bics r3, r2 + 8007c6e: 0019 movs r1, r3 + 8007c70: 687b ldr r3, [r7, #4] + 8007c72: 6b1a ldr r2, [r3, #48] @ 0x30 + 8007c74: 4b1b ldr r3, [pc, #108] @ (8007ce4 ) + 8007c76: 430a orrs r2, r1 + 8007c78: 62da str r2, [r3, #44] @ 0x2c + 8007c7a: 4b1a ldr r3, [pc, #104] @ (8007ce4 ) + 8007c7c: 685b ldr r3, [r3, #4] + 8007c7e: 4a1e ldr r2, [pc, #120] @ (8007cf8 ) + 8007c80: 4013 ands r3, r2 + 8007c82: 0019 movs r1, r3 + 8007c84: 687b ldr r3, [r7, #4] + 8007c86: 6ada ldr r2, [r3, #44] @ 0x2c + 8007c88: 687b ldr r3, [r7, #4] + 8007c8a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007c8c: 431a orrs r2, r3 + 8007c8e: 4b15 ldr r3, [pc, #84] @ (8007ce4 ) + 8007c90: 430a orrs r2, r1 + 8007c92: 605a str r2, [r3, #4] + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8007c94: 4b13 ldr r3, [pc, #76] @ (8007ce4 ) + 8007c96: 681a ldr r2, [r3, #0] + 8007c98: 4b12 ldr r3, [pc, #72] @ (8007ce4 ) + 8007c9a: 2180 movs r1, #128 @ 0x80 + 8007c9c: 0449 lsls r1, r1, #17 + 8007c9e: 430a orrs r2, r1 + 8007ca0: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007ca2: f7fe fe23 bl 80068ec + 8007ca6: 0003 movs r3, r0 + 8007ca8: 61bb str r3, [r7, #24] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007caa: e008 b.n 8007cbe + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8007cac: f7fe fe1e bl 80068ec + 8007cb0: 0002 movs r2, r0 + 8007cb2: 69bb ldr r3, [r7, #24] + 8007cb4: 1ad3 subs r3, r2, r3 + 8007cb6: 2b02 cmp r3, #2 + 8007cb8: d901 bls.n 8007cbe + { + return HAL_TIMEOUT; + 8007cba: 2303 movs r3, #3 + 8007cbc: e054 b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007cbe: 4b09 ldr r3, [pc, #36] @ (8007ce4 ) + 8007cc0: 681a ldr r2, [r3, #0] + 8007cc2: 2380 movs r3, #128 @ 0x80 + 8007cc4: 049b lsls r3, r3, #18 + 8007cc6: 4013 ands r3, r2 + 8007cc8: d0f0 beq.n 8007cac + 8007cca: e04c b.n 8007d66 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8007ccc: 4b05 ldr r3, [pc, #20] @ (8007ce4 ) + 8007cce: 681a ldr r2, [r3, #0] + 8007cd0: 4b04 ldr r3, [pc, #16] @ (8007ce4 ) + 8007cd2: 4908 ldr r1, [pc, #32] @ (8007cf4 ) + 8007cd4: 400a ands r2, r1 + 8007cd6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007cd8: f7fe fe08 bl 80068ec + 8007cdc: 0003 movs r3, r0 + 8007cde: 61bb str r3, [r7, #24] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007ce0: e015 b.n 8007d0e + 8007ce2: 46c0 nop @ (mov r8, r8) + 8007ce4: 40021000 .word 0x40021000 + 8007ce8: 00001388 .word 0x00001388 + 8007cec: efffffff .word 0xefffffff + 8007cf0: fffeffff .word 0xfffeffff + 8007cf4: feffffff .word 0xfeffffff + 8007cf8: ffc27fff .word 0xffc27fff + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8007cfc: f7fe fdf6 bl 80068ec + 8007d00: 0002 movs r2, r0 + 8007d02: 69bb ldr r3, [r7, #24] + 8007d04: 1ad3 subs r3, r2, r3 + 8007d06: 2b02 cmp r3, #2 + 8007d08: d901 bls.n 8007d0e + { + return HAL_TIMEOUT; + 8007d0a: 2303 movs r3, #3 + 8007d0c: e02c b.n 8007d68 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007d0e: 4b18 ldr r3, [pc, #96] @ (8007d70 ) + 8007d10: 681a ldr r2, [r3, #0] + 8007d12: 2380 movs r3, #128 @ 0x80 + 8007d14: 049b lsls r3, r3, #18 + 8007d16: 4013 ands r3, r2 + 8007d18: d1f0 bne.n 8007cfc + 8007d1a: e024 b.n 8007d66 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8007d1c: 687b ldr r3, [r7, #4] + 8007d1e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8007d20: 2b01 cmp r3, #1 + 8007d22: d101 bne.n 8007d28 + { + return HAL_ERROR; + 8007d24: 2301 movs r3, #1 + 8007d26: e01f b.n 8007d68 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8007d28: 4b11 ldr r3, [pc, #68] @ (8007d70 ) + 8007d2a: 685b ldr r3, [r3, #4] + 8007d2c: 617b str r3, [r7, #20] + pll_config2 = RCC->CFGR2; + 8007d2e: 4b10 ldr r3, [pc, #64] @ (8007d70 ) + 8007d30: 6adb ldr r3, [r3, #44] @ 0x2c + 8007d32: 613b str r3, [r7, #16] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8007d34: 697a ldr r2, [r7, #20] + 8007d36: 23c0 movs r3, #192 @ 0xc0 + 8007d38: 025b lsls r3, r3, #9 + 8007d3a: 401a ands r2, r3 + 8007d3c: 687b ldr r3, [r7, #4] + 8007d3e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8007d40: 429a cmp r2, r3 + 8007d42: d10e bne.n 8007d62 + (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || + 8007d44: 693b ldr r3, [r7, #16] + 8007d46: 220f movs r2, #15 + 8007d48: 401a ands r2, r3 + 8007d4a: 687b ldr r3, [r7, #4] + 8007d4c: 6b1b ldr r3, [r3, #48] @ 0x30 + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8007d4e: 429a cmp r2, r3 + 8007d50: d107 bne.n 8007d62 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 8007d52: 697a ldr r2, [r7, #20] + 8007d54: 23f0 movs r3, #240 @ 0xf0 + 8007d56: 039b lsls r3, r3, #14 + 8007d58: 401a ands r2, r3 + 8007d5a: 687b ldr r3, [r7, #4] + 8007d5c: 6adb ldr r3, [r3, #44] @ 0x2c + (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || + 8007d5e: 429a cmp r2, r3 + 8007d60: d001 beq.n 8007d66 + { + return HAL_ERROR; + 8007d62: 2301 movs r3, #1 + 8007d64: e000 b.n 8007d68 + } + } + } + } + + return HAL_OK; + 8007d66: 2300 movs r3, #0 +} + 8007d68: 0018 movs r0, r3 + 8007d6a: 46bd mov sp, r7 + 8007d6c: b008 add sp, #32 + 8007d6e: bd80 pop {r7, pc} + 8007d70: 40021000 .word 0x40021000 + +08007d74 : + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8007d74: b580 push {r7, lr} + 8007d76: b084 sub sp, #16 + 8007d78: af00 add r7, sp, #0 + 8007d7a: 6078 str r0, [r7, #4] + 8007d7c: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8007d7e: 687b ldr r3, [r7, #4] + 8007d80: 2b00 cmp r3, #0 + 8007d82: d101 bne.n 8007d88 + { + return HAL_ERROR; + 8007d84: 2301 movs r3, #1 + 8007d86: e0bf b.n 8007f08 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8007d88: 4b61 ldr r3, [pc, #388] @ (8007f10 ) + 8007d8a: 681b ldr r3, [r3, #0] + 8007d8c: 2201 movs r2, #1 + 8007d8e: 4013 ands r3, r2 + 8007d90: 683a ldr r2, [r7, #0] + 8007d92: 429a cmp r2, r3 + 8007d94: d911 bls.n 8007dba + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8007d96: 4b5e ldr r3, [pc, #376] @ (8007f10 ) + 8007d98: 681b ldr r3, [r3, #0] + 8007d9a: 2201 movs r2, #1 + 8007d9c: 4393 bics r3, r2 + 8007d9e: 0019 movs r1, r3 + 8007da0: 4b5b ldr r3, [pc, #364] @ (8007f10 ) + 8007da2: 683a ldr r2, [r7, #0] + 8007da4: 430a orrs r2, r1 + 8007da6: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8007da8: 4b59 ldr r3, [pc, #356] @ (8007f10 ) + 8007daa: 681b ldr r3, [r3, #0] + 8007dac: 2201 movs r2, #1 + 8007dae: 4013 ands r3, r2 + 8007db0: 683a ldr r2, [r7, #0] + 8007db2: 429a cmp r2, r3 + 8007db4: d001 beq.n 8007dba + { + return HAL_ERROR; + 8007db6: 2301 movs r3, #1 + 8007db8: e0a6 b.n 8007f08 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8007dba: 687b ldr r3, [r7, #4] + 8007dbc: 681b ldr r3, [r3, #0] + 8007dbe: 2202 movs r2, #2 + 8007dc0: 4013 ands r3, r2 + 8007dc2: d015 beq.n 8007df0 + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8007dc4: 687b ldr r3, [r7, #4] + 8007dc6: 681b ldr r3, [r3, #0] + 8007dc8: 2204 movs r2, #4 + 8007dca: 4013 ands r3, r2 + 8007dcc: d006 beq.n 8007ddc + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + 8007dce: 4b51 ldr r3, [pc, #324] @ (8007f14 ) + 8007dd0: 685a ldr r2, [r3, #4] + 8007dd2: 4b50 ldr r3, [pc, #320] @ (8007f14 ) + 8007dd4: 21e0 movs r1, #224 @ 0xe0 + 8007dd6: 00c9 lsls r1, r1, #3 + 8007dd8: 430a orrs r2, r1 + 8007dda: 605a str r2, [r3, #4] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8007ddc: 4b4d ldr r3, [pc, #308] @ (8007f14 ) + 8007dde: 685b ldr r3, [r3, #4] + 8007de0: 22f0 movs r2, #240 @ 0xf0 + 8007de2: 4393 bics r3, r2 + 8007de4: 0019 movs r1, r3 + 8007de6: 687b ldr r3, [r7, #4] + 8007de8: 689a ldr r2, [r3, #8] + 8007dea: 4b4a ldr r3, [pc, #296] @ (8007f14 ) + 8007dec: 430a orrs r2, r1 + 8007dee: 605a str r2, [r3, #4] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8007df0: 687b ldr r3, [r7, #4] + 8007df2: 681b ldr r3, [r3, #0] + 8007df4: 2201 movs r2, #1 + 8007df6: 4013 ands r3, r2 + 8007df8: d04c beq.n 8007e94 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8007dfa: 687b ldr r3, [r7, #4] + 8007dfc: 685b ldr r3, [r3, #4] + 8007dfe: 2b01 cmp r3, #1 + 8007e00: d107 bne.n 8007e12 + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8007e02: 4b44 ldr r3, [pc, #272] @ (8007f14 ) + 8007e04: 681a ldr r2, [r3, #0] + 8007e06: 2380 movs r3, #128 @ 0x80 + 8007e08: 029b lsls r3, r3, #10 + 8007e0a: 4013 ands r3, r2 + 8007e0c: d120 bne.n 8007e50 + { + return HAL_ERROR; + 8007e0e: 2301 movs r3, #1 + 8007e10: e07a b.n 8007f08 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8007e12: 687b ldr r3, [r7, #4] + 8007e14: 685b ldr r3, [r3, #4] + 8007e16: 2b02 cmp r3, #2 + 8007e18: d107 bne.n 8007e2a + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007e1a: 4b3e ldr r3, [pc, #248] @ (8007f14 ) + 8007e1c: 681a ldr r2, [r3, #0] + 8007e1e: 2380 movs r3, #128 @ 0x80 + 8007e20: 049b lsls r3, r3, #18 + 8007e22: 4013 ands r3, r2 + 8007e24: d114 bne.n 8007e50 + { + return HAL_ERROR; + 8007e26: 2301 movs r3, #1 + 8007e28: e06e b.n 8007f08 + } + } +#if defined(RCC_CFGR_SWS_HSI48) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + 8007e2a: 687b ldr r3, [r7, #4] + 8007e2c: 685b ldr r3, [r3, #4] + 8007e2e: 2b03 cmp r3, #3 + 8007e30: d107 bne.n 8007e42 + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + 8007e32: 4b38 ldr r3, [pc, #224] @ (8007f14 ) + 8007e34: 6b5a ldr r2, [r3, #52] @ 0x34 + 8007e36: 2380 movs r3, #128 @ 0x80 + 8007e38: 025b lsls r3, r3, #9 + 8007e3a: 4013 ands r3, r2 + 8007e3c: d108 bne.n 8007e50 + { + return HAL_ERROR; + 8007e3e: 2301 movs r3, #1 + 8007e40: e062 b.n 8007f08 +#endif /* RCC_CFGR_SWS_HSI48 */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007e42: 4b34 ldr r3, [pc, #208] @ (8007f14 ) + 8007e44: 681b ldr r3, [r3, #0] + 8007e46: 2202 movs r2, #2 + 8007e48: 4013 ands r3, r2 + 8007e4a: d101 bne.n 8007e50 + { + return HAL_ERROR; + 8007e4c: 2301 movs r3, #1 + 8007e4e: e05b b.n 8007f08 + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8007e50: 4b30 ldr r3, [pc, #192] @ (8007f14 ) + 8007e52: 685b ldr r3, [r3, #4] + 8007e54: 2203 movs r2, #3 + 8007e56: 4393 bics r3, r2 + 8007e58: 0019 movs r1, r3 + 8007e5a: 687b ldr r3, [r7, #4] + 8007e5c: 685a ldr r2, [r3, #4] + 8007e5e: 4b2d ldr r3, [pc, #180] @ (8007f14 ) + 8007e60: 430a orrs r2, r1 + 8007e62: 605a str r2, [r3, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8007e64: f7fe fd42 bl 80068ec + 8007e68: 0003 movs r3, r0 + 8007e6a: 60fb str r3, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8007e6c: e009 b.n 8007e82 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8007e6e: f7fe fd3d bl 80068ec + 8007e72: 0002 movs r2, r0 + 8007e74: 68fb ldr r3, [r7, #12] + 8007e76: 1ad3 subs r3, r2, r3 + 8007e78: 4a27 ldr r2, [pc, #156] @ (8007f18 ) + 8007e7a: 4293 cmp r3, r2 + 8007e7c: d901 bls.n 8007e82 + { + return HAL_TIMEOUT; + 8007e7e: 2303 movs r3, #3 + 8007e80: e042 b.n 8007f08 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8007e82: 4b24 ldr r3, [pc, #144] @ (8007f14 ) + 8007e84: 685b ldr r3, [r3, #4] + 8007e86: 220c movs r2, #12 + 8007e88: 401a ands r2, r3 + 8007e8a: 687b ldr r3, [r7, #4] + 8007e8c: 685b ldr r3, [r3, #4] + 8007e8e: 009b lsls r3, r3, #2 + 8007e90: 429a cmp r2, r3 + 8007e92: d1ec bne.n 8007e6e + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8007e94: 4b1e ldr r3, [pc, #120] @ (8007f10 ) + 8007e96: 681b ldr r3, [r3, #0] + 8007e98: 2201 movs r2, #1 + 8007e9a: 4013 ands r3, r2 + 8007e9c: 683a ldr r2, [r7, #0] + 8007e9e: 429a cmp r2, r3 + 8007ea0: d211 bcs.n 8007ec6 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8007ea2: 4b1b ldr r3, [pc, #108] @ (8007f10 ) + 8007ea4: 681b ldr r3, [r3, #0] + 8007ea6: 2201 movs r2, #1 + 8007ea8: 4393 bics r3, r2 + 8007eaa: 0019 movs r1, r3 + 8007eac: 4b18 ldr r3, [pc, #96] @ (8007f10 ) + 8007eae: 683a ldr r2, [r7, #0] + 8007eb0: 430a orrs r2, r1 + 8007eb2: 601a str r2, [r3, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8007eb4: 4b16 ldr r3, [pc, #88] @ (8007f10 ) + 8007eb6: 681b ldr r3, [r3, #0] + 8007eb8: 2201 movs r2, #1 + 8007eba: 4013 ands r3, r2 + 8007ebc: 683a ldr r2, [r7, #0] + 8007ebe: 429a cmp r2, r3 + 8007ec0: d001 beq.n 8007ec6 + { + return HAL_ERROR; + 8007ec2: 2301 movs r3, #1 + 8007ec4: e020 b.n 8007f08 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8007ec6: 687b ldr r3, [r7, #4] + 8007ec8: 681b ldr r3, [r3, #0] + 8007eca: 2204 movs r2, #4 + 8007ecc: 4013 ands r3, r2 + 8007ece: d009 beq.n 8007ee4 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + 8007ed0: 4b10 ldr r3, [pc, #64] @ (8007f14 ) + 8007ed2: 685b ldr r3, [r3, #4] + 8007ed4: 4a11 ldr r2, [pc, #68] @ (8007f1c ) + 8007ed6: 4013 ands r3, r2 + 8007ed8: 0019 movs r1, r3 + 8007eda: 687b ldr r3, [r7, #4] + 8007edc: 68da ldr r2, [r3, #12] + 8007ede: 4b0d ldr r3, [pc, #52] @ (8007f14 ) + 8007ee0: 430a orrs r2, r1 + 8007ee2: 605a str r2, [r3, #4] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + 8007ee4: f000 f820 bl 8007f28 + 8007ee8: 0001 movs r1, r0 + 8007eea: 4b0a ldr r3, [pc, #40] @ (8007f14 ) + 8007eec: 685b ldr r3, [r3, #4] + 8007eee: 091b lsrs r3, r3, #4 + 8007ef0: 220f movs r2, #15 + 8007ef2: 4013 ands r3, r2 + 8007ef4: 4a0a ldr r2, [pc, #40] @ (8007f20 ) + 8007ef6: 5cd3 ldrb r3, [r2, r3] + 8007ef8: 000a movs r2, r1 + 8007efa: 40da lsrs r2, r3 + 8007efc: 4b09 ldr r3, [pc, #36] @ (8007f24 ) + 8007efe: 601a str r2, [r3, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + 8007f00: 2000 movs r0, #0 + 8007f02: f7fe fcad bl 8006860 + + return HAL_OK; + 8007f06: 2300 movs r3, #0 +} + 8007f08: 0018 movs r0, r3 + 8007f0a: 46bd mov sp, r7 + 8007f0c: b004 add sp, #16 + 8007f0e: bd80 pop {r7, pc} + 8007f10: 40022000 .word 0x40022000 + 8007f14: 40021000 .word 0x40021000 + 8007f18: 00001388 .word 0x00001388 + 8007f1c: fffff8ff .word 0xfffff8ff + 8007f20: 08008ae0 .word 0x08008ae0 + 8007f24: 20000004 .word 0x20000004 + +08007f28 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8007f28: b590 push {r4, r7, lr} + 8007f2a: b08f sub sp, #60 @ 0x3c + 8007f2c: af00 add r7, sp, #0 + const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 8007f2e: 2314 movs r3, #20 + 8007f30: 18fb adds r3, r7, r3 + 8007f32: 4a38 ldr r2, [pc, #224] @ (8008014 ) + 8007f34: ca13 ldmia r2!, {r0, r1, r4} + 8007f36: c313 stmia r3!, {r0, r1, r4} + 8007f38: 6812 ldr r2, [r2, #0] + 8007f3a: 601a str r2, [r3, #0] + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 8007f3c: 1d3b adds r3, r7, #4 + 8007f3e: 4a36 ldr r2, [pc, #216] @ (8008018 ) + 8007f40: ca13 ldmia r2!, {r0, r1, r4} + 8007f42: c313 stmia r3!, {r0, r1, r4} + 8007f44: 6812 ldr r2, [r2, #0] + 8007f46: 601a str r2, [r3, #0] + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 8007f48: 2300 movs r3, #0 + 8007f4a: 62fb str r3, [r7, #44] @ 0x2c + 8007f4c: 2300 movs r3, #0 + 8007f4e: 62bb str r3, [r7, #40] @ 0x28 + 8007f50: 2300 movs r3, #0 + 8007f52: 637b str r3, [r7, #52] @ 0x34 + 8007f54: 2300 movs r3, #0 + 8007f56: 627b str r3, [r7, #36] @ 0x24 + uint32_t sysclockfreq = 0U; + 8007f58: 2300 movs r3, #0 + 8007f5a: 633b str r3, [r7, #48] @ 0x30 + + tmpreg = RCC->CFGR; + 8007f5c: 4b2f ldr r3, [pc, #188] @ (800801c ) + 8007f5e: 685b ldr r3, [r3, #4] + 8007f60: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8007f62: 6afb ldr r3, [r7, #44] @ 0x2c + 8007f64: 220c movs r2, #12 + 8007f66: 4013 ands r3, r2 + 8007f68: 2b0c cmp r3, #12 + 8007f6a: d047 beq.n 8007ffc + 8007f6c: d849 bhi.n 8008002 + 8007f6e: 2b04 cmp r3, #4 + 8007f70: d002 beq.n 8007f78 + 8007f72: 2b08 cmp r3, #8 + 8007f74: d003 beq.n 8007f7e + 8007f76: e044 b.n 8008002 + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8007f78: 4b29 ldr r3, [pc, #164] @ (8008020 ) + 8007f7a: 633b str r3, [r7, #48] @ 0x30 + break; + 8007f7c: e044 b.n 8008008 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + 8007f7e: 6afb ldr r3, [r7, #44] @ 0x2c + 8007f80: 0c9b lsrs r3, r3, #18 + 8007f82: 220f movs r2, #15 + 8007f84: 4013 ands r3, r2 + 8007f86: 2214 movs r2, #20 + 8007f88: 18ba adds r2, r7, r2 + 8007f8a: 5cd3 ldrb r3, [r2, r3] + 8007f8c: 627b str r3, [r7, #36] @ 0x24 + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + 8007f8e: 4b23 ldr r3, [pc, #140] @ (800801c ) + 8007f90: 6adb ldr r3, [r3, #44] @ 0x2c + 8007f92: 220f movs r2, #15 + 8007f94: 4013 ands r3, r2 + 8007f96: 1d3a adds r2, r7, #4 + 8007f98: 5cd3 ldrb r3, [r2, r3] + 8007f9a: 62bb str r3, [r7, #40] @ 0x28 + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + 8007f9c: 6afa ldr r2, [r7, #44] @ 0x2c + 8007f9e: 23c0 movs r3, #192 @ 0xc0 + 8007fa0: 025b lsls r3, r3, #9 + 8007fa2: 401a ands r2, r3 + 8007fa4: 2380 movs r3, #128 @ 0x80 + 8007fa6: 025b lsls r3, r3, #9 + 8007fa8: 429a cmp r2, r3 + 8007faa: d109 bne.n 8007fc0 + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 8007fac: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8007fae: 481c ldr r0, [pc, #112] @ (8008020 ) + 8007fb0: f7f8 f8aa bl 8000108 <__udivsi3> + 8007fb4: 0003 movs r3, r0 + 8007fb6: 001a movs r2, r3 + 8007fb8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007fba: 4353 muls r3, r2 + 8007fbc: 637b str r3, [r7, #52] @ 0x34 + 8007fbe: e01a b.n 8007ff6 + } +#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + 8007fc0: 6afa ldr r2, [r7, #44] @ 0x2c + 8007fc2: 23c0 movs r3, #192 @ 0xc0 + 8007fc4: 025b lsls r3, r3, #9 + 8007fc6: 401a ands r2, r3 + 8007fc8: 23c0 movs r3, #192 @ 0xc0 + 8007fca: 025b lsls r3, r3, #9 + 8007fcc: 429a cmp r2, r3 + 8007fce: d109 bne.n 8007fe4 + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 8007fd0: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8007fd2: 4814 ldr r0, [pc, #80] @ (8008024 ) + 8007fd4: f7f8 f898 bl 8000108 <__udivsi3> + 8007fd8: 0003 movs r3, r0 + 8007fda: 001a movs r2, r3 + 8007fdc: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007fde: 4353 muls r3, r2 + 8007fe0: 637b str r3, [r7, #52] @ 0x34 + 8007fe2: e008 b.n 8007ff6 +#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ + else + { +#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 8007fe4: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8007fe6: 480e ldr r0, [pc, #56] @ (8008020 ) + 8007fe8: f7f8 f88e bl 8000108 <__udivsi3> + 8007fec: 0003 movs r3, r0 + 8007fee: 001a movs r2, r3 + 8007ff0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007ff2: 4353 muls r3, r2 + 8007ff4: 637b str r3, [r7, #52] @ 0x34 +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); +#endif + } + sysclockfreq = pllclk; + 8007ff6: 6b7b ldr r3, [r7, #52] @ 0x34 + 8007ff8: 633b str r3, [r7, #48] @ 0x30 + break; + 8007ffa: e005 b.n 8008008 + } +#if defined(RCC_CFGR_SWS_HSI48) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + { + sysclockfreq = HSI48_VALUE; + 8007ffc: 4b09 ldr r3, [pc, #36] @ (8008024 ) + 8007ffe: 633b str r3, [r7, #48] @ 0x30 + break; + 8008000: e002 b.n 8008008 + } +#endif /* RCC_CFGR_SWS_HSI48 */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + 8008002: 4b07 ldr r3, [pc, #28] @ (8008020 ) + 8008004: 633b str r3, [r7, #48] @ 0x30 + break; + 8008006: 46c0 nop @ (mov r8, r8) + } + } + return sysclockfreq; + 8008008: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 800800a: 0018 movs r0, r3 + 800800c: 46bd mov sp, r7 + 800800e: b00f add sp, #60 @ 0x3c + 8008010: bd90 pop {r4, r7, pc} + 8008012: 46c0 nop @ (mov r8, r8) + 8008014: 08008994 .word 0x08008994 + 8008018: 080089a4 .word 0x080089a4 + 800801c: 40021000 .word 0x40021000 + 8008020: 007a1200 .word 0x007a1200 + 8008024: 02dc6c00 .word 0x02dc6c00 + +08008028 : + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8008028: b580 push {r7, lr} + 800802a: af00 add r7, sp, #0 + return SystemCoreClock; + 800802c: 4b02 ldr r3, [pc, #8] @ (8008038 ) + 800802e: 681b ldr r3, [r3, #0] +} + 8008030: 0018 movs r0, r3 + 8008032: 46bd mov sp, r7 + 8008034: bd80 pop {r7, pc} + 8008036: 46c0 nop @ (mov r8, r8) + 8008038: 20000004 .word 0x20000004 + +0800803c : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 800803c: b580 push {r7, lr} + 800803e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); + 8008040: f7ff fff2 bl 8008028 + 8008044: 0001 movs r1, r0 + 8008046: 4b06 ldr r3, [pc, #24] @ (8008060 ) + 8008048: 685b ldr r3, [r3, #4] + 800804a: 0a1b lsrs r3, r3, #8 + 800804c: 2207 movs r2, #7 + 800804e: 4013 ands r3, r2 + 8008050: 4a04 ldr r2, [pc, #16] @ (8008064 ) + 8008052: 5cd3 ldrb r3, [r2, r3] + 8008054: 40d9 lsrs r1, r3 + 8008056: 000b movs r3, r1 +} + 8008058: 0018 movs r0, r3 + 800805a: 46bd mov sp, r7 + 800805c: bd80 pop {r7, pc} + 800805e: 46c0 nop @ (mov r8, r8) + 8008060: 40021000 .word 0x40021000 + 8008064: 08008af0 .word 0x08008af0 + +08008068 : + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8008068: b580 push {r7, lr} + 800806a: b086 sub sp, #24 + 800806c: af00 add r7, sp, #0 + 800806e: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8008070: 2300 movs r3, #0 + 8008072: 613b str r3, [r7, #16] + uint32_t temp_reg = 0U; + 8008074: 2300 movs r3, #0 + 8008076: 60fb str r3, [r7, #12] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8008078: 687b ldr r3, [r7, #4] + 800807a: 681a ldr r2, [r3, #0] + 800807c: 2380 movs r3, #128 @ 0x80 + 800807e: 025b lsls r3, r3, #9 + 8008080: 4013 ands r3, r2 + 8008082: d100 bne.n 8008086 + 8008084: e08e b.n 80081a4 + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + 8008086: 2017 movs r0, #23 + 8008088: 183b adds r3, r7, r0 + 800808a: 2200 movs r2, #0 + 800808c: 701a strb r2, [r3, #0] + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800808e: 4b6e ldr r3, [pc, #440] @ (8008248 ) + 8008090: 69da ldr r2, [r3, #28] + 8008092: 2380 movs r3, #128 @ 0x80 + 8008094: 055b lsls r3, r3, #21 + 8008096: 4013 ands r3, r2 + 8008098: d110 bne.n 80080bc + { + __HAL_RCC_PWR_CLK_ENABLE(); + 800809a: 4b6b ldr r3, [pc, #428] @ (8008248 ) + 800809c: 69da ldr r2, [r3, #28] + 800809e: 4b6a ldr r3, [pc, #424] @ (8008248 ) + 80080a0: 2180 movs r1, #128 @ 0x80 + 80080a2: 0549 lsls r1, r1, #21 + 80080a4: 430a orrs r2, r1 + 80080a6: 61da str r2, [r3, #28] + 80080a8: 4b67 ldr r3, [pc, #412] @ (8008248 ) + 80080aa: 69da ldr r2, [r3, #28] + 80080ac: 2380 movs r3, #128 @ 0x80 + 80080ae: 055b lsls r3, r3, #21 + 80080b0: 4013 ands r3, r2 + 80080b2: 60bb str r3, [r7, #8] + 80080b4: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 80080b6: 183b adds r3, r7, r0 + 80080b8: 2201 movs r2, #1 + 80080ba: 701a strb r2, [r3, #0] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80080bc: 4b63 ldr r3, [pc, #396] @ (800824c ) + 80080be: 681a ldr r2, [r3, #0] + 80080c0: 2380 movs r3, #128 @ 0x80 + 80080c2: 005b lsls r3, r3, #1 + 80080c4: 4013 ands r3, r2 + 80080c6: d11a bne.n 80080fe + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80080c8: 4b60 ldr r3, [pc, #384] @ (800824c ) + 80080ca: 681a ldr r2, [r3, #0] + 80080cc: 4b5f ldr r3, [pc, #380] @ (800824c ) + 80080ce: 2180 movs r1, #128 @ 0x80 + 80080d0: 0049 lsls r1, r1, #1 + 80080d2: 430a orrs r2, r1 + 80080d4: 601a str r2, [r3, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80080d6: f7fe fc09 bl 80068ec + 80080da: 0003 movs r3, r0 + 80080dc: 613b str r3, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80080de: e008 b.n 80080f2 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80080e0: f7fe fc04 bl 80068ec + 80080e4: 0002 movs r2, r0 + 80080e6: 693b ldr r3, [r7, #16] + 80080e8: 1ad3 subs r3, r2, r3 + 80080ea: 2b64 cmp r3, #100 @ 0x64 + 80080ec: d901 bls.n 80080f2 + { + return HAL_TIMEOUT; + 80080ee: 2303 movs r3, #3 + 80080f0: e0a6 b.n 8008240 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80080f2: 4b56 ldr r3, [pc, #344] @ (800824c ) + 80080f4: 681a ldr r2, [r3, #0] + 80080f6: 2380 movs r3, #128 @ 0x80 + 80080f8: 005b lsls r3, r3, #1 + 80080fa: 4013 ands r3, r2 + 80080fc: d0f0 beq.n 80080e0 + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 80080fe: 4b52 ldr r3, [pc, #328] @ (8008248 ) + 8008100: 6a1a ldr r2, [r3, #32] + 8008102: 23c0 movs r3, #192 @ 0xc0 + 8008104: 009b lsls r3, r3, #2 + 8008106: 4013 ands r3, r2 + 8008108: 60fb str r3, [r7, #12] + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 800810a: 68fb ldr r3, [r7, #12] + 800810c: 2b00 cmp r3, #0 + 800810e: d034 beq.n 800817a + 8008110: 687b ldr r3, [r7, #4] + 8008112: 685a ldr r2, [r3, #4] + 8008114: 23c0 movs r3, #192 @ 0xc0 + 8008116: 009b lsls r3, r3, #2 + 8008118: 4013 ands r3, r2 + 800811a: 68fa ldr r2, [r7, #12] + 800811c: 429a cmp r2, r3 + 800811e: d02c beq.n 800817a + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8008120: 4b49 ldr r3, [pc, #292] @ (8008248 ) + 8008122: 6a1b ldr r3, [r3, #32] + 8008124: 4a4a ldr r2, [pc, #296] @ (8008250 ) + 8008126: 4013 ands r3, r2 + 8008128: 60fb str r3, [r7, #12] + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 800812a: 4b47 ldr r3, [pc, #284] @ (8008248 ) + 800812c: 6a1a ldr r2, [r3, #32] + 800812e: 4b46 ldr r3, [pc, #280] @ (8008248 ) + 8008130: 2180 movs r1, #128 @ 0x80 + 8008132: 0249 lsls r1, r1, #9 + 8008134: 430a orrs r2, r1 + 8008136: 621a str r2, [r3, #32] + __HAL_RCC_BACKUPRESET_RELEASE(); + 8008138: 4b43 ldr r3, [pc, #268] @ (8008248 ) + 800813a: 6a1a ldr r2, [r3, #32] + 800813c: 4b42 ldr r3, [pc, #264] @ (8008248 ) + 800813e: 4945 ldr r1, [pc, #276] @ (8008254 ) + 8008140: 400a ands r2, r1 + 8008142: 621a str r2, [r3, #32] + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + 8008144: 4b40 ldr r3, [pc, #256] @ (8008248 ) + 8008146: 68fa ldr r2, [r7, #12] + 8008148: 621a str r2, [r3, #32] + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 800814a: 68fb ldr r3, [r7, #12] + 800814c: 2201 movs r2, #1 + 800814e: 4013 ands r3, r2 + 8008150: d013 beq.n 800817a + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8008152: f7fe fbcb bl 80068ec + 8008156: 0003 movs r3, r0 + 8008158: 613b str r3, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 800815a: e009 b.n 8008170 + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800815c: f7fe fbc6 bl 80068ec + 8008160: 0002 movs r2, r0 + 8008162: 693b ldr r3, [r7, #16] + 8008164: 1ad3 subs r3, r2, r3 + 8008166: 4a3c ldr r2, [pc, #240] @ (8008258 ) + 8008168: 4293 cmp r3, r2 + 800816a: d901 bls.n 8008170 + { + return HAL_TIMEOUT; + 800816c: 2303 movs r3, #3 + 800816e: e067 b.n 8008240 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8008170: 4b35 ldr r3, [pc, #212] @ (8008248 ) + 8008172: 6a1b ldr r3, [r3, #32] + 8008174: 2202 movs r2, #2 + 8008176: 4013 ands r3, r2 + 8008178: d0f0 beq.n 800815c + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800817a: 4b33 ldr r3, [pc, #204] @ (8008248 ) + 800817c: 6a1b ldr r3, [r3, #32] + 800817e: 4a34 ldr r2, [pc, #208] @ (8008250 ) + 8008180: 4013 ands r3, r2 + 8008182: 0019 movs r1, r3 + 8008184: 687b ldr r3, [r7, #4] + 8008186: 685a ldr r2, [r3, #4] + 8008188: 4b2f ldr r3, [pc, #188] @ (8008248 ) + 800818a: 430a orrs r2, r1 + 800818c: 621a str r2, [r3, #32] + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800818e: 2317 movs r3, #23 + 8008190: 18fb adds r3, r7, r3 + 8008192: 781b ldrb r3, [r3, #0] + 8008194: 2b01 cmp r3, #1 + 8008196: d105 bne.n 80081a4 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8008198: 4b2b ldr r3, [pc, #172] @ (8008248 ) + 800819a: 69da ldr r2, [r3, #28] + 800819c: 4b2a ldr r3, [pc, #168] @ (8008248 ) + 800819e: 492f ldr r1, [pc, #188] @ (800825c ) + 80081a0: 400a ands r2, r1 + 80081a2: 61da str r2, [r3, #28] + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 80081a4: 687b ldr r3, [r7, #4] + 80081a6: 681b ldr r3, [r3, #0] + 80081a8: 2201 movs r2, #1 + 80081aa: 4013 ands r3, r2 + 80081ac: d009 beq.n 80081c2 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 80081ae: 4b26 ldr r3, [pc, #152] @ (8008248 ) + 80081b0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80081b2: 2203 movs r2, #3 + 80081b4: 4393 bics r3, r2 + 80081b6: 0019 movs r1, r3 + 80081b8: 687b ldr r3, [r7, #4] + 80081ba: 689a ldr r2, [r3, #8] + 80081bc: 4b22 ldr r3, [pc, #136] @ (8008248 ) + 80081be: 430a orrs r2, r1 + 80081c0: 631a str r2, [r3, #48] @ 0x30 + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 80081c2: 687b ldr r3, [r7, #4] + 80081c4: 681b ldr r3, [r3, #0] + 80081c6: 2202 movs r2, #2 + 80081c8: 4013 ands r3, r2 + 80081ca: d009 beq.n 80081e0 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 80081cc: 4b1e ldr r3, [pc, #120] @ (8008248 ) + 80081ce: 6b1b ldr r3, [r3, #48] @ 0x30 + 80081d0: 4a23 ldr r2, [pc, #140] @ (8008260 ) + 80081d2: 4013 ands r3, r2 + 80081d4: 0019 movs r1, r3 + 80081d6: 687b ldr r3, [r7, #4] + 80081d8: 68da ldr r2, [r3, #12] + 80081da: 4b1b ldr r3, [pc, #108] @ (8008248 ) + 80081dc: 430a orrs r2, r1 + 80081de: 631a str r2, [r3, #48] @ 0x30 + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* STM32F091xC || STM32F098xx */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 80081e0: 687b ldr r3, [r7, #4] + 80081e2: 681b ldr r3, [r3, #0] + 80081e4: 2220 movs r2, #32 + 80081e6: 4013 ands r3, r2 + 80081e8: d009 beq.n 80081fe + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 80081ea: 4b17 ldr r3, [pc, #92] @ (8008248 ) + 80081ec: 6b1b ldr r3, [r3, #48] @ 0x30 + 80081ee: 2210 movs r2, #16 + 80081f0: 4393 bics r3, r2 + 80081f2: 0019 movs r1, r3 + 80081f4: 687b ldr r3, [r7, #4] + 80081f6: 691a ldr r2, [r3, #16] + 80081f8: 4b13 ldr r3, [pc, #76] @ (8008248 ) + 80081fa: 430a orrs r2, r1 + 80081fc: 631a str r2, [r3, #48] @ 0x30 + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 80081fe: 687b ldr r3, [r7, #4] + 8008200: 681a ldr r2, [r3, #0] + 8008202: 2380 movs r3, #128 @ 0x80 + 8008204: 029b lsls r3, r3, #10 + 8008206: 4013 ands r3, r2 + 8008208: d009 beq.n 800821e + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 800820a: 4b0f ldr r3, [pc, #60] @ (8008248 ) + 800820c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800820e: 2280 movs r2, #128 @ 0x80 + 8008210: 4393 bics r3, r2 + 8008212: 0019 movs r1, r3 + 8008214: 687b ldr r3, [r7, #4] + 8008216: 699a ldr r2, [r3, #24] + 8008218: 4b0b ldr r3, [pc, #44] @ (8008248 ) + 800821a: 430a orrs r2, r1 + 800821c: 631a str r2, [r3, #48] @ 0x30 +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 800821e: 687b ldr r3, [r7, #4] + 8008220: 681a ldr r2, [r3, #0] + 8008222: 2380 movs r3, #128 @ 0x80 + 8008224: 00db lsls r3, r3, #3 + 8008226: 4013 ands r3, r2 + 8008228: d009 beq.n 800823e + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 800822a: 4b07 ldr r3, [pc, #28] @ (8008248 ) + 800822c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800822e: 2240 movs r2, #64 @ 0x40 + 8008230: 4393 bics r3, r2 + 8008232: 0019 movs r1, r3 + 8008234: 687b ldr r3, [r7, #4] + 8008236: 695a ldr r2, [r3, #20] + 8008238: 4b03 ldr r3, [pc, #12] @ (8008248 ) + 800823a: 430a orrs r2, r1 + 800823c: 631a str r2, [r3, #48] @ 0x30 +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + return HAL_OK; + 800823e: 2300 movs r3, #0 +} + 8008240: 0018 movs r0, r3 + 8008242: 46bd mov sp, r7 + 8008244: b006 add sp, #24 + 8008246: bd80 pop {r7, pc} + 8008248: 40021000 .word 0x40021000 + 800824c: 40007000 .word 0x40007000 + 8008250: fffffcff .word 0xfffffcff + 8008254: fffeffff .word 0xfffeffff + 8008258: 00001388 .word 0x00001388 + 800825c: efffffff .word 0xefffffff + 8008260: fffcffff .word 0xfffcffff + +08008264 : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8008264: b580 push {r7, lr} + 8008266: b082 sub sp, #8 + 8008268: af00 add r7, sp, #0 + 800826a: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 800826c: 687b ldr r3, [r7, #4] + 800826e: 2b00 cmp r3, #0 + 8008270: d101 bne.n 8008276 + { + return HAL_ERROR; + 8008272: 2301 movs r3, #1 + 8008274: e044 b.n 8008300 + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 8008276: 687b ldr r3, [r7, #4] + 8008278: 6f9b ldr r3, [r3, #120] @ 0x78 + 800827a: 2b00 cmp r3, #0 + 800827c: d107 bne.n 800828e + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 800827e: 687b ldr r3, [r7, #4] + 8008280: 2274 movs r2, #116 @ 0x74 + 8008282: 2100 movs r1, #0 + 8008284: 5499 strb r1, [r3, r2] + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8008286: 687b ldr r3, [r7, #4] + 8008288: 0018 movs r0, r3 + 800828a: f7fd fdcd bl 8005e28 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 800828e: 687b ldr r3, [r7, #4] + 8008290: 2224 movs r2, #36 @ 0x24 + 8008292: 679a str r2, [r3, #120] @ 0x78 + + __HAL_UART_DISABLE(huart); + 8008294: 687b ldr r3, [r7, #4] + 8008296: 681b ldr r3, [r3, #0] + 8008298: 681a ldr r2, [r3, #0] + 800829a: 687b ldr r3, [r7, #4] + 800829c: 681b ldr r3, [r3, #0] + 800829e: 2101 movs r1, #1 + 80082a0: 438a bics r2, r1 + 80082a2: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 80082a4: 687b ldr r3, [r7, #4] + 80082a6: 0018 movs r0, r3 + 80082a8: f000 f830 bl 800830c + 80082ac: 0003 movs r3, r0 + 80082ae: 2b01 cmp r3, #1 + 80082b0: d101 bne.n 80082b6 + { + return HAL_ERROR; + 80082b2: 2301 movs r3, #1 + 80082b4: e024 b.n 8008300 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 80082b6: 687b ldr r3, [r7, #4] + 80082b8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80082ba: 2b00 cmp r3, #0 + 80082bc: d003 beq.n 80082c6 + { + UART_AdvFeatureConfig(huart); + 80082be: 687b ldr r3, [r7, #4] + 80082c0: 0018 movs r0, r3 + 80082c2: f000 f9ab bl 800861c + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register, + - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/ +#if defined (USART_CR2_LINEN) + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 80082c6: 687b ldr r3, [r7, #4] + 80082c8: 681b ldr r3, [r3, #0] + 80082ca: 685a ldr r2, [r3, #4] + 80082cc: 687b ldr r3, [r7, #4] + 80082ce: 681b ldr r3, [r3, #0] + 80082d0: 490d ldr r1, [pc, #52] @ (8008308 ) + 80082d2: 400a ands r2, r1 + 80082d4: 605a str r2, [r3, #4] +#else + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); +#endif /* USART_CR2_LINEN */ +#if defined (USART_CR3_SCEN) +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 80082d6: 687b ldr r3, [r7, #4] + 80082d8: 681b ldr r3, [r3, #0] + 80082da: 689a ldr r2, [r3, #8] + 80082dc: 687b ldr r3, [r7, #4] + 80082de: 681b ldr r3, [r3, #0] + 80082e0: 212a movs r1, #42 @ 0x2a + 80082e2: 438a bics r2, r1 + 80082e4: 609a str r2, [r3, #8] +#else + CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL); +#endif /* USART_CR3_IREN*/ +#endif /* USART_CR3_SCEN */ + + __HAL_UART_ENABLE(huart); + 80082e6: 687b ldr r3, [r7, #4] + 80082e8: 681b ldr r3, [r3, #0] + 80082ea: 681a ldr r2, [r3, #0] + 80082ec: 687b ldr r3, [r7, #4] + 80082ee: 681b ldr r3, [r3, #0] + 80082f0: 2101 movs r1, #1 + 80082f2: 430a orrs r2, r1 + 80082f4: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 80082f6: 687b ldr r3, [r7, #4] + 80082f8: 0018 movs r0, r3 + 80082fa: f000 fa43 bl 8008784 + 80082fe: 0003 movs r3, r0 +} + 8008300: 0018 movs r0, r3 + 8008302: 46bd mov sp, r7 + 8008304: b002 add sp, #8 + 8008306: bd80 pop {r7, pc} + 8008308: ffffb7ff .word 0xffffb7ff + +0800830c : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 800830c: b580 push {r7, lr} + 800830e: b088 sub sp, #32 + 8008310: af00 add r7, sp, #0 + 8008312: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 8008314: 231e movs r3, #30 + 8008316: 18fb adds r3, r7, r3 + 8008318: 2200 movs r2, #0 + 800831a: 701a strb r2, [r3, #0] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 800831c: 687b ldr r3, [r7, #4] + 800831e: 689a ldr r2, [r3, #8] + 8008320: 687b ldr r3, [r7, #4] + 8008322: 691b ldr r3, [r3, #16] + 8008324: 431a orrs r2, r3 + 8008326: 687b ldr r3, [r7, #4] + 8008328: 695b ldr r3, [r3, #20] + 800832a: 431a orrs r2, r3 + 800832c: 687b ldr r3, [r7, #4] + 800832e: 69db ldr r3, [r3, #28] + 8008330: 4313 orrs r3, r2 + 8008332: 617b str r3, [r7, #20] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8008334: 687b ldr r3, [r7, #4] + 8008336: 681b ldr r3, [r3, #0] + 8008338: 681b ldr r3, [r3, #0] + 800833a: 4aaf ldr r2, [pc, #700] @ (80085f8 ) + 800833c: 4013 ands r3, r2 + 800833e: 0019 movs r1, r3 + 8008340: 687b ldr r3, [r7, #4] + 8008342: 681b ldr r3, [r3, #0] + 8008344: 697a ldr r2, [r7, #20] + 8008346: 430a orrs r2, r1 + 8008348: 601a str r2, [r3, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 800834a: 687b ldr r3, [r7, #4] + 800834c: 681b ldr r3, [r3, #0] + 800834e: 685b ldr r3, [r3, #4] + 8008350: 4aaa ldr r2, [pc, #680] @ (80085fc ) + 8008352: 4013 ands r3, r2 + 8008354: 0019 movs r1, r3 + 8008356: 687b ldr r3, [r7, #4] + 8008358: 68da ldr r2, [r3, #12] + 800835a: 687b ldr r3, [r7, #4] + 800835c: 681b ldr r3, [r3, #0] + 800835e: 430a orrs r2, r1 + 8008360: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8008362: 687b ldr r3, [r7, #4] + 8008364: 699b ldr r3, [r3, #24] + 8008366: 617b str r3, [r7, #20] + + tmpreg |= huart->Init.OneBitSampling; + 8008368: 687b ldr r3, [r7, #4] + 800836a: 6a1b ldr r3, [r3, #32] + 800836c: 697a ldr r2, [r7, #20] + 800836e: 4313 orrs r3, r2 + 8008370: 617b str r3, [r7, #20] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8008372: 687b ldr r3, [r7, #4] + 8008374: 681b ldr r3, [r3, #0] + 8008376: 689b ldr r3, [r3, #8] + 8008378: 4aa1 ldr r2, [pc, #644] @ (8008600 ) + 800837a: 4013 ands r3, r2 + 800837c: 0019 movs r1, r3 + 800837e: 687b ldr r3, [r7, #4] + 8008380: 681b ldr r3, [r3, #0] + 8008382: 697a ldr r2, [r7, #20] + 8008384: 430a orrs r2, r1 + 8008386: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 8008388: 687b ldr r3, [r7, #4] + 800838a: 681b ldr r3, [r3, #0] + 800838c: 4a9d ldr r2, [pc, #628] @ (8008604 ) + 800838e: 4293 cmp r3, r2 + 8008390: d127 bne.n 80083e2 + 8008392: 4b9d ldr r3, [pc, #628] @ (8008608 ) + 8008394: 6b1b ldr r3, [r3, #48] @ 0x30 + 8008396: 2203 movs r2, #3 + 8008398: 4013 ands r3, r2 + 800839a: 2b03 cmp r3, #3 + 800839c: d00d beq.n 80083ba + 800839e: d81b bhi.n 80083d8 + 80083a0: 2b02 cmp r3, #2 + 80083a2: d014 beq.n 80083ce + 80083a4: d818 bhi.n 80083d8 + 80083a6: 2b00 cmp r3, #0 + 80083a8: d002 beq.n 80083b0 + 80083aa: 2b01 cmp r3, #1 + 80083ac: d00a beq.n 80083c4 + 80083ae: e013 b.n 80083d8 + 80083b0: 231f movs r3, #31 + 80083b2: 18fb adds r3, r7, r3 + 80083b4: 2200 movs r2, #0 + 80083b6: 701a strb r2, [r3, #0] + 80083b8: e065 b.n 8008486 + 80083ba: 231f movs r3, #31 + 80083bc: 18fb adds r3, r7, r3 + 80083be: 2202 movs r2, #2 + 80083c0: 701a strb r2, [r3, #0] + 80083c2: e060 b.n 8008486 + 80083c4: 231f movs r3, #31 + 80083c6: 18fb adds r3, r7, r3 + 80083c8: 2204 movs r2, #4 + 80083ca: 701a strb r2, [r3, #0] + 80083cc: e05b b.n 8008486 + 80083ce: 231f movs r3, #31 + 80083d0: 18fb adds r3, r7, r3 + 80083d2: 2208 movs r2, #8 + 80083d4: 701a strb r2, [r3, #0] + 80083d6: e056 b.n 8008486 + 80083d8: 231f movs r3, #31 + 80083da: 18fb adds r3, r7, r3 + 80083dc: 2210 movs r2, #16 + 80083de: 701a strb r2, [r3, #0] + 80083e0: e051 b.n 8008486 + 80083e2: 687b ldr r3, [r7, #4] + 80083e4: 681b ldr r3, [r3, #0] + 80083e6: 4a89 ldr r2, [pc, #548] @ (800860c ) + 80083e8: 4293 cmp r3, r2 + 80083ea: d134 bne.n 8008456 + 80083ec: 4b86 ldr r3, [pc, #536] @ (8008608 ) + 80083ee: 6b1a ldr r2, [r3, #48] @ 0x30 + 80083f0: 23c0 movs r3, #192 @ 0xc0 + 80083f2: 029b lsls r3, r3, #10 + 80083f4: 4013 ands r3, r2 + 80083f6: 22c0 movs r2, #192 @ 0xc0 + 80083f8: 0292 lsls r2, r2, #10 + 80083fa: 4293 cmp r3, r2 + 80083fc: d017 beq.n 800842e + 80083fe: 22c0 movs r2, #192 @ 0xc0 + 8008400: 0292 lsls r2, r2, #10 + 8008402: 4293 cmp r3, r2 + 8008404: d822 bhi.n 800844c + 8008406: 2280 movs r2, #128 @ 0x80 + 8008408: 0292 lsls r2, r2, #10 + 800840a: 4293 cmp r3, r2 + 800840c: d019 beq.n 8008442 + 800840e: 2280 movs r2, #128 @ 0x80 + 8008410: 0292 lsls r2, r2, #10 + 8008412: 4293 cmp r3, r2 + 8008414: d81a bhi.n 800844c + 8008416: 2b00 cmp r3, #0 + 8008418: d004 beq.n 8008424 + 800841a: 2280 movs r2, #128 @ 0x80 + 800841c: 0252 lsls r2, r2, #9 + 800841e: 4293 cmp r3, r2 + 8008420: d00a beq.n 8008438 + 8008422: e013 b.n 800844c + 8008424: 231f movs r3, #31 + 8008426: 18fb adds r3, r7, r3 + 8008428: 2200 movs r2, #0 + 800842a: 701a strb r2, [r3, #0] + 800842c: e02b b.n 8008486 + 800842e: 231f movs r3, #31 + 8008430: 18fb adds r3, r7, r3 + 8008432: 2202 movs r2, #2 + 8008434: 701a strb r2, [r3, #0] + 8008436: e026 b.n 8008486 + 8008438: 231f movs r3, #31 + 800843a: 18fb adds r3, r7, r3 + 800843c: 2204 movs r2, #4 + 800843e: 701a strb r2, [r3, #0] + 8008440: e021 b.n 8008486 + 8008442: 231f movs r3, #31 + 8008444: 18fb adds r3, r7, r3 + 8008446: 2208 movs r2, #8 + 8008448: 701a strb r2, [r3, #0] + 800844a: e01c b.n 8008486 + 800844c: 231f movs r3, #31 + 800844e: 18fb adds r3, r7, r3 + 8008450: 2210 movs r2, #16 + 8008452: 701a strb r2, [r3, #0] + 8008454: e017 b.n 8008486 + 8008456: 687b ldr r3, [r7, #4] + 8008458: 681b ldr r3, [r3, #0] + 800845a: 4a6d ldr r2, [pc, #436] @ (8008610 ) + 800845c: 4293 cmp r3, r2 + 800845e: d104 bne.n 800846a + 8008460: 231f movs r3, #31 + 8008462: 18fb adds r3, r7, r3 + 8008464: 2200 movs r2, #0 + 8008466: 701a strb r2, [r3, #0] + 8008468: e00d b.n 8008486 + 800846a: 687b ldr r3, [r7, #4] + 800846c: 681b ldr r3, [r3, #0] + 800846e: 4a69 ldr r2, [pc, #420] @ (8008614 ) + 8008470: 4293 cmp r3, r2 + 8008472: d104 bne.n 800847e + 8008474: 231f movs r3, #31 + 8008476: 18fb adds r3, r7, r3 + 8008478: 2200 movs r2, #0 + 800847a: 701a strb r2, [r3, #0] + 800847c: e003 b.n 8008486 + 800847e: 231f movs r3, #31 + 8008480: 18fb adds r3, r7, r3 + 8008482: 2210 movs r2, #16 + 8008484: 701a strb r2, [r3, #0] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 8008486: 687b ldr r3, [r7, #4] + 8008488: 69da ldr r2, [r3, #28] + 800848a: 2380 movs r3, #128 @ 0x80 + 800848c: 021b lsls r3, r3, #8 + 800848e: 429a cmp r2, r3 + 8008490: d15d bne.n 800854e + { + switch (clocksource) + 8008492: 231f movs r3, #31 + 8008494: 18fb adds r3, r7, r3 + 8008496: 781b ldrb r3, [r3, #0] + 8008498: 2b08 cmp r3, #8 + 800849a: d015 beq.n 80084c8 + 800849c: dc18 bgt.n 80084d0 + 800849e: 2b04 cmp r3, #4 + 80084a0: d00d beq.n 80084be + 80084a2: dc15 bgt.n 80084d0 + 80084a4: 2b00 cmp r3, #0 + 80084a6: d002 beq.n 80084ae + 80084a8: 2b02 cmp r3, #2 + 80084aa: d005 beq.n 80084b8 + 80084ac: e010 b.n 80084d0 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 80084ae: f7ff fdc5 bl 800803c + 80084b2: 0003 movs r3, r0 + 80084b4: 61bb str r3, [r7, #24] + break; + 80084b6: e012 b.n 80084de + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 80084b8: 4b57 ldr r3, [pc, #348] @ (8008618 ) + 80084ba: 61bb str r3, [r7, #24] + break; + 80084bc: e00f b.n 80084de + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 80084be: f7ff fd33 bl 8007f28 + 80084c2: 0003 movs r3, r0 + 80084c4: 61bb str r3, [r7, #24] + break; + 80084c6: e00a b.n 80084de + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 80084c8: 2380 movs r3, #128 @ 0x80 + 80084ca: 021b lsls r3, r3, #8 + 80084cc: 61bb str r3, [r7, #24] + break; + 80084ce: e006 b.n 80084de + default: + pclk = 0U; + 80084d0: 2300 movs r3, #0 + 80084d2: 61bb str r3, [r7, #24] + ret = HAL_ERROR; + 80084d4: 231e movs r3, #30 + 80084d6: 18fb adds r3, r7, r3 + 80084d8: 2201 movs r2, #1 + 80084da: 701a strb r2, [r3, #0] + break; + 80084dc: 46c0 nop @ (mov r8, r8) + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 80084de: 69bb ldr r3, [r7, #24] + 80084e0: 2b00 cmp r3, #0 + 80084e2: d100 bne.n 80084e6 + 80084e4: e07b b.n 80085de + { + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 80084e6: 69bb ldr r3, [r7, #24] + 80084e8: 005a lsls r2, r3, #1 + 80084ea: 687b ldr r3, [r7, #4] + 80084ec: 685b ldr r3, [r3, #4] + 80084ee: 085b lsrs r3, r3, #1 + 80084f0: 18d2 adds r2, r2, r3 + 80084f2: 687b ldr r3, [r7, #4] + 80084f4: 685b ldr r3, [r3, #4] + 80084f6: 0019 movs r1, r3 + 80084f8: 0010 movs r0, r2 + 80084fa: f7f7 fe05 bl 8000108 <__udivsi3> + 80084fe: 0003 movs r3, r0 + 8008500: b29b uxth r3, r3 + 8008502: 613b str r3, [r7, #16] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8008504: 693b ldr r3, [r7, #16] + 8008506: 2b0f cmp r3, #15 + 8008508: d91c bls.n 8008544 + 800850a: 693a ldr r2, [r7, #16] + 800850c: 2380 movs r3, #128 @ 0x80 + 800850e: 025b lsls r3, r3, #9 + 8008510: 429a cmp r2, r3 + 8008512: d217 bcs.n 8008544 + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 8008514: 693b ldr r3, [r7, #16] + 8008516: b29a uxth r2, r3 + 8008518: 200e movs r0, #14 + 800851a: 183b adds r3, r7, r0 + 800851c: 210f movs r1, #15 + 800851e: 438a bics r2, r1 + 8008520: 801a strh r2, [r3, #0] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 8008522: 693b ldr r3, [r7, #16] + 8008524: 085b lsrs r3, r3, #1 + 8008526: b29b uxth r3, r3 + 8008528: 2207 movs r2, #7 + 800852a: 4013 ands r3, r2 + 800852c: b299 uxth r1, r3 + 800852e: 183b adds r3, r7, r0 + 8008530: 183a adds r2, r7, r0 + 8008532: 8812 ldrh r2, [r2, #0] + 8008534: 430a orrs r2, r1 + 8008536: 801a strh r2, [r3, #0] + huart->Instance->BRR = brrtemp; + 8008538: 687b ldr r3, [r7, #4] + 800853a: 681b ldr r3, [r3, #0] + 800853c: 183a adds r2, r7, r0 + 800853e: 8812 ldrh r2, [r2, #0] + 8008540: 60da str r2, [r3, #12] + 8008542: e04c b.n 80085de + } + else + { + ret = HAL_ERROR; + 8008544: 231e movs r3, #30 + 8008546: 18fb adds r3, r7, r3 + 8008548: 2201 movs r2, #1 + 800854a: 701a strb r2, [r3, #0] + 800854c: e047 b.n 80085de + } + } + } + else + { + switch (clocksource) + 800854e: 231f movs r3, #31 + 8008550: 18fb adds r3, r7, r3 + 8008552: 781b ldrb r3, [r3, #0] + 8008554: 2b08 cmp r3, #8 + 8008556: d015 beq.n 8008584 + 8008558: dc18 bgt.n 800858c + 800855a: 2b04 cmp r3, #4 + 800855c: d00d beq.n 800857a + 800855e: dc15 bgt.n 800858c + 8008560: 2b00 cmp r3, #0 + 8008562: d002 beq.n 800856a + 8008564: 2b02 cmp r3, #2 + 8008566: d005 beq.n 8008574 + 8008568: e010 b.n 800858c + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 800856a: f7ff fd67 bl 800803c + 800856e: 0003 movs r3, r0 + 8008570: 61bb str r3, [r7, #24] + break; + 8008572: e012 b.n 800859a + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8008574: 4b28 ldr r3, [pc, #160] @ (8008618 ) + 8008576: 61bb str r3, [r7, #24] + break; + 8008578: e00f b.n 800859a + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800857a: f7ff fcd5 bl 8007f28 + 800857e: 0003 movs r3, r0 + 8008580: 61bb str r3, [r7, #24] + break; + 8008582: e00a b.n 800859a + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8008584: 2380 movs r3, #128 @ 0x80 + 8008586: 021b lsls r3, r3, #8 + 8008588: 61bb str r3, [r7, #24] + break; + 800858a: e006 b.n 800859a + default: + pclk = 0U; + 800858c: 2300 movs r3, #0 + 800858e: 61bb str r3, [r7, #24] + ret = HAL_ERROR; + 8008590: 231e movs r3, #30 + 8008592: 18fb adds r3, r7, r3 + 8008594: 2201 movs r2, #1 + 8008596: 701a strb r2, [r3, #0] + break; + 8008598: 46c0 nop @ (mov r8, r8) + } + + if (pclk != 0U) + 800859a: 69bb ldr r3, [r7, #24] + 800859c: 2b00 cmp r3, #0 + 800859e: d01e beq.n 80085de + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 80085a0: 687b ldr r3, [r7, #4] + 80085a2: 685b ldr r3, [r3, #4] + 80085a4: 085a lsrs r2, r3, #1 + 80085a6: 69bb ldr r3, [r7, #24] + 80085a8: 18d2 adds r2, r2, r3 + 80085aa: 687b ldr r3, [r7, #4] + 80085ac: 685b ldr r3, [r3, #4] + 80085ae: 0019 movs r1, r3 + 80085b0: 0010 movs r0, r2 + 80085b2: f7f7 fda9 bl 8000108 <__udivsi3> + 80085b6: 0003 movs r3, r0 + 80085b8: b29b uxth r3, r3 + 80085ba: 613b str r3, [r7, #16] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 80085bc: 693b ldr r3, [r7, #16] + 80085be: 2b0f cmp r3, #15 + 80085c0: d909 bls.n 80085d6 + 80085c2: 693a ldr r2, [r7, #16] + 80085c4: 2380 movs r3, #128 @ 0x80 + 80085c6: 025b lsls r3, r3, #9 + 80085c8: 429a cmp r2, r3 + 80085ca: d204 bcs.n 80085d6 + { + huart->Instance->BRR = usartdiv; + 80085cc: 687b ldr r3, [r7, #4] + 80085ce: 681b ldr r3, [r3, #0] + 80085d0: 693a ldr r2, [r7, #16] + 80085d2: 60da str r2, [r3, #12] + 80085d4: e003 b.n 80085de + } + else + { + ret = HAL_ERROR; + 80085d6: 231e movs r3, #30 + 80085d8: 18fb adds r3, r7, r3 + 80085da: 2201 movs r2, #1 + 80085dc: 701a strb r2, [r3, #0] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 80085de: 687b ldr r3, [r7, #4] + 80085e0: 2200 movs r2, #0 + 80085e2: 665a str r2, [r3, #100] @ 0x64 + huart->TxISR = NULL; + 80085e4: 687b ldr r3, [r7, #4] + 80085e6: 2200 movs r2, #0 + 80085e8: 669a str r2, [r3, #104] @ 0x68 + + return ret; + 80085ea: 231e movs r3, #30 + 80085ec: 18fb adds r3, r7, r3 + 80085ee: 781b ldrb r3, [r3, #0] +} + 80085f0: 0018 movs r0, r3 + 80085f2: 46bd mov sp, r7 + 80085f4: b008 add sp, #32 + 80085f6: bd80 pop {r7, pc} + 80085f8: efff69f3 .word 0xefff69f3 + 80085fc: ffffcfff .word 0xffffcfff + 8008600: fffff4ff .word 0xfffff4ff + 8008604: 40013800 .word 0x40013800 + 8008608: 40021000 .word 0x40021000 + 800860c: 40004400 .word 0x40004400 + 8008610: 40004800 .word 0x40004800 + 8008614: 40004c00 .word 0x40004c00 + 8008618: 007a1200 .word 0x007a1200 + +0800861c : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 800861c: b580 push {r7, lr} + 800861e: b082 sub sp, #8 + 8008620: af00 add r7, sp, #0 + 8008622: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 8008624: 687b ldr r3, [r7, #4] + 8008626: 6a5b ldr r3, [r3, #36] @ 0x24 + 8008628: 2201 movs r2, #1 + 800862a: 4013 ands r3, r2 + 800862c: d00b beq.n 8008646 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800862e: 687b ldr r3, [r7, #4] + 8008630: 681b ldr r3, [r3, #0] + 8008632: 685b ldr r3, [r3, #4] + 8008634: 4a4a ldr r2, [pc, #296] @ (8008760 ) + 8008636: 4013 ands r3, r2 + 8008638: 0019 movs r1, r3 + 800863a: 687b ldr r3, [r7, #4] + 800863c: 6a9a ldr r2, [r3, #40] @ 0x28 + 800863e: 687b ldr r3, [r7, #4] + 8008640: 681b ldr r3, [r3, #0] + 8008642: 430a orrs r2, r1 + 8008644: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8008646: 687b ldr r3, [r7, #4] + 8008648: 6a5b ldr r3, [r3, #36] @ 0x24 + 800864a: 2202 movs r2, #2 + 800864c: 4013 ands r3, r2 + 800864e: d00b beq.n 8008668 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8008650: 687b ldr r3, [r7, #4] + 8008652: 681b ldr r3, [r3, #0] + 8008654: 685b ldr r3, [r3, #4] + 8008656: 4a43 ldr r2, [pc, #268] @ (8008764 ) + 8008658: 4013 ands r3, r2 + 800865a: 0019 movs r1, r3 + 800865c: 687b ldr r3, [r7, #4] + 800865e: 6ada ldr r2, [r3, #44] @ 0x2c + 8008660: 687b ldr r3, [r7, #4] + 8008662: 681b ldr r3, [r3, #0] + 8008664: 430a orrs r2, r1 + 8008666: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 8008668: 687b ldr r3, [r7, #4] + 800866a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800866c: 2204 movs r2, #4 + 800866e: 4013 ands r3, r2 + 8008670: d00b beq.n 800868a + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 8008672: 687b ldr r3, [r7, #4] + 8008674: 681b ldr r3, [r3, #0] + 8008676: 685b ldr r3, [r3, #4] + 8008678: 4a3b ldr r2, [pc, #236] @ (8008768 ) + 800867a: 4013 ands r3, r2 + 800867c: 0019 movs r1, r3 + 800867e: 687b ldr r3, [r7, #4] + 8008680: 6b1a ldr r2, [r3, #48] @ 0x30 + 8008682: 687b ldr r3, [r7, #4] + 8008684: 681b ldr r3, [r3, #0] + 8008686: 430a orrs r2, r1 + 8008688: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 800868a: 687b ldr r3, [r7, #4] + 800868c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800868e: 2208 movs r2, #8 + 8008690: 4013 ands r3, r2 + 8008692: d00b beq.n 80086ac + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8008694: 687b ldr r3, [r7, #4] + 8008696: 681b ldr r3, [r3, #0] + 8008698: 685b ldr r3, [r3, #4] + 800869a: 4a34 ldr r2, [pc, #208] @ (800876c ) + 800869c: 4013 ands r3, r2 + 800869e: 0019 movs r1, r3 + 80086a0: 687b ldr r3, [r7, #4] + 80086a2: 6b5a ldr r2, [r3, #52] @ 0x34 + 80086a4: 687b ldr r3, [r7, #4] + 80086a6: 681b ldr r3, [r3, #0] + 80086a8: 430a orrs r2, r1 + 80086aa: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 80086ac: 687b ldr r3, [r7, #4] + 80086ae: 6a5b ldr r3, [r3, #36] @ 0x24 + 80086b0: 2210 movs r2, #16 + 80086b2: 4013 ands r3, r2 + 80086b4: d00b beq.n 80086ce + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 80086b6: 687b ldr r3, [r7, #4] + 80086b8: 681b ldr r3, [r3, #0] + 80086ba: 689b ldr r3, [r3, #8] + 80086bc: 4a2c ldr r2, [pc, #176] @ (8008770 ) + 80086be: 4013 ands r3, r2 + 80086c0: 0019 movs r1, r3 + 80086c2: 687b ldr r3, [r7, #4] + 80086c4: 6b9a ldr r2, [r3, #56] @ 0x38 + 80086c6: 687b ldr r3, [r7, #4] + 80086c8: 681b ldr r3, [r3, #0] + 80086ca: 430a orrs r2, r1 + 80086cc: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 80086ce: 687b ldr r3, [r7, #4] + 80086d0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80086d2: 2220 movs r2, #32 + 80086d4: 4013 ands r3, r2 + 80086d6: d00b beq.n 80086f0 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 80086d8: 687b ldr r3, [r7, #4] + 80086da: 681b ldr r3, [r3, #0] + 80086dc: 689b ldr r3, [r3, #8] + 80086de: 4a25 ldr r2, [pc, #148] @ (8008774 ) + 80086e0: 4013 ands r3, r2 + 80086e2: 0019 movs r1, r3 + 80086e4: 687b ldr r3, [r7, #4] + 80086e6: 6bda ldr r2, [r3, #60] @ 0x3c + 80086e8: 687b ldr r3, [r7, #4] + 80086ea: 681b ldr r3, [r3, #0] + 80086ec: 430a orrs r2, r1 + 80086ee: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 80086f0: 687b ldr r3, [r7, #4] + 80086f2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80086f4: 2240 movs r2, #64 @ 0x40 + 80086f6: 4013 ands r3, r2 + 80086f8: d01d beq.n 8008736 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 80086fa: 687b ldr r3, [r7, #4] + 80086fc: 681b ldr r3, [r3, #0] + 80086fe: 685b ldr r3, [r3, #4] + 8008700: 4a1d ldr r2, [pc, #116] @ (8008778 ) + 8008702: 4013 ands r3, r2 + 8008704: 0019 movs r1, r3 + 8008706: 687b ldr r3, [r7, #4] + 8008708: 6c1a ldr r2, [r3, #64] @ 0x40 + 800870a: 687b ldr r3, [r7, #4] + 800870c: 681b ldr r3, [r3, #0] + 800870e: 430a orrs r2, r1 + 8008710: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8008712: 687b ldr r3, [r7, #4] + 8008714: 6c1a ldr r2, [r3, #64] @ 0x40 + 8008716: 2380 movs r3, #128 @ 0x80 + 8008718: 035b lsls r3, r3, #13 + 800871a: 429a cmp r2, r3 + 800871c: d10b bne.n 8008736 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 800871e: 687b ldr r3, [r7, #4] + 8008720: 681b ldr r3, [r3, #0] + 8008722: 685b ldr r3, [r3, #4] + 8008724: 4a15 ldr r2, [pc, #84] @ (800877c ) + 8008726: 4013 ands r3, r2 + 8008728: 0019 movs r1, r3 + 800872a: 687b ldr r3, [r7, #4] + 800872c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800872e: 687b ldr r3, [r7, #4] + 8008730: 681b ldr r3, [r3, #0] + 8008732: 430a orrs r2, r1 + 8008734: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8008736: 687b ldr r3, [r7, #4] + 8008738: 6a5b ldr r3, [r3, #36] @ 0x24 + 800873a: 2280 movs r2, #128 @ 0x80 + 800873c: 4013 ands r3, r2 + 800873e: d00b beq.n 8008758 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8008740: 687b ldr r3, [r7, #4] + 8008742: 681b ldr r3, [r3, #0] + 8008744: 685b ldr r3, [r3, #4] + 8008746: 4a0e ldr r2, [pc, #56] @ (8008780 ) + 8008748: 4013 ands r3, r2 + 800874a: 0019 movs r1, r3 + 800874c: 687b ldr r3, [r7, #4] + 800874e: 6c9a ldr r2, [r3, #72] @ 0x48 + 8008750: 687b ldr r3, [r7, #4] + 8008752: 681b ldr r3, [r3, #0] + 8008754: 430a orrs r2, r1 + 8008756: 605a str r2, [r3, #4] + } +} + 8008758: 46c0 nop @ (mov r8, r8) + 800875a: 46bd mov sp, r7 + 800875c: b002 add sp, #8 + 800875e: bd80 pop {r7, pc} + 8008760: fffdffff .word 0xfffdffff + 8008764: fffeffff .word 0xfffeffff + 8008768: fffbffff .word 0xfffbffff + 800876c: ffff7fff .word 0xffff7fff + 8008770: ffffefff .word 0xffffefff + 8008774: ffffdfff .word 0xffffdfff + 8008778: ffefffff .word 0xffefffff + 800877c: ff9fffff .word 0xff9fffff + 8008780: fff7ffff .word 0xfff7ffff + +08008784 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8008784: b580 push {r7, lr} + 8008786: b086 sub sp, #24 + 8008788: af02 add r7, sp, #8 + 800878a: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800878c: 687b ldr r3, [r7, #4] + 800878e: 2280 movs r2, #128 @ 0x80 + 8008790: 2100 movs r1, #0 + 8008792: 5099 str r1, [r3, r2] + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8008794: f7fe f8aa bl 80068ec + 8008798: 0003 movs r3, r0 + 800879a: 60fb str r3, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 800879c: 687b ldr r3, [r7, #4] + 800879e: 681b ldr r3, [r3, #0] + 80087a0: 681b ldr r3, [r3, #0] + 80087a2: 2208 movs r2, #8 + 80087a4: 4013 ands r3, r2 + 80087a6: 2b08 cmp r3, #8 + 80087a8: d10c bne.n 80087c4 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80087aa: 68fb ldr r3, [r7, #12] + 80087ac: 2280 movs r2, #128 @ 0x80 + 80087ae: 0391 lsls r1, r2, #14 + 80087b0: 6878 ldr r0, [r7, #4] + 80087b2: 4a17 ldr r2, [pc, #92] @ (8008810 ) + 80087b4: 9200 str r2, [sp, #0] + 80087b6: 2200 movs r2, #0 + 80087b8: f000 f82c bl 8008814 + 80087bc: 1e03 subs r3, r0, #0 + 80087be: d001 beq.n 80087c4 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 80087c0: 2303 movs r3, #3 + 80087c2: e021 b.n 8008808 + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + 80087c4: 687b ldr r3, [r7, #4] + 80087c6: 681b ldr r3, [r3, #0] + 80087c8: 681b ldr r3, [r3, #0] + 80087ca: 2204 movs r2, #4 + 80087cc: 4013 ands r3, r2 + 80087ce: 2b04 cmp r3, #4 + 80087d0: d10c bne.n 80087ec + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 80087d2: 68fb ldr r3, [r7, #12] + 80087d4: 2280 movs r2, #128 @ 0x80 + 80087d6: 03d1 lsls r1, r2, #15 + 80087d8: 6878 ldr r0, [r7, #4] + 80087da: 4a0d ldr r2, [pc, #52] @ (8008810 ) + 80087dc: 9200 str r2, [sp, #0] + 80087de: 2200 movs r2, #0 + 80087e0: f000 f818 bl 8008814 + 80087e4: 1e03 subs r3, r0, #0 + 80087e6: d001 beq.n 80087ec + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 80087e8: 2303 movs r3, #3 + 80087ea: e00d b.n 8008808 + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 80087ec: 687b ldr r3, [r7, #4] + 80087ee: 2220 movs r2, #32 + 80087f0: 679a str r2, [r3, #120] @ 0x78 + huart->RxState = HAL_UART_STATE_READY; + 80087f2: 687b ldr r3, [r7, #4] + 80087f4: 2220 movs r2, #32 + 80087f6: 67da str r2, [r3, #124] @ 0x7c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80087f8: 687b ldr r3, [r7, #4] + 80087fa: 2200 movs r2, #0 + 80087fc: 661a str r2, [r3, #96] @ 0x60 + + __HAL_UNLOCK(huart); + 80087fe: 687b ldr r3, [r7, #4] + 8008800: 2274 movs r2, #116 @ 0x74 + 8008802: 2100 movs r1, #0 + 8008804: 5499 strb r1, [r3, r2] + + return HAL_OK; + 8008806: 2300 movs r3, #0 +} + 8008808: 0018 movs r0, r3 + 800880a: 46bd mov sp, r7 + 800880c: b004 add sp, #16 + 800880e: bd80 pop {r7, pc} + 8008810: 01ffffff .word 0x01ffffff + +08008814 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 8008814: b580 push {r7, lr} + 8008816: b084 sub sp, #16 + 8008818: af00 add r7, sp, #0 + 800881a: 60f8 str r0, [r7, #12] + 800881c: 60b9 str r1, [r7, #8] + 800881e: 603b str r3, [r7, #0] + 8008820: 1dfb adds r3, r7, #7 + 8008822: 701a strb r2, [r3, #0] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8008824: e05e b.n 80088e4 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8008826: 69bb ldr r3, [r7, #24] + 8008828: 3301 adds r3, #1 + 800882a: d05b beq.n 80088e4 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800882c: f7fe f85e bl 80068ec + 8008830: 0002 movs r2, r0 + 8008832: 683b ldr r3, [r7, #0] + 8008834: 1ad3 subs r3, r2, r3 + 8008836: 69ba ldr r2, [r7, #24] + 8008838: 429a cmp r2, r3 + 800883a: d302 bcc.n 8008842 + 800883c: 69bb ldr r3, [r7, #24] + 800883e: 2b00 cmp r3, #0 + 8008840: d11b bne.n 800887a + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 8008842: 68fb ldr r3, [r7, #12] + 8008844: 681b ldr r3, [r3, #0] + 8008846: 681a ldr r2, [r3, #0] + 8008848: 68fb ldr r3, [r7, #12] + 800884a: 681b ldr r3, [r3, #0] + 800884c: 492f ldr r1, [pc, #188] @ (800890c ) + 800884e: 400a ands r2, r1 + 8008850: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8008852: 68fb ldr r3, [r7, #12] + 8008854: 681b ldr r3, [r3, #0] + 8008856: 689a ldr r2, [r3, #8] + 8008858: 68fb ldr r3, [r7, #12] + 800885a: 681b ldr r3, [r3, #0] + 800885c: 2101 movs r1, #1 + 800885e: 438a bics r2, r1 + 8008860: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 8008862: 68fb ldr r3, [r7, #12] + 8008864: 2220 movs r2, #32 + 8008866: 679a str r2, [r3, #120] @ 0x78 + huart->RxState = HAL_UART_STATE_READY; + 8008868: 68fb ldr r3, [r7, #12] + 800886a: 2220 movs r2, #32 + 800886c: 67da str r2, [r3, #124] @ 0x7c + + __HAL_UNLOCK(huart); + 800886e: 68fb ldr r3, [r7, #12] + 8008870: 2274 movs r2, #116 @ 0x74 + 8008872: 2100 movs r1, #0 + 8008874: 5499 strb r1, [r3, r2] + + return HAL_TIMEOUT; + 8008876: 2303 movs r3, #3 + 8008878: e044 b.n 8008904 + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + 800887a: 68fb ldr r3, [r7, #12] + 800887c: 681b ldr r3, [r3, #0] + 800887e: 681b ldr r3, [r3, #0] + 8008880: 2204 movs r2, #4 + 8008882: 4013 ands r3, r2 + 8008884: d02e beq.n 80088e4 + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 8008886: 68fb ldr r3, [r7, #12] + 8008888: 681b ldr r3, [r3, #0] + 800888a: 69da ldr r2, [r3, #28] + 800888c: 2380 movs r3, #128 @ 0x80 + 800888e: 011b lsls r3, r3, #4 + 8008890: 401a ands r2, r3 + 8008892: 2380 movs r3, #128 @ 0x80 + 8008894: 011b lsls r3, r3, #4 + 8008896: 429a cmp r2, r3 + 8008898: d124 bne.n 80088e4 + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 800889a: 68fb ldr r3, [r7, #12] + 800889c: 681b ldr r3, [r3, #0] + 800889e: 2280 movs r2, #128 @ 0x80 + 80088a0: 0112 lsls r2, r2, #4 + 80088a2: 621a str r2, [r3, #32] + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 80088a4: 68fb ldr r3, [r7, #12] + 80088a6: 681b ldr r3, [r3, #0] + 80088a8: 681a ldr r2, [r3, #0] + 80088aa: 68fb ldr r3, [r7, #12] + 80088ac: 681b ldr r3, [r3, #0] + 80088ae: 4917 ldr r1, [pc, #92] @ (800890c ) + 80088b0: 400a ands r2, r1 + 80088b2: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80088b4: 68fb ldr r3, [r7, #12] + 80088b6: 681b ldr r3, [r3, #0] + 80088b8: 689a ldr r2, [r3, #8] + 80088ba: 68fb ldr r3, [r7, #12] + 80088bc: 681b ldr r3, [r3, #0] + 80088be: 2101 movs r1, #1 + 80088c0: 438a bics r2, r1 + 80088c2: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 80088c4: 68fb ldr r3, [r7, #12] + 80088c6: 2220 movs r2, #32 + 80088c8: 679a str r2, [r3, #120] @ 0x78 + huart->RxState = HAL_UART_STATE_READY; + 80088ca: 68fb ldr r3, [r7, #12] + 80088cc: 2220 movs r2, #32 + 80088ce: 67da str r2, [r3, #124] @ 0x7c + huart->ErrorCode = HAL_UART_ERROR_RTO; + 80088d0: 68fb ldr r3, [r7, #12] + 80088d2: 2280 movs r2, #128 @ 0x80 + 80088d4: 2120 movs r1, #32 + 80088d6: 5099 str r1, [r3, r2] + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 80088d8: 68fb ldr r3, [r7, #12] + 80088da: 2274 movs r2, #116 @ 0x74 + 80088dc: 2100 movs r1, #0 + 80088de: 5499 strb r1, [r3, r2] + + return HAL_TIMEOUT; + 80088e0: 2303 movs r3, #3 + 80088e2: e00f b.n 8008904 + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 80088e4: 68fb ldr r3, [r7, #12] + 80088e6: 681b ldr r3, [r3, #0] + 80088e8: 69db ldr r3, [r3, #28] + 80088ea: 68ba ldr r2, [r7, #8] + 80088ec: 4013 ands r3, r2 + 80088ee: 68ba ldr r2, [r7, #8] + 80088f0: 1ad3 subs r3, r2, r3 + 80088f2: 425a negs r2, r3 + 80088f4: 4153 adcs r3, r2 + 80088f6: b2db uxtb r3, r3 + 80088f8: 001a movs r2, r3 + 80088fa: 1dfb adds r3, r7, #7 + 80088fc: 781b ldrb r3, [r3, #0] + 80088fe: 429a cmp r2, r3 + 8008900: d091 beq.n 8008826 + } + } + } + } + return HAL_OK; + 8008902: 2300 movs r3, #0 +} + 8008904: 0018 movs r0, r3 + 8008906: 46bd mov sp, r7 + 8008908: b004 add sp, #16 + 800890a: bd80 pop {r7, pc} + 800890c: fffffe5f .word 0xfffffe5f + +08008910 : + 8008910: 0003 movs r3, r0 + 8008912: 1882 adds r2, r0, r2 + 8008914: 4293 cmp r3, r2 + 8008916: d100 bne.n 800891a + 8008918: 4770 bx lr + 800891a: 7019 strb r1, [r3, #0] + 800891c: 3301 adds r3, #1 + 800891e: e7f9 b.n 8008914 + +08008920 <__libc_init_array>: + 8008920: b570 push {r4, r5, r6, lr} + 8008922: 2600 movs r6, #0 + 8008924: 4c0c ldr r4, [pc, #48] @ (8008958 <__libc_init_array+0x38>) + 8008926: 4d0d ldr r5, [pc, #52] @ (800895c <__libc_init_array+0x3c>) + 8008928: 1b64 subs r4, r4, r5 + 800892a: 10a4 asrs r4, r4, #2 + 800892c: 42a6 cmp r6, r4 + 800892e: d109 bne.n 8008944 <__libc_init_array+0x24> + 8008930: 2600 movs r6, #0 + 8008932: f000 f823 bl 800897c <_init> + 8008936: 4c0a ldr r4, [pc, #40] @ (8008960 <__libc_init_array+0x40>) + 8008938: 4d0a ldr r5, [pc, #40] @ (8008964 <__libc_init_array+0x44>) + 800893a: 1b64 subs r4, r4, r5 + 800893c: 10a4 asrs r4, r4, #2 + 800893e: 42a6 cmp r6, r4 + 8008940: d105 bne.n 800894e <__libc_init_array+0x2e> + 8008942: bd70 pop {r4, r5, r6, pc} + 8008944: 00b3 lsls r3, r6, #2 + 8008946: 58eb ldr r3, [r5, r3] + 8008948: 4798 blx r3 + 800894a: 3601 adds r6, #1 + 800894c: e7ee b.n 800892c <__libc_init_array+0xc> + 800894e: 00b3 lsls r3, r6, #2 + 8008950: 58eb ldr r3, [r5, r3] + 8008952: 4798 blx r3 + 8008954: 3601 adds r6, #1 + 8008956: e7f2 b.n 800893e <__libc_init_array+0x1e> + 8008958: 08008b20 .word 0x08008b20 + 800895c: 08008b20 .word 0x08008b20 + 8008960: 08008b24 .word 0x08008b24 + 8008964: 08008b20 .word 0x08008b20 + +08008968 : + 8008968: 2300 movs r3, #0 + 800896a: b510 push {r4, lr} + 800896c: 429a cmp r2, r3 + 800896e: d100 bne.n 8008972 + 8008970: bd10 pop {r4, pc} + 8008972: 5ccc ldrb r4, [r1, r3] + 8008974: 54c4 strb r4, [r0, r3] + 8008976: 3301 adds r3, #1 + 8008978: e7f8 b.n 800896c + ... + +0800897c <_init>: + 800897c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800897e: 46c0 nop @ (mov r8, r8) + 8008980: bcf8 pop {r3, r4, r5, r6, r7} + 8008982: bc08 pop {r3} + 8008984: 469e mov lr, r3 + 8008986: 4770 bx lr + +08008988 <_fini>: + 8008988: b5f8 push {r3, r4, r5, r6, r7, lr} + 800898a: 46c0 nop @ (mov r8, r8) + 800898c: bcf8 pop {r3, r4, r5, r6, r7} + 800898e: bc08 pop {r3} + 8008990: 469e mov lr, r3 + 8008992: 4770 bx lr diff --git a/DBW_V2/Debug/DBW_V2.map b/DBW_V2/Debug/DBW_V2.map new file mode 100644 index 0000000..e0bcff6 --- /dev/null +++ b/DBW_V2/Debug/DBW_V2.map @@ -0,0 +1,5540 @@ +Archive member included to satisfy reference by file (symbol) + +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) (__stdio_exit_handler) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (_fwalk_sglue) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (__sread) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) (_close_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) (errno) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) (_impure_ptr) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) (_lseek_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) (_read_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) (_write_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + ./Core/Src/syscalls.o (__errno) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + ./Core/Src/main.o (memcpy) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) (_free_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (_malloc_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) (__malloc_lock) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (_fflush_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) (_sbrk_r) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + ./Core/Src/dbw.o (__aeabi_uidiv) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + ./Core/Src/dbw.o (__aeabi_idiv) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) (__aeabi_idiv0) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) + ./Core/Src/dbw.o (__aeabi_fcmplt) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + ./Core/Src/dbw.o (__aeabi_f2uiz) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + ./Core/Src/mazda_can.o (__aeabi_d2uiz) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + ./Core/Src/adc.o (__aeabi_fadd) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + ./Core/Src/adc.o (__aeabi_fdiv) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) (__eqsf2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) (__gesf2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) (__lesf2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + ./Core/Src/adc.o (__aeabi_fmul) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + ./Core/Src/adc.o (__aeabi_fsub) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + ./Core/Src/adc.o (__aeabi_f2iz) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + ./Core/Src/adc.o (__aeabi_i2f) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + ./Core/Src/adc.o (__aeabi_ui2f) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + ./Core/Src/mazda_can.o (__aeabi_dmul) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) (__aeabi_dsub) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) (__aeabi_d2iz) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + ./Core/Src/mazda_can.o (__aeabi_i2d) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) (__aeabi_dcmpge) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) (__clzsi2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) (__eqdf2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) (__gedf2) +C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) (__ledf2) + +Discarded input sections + + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + .data 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + .rodata 0x00000000 0x24 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x00000000 0x80 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.extab 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.exidx 0x00000000 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.attributes + 0x00000000 0x1b C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/adc.o + .text 0x00000000 0x0 ./Core/Src/adc.o + .data 0x00000000 0x0 ./Core/Src/adc.o + .bss 0x00000000 0x0 ./Core/Src/adc.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/can.o + .text 0x00000000 0x0 ./Core/Src/can.o + .data 0x00000000 0x0 ./Core/Src/can.o + .bss 0x00000000 0x0 ./Core/Src/can.o + .text.__NVIC_EnableIRQ + 0x00000000 0x34 ./Core/Src/can.o + .bss.CAN_TX_Msg + 0x00000000 0x10 ./Core/Src/can.o + .bss.CAN_RX_Msg + 0x00000000 0x10 ./Core/Src/can.o + .data.CAN_Speed + 0x00000000 0x4 ./Core/Src/can.o + .bss.CAN_Filter_Idx + 0x00000000 0x1 ./Core/Src/can.o + .text.CAN_Init + 0x00000000 0x80 ./Core/Src/can.o + .text.CAN_Setup + 0x00000000 0xec ./Core/Src/can.o + .text.CAN_Start + 0x00000000 0x2c ./Core/Src/can.o + .text.CAN_Wait_Ready + 0x00000000 0x28 ./Core/Src/can.o + .text.CAN_Recive_Msg + 0x00000000 0x118 ./Core/Src/can.o + .text.CAN_Write_Filter + 0x00000000 0x160 ./Core/Src/can.o + .debug_macro 0x00000000 0xaae ./Core/Src/can.o + .debug_macro 0x00000000 0x139 ./Core/Src/can.o + .debug_macro 0x00000000 0x2e ./Core/Src/can.o + .debug_macro 0x00000000 0x22 ./Core/Src/can.o + .debug_macro 0x00000000 0x22 ./Core/Src/can.o + .debug_macro 0x00000000 0x8e ./Core/Src/can.o + .debug_macro 0x00000000 0x51 ./Core/Src/can.o + .debug_macro 0x00000000 0x103 ./Core/Src/can.o + .debug_macro 0x00000000 0x6a ./Core/Src/can.o + .debug_macro 0x00000000 0x1df ./Core/Src/can.o + .debug_macro 0x00000000 0x1c ./Core/Src/can.o + .debug_macro 0x00000000 0x22 ./Core/Src/can.o + .debug_macro 0x00000000 0xaf ./Core/Src/can.o + .debug_macro 0x00000000 0x391 ./Core/Src/can.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/can.o + .debug_macro 0x00000000 0x3c ./Core/Src/can.o + .debug_macro 0x00000000 0x3461 ./Core/Src/can.o + .debug_macro 0x00000000 0x190 ./Core/Src/can.o + .debug_macro 0x00000000 0x55 ./Core/Src/can.o + .debug_macro 0x00000000 0x946 ./Core/Src/can.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/can.o + .debug_macro 0x00000000 0x12f ./Core/Src/can.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/can.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/can.o + .debug_macro 0x00000000 0x22c ./Core/Src/can.o + .debug_macro 0x00000000 0x34 ./Core/Src/can.o + .debug_macro 0x00000000 0x43 ./Core/Src/can.o + .debug_macro 0x00000000 0x28 ./Core/Src/can.o + .debug_macro 0x00000000 0x33d ./Core/Src/can.o + .debug_macro 0x00000000 0xd4 ./Core/Src/can.o + .debug_macro 0x00000000 0x408 ./Core/Src/can.o + .debug_macro 0x00000000 0xb0 ./Core/Src/can.o + .debug_macro 0x00000000 0x217 ./Core/Src/can.o + .debug_macro 0x00000000 0x22c ./Core/Src/can.o + .debug_macro 0x00000000 0x60 ./Core/Src/can.o + .debug_macro 0x00000000 0xa5 ./Core/Src/can.o + .debug_macro 0x00000000 0x4c ./Core/Src/can.o + .debug_macro 0x00000000 0x16d ./Core/Src/can.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/can.o + .debug_macro 0x00000000 0x44 ./Core/Src/can.o + .debug_macro 0x00000000 0x130 ./Core/Src/can.o + .debug_macro 0x00000000 0xca ./Core/Src/can.o + .debug_macro 0x00000000 0x108 ./Core/Src/can.o + .debug_macro 0x00000000 0x4c ./Core/Src/can.o + .debug_macro 0x00000000 0x58 ./Core/Src/can.o + .debug_macro 0x00000000 0xd0 ./Core/Src/can.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/dbw.o + .text 0x00000000 0x0 ./Core/Src/dbw.o + .data 0x00000000 0x0 ./Core/Src/dbw.o + .bss 0x00000000 0x0 ./Core/Src/dbw.o + .bss.ctl_period + 0x00000000 0x2 ./Core/Src/dbw.o + .text.intrp_1d_uitable + 0x00000000 0x10c ./Core/Src/dbw.o + .text.intrp_1dstable + 0x00000000 0x1b4 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xaae ./Core/Src/dbw.o + .debug_macro 0x00000000 0x139 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x2e ./Core/Src/dbw.o + .debug_macro 0x00000000 0x22 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x22 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x8e ./Core/Src/dbw.o + .debug_macro 0x00000000 0x51 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x103 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x6a ./Core/Src/dbw.o + .debug_macro 0x00000000 0x1df ./Core/Src/dbw.o + .debug_macro 0x00000000 0x1c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x22 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xaf ./Core/Src/dbw.o + .debug_macro 0x00000000 0x391 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x3c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x3461 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x190 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x55 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x946 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x12f ./Core/Src/dbw.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x22c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x34 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x43 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x28 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x33d ./Core/Src/dbw.o + .debug_macro 0x00000000 0xd4 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x408 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xb0 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x217 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x22c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x60 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xa5 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x4c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x16d ./Core/Src/dbw.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x44 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x130 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xca ./Core/Src/dbw.o + .debug_macro 0x00000000 0x108 ./Core/Src/dbw.o + .debug_macro 0x00000000 0x4c ./Core/Src/dbw.o + .debug_macro 0x00000000 0x58 ./Core/Src/dbw.o + .debug_macro 0x00000000 0xd0 ./Core/Src/dbw.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/inputs.o + .text 0x00000000 0x0 ./Core/Src/inputs.o + .data 0x00000000 0x0 ./Core/Src/inputs.o + .bss 0x00000000 0x0 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xaae ./Core/Src/inputs.o + .debug_macro 0x00000000 0x139 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x2e ./Core/Src/inputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x8e ./Core/Src/inputs.o + .debug_macro 0x00000000 0x51 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x103 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x6a ./Core/Src/inputs.o + .debug_macro 0x00000000 0x1df ./Core/Src/inputs.o + .debug_macro 0x00000000 0x1c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xaf ./Core/Src/inputs.o + .debug_macro 0x00000000 0x391 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x3c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x3461 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x190 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x55 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x946 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x12f ./Core/Src/inputs.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x22c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x34 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x43 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x28 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x33d ./Core/Src/inputs.o + .debug_macro 0x00000000 0xd4 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x408 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xb0 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x217 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x22c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x60 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xa5 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x4c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x16d ./Core/Src/inputs.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x44 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x130 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xca ./Core/Src/inputs.o + .debug_macro 0x00000000 0x108 ./Core/Src/inputs.o + .debug_macro 0x00000000 0x4c ./Core/Src/inputs.o + .debug_macro 0x00000000 0x58 ./Core/Src/inputs.o + .debug_macro 0x00000000 0xd0 ./Core/Src/inputs.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/main.o + .text 0x00000000 0x0 ./Core/Src/main.o + .data 0x00000000 0x0 ./Core/Src/main.o + .bss 0x00000000 0x0 ./Core/Src/main.o + .bss.hcan 0x00000000 0x28 ./Core/Src/main.o + .debug_macro 0x00000000 0xaae ./Core/Src/main.o + .debug_macro 0x00000000 0x139 ./Core/Src/main.o + .debug_macro 0x00000000 0x2e ./Core/Src/main.o + .debug_macro 0x00000000 0x22 ./Core/Src/main.o + .debug_macro 0x00000000 0x22 ./Core/Src/main.o + .debug_macro 0x00000000 0x8e ./Core/Src/main.o + .debug_macro 0x00000000 0x51 ./Core/Src/main.o + .debug_macro 0x00000000 0x103 ./Core/Src/main.o + .debug_macro 0x00000000 0x6a ./Core/Src/main.o + .debug_macro 0x00000000 0x1df ./Core/Src/main.o + .debug_macro 0x00000000 0x1c ./Core/Src/main.o + .debug_macro 0x00000000 0x22 ./Core/Src/main.o + .debug_macro 0x00000000 0xaf ./Core/Src/main.o + .debug_macro 0x00000000 0x391 ./Core/Src/main.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/main.o + .debug_macro 0x00000000 0x3c ./Core/Src/main.o + .debug_macro 0x00000000 0x3461 ./Core/Src/main.o + .debug_macro 0x00000000 0x190 ./Core/Src/main.o + .debug_macro 0x00000000 0x55 ./Core/Src/main.o + .debug_macro 0x00000000 0x946 ./Core/Src/main.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/main.o + .debug_macro 0x00000000 0x12f ./Core/Src/main.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/main.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/main.o + .debug_macro 0x00000000 0x22c ./Core/Src/main.o + .debug_macro 0x00000000 0x34 ./Core/Src/main.o + .debug_macro 0x00000000 0x43 ./Core/Src/main.o + .debug_macro 0x00000000 0x28 ./Core/Src/main.o + .debug_macro 0x00000000 0x33d ./Core/Src/main.o + .debug_macro 0x00000000 0xd4 ./Core/Src/main.o + .debug_macro 0x00000000 0x408 ./Core/Src/main.o + .debug_macro 0x00000000 0xb0 ./Core/Src/main.o + .debug_macro 0x00000000 0x217 ./Core/Src/main.o + .debug_macro 0x00000000 0x22c ./Core/Src/main.o + .debug_macro 0x00000000 0x60 ./Core/Src/main.o + .debug_macro 0x00000000 0xa5 ./Core/Src/main.o + .debug_macro 0x00000000 0x4c ./Core/Src/main.o + .debug_macro 0x00000000 0x16d ./Core/Src/main.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/main.o + .debug_macro 0x00000000 0x44 ./Core/Src/main.o + .debug_macro 0x00000000 0x130 ./Core/Src/main.o + .debug_macro 0x00000000 0xca ./Core/Src/main.o + .debug_macro 0x00000000 0x108 ./Core/Src/main.o + .debug_macro 0x00000000 0x4c ./Core/Src/main.o + .debug_macro 0x00000000 0x58 ./Core/Src/main.o + .debug_macro 0x00000000 0xd0 ./Core/Src/main.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/mazda_can.o + .text 0x00000000 0x0 ./Core/Src/mazda_can.o + .data 0x00000000 0x0 ./Core/Src/mazda_can.o + .bss 0x00000000 0x0 ./Core/Src/mazda_can.o + .bss.var_time 0x00000000 0x4 ./Core/Src/mazda_can.o + .bss.rpm_time 0x00000000 0x4 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xaae ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x139 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x2e ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x22 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x22 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x8e ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x51 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x103 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x6a ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x1df ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x1c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x22 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xaf ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x391 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x3c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x3461 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x190 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x55 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x946 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x12f ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x22c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x34 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x43 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x28 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x33d ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xd4 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x408 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xb0 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x217 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x22c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x60 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xa5 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x4c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x16d ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x44 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x130 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xca ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x108 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x4c ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0x58 ./Core/Src/mazda_can.o + .debug_macro 0x00000000 0xd0 ./Core/Src/mazda_can.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/outputs.o + .text 0x00000000 0x0 ./Core/Src/outputs.o + .data 0x00000000 0x0 ./Core/Src/outputs.o + .bss 0x00000000 0x0 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xaae ./Core/Src/outputs.o + .debug_macro 0x00000000 0x139 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x2e ./Core/Src/outputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x8e ./Core/Src/outputs.o + .debug_macro 0x00000000 0x51 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x103 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x6a ./Core/Src/outputs.o + .debug_macro 0x00000000 0x1df ./Core/Src/outputs.o + .debug_macro 0x00000000 0x1c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x22 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xaf ./Core/Src/outputs.o + .debug_macro 0x00000000 0x391 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x3c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x3461 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x190 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x55 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x946 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x12f ./Core/Src/outputs.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x22c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x34 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x43 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x28 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x33d ./Core/Src/outputs.o + .debug_macro 0x00000000 0xd4 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x408 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xb0 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x217 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x22c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x60 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xa5 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x4c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x16d ./Core/Src/outputs.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x44 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x130 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xca ./Core/Src/outputs.o + .debug_macro 0x00000000 0x108 ./Core/Src/outputs.o + .debug_macro 0x00000000 0x4c ./Core/Src/outputs.o + .debug_macro 0x00000000 0x58 ./Core/Src/outputs.o + .debug_macro 0x00000000 0xd0 ./Core/Src/outputs.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/safety.o + .text 0x00000000 0x0 ./Core/Src/safety.o + .data 0x00000000 0x0 ./Core/Src/safety.o + .bss 0x00000000 0x0 ./Core/Src/safety.o + .text.Flash_Write_Protect + 0x00000000 0x50 ./Core/Src/safety.o + .text.Flash_Write_Unprotect + 0x00000000 0x50 ./Core/Src/safety.o + .text.Watch_Dog_Update + 0x00000000 0x18 ./Core/Src/safety.o + .text.Watch_Dog_Init + 0x00000000 0x64 ./Core/Src/safety.o + .debug_macro 0x00000000 0xaae ./Core/Src/safety.o + .debug_macro 0x00000000 0x139 ./Core/Src/safety.o + .debug_macro 0x00000000 0x2e ./Core/Src/safety.o + .debug_macro 0x00000000 0x22 ./Core/Src/safety.o + .debug_macro 0x00000000 0x22 ./Core/Src/safety.o + .debug_macro 0x00000000 0x8e ./Core/Src/safety.o + .debug_macro 0x00000000 0x51 ./Core/Src/safety.o + .debug_macro 0x00000000 0x103 ./Core/Src/safety.o + .debug_macro 0x00000000 0x6a ./Core/Src/safety.o + .debug_macro 0x00000000 0x1df ./Core/Src/safety.o + .debug_macro 0x00000000 0x1c ./Core/Src/safety.o + .debug_macro 0x00000000 0x22 ./Core/Src/safety.o + .debug_macro 0x00000000 0xaf ./Core/Src/safety.o + .debug_macro 0x00000000 0x391 ./Core/Src/safety.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/safety.o + .debug_macro 0x00000000 0x3c ./Core/Src/safety.o + .debug_macro 0x00000000 0x3461 ./Core/Src/safety.o + .debug_macro 0x00000000 0x190 ./Core/Src/safety.o + .debug_macro 0x00000000 0x55 ./Core/Src/safety.o + .debug_macro 0x00000000 0x946 ./Core/Src/safety.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/safety.o + .debug_macro 0x00000000 0x12f ./Core/Src/safety.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/safety.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/safety.o + .debug_macro 0x00000000 0x22c ./Core/Src/safety.o + .debug_macro 0x00000000 0x34 ./Core/Src/safety.o + .debug_macro 0x00000000 0x43 ./Core/Src/safety.o + .debug_macro 0x00000000 0x28 ./Core/Src/safety.o + .debug_macro 0x00000000 0x33d ./Core/Src/safety.o + .debug_macro 0x00000000 0xd4 ./Core/Src/safety.o + .debug_macro 0x00000000 0x408 ./Core/Src/safety.o + .debug_macro 0x00000000 0xb0 ./Core/Src/safety.o + .debug_macro 0x00000000 0x217 ./Core/Src/safety.o + .debug_macro 0x00000000 0x22c ./Core/Src/safety.o + .debug_macro 0x00000000 0x60 ./Core/Src/safety.o + .debug_macro 0x00000000 0xa5 ./Core/Src/safety.o + .debug_macro 0x00000000 0x4c ./Core/Src/safety.o + .debug_macro 0x00000000 0x16d ./Core/Src/safety.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/safety.o + .debug_macro 0x00000000 0x44 ./Core/Src/safety.o + .debug_macro 0x00000000 0x130 ./Core/Src/safety.o + .debug_macro 0x00000000 0xca ./Core/Src/safety.o + .debug_macro 0x00000000 0x108 ./Core/Src/safety.o + .debug_macro 0x00000000 0x4c ./Core/Src/safety.o + .debug_macro 0x00000000 0x58 ./Core/Src/safety.o + .debug_macro 0x00000000 0xd0 ./Core/Src/safety.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_hal_msp.o + .text 0x00000000 0x0 ./Core/Src/stm32f0xx_hal_msp.o + .data 0x00000000 0x0 ./Core/Src/stm32f0xx_hal_msp.o + .bss 0x00000000 0x0 ./Core/Src/stm32f0xx_hal_msp.o + .text.HAL_ADC_MspDeInit + 0x00000000 0x40 ./Core/Src/stm32f0xx_hal_msp.o + .text.HAL_CAN_MspInit + 0x00000000 0x9c ./Core/Src/stm32f0xx_hal_msp.o + .text.HAL_CAN_MspDeInit + 0x00000000 0x44 ./Core/Src/stm32f0xx_hal_msp.o + .text.HAL_UART_MspDeInit + 0x00000000 0x44 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xaae ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x139 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x2e ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x8e ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x51 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x103 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x6a ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x1df ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xaf ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x391 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x3c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x3461 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x190 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x55 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x946 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x12f ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x22c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x43 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x28 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x33d ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xd4 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x408 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xb0 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x217 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x22c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x60 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xa5 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x4c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x16d ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x44 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x130 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xca ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x108 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x4c ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0x58 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00000000 0xd0 ./Core/Src/stm32f0xx_hal_msp.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/stm32f0xx_it.o + .text 0x00000000 0x0 ./Core/Src/stm32f0xx_it.o + .data 0x00000000 0x0 ./Core/Src/stm32f0xx_it.o + .bss 0x00000000 0x0 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xaae ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x139 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x2e ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x8e ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x51 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x103 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x6a ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x1df ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x1c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x22 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xaf ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x391 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x3c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x3461 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x190 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x55 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x946 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x12f ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x22c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x34 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x43 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x28 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x33d ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xd4 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x408 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xb0 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x217 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x22c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x60 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xa5 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x4c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x16d ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x44 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x130 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xca ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x108 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x4c ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0x58 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00000000 0xd0 ./Core/Src/stm32f0xx_it.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/syscalls.o + .text 0x00000000 0x0 ./Core/Src/syscalls.o + .data 0x00000000 0x0 ./Core/Src/syscalls.o + .bss 0x00000000 0x0 ./Core/Src/syscalls.o + .bss.__env 0x00000000 0x4 ./Core/Src/syscalls.o + .data.environ 0x00000000 0x4 ./Core/Src/syscalls.o + .text.initialise_monitor_handles + 0x00000000 0xa ./Core/Src/syscalls.o + .text._getpid 0x00000000 0xc ./Core/Src/syscalls.o + .text._kill 0x00000000 0x20 ./Core/Src/syscalls.o + .text._exit 0x00000000 0x1a ./Core/Src/syscalls.o + .text._read 0x00000000 0x3a ./Core/Src/syscalls.o + .text._write 0x00000000 0x38 ./Core/Src/syscalls.o + .text._close 0x00000000 0x14 ./Core/Src/syscalls.o + .text._fstat 0x00000000 0x1c ./Core/Src/syscalls.o + .text._isatty 0x00000000 0x12 ./Core/Src/syscalls.o + .text._lseek 0x00000000 0x16 ./Core/Src/syscalls.o + .text._open 0x00000000 0x1c ./Core/Src/syscalls.o + .text._wait 0x00000000 0x1e ./Core/Src/syscalls.o + .text._unlink 0x00000000 0x1e ./Core/Src/syscalls.o + .text._times 0x00000000 0x14 ./Core/Src/syscalls.o + .text._stat 0x00000000 0x1c ./Core/Src/syscalls.o + .text._link 0x00000000 0x20 ./Core/Src/syscalls.o + .text._fork 0x00000000 0x18 ./Core/Src/syscalls.o + .text._execve 0x00000000 0x22 ./Core/Src/syscalls.o + .debug_info 0x00000000 0x6b0 ./Core/Src/syscalls.o + .debug_abbrev 0x00000000 0x1b6 ./Core/Src/syscalls.o + .debug_aranges + 0x00000000 0xa8 ./Core/Src/syscalls.o + .debug_rnglists + 0x00000000 0x79 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x274 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0xaae ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x22 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x5b ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x24 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x94 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x43 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x34 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x57 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x190 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x364 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x4a ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x34 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x58 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x8e ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x17e ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x3c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x6a ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x52 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x22 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x52 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0xcf ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x3d ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x35 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x12c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x29 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x242 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x1c ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x10 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x146 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x103 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x1df ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x18a ./Core/Src/syscalls.o + .debug_macro 0x00000000 0x16 ./Core/Src/syscalls.o + .debug_macro 0x00000000 0xce ./Core/Src/syscalls.o + .debug_line 0x00000000 0x8b7 ./Core/Src/syscalls.o + .debug_str 0x00000000 0x9857 ./Core/Src/syscalls.o + .comment 0x00000000 0x44 ./Core/Src/syscalls.o + .debug_frame 0x00000000 0x244 ./Core/Src/syscalls.o + .ARM.attributes + 0x00000000 0x2c ./Core/Src/syscalls.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/sysmem.o + .text 0x00000000 0x0 ./Core/Src/sysmem.o + .data 0x00000000 0x0 ./Core/Src/sysmem.o + .bss 0x00000000 0x0 ./Core/Src/sysmem.o + .text._sbrk 0x00000000 0x58 ./Core/Src/sysmem.o + .bss.heap_end.0 + 0x00000000 0x4 ./Core/Src/sysmem.o + .debug_info 0x00000000 0x104 ./Core/Src/sysmem.o + .debug_abbrev 0x00000000 0xc0 ./Core/Src/sysmem.o + .debug_aranges + 0x00000000 0x20 ./Core/Src/sysmem.o + .debug_rnglists + 0x00000000 0x13 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1aa ./Core/Src/sysmem.o + .debug_macro 0x00000000 0xaae ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x22 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x5b ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x24 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x94 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x43 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x34 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x190 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x57 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x364 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x16 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x4a ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x34 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x58 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x8e ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x17e ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x23c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x3c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x16 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x146 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x6a ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x52 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x22 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x10 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x52 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0xc1 ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x1c ./Core/Src/sysmem.o + .debug_macro 0x00000000 0x3d ./Core/Src/sysmem.o + .debug_line 0x00000000 0x615 ./Core/Src/sysmem.o + .debug_str 0x00000000 0x7b35 ./Core/Src/sysmem.o + .comment 0x00000000 0x44 ./Core/Src/sysmem.o + .debug_frame 0x00000000 0x30 ./Core/Src/sysmem.o + .ARM.attributes + 0x00000000 0x2c ./Core/Src/sysmem.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/system_stm32f0xx.o + .text 0x00000000 0x0 ./Core/Src/system_stm32f0xx.o + .data 0x00000000 0x0 ./Core/Src/system_stm32f0xx.o + .bss 0x00000000 0x0 ./Core/Src/system_stm32f0xx.o + .text.SystemCoreClockUpdate + 0x00000000 0x10c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xaae ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x2e ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x22 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x22 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x8e ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x51 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x103 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x6a ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x1df ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x1c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x22 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xaf ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x391 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x3c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x139 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x3461 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x190 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x55 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x946 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x12f ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x22c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x34 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x43 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x28 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x33d ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xd4 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x408 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xb0 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x217 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x22c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x60 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0xa5 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x4c ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x16d ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x44 ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00000000 0x130 ./Core/Src/system_stm32f0xx.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .group 0x00000000 0xc ./Core/Src/ts_comms.o + .text 0x00000000 0x0 ./Core/Src/ts_comms.o + .data 0x00000000 0x0 ./Core/Src/ts_comms.o + .bss 0x00000000 0x0 ./Core/Src/ts_comms.o + .text.calc_crc + 0x00000000 0x98 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xaae ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x139 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x2e ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x22 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x22 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x8e ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x51 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x103 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x6a ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x1df ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x1c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x22 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xaf ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x391 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xfe50 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x3c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x3461 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x190 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x55 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x946 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x5f3 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x12f ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x1a7 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x22c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x34 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x43 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x28 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x33d ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xd4 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x408 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xb0 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x217 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x22c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x60 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xa5 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x4c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x16d ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x5a5 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x44 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x130 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xca ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x108 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x4c ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0x58 ./Core/Src/ts_comms.o + .debug_macro 0x00000000 0xd0 ./Core/Src/ts_comms.o + .text 0x00000000 0x14 ./Core/Startup/startup_stm32f072c8tx.o + .data 0x00000000 0x0 ./Core/Startup/startup_stm32f072c8tx.o + .bss 0x00000000 0x0 ./Core/Startup/startup_stm32f072c8tx.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DeInit + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspInit + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_MspDeInit + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetTickPrio + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_SetTickFreq + 0x00000000 0x6c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetTickFreq + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_Delay + 0x00000000 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_SuspendTick + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_ResumeTick + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetHalVersion + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetREVID + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetDEVID + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw0 + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw1 + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_GetUIDw2 + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_DeInit + 0x00000000 0x114 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_MspInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_MspDeInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Start + 0x00000000 0xa8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Stop + 0x00000000 0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_PollForConversion + 0x00000000 0x124 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_PollForEvent + 0x00000000 0xb2 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Start_IT + 0x00000000 0xe4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Stop_IT + 0x00000000 0x94 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Start_DMA + 0x00000000 0x104 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_Stop_DMA + 0x00000000 0xec ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_GetValue + 0x00000000 0x16 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_IRQHandler + 0x00000000 0x170 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_ConvCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_ConvHalfCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_LevelOutOfWindowCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_ErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_AnalogWDGConfig + 0x00000000 0x11c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_GetState + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.HAL_ADC_GetError + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_Enable + 0x00000000 0xf8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_Disable + 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_ConversionStop + 0x00000000 0x8c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_DMAConvCplt + 0x00000000 0xb4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_DMAHalfConvCplt + 0x00000000 0x1e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .text.ADC_DMAError + 0x00000000 0x36 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .text.HAL_ADCEx_Calibration_Start + 0x00000000 0x13c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_info 0x00000000 0x571 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_abbrev 0x00000000 0x181 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_aranges + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_rnglists + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x1d8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_line 0x00000000 0x80e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_str 0x00000000 0x8f061 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .debug_frame 0x00000000 0x30 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_Init + 0x00000000 0x1fc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_DeInit + 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_MspInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_MspDeInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_ConfigFilter + 0x00000000 0x1e4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_Start + 0x00000000 0x8c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_Stop + 0x00000000 0x96 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_RequestSleep + 0x00000000 0x52 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_WakeUp + 0x00000000 0x8c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_IsSleepActive + 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_AddTxMessage + 0x00000000 0x1bc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_AbortTxRequest + 0x00000000 0x90 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetTxMailboxesFreeLevel + 0x00000000 0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_IsTxMessagePending + 0x00000000 0x4e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetTxTimestamp + 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetRxMessage + 0x00000000 0x238 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetRxFifoFillLevel + 0x00000000 0x56 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_ActivateNotification + 0x00000000 0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_DeactivateNotification + 0x00000000 0x56 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_IRQHandler + 0x00000000 0x368 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox0CompleteCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox1CompleteCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox2CompleteCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox0AbortCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox1AbortCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_TxMailbox2AbortCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_RxFifo0MsgPendingCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_RxFifo0FullCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_RxFifo1MsgPendingCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_RxFifo1FullCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_SleepCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_WakeUpFromRxMsgCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_ErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetState + 0x00000000 0x5e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_GetError + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .text.HAL_CAN_ResetError + 0x00000000 0x5a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_info 0x00000000 0xeab ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_abbrev 0x00000000 0x1cd ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_aranges + 0x00000000 0x138 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_rnglists + 0x00000000 0xee ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x1d4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_line 0x00000000 0x1209 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_str 0x00000000 0x8f4ab ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .debug_frame 0x00000000 0x490 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_GetPendingIRQ + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_SetPendingIRQ + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_ClearPendingIRQ + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_GetPriority + 0x00000000 0x7c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.__NVIC_SystemReset + 0x00000000 0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_EnableIRQ + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x00000000 0x8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x00000000 0xe ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Init + 0x00000000 0x90 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x00000000 0x92 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start + 0x00000000 0x92 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x00000000 0xcc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort + 0x00000000 0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x00000000 0x8a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x00000000 0x132 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x00000000 0x144 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x00000000 0xa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .rodata.HAL_DMA_UnRegisterCallback + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetState + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.HAL_DMA_GetError + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.DMA_SetConfig + 0x00000000 0x58 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .text.DMA_CalcBaseAndBitshift + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_info 0x00000000 0x6ea ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_abbrev 0x00000000 0x224 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_aranges + 0x00000000 0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_rnglists + 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_line 0x00000000 0xcf8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_str 0x00000000 0x8f080 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .debug_frame 0x00000000 0x1d0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_SetConfigLine + 0x00000000 0x148 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_GetConfigLine + 0x00000000 0xfc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_ClearConfigLine + 0x00000000 0xc0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_RegisterCallback + 0x00000000 0x42 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_GetHandle + 0x00000000 0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_IRQHandler + 0x00000000 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_GetPending + 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_ClearPending + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .text.HAL_EXTI_GenerateSWI + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_info 0x00000000 0x4d8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_abbrev 0x00000000 0x1c6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_aranges + 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_rnglists + 0x00000000 0x46 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_line 0x00000000 0xa79 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_str 0x00000000 0x8ee3e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .debug_frame 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x00000000 0xa4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x00000000 0x1d0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x00000000 0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBErase + 0x00000000 0x9c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x00000000 0x124 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetUserData + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_EnableWRP + 0x00000000 0x1ac ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_DisableWRP + 0x00000000 0x1a8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x00000000 0xc0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_UserConfig + 0x00000000 0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_ProgramData + 0x00000000 0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_GetWRP + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_GetRDP + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_OB_GetUser + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x00000000 0x1b0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_ReadPin + 0x00000000 0x3a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x00000000 0x52 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Init + 0x00000000 0x12c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x00000000 0x210 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x00000000 0x210 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x00000000 0x214 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x00000000 0xf8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x00000000 0xf8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x00000000 0xac ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x00000000 0xac ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x00000000 0x20c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x00000000 0x20c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x00000000 0x180 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x00000000 0x180 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x00000000 0x25c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x00000000 0x268 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x00000000 0x150 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x00000000 0x154 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x00000000 0x21c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x00000000 0x220 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x00000000 0x234 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_IT + 0x00000000 0x124 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_DMA + 0x00000000 0x234 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_IT + 0x00000000 0x124 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_DMA + 0x00000000 0x234 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_IT + 0x00000000 0x160 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_DMA + 0x00000000 0x298 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_IT + 0x00000000 0x164 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_DMA + 0x00000000 0x294 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x00000000 0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x00000000 0xac ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x00000000 0xc4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x00000000 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x00000000 0x284 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x00000000 0x228 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x00000000 0x218 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x00000000 0x1ec ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x00000000 0xc8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x00000000 0xc4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITAddrCplt + 0x00000000 0x148 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterSeqCplt + 0x00000000 0x82 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveSeqCplt + 0x00000000 0xcc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x00000000 0x1a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x00000000 0x248 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x00000000 0xb4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ITError + 0x00000000 0x1c4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_TreatErrorCallback + 0x00000000 0x52 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x00000000 0xa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x00000000 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x00000000 0xa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x00000000 0x50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAError + 0x00000000 0x32 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_DMAAbort + 0x00000000 0x3e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x00000000 0x7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x00000000 0x7e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x00000000 0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x00000000 0xd8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x00000000 0xcc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_TransferConfig + 0x00000000 0x6c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x00000000 0xd0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x00000000 0xc6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .text.I2C_ConvertOtherXferOptions + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_info 0x00000000 0x1f3f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_abbrev 0x00000000 0x259 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_aranges + 0x00000000 0x290 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_rnglists + 0x00000000 0x218 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x291 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_line 0x00000000 0x3170 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_str 0x00000000 0x8ff9f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .debug_frame 0x00000000 0xa24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x00000000 0x98 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x00000000 0x98 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableWakeUp + 0x00000000 0x82 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableWakeUp + 0x00000000 0x84 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableFastModePlus + 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableFastModePlus + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_info 0x00000000 0x816 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_abbrev 0x00000000 0x1c3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_aranges + 0x00000000 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_rnglists + 0x00000000 0x35 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_line 0x00000000 0x8e3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_str 0x00000000 0x8f24c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .debug_frame 0x00000000 0xd0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x00000000 0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x00000000 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x00000000 0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_info 0x00000000 0x3a8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_abbrev 0x00000000 0x142 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_aranges + 0x00000000 0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_rnglists + 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_line 0x00000000 0x8d8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_str 0x00000000 0x8ee17 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .debug_frame 0x00000000 0x170 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWR_ConfigPVD + 0x00000000 0xc4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWR_EnablePVD + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWR_DisablePVD + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWR_PVD_IRQHandler + 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWR_PVDCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableVddio2Monitor + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableVddio2Monitor + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWREx_Vddio2Monitor_IRQHandler + 0x00000000 0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .text.HAL_PWREx_Vddio2MonitorCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_info 0x00000000 0x214 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_abbrev 0x00000000 0x13b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_aranges + 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_rnglists + 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1e4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_line 0x00000000 0x884 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_str 0x00000000 0x8edd0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .debug_frame 0x00000000 0x110 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x00000000 0x10c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x00000000 0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_DisableCSS + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x00000000 0x158 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x00000000 0x54 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x00000000 0x94 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x00000000 0x324 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRSConfig + 0x00000000 0x90 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate + 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRSGetSynchronizationInfo + 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRSWaitSynchronization + 0x00000000 0xf4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRS_IRQHandler + 0x00000000 0xcc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRS_SyncOkCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRS_SyncWarnCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRS_ExpectedSyncCallback + 0x00000000 0xa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .text.HAL_RCCEx_CRS_ErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_info 0x00000000 0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_abbrev 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_aranges + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x1cd ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_line 0x00000000 0x773 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .debug_str 0x00000000 0x8ec0e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_info 0x00000000 0x70 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_abbrev 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_aranges + 0x00000000 0x18 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_line 0x00000000 0x776 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .debug_str 0x00000000 0x8ec11 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_HalfDuplex_Init + 0x00000000 0xb8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_LIN_Init + 0x00000000 0xf0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_MultiProcessor_Init + 0x00000000 0xf0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_DeInit + 0x00000000 0x74 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_MspInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_MspDeInit + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Transmit + 0x00000000 0x150 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Receive + 0x00000000 0x1e0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Transmit_IT + 0x00000000 0xdc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Receive_IT + 0x00000000 0xa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Transmit_DMA + 0x00000000 0x124 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Receive_DMA + 0x00000000 0xa0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_DMAPause + 0x00000000 0xa8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_DMAResume + 0x00000000 0x8a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_DMAStop + 0x00000000 0xda ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Abort + 0x00000000 0x140 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortTransmit + 0x00000000 0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortReceive + 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_Abort_IT + 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortTransmit_IT + 0x00000000 0xac ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortReceive_IT + 0x00000000 0x104 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_IRQHandler + 0x00000000 0x404 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_TxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_TxHalfCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_RxCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_RxHalfCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_ErrorCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortTransmitCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_AbortReceiveCpltCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UARTEx_RxEventCallback + 0x00000000 0x16 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_ReceiverTimeout_Config + 0x00000000 0x26 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_EnableReceiverTimeout + 0x00000000 0x5a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_DisableReceiverTimeout + 0x00000000 0x5c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_MultiProcessor_EnableMuteMode + 0x00000000 0x4e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_MultiProcessor_DisableMuteMode + 0x00000000 0x50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_MultiProcessor_EnterMuteMode + 0x00000000 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_HalfDuplex_EnableTransmitter + 0x00000000 0x5c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_HalfDuplex_EnableReceiver + 0x00000000 0x5c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_LIN_SendBreak + 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_GetState + 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.HAL_UART_GetError + 0x00000000 0x16 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_Start_Receive_IT + 0x00000000 0x11c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_Start_Receive_DMA + 0x00000000 0xdc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_EndTxTransfer + 0x00000000 0x26 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_EndRxTransfer + 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMATransmitCplt + 0x00000000 0x50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x00000000 0x1e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMAReceiveCplt + 0x00000000 0x9c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMARxHalfCplt + 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMAError + 0x00000000 0x82 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMAAbortOnError + 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMATxAbortCallback + 0x00000000 0x6c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMARxAbortCallback + 0x00000000 0x7c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMATxOnlyAbortCallback + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_DMARxOnlyAbortCallback + 0x00000000 0x4a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_TxISR_8BIT + 0x00000000 0x6e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_TxISR_16BIT + 0x00000000 0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_EndTransmit_IT + 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_RxISR_8BIT + 0x00000000 0xe8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .text.UART_RxISR_16BIT + 0x00000000 0xe8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .group 0x00000000 0xc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .data 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .bss 0x00000000 0x0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_RS485Ex_Init + 0x00000000 0xe0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_WakeupCallback + 0x00000000 0x10 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_MultiProcessorEx_AddressLength_Set + 0x00000000 0x62 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_StopModeWakeUpSourceConfig + 0x00000000 0xcc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_EnableStopMode + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_DisableStopMode + 0x00000000 0x40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle + 0x00000000 0x248 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_IT + 0x00000000 0xbe ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_DMA + 0x00000000 0xbe ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text.UARTEx_Wakeup_AddressConfig + 0x00000000 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_info 0x00000000 0xa40 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_abbrev 0x00000000 0x21c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_aranges + 0x00000000 0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_rnglists + 0x00000000 0x4e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xaae ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x139 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x2e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x8e ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x51 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x103 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x6a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x1df ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x22 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xaf ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x391 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xfe50 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x3461 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x190 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x55 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x946 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x5f3 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x12f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x1a7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x34 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x43 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x33d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xd4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x408 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xb0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x217 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x22c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0xa5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x16d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x5a5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_macro 0x00000000 0x130 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_line 0x00000000 0xb09 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_str 0x00000000 0x8f2fa ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .comment 0x00000000 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .debug_frame 0x00000000 0x158 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .ARM.attributes + 0x00000000 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .text.exit 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .debug_frame 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-exit.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.std 0x00000000 0x6c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.stdio_exit_handler + 0x00000000 0x1c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.cleanup_stdio + 0x00000000 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__fp_lock + 0x00000000 0x18 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__fp_unlock + 0x00000000 0x18 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.global_stdio_init.part.0 + 0x00000000 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__sfp_lock_acquire + 0x00000000 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__sfp_lock_release + 0x00000000 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__sfp 0x00000000 0xa8 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__sinit 0x00000000 0x30 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__fp_lock_all + 0x00000000 0x1c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text.__fp_unlock_all + 0x00000000 0x1c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .data.__sglue 0x00000000 0xc C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .bss.__sf 0x00000000 0x138 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .bss.__stdio_exit_handler + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .debug_frame 0x00000000 0x138 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .text._fwalk_sglue + 0x00000000 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .debug_frame 0x00000000 0x34 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fwalk.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text.__sread 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text.__seofread + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text.__swrite + 0x00000000 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text.__sseek 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text.__sclose + 0x00000000 0xc C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .debug_frame 0x00000000 0x90 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-stdio.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .text._close_r + 0x00000000 0x24 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-closer.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .text._reclaim_reent + 0x00000000 0xd4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .bss.errno 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-reent.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .data._impure_ptr + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .data._impure_data + 0x00000000 0x4c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-impure.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .text._lseek_r + 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lseekr.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .text._read_r 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-readr.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .text._write_r + 0x00000000 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-writer.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .text.__errno 0x00000000 0xc C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .debug_frame 0x00000000 0x20 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-errno.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_init + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_init_recursive + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_close + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_close_recursive + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_acquire + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_acquire_recursive + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_try_acquire + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_try_acquire_recursive + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_release + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text.__retarget_lock_release_recursive + 0x00000000 0x2 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___arc4random_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___dd_hash_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___tz_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___env_recursive_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___malloc_recursive_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___at_quick_exit_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___atexit_recursive_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .bss.__lock___sfp_recursive_mutex + 0x00000000 0x1 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .debug_frame 0x00000000 0xb0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-lock.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .text._free_r 0x00000000 0x94 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-freer.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .text.sbrk_aligned + 0x00000000 0x44 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .text._malloc_r + 0x00000000 0x100 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .bss.__malloc_sbrk_start + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .bss.__malloc_free_list + 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .debug_frame 0x00000000 0x50 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .text.__malloc_lock + 0x00000000 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .text.__malloc_unlock + 0x00000000 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .debug_frame 0x00000000 0x40 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mlock.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .text.__sflush_r + 0x00000000 0x114 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .text._fflush_r + 0x00000000 0x56 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .text.fflush 0x00000000 0x30 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .debug_frame 0x00000000 0x68 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-fflush.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .text._sbrk_r 0x00000000 0x24 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .debug_frame 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .rodata 0x00000000 0x24 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .eh_frame 0x00000000 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .ARM.attributes + 0x00000000 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o + .text 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + .data 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + .bss 0x00000000 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00004000 xrw +FLASH 0x08000000 0x0000e000 xr +CONST 0x0800e000 0x00001000 xr +CONFIG 0x0800f000 0x00001000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD ./Core/Src/adc.o +LOAD ./Core/Src/can.o +LOAD ./Core/Src/dbw.o +LOAD ./Core/Src/inputs.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/mazda_can.o +LOAD ./Core/Src/outputs.o +LOAD ./Core/Src/safety.o +LOAD ./Core/Src/stm32f0xx_hal_msp.o +LOAD ./Core/Src/stm32f0xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f0xx.o +LOAD ./Core/Src/ts_comms.o +LOAD ./Core/Startup/startup_stm32f072c8tx.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o +LOAD ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o +START GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libstdc++_nano.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libsupc++_nano.a +END GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libstdc++_nano.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +START GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + 0x20004000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0xc0 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0xc0 ./Core/Startup/startup_stm32f072c8tx.o + 0x08000000 g_pfnVectors + 0x080000c0 . = ALIGN (0x4) + +.config 0x0800f000 0x358 + *(.config .config.*) + .config 0x0800f000 0x358 ./Core/Src/dbw.o + 0x0800f000 config_flash + +.text 0x080000c0 0x88d4 + 0x080000c0 . = ALIGN (0x4) + *(.text) + .text 0x080000c0 0x48 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x08000108 0x114 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + 0x08000108 __aeabi_uidiv + 0x08000108 __udivsi3 + 0x08000214 __aeabi_uidivmod + .text 0x0800021c 0x1d4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + 0x0800021c __divsi3 + 0x0800021c __aeabi_idiv + 0x080003e8 __aeabi_idivmod + .text 0x080003f0 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + 0x080003f0 __aeabi_idiv0 + 0x080003f0 __aeabi_ldiv0 + .text 0x080003f4 0x74 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) + 0x080003f4 __aeabi_cfrcmple + 0x080003fc __aeabi_cfcmpeq + 0x080003fc __aeabi_cfcmple + 0x0800040c __aeabi_fcmpeq + 0x08000418 __aeabi_fcmplt + 0x0800042c __aeabi_fcmple + 0x08000440 __aeabi_fcmpgt + 0x08000454 __aeabi_fcmpge + .text 0x08000468 0x30 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + 0x08000468 __fixunssfsi + 0x08000468 __aeabi_f2uiz + .text 0x08000498 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + 0x08000498 __aeabi_d2uiz + 0x08000498 __fixunsdfsi + .text 0x080004d4 0x41c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + 0x080004d4 __aeabi_fadd + .text 0x080008f0 0x22c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + 0x080008f0 __aeabi_fdiv + .text 0x08000b1c 0x50 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + 0x08000b1c __eqsf2 + 0x08000b1c __nesf2 + .text 0x08000b6c 0x90 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + 0x08000b6c __gesf2 + 0x08000b6c __gtsf2 + .text 0x08000bfc 0x90 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + 0x08000bfc __ltsf2 + 0x08000bfc __lesf2 + .text 0x08000c8c 0x2a4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + 0x08000c8c __aeabi_fmul + .text 0x08000f30 0x484 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + 0x08000f30 __aeabi_fsub + .text 0x080013b4 0x40 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + 0x080013b4 __aeabi_f2iz + .text 0x080013f4 0xa0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + 0x080013f4 __aeabi_i2f + .text 0x08001494 0x8c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + 0x08001494 __aeabi_ui2f + .text 0x08001520 0x590 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + 0x08001520 __aeabi_dmul + .text 0x08001ab0 0x870 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + 0x08001ab0 __aeabi_dsub + .text 0x08002320 0x78 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + 0x08002320 __aeabi_d2iz + .text 0x08002398 0x5c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + 0x08002398 __aeabi_i2d + .text 0x080023f4 0x7c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) + 0x080023f4 __aeabi_cdrcmple + 0x08002404 __aeabi_cdcmple + 0x08002404 __aeabi_cdcmpeq + 0x08002414 __aeabi_dcmpeq + 0x08002420 __aeabi_dcmplt + 0x08002434 __aeabi_dcmple + 0x08002448 __aeabi_dcmpgt + 0x0800245c __aeabi_dcmpge + .text 0x08002470 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o) + 0x08002470 __clzsi2 + .text 0x080024ac 0x8c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + 0x080024ac __nedf2 + 0x080024ac __eqdf2 + .text 0x08002538 0xe0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + 0x08002538 __gedf2 + 0x08002538 __gtdf2 + .text 0x08002618 0xdc C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + 0x08002618 __ledf2 + 0x08002618 __ltdf2 + *(.text*) + .text.Adc_Init + 0x080026f4 0xb0 ./Core/Src/adc.o + 0x080026f4 Adc_Init + .text.LPF 0x080027a4 0x9c ./Core/Src/adc.o + 0x080027a4 LPF + .text.Adc_Read + 0x08002840 0x6c ./Core/Src/adc.o + 0x08002840 Adc_Read + .text.CAN_Send_Msg + 0x080028ac 0x130 ./Core/Src/can.o + 0x080028ac CAN_Send_Msg + .text.CEC_CAN_IRQHandler + 0x080029dc 0x68 ./Core/Src/can.o + 0x080029dc CEC_CAN_IRQHandler + .text.CAN_Send_TX_Buffer + 0x08002a44 0x70 ./Core/Src/can.o + 0x08002a44 CAN_Send_TX_Buffer + .text.CAN_Add_TX_Buffer + 0x08002ab4 0x184 ./Core/Src/can.o + 0x08002ab4 CAN_Add_TX_Buffer + .text.CAN_Add_RX_Buffer + 0x08002c38 0x22c ./Core/Src/can.o + 0x08002c38 CAN_Add_RX_Buffer + .text.CAN_Read_RX_Buffer + 0x08002e64 0x160 ./Core/Src/can.o + 0x08002e64 CAN_Read_RX_Buffer + .text.__NVIC_EnableIRQ + 0x08002fc4 0x34 ./Core/Src/dbw.o + .text.__NVIC_DisableIRQ + 0x08002ff8 0x44 ./Core/Src/dbw.o + .text.Apply_Sensor_Calibration + 0x0800303c 0x214 ./Core/Src/dbw.o + 0x0800303c Apply_Sensor_Calibration + .text.DBW_Init + 0x08003250 0x94 ./Core/Src/dbw.o + 0x08003250 DBW_Init + .text.DBW_Process + 0x080032e4 0x644 ./Core/Src/dbw.o + 0x080032e4 DBW_Process + .text.DBW_Pwm_Init + 0x08003928 0x15c ./Core/Src/dbw.o + 0x08003928 DBW_Pwm_Init + .text.TIM2_IRQHandler + 0x08003a84 0x29c ./Core/Src/dbw.o + 0x08003a84 TIM2_IRQHandler + .text.DBW_Pwm_Set_Duty + 0x08003d20 0x1b0 ./Core/Src/dbw.o + 0x08003d20 DBW_Pwm_Set_Duty + .text.intrp_1d_ss_table + 0x08003ed0 0x144 ./Core/Src/dbw.o + 0x08003ed0 intrp_1d_ss_table + .text.DBW_Start + 0x08004014 0x2c ./Core/Src/dbw.o + 0x08004014 DBW_Start + .text.DBW_Stop + 0x08004040 0x2c ./Core/Src/dbw.o + 0x08004040 DBW_Stop + .text.DBW_TPS_AutoCal + 0x0800406c 0x218 ./Core/Src/dbw.o + 0x0800406c DBW_TPS_AutoCal + .text.DBW_Read_sensors + 0x08004284 0x234 ./Core/Src/dbw.o + 0x08004284 DBW_Read_sensors + .text.__NVIC_EnableIRQ + 0x080044b8 0x34 ./Core/Src/inputs.o + .text.TIM3_Init + 0x080044ec 0xd8 ./Core/Src/inputs.o + 0x080044ec TIM3_Init + .text.TIM14_Init + 0x080045c4 0xcc ./Core/Src/inputs.o + 0x080045c4 TIM14_Init + .text.TIM3_IRQHandler + 0x08004690 0x6c ./Core/Src/inputs.o + 0x08004690 TIM3_IRQHandler + .text.TIM14_IRQHandler + 0x080046fc 0xb8 ./Core/Src/inputs.o + 0x080046fc TIM14_IRQHandler + .text.__NVIC_EnableIRQ + 0x080047b4 0x34 ./Core/Src/main.o + .text.main 0x080047e8 0x224 ./Core/Src/main.o + 0x080047e8 main + .text.SystemClock_Config + 0x08004a0c 0xca ./Core/Src/main.o + 0x08004a0c SystemClock_Config + *fill* 0x08004ad6 0x2 + .text.MX_ADC_Init + 0x08004ad8 0x138 ./Core/Src/main.o + .text.MX_USART1_UART_Init + 0x08004c10 0x60 ./Core/Src/main.o + .text.MX_GPIO_Init + 0x08004c70 0xb0 ./Core/Src/main.o + .text.Error_Handler + 0x08004d20 0xa ./Core/Src/main.o + 0x08004d20 Error_Handler + *fill* 0x08004d2a 0x2 + .text.MAZDA_Send_Data + 0x08004d2c 0x364 ./Core/Src/mazda_can.o + 0x08004d2c MAZDA_Send_Data + .text.MAZDA_CAN_Read + 0x08005090 0xec ./Core/Src/mazda_can.o + 0x08005090 MAZDA_CAN_Read + .text.__NVIC_EnableIRQ + 0x0800517c 0x34 ./Core/Src/outputs.o + .text.TIM16_Init + 0x080051b0 0x74 ./Core/Src/outputs.o + 0x080051b0 TIM16_Init + .text.TIM17_Init + 0x08005224 0x74 ./Core/Src/outputs.o + 0x08005224 TIM17_Init + .text.VSS_Set 0x08005298 0x54 ./Core/Src/outputs.o + 0x08005298 VSS_Set + .text.TIM16_IRQHandler + 0x080052ec 0x28 ./Core/Src/outputs.o + 0x080052ec TIM16_IRQHandler + .text.TIM17_IRQHandler + 0x08005314 0x20 ./Core/Src/outputs.o + 0x08005314 TIM17_IRQHandler + .text.Check_Safety_Limits + 0x08005334 0x334 ./Core/Src/safety.o + 0x08005334 Check_Safety_Limits + .text.Check_Adc_Range + 0x08005668 0x510 ./Core/Src/safety.o + 0x08005668 Check_Adc_Range + .text.Safety_TPS_Safety_Timer + 0x08005b78 0x38 ./Core/Src/safety.o + 0x08005b78 Safety_TPS_Safety_Timer + .text.Safety_TPS_Safety_Timer_Start + 0x08005bb0 0x44 ./Core/Src/safety.o + 0x08005bb0 Safety_TPS_Safety_Timer_Start + .text.Check_TPS_Target + 0x08005bf4 0x160 ./Core/Src/safety.o + 0x08005bf4 Check_TPS_Target + .text.HAL_MspInit + 0x08005d54 0x48 ./Core/Src/stm32f0xx_hal_msp.o + 0x08005d54 HAL_MspInit + .text.HAL_ADC_MspInit + 0x08005d9c 0x8c ./Core/Src/stm32f0xx_hal_msp.o + 0x08005d9c HAL_ADC_MspInit + .text.HAL_UART_MspInit + 0x08005e28 0x9c ./Core/Src/stm32f0xx_hal_msp.o + 0x08005e28 HAL_UART_MspInit + .text.NMI_Handler + 0x08005ec4 0xa ./Core/Src/stm32f0xx_it.o + 0x08005ec4 NMI_Handler + .text.HardFault_Handler + 0x08005ece 0x8 ./Core/Src/stm32f0xx_it.o + 0x08005ece HardFault_Handler + .text.SVC_Handler + 0x08005ed6 0xa ./Core/Src/stm32f0xx_it.o + 0x08005ed6 SVC_Handler + .text.PendSV_Handler + 0x08005ee0 0xa ./Core/Src/stm32f0xx_it.o + 0x08005ee0 PendSV_Handler + *fill* 0x08005eea 0x2 + .text.SysTick_Handler + 0x08005eec 0x7c ./Core/Src/stm32f0xx_it.o + 0x08005eec SysTick_Handler + .text.SystemInit + 0x08005f68 0xa ./Core/Src/system_stm32f0xx.o + 0x08005f68 SystemInit + *fill* 0x08005f72 0x2 + .text.Comms_Init + 0x08005f74 0x40 ./Core/Src/ts_comms.o + 0x08005f74 Comms_Init + .text.USART1_IRQHandler + 0x08005fb4 0xa0 ./Core/Src/ts_comms.o + 0x08005fb4 USART1_IRQHandler + .text.Comms_Reset + 0x08006054 0x3c ./Core/Src/ts_comms.o + 0x08006054 Comms_Reset + .text.Rx_Char 0x08006090 0x398 ./Core/Src/ts_comms.o + 0x08006090 Rx_Char + .text.TX_Schedule + 0x08006428 0x70 ./Core/Src/ts_comms.o + 0x08006428 TX_Schedule + .text.Poll_Tx 0x08006498 0x74 ./Core/Src/ts_comms.o + 0x08006498 Poll_Tx + .text.TX_Done 0x0800650c 0x34 ./Core/Src/ts_comms.o + 0x0800650c TX_Done + .text.CRC32 0x08006540 0x50 ./Core/Src/ts_comms.o + 0x08006540 CRC32 + .text.Copy_Tx_Vars + 0x08006590 0xf8 ./Core/Src/ts_comms.o + 0x08006590 Copy_Tx_Vars + .text.crc32 0x08006688 0x20 ./Core/Src/ts_comms.o + 0x08006688 crc32 + .text.crc32inc + 0x080066a8 0x54 ./Core/Src/ts_comms.o + 0x080066a8 crc32inc + .text.Write_Config + 0x080066fc 0xac ./Core/Src/ts_comms.o + 0x080066fc Write_Config + .text.TS_Comms_RX_Timeout + 0x080067a8 0x3c ./Core/Src/ts_comms.o + 0x080067a8 TS_Comms_RX_Timeout + .text.Reset_Handler + 0x080067e4 0x50 ./Core/Startup/startup_stm32f072c8tx.o + 0x080067e4 Reset_Handler + .text.Default_Handler + 0x08006834 0x2 ./Core/Startup/startup_stm32f072c8tx.o + 0x08006834 TIM1_CC_IRQHandler + 0x08006834 TSC_IRQHandler + 0x08006834 ADC1_COMP_IRQHandler + 0x08006834 I2C1_IRQHandler + 0x08006834 RCC_CRS_IRQHandler + 0x08006834 SPI1_IRQHandler + 0x08006834 TIM6_DAC_IRQHandler + 0x08006834 USART3_4_IRQHandler + 0x08006834 EXTI2_3_IRQHandler + 0x08006834 I2C2_IRQHandler + 0x08006834 RTC_IRQHandler + 0x08006834 PVD_VDDIO2_IRQHandler + 0x08006834 DMA1_Channel4_5_6_7_IRQHandler + 0x08006834 EXTI4_15_IRQHandler + 0x08006834 DMA1_Channel1_IRQHandler + 0x08006834 Default_Handler + 0x08006834 TIM7_IRQHandler + 0x08006834 TIM15_IRQHandler + 0x08006834 EXTI0_1_IRQHandler + 0x08006834 USB_IRQHandler + 0x08006834 SPI2_IRQHandler + 0x08006834 WWDG_IRQHandler + 0x08006834 DMA1_Channel2_3_IRQHandler + 0x08006834 USART2_IRQHandler + 0x08006834 FLASH_IRQHandler + 0x08006834 TIM1_BRK_UP_TRG_COM_IRQHandler + *fill* 0x08006836 0x2 + .text.HAL_Init + 0x08006838 0x28 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x08006838 HAL_Init + .text.HAL_InitTick + 0x08006860 0x68 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x08006860 HAL_InitTick + .text.HAL_IncTick + 0x080068c8 0x24 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x080068c8 HAL_IncTick + .text.HAL_GetTick + 0x080068ec 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x080068ec HAL_GetTick + .text.HAL_ADC_Init + 0x08006900 0x280 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + 0x08006900 HAL_ADC_Init + .text.HAL_ADC_ConfigChannel + 0x08006b80 0x21c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + 0x08006b80 HAL_ADC_ConfigChannel + .text.__NVIC_SetPriority + 0x08006d9c 0xdc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.SysTick_Config + 0x08006e78 0x48 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .text.HAL_NVIC_SetPriority + 0x08006ec0 0x2a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x08006ec0 HAL_NVIC_SetPriority + .text.HAL_SYSTICK_Config + 0x08006eea 0x1a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + 0x08006eea HAL_SYSTICK_Config + .text.HAL_FLASH_Program + 0x08006f04 0x12c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + 0x08006f04 HAL_FLASH_Program + .text.HAL_FLASH_Unlock + 0x08007030 0x4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + 0x08007030 HAL_FLASH_Unlock + .text.HAL_FLASH_Lock + 0x0800707c 0x1c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + 0x0800707c HAL_FLASH_Lock + .text.FLASH_Program_HalfWord + 0x08007098 0x38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x080070d0 0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + 0x080070d0 FLASH_WaitForLastOperation + .text.FLASH_SetErrorCode + 0x08007150 0x60 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .text.HAL_FLASHEx_Erase + 0x080071b0 0xec ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + 0x080071b0 HAL_FLASHEx_Erase + .text.FLASH_MassErase + 0x0800729c 0x30 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .text.FLASH_PageErase + 0x080072cc 0x3c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + 0x080072cc FLASH_PageErase + .text.HAL_GPIO_Init + 0x08007308 0x2f0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x08007308 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x080075f8 0x3a ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x080075f8 HAL_GPIO_WritePin + .text.HAL_GPIO_TogglePin + 0x08007632 0x36 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + 0x08007632 HAL_GPIO_TogglePin + .text.HAL_RCC_OscConfig + 0x08007668 0x70c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x08007668 HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x08007d74 0x1b4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x08007d74 HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x08007f28 0x100 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x08007f28 HAL_RCC_GetSysClockFreq + .text.HAL_RCC_GetHCLKFreq + 0x08008028 0x14 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x08008028 HAL_RCC_GetHCLKFreq + .text.HAL_RCC_GetPCLK1Freq + 0x0800803c 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + 0x0800803c HAL_RCC_GetPCLK1Freq + .text.HAL_RCCEx_PeriphCLKConfig + 0x08008068 0x1fc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + 0x08008068 HAL_RCCEx_PeriphCLKConfig + .text.HAL_UART_Init + 0x08008264 0xa8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + 0x08008264 HAL_UART_Init + .text.UART_SetConfig + 0x0800830c 0x310 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + 0x0800830c UART_SetConfig + .text.UART_AdvFeatureConfig + 0x0800861c 0x168 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + 0x0800861c UART_AdvFeatureConfig + .text.UART_CheckIdleState + 0x08008784 0x90 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + 0x08008784 UART_CheckIdleState + .text.UART_WaitOnFlagUntilTimeout + 0x08008814 0xfc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + 0x08008814 UART_WaitOnFlagUntilTimeout + .text.memset 0x08008910 0x10 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + 0x08008910 memset + .text.__libc_init_array + 0x08008920 0x48 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + 0x08008920 __libc_init_array + .text.memcpy 0x08008968 0x12 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + 0x08008968 memcpy + *(.glue_7) + .glue_7 0x0800897a 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0800897a 0x0 linker stubs + *(.eh_frame) + *fill* 0x0800897a 0x2 + .eh_frame 0x0800897c 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + *(.init) + .init 0x0800897c 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + 0x0800897c _init + .init 0x08008980 0x8 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + *(.fini) + .fini 0x08008988 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + 0x08008988 _fini + .fini 0x0800898c 0x8 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o + 0x08008994 . = ALIGN (0x4) + 0x08008994 _etext = . + +.vfp11_veneer 0x08008994 0x0 + .vfp11_veneer 0x08008994 0x0 linker stubs + +.v4_bx 0x08008994 0x0 + .v4_bx 0x08008994 0x0 linker stubs + +.iplt 0x08008994 0x0 + .iplt 0x08008994 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + +.rodata 0x08008994 0x18c + 0x08008994 . = ALIGN (0x4) + *(.rodata) + .rodata 0x08008994 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .rodata 0x080089b4 0x7c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + *(.rodata*) + .rodata.msg1 0x08008a30 0x2a ./Core/Src/safety.o + 0x08008a30 msg1 + *fill* 0x08008a5a 0x2 + .rodata.msg2 0x08008a5c 0x2a ./Core/Src/safety.o + 0x08008a5c msg2 + *fill* 0x08008a86 0x2 + .rodata.msg3 0x08008a88 0x2a ./Core/Src/safety.o + 0x08008a88 msg3 + *fill* 0x08008ab2 0x2 + .rodata.msg4 0x08008ab4 0x2a ./Core/Src/safety.o + 0x08008ab4 msg4 + *fill* 0x08008ade 0x2 + .rodata.AHBPrescTable + 0x08008ae0 0x10 ./Core/Src/system_stm32f0xx.o + 0x08008ae0 AHBPrescTable + .rodata.APBPrescTable + 0x08008af0 0x8 ./Core/Src/system_stm32f0xx.o + 0x08008af0 APBPrescTable + .rodata.Signature + 0x08008af8 0x14 ./Core/Src/ts_comms.o + 0x08008af8 Signature + .rodata.Revision + 0x08008b0c 0x14 ./Core/Src/ts_comms.o + 0x08008b0c Revision + 0x08008b20 . = ALIGN (0x4) + +.rel.dyn 0x08008b20 0x0 + .rel.iplt 0x08008b20 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + +.ARM.extab 0x08008b20 0x0 + 0x08008b20 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x08008b20 . = ALIGN (0x4) + +.ARM 0x08008b20 0x0 + 0x08008b20 . = ALIGN (0x4) + 0x08008b20 __exidx_start = . + *(.ARM.exidx*) + 0x08008b20 __exidx_end = . + 0x08008b20 . = ALIGN (0x4) + +.preinit_array 0x08008b20 0x0 + 0x08008b20 . = ALIGN (0x4) + 0x08008b20 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08008b20 PROVIDE (__preinit_array_end = .) + 0x08008b20 . = ALIGN (0x4) + +.init_array 0x08008b20 0x4 + 0x08008b20 . = ALIGN (0x4) + 0x08008b20 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08008b20 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + 0x08008b24 PROVIDE (__init_array_end = .) + 0x08008b24 . = ALIGN (0x4) + +.fini_array 0x08008b24 0x4 + 0x08008b24 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08008b24 0x4 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08008b28 . = ALIGN (0x4) + 0x08008b28 _sidata = LOADADDR (.data) + +.data 0x20000000 0x414 load address 0x08008b28 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.ac_timer + 0x20000000 0x4 ./Core/Src/dbw.o + 0x20000000 ac_timer + .data.SystemCoreClock + 0x20000004 0x4 ./Core/Src/system_stm32f0xx.o + 0x20000004 SystemCoreClock + .data.Store_config + 0x20000008 0x4 ./Core/Src/ts_comms.o + 0x20000008 Store_config + .data.crc32_tab + 0x2000000c 0x400 ./Core/Src/ts_comms.o + .data.uwTickPrio + 0x2000040c 0x4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x2000040c uwTickPrio + .data.uwTickFreq + 0x20000410 0x1 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x20000410 uwTickFreq + 0x20000414 . = ALIGN (0x4) + *fill* 0x20000411 0x3 + 0x20000414 _edata = . + +.igot.plt 0x20000414 0x0 load address 0x08008f3c + .igot.plt 0x20000414 0x0 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + 0x20000414 . = ALIGN (0x4) + +.bss 0x20000418 0x9b8 load address 0x08008f3c + 0x20000418 _sbss = . + 0x20000418 __bss_start__ = _sbss + *(.bss) + .bss 0x20000418 0x1c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + *(.bss*) + .bss.CAN_TX_Rdy + 0x20000434 0x1 ./Core/Src/can.o + 0x20000434 CAN_TX_Rdy + .bss.CAN_RX_Rdy + 0x20000435 0x1 ./Core/Src/can.o + 0x20000435 CAN_RX_Rdy + *fill* 0x20000436 0x2 + .bss.CAN_TX_Buffer + 0x20000438 0x104 ./Core/Src/can.o + 0x20000438 CAN_TX_Buffer + .bss.CAN_RX_Buffer + 0x2000053c 0x104 ./Core/Src/can.o + 0x2000053c CAN_RX_Buffer + .bss.config_ram + 0x20000640 0x358 ./Core/Src/dbw.o + 0x20000640 config_ram + .bss.var 0x20000998 0x34 ./Core/Src/dbw.o + 0x20000998 var + .bss.config 0x200009cc 0x4 ./Core/Src/dbw.o + 0x200009cc config + .bss.ac_mode 0x200009d0 0x4 ./Core/Src/dbw.o + 0x200009d0 ac_mode + .bss.ttl1_pwm 0x200009d4 0x28 ./Core/Src/dbw.o + 0x200009d4 ttl1_pwm + .bss.pps1_gain + 0x200009fc 0x4 ./Core/Src/dbw.o + 0x200009fc pps1_gain + .bss.pps1_offset + 0x20000a00 0x4 ./Core/Src/dbw.o + 0x20000a00 pps1_offset + .bss.pps2_gain + 0x20000a04 0x4 ./Core/Src/dbw.o + 0x20000a04 pps2_gain + .bss.pps2_offset + 0x20000a08 0x4 ./Core/Src/dbw.o + 0x20000a08 pps2_offset + .bss.tps1_gain + 0x20000a0c 0x4 ./Core/Src/dbw.o + 0x20000a0c tps1_gain + .bss.tps1_offset + 0x20000a10 0x4 ./Core/Src/dbw.o + 0x20000a10 tps1_offset + .bss.tps2_gain + 0x20000a14 0x4 ./Core/Src/dbw.o + 0x20000a14 tps2_gain + .bss.tps2_offset + 0x20000a18 0x4 ./Core/Src/dbw.o + 0x20000a18 tps2_offset + .bss.dbw_fast_process_timer + 0x20000a1c 0x2 ./Core/Src/dbw.o + 0x20000a1c dbw_fast_process_timer + .bss.dbw_slow_process_timer + 0x20000a1e 0x2 ./Core/Src/dbw.o + 0x20000a1e dbw_slow_process_timer + .bss.vbat_corr + 0x20000a20 0x4 ./Core/Src/dbw.o + 0x20000a20 vbat_corr + .bss.tps_slow_t + 0x20000a24 0x4 ./Core/Src/dbw.o + 0x20000a24 tps_slow_t + .bss.p_comp 0x20000a28 0x4 ./Core/Src/dbw.o + 0x20000a28 p_comp + .bss.i_comp 0x20000a2c 0x4 ./Core/Src/dbw.o + 0x20000a2c i_comp + .bss.d_comp 0x20000a30 0x4 ./Core/Src/dbw.o + 0x20000a30 d_comp + .bss.tps_error_t + 0x20000a34 0x4 ./Core/Src/dbw.o + 0x20000a34 tps_error_t + .bss.can_target + 0x20000a38 0x4 ./Core/Src/dbw.o + 0x20000a38 can_target + .bss.spring_preload + 0x20000a3c 0x4 ./Core/Src/dbw.o + 0x20000a3c spring_preload + .bss.idle_adder + 0x20000a40 0x4 ./Core/Src/dbw.o + 0x20000a40 idle_adder + .bss.counter0 0x20000a44 0x4 ./Core/Src/inputs.o + 0x20000a44 counter0 + .bss.counter1 0x20000a48 0x4 ./Core/Src/inputs.o + 0x20000a48 counter1 + .bss.Counter 0x20000a4c 0x4 ./Core/Src/inputs.o + 0x20000a4c Counter + .bss.gap 0x20000a50 0x1 ./Core/Src/inputs.o + 0x20000a50 gap + *fill* 0x20000a51 0x3 + .bss.hadc 0x20000a54 0x40 ./Core/Src/main.o + 0x20000a54 hadc + .bss.huart1 0x20000a94 0x84 ./Core/Src/main.o + 0x20000a94 huart1 + .bss.can_tim 0x20000b18 0x4 ./Core/Src/mazda_can.o + 0x20000b18 can_tim + .bss.tmpCanMsg + 0x20000b1c 0x10 ./Core/Src/mazda_can.o + 0x20000b1c tmpCanMsg + .bss.dbw_target_tmr1 + 0x20000b2c 0x4 ./Core/Src/safety.o + 0x20000b2c dbw_target_tmr1 + .bss.dbw_target_tmr2 + 0x20000b30 0x4 ./Core/Src/safety.o + 0x20000b30 dbw_target_tmr2 + .bss.RX 0x20000b34 0x11c ./Core/Src/ts_comms.o + 0x20000b34 RX + .bss.TX 0x20000c50 0x11c ./Core/Src/ts_comms.o + 0x20000c50 TX + .bss.SCI_flags + 0x20000d6c 0x1 ./Core/Src/ts_comms.o + 0x20000d6c SCI_flags + *fill* 0x20000d6d 0x3 + .bss.crc32_bufer + 0x20000d70 0x8 ./Core/Src/ts_comms.o + 0x20000d70 crc32_bufer + .bss.tx_bufer 0x20000d78 0x34 ./Core/Src/ts_comms.o + 0x20000d78 tx_bufer + .bss.uwTick 0x20000dac 0x4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + 0x20000dac uwTick + .bss.pFlash 0x20000db0 0x20 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + 0x20000db0 pFlash + *(COMMON) + 0x20000dd0 . = ALIGN (0x4) + 0x20000dd0 _ebss = . + 0x20000dd0 __bss_end__ = _ebss + +._user_heap_stack + 0x20000dd0 0x600 load address 0x08008f3c + 0x20000dd0 . = ALIGN (0x8) + 0x20000dd0 PROVIDE (end = .) + [!provide] PROVIDE (_end = .) + 0x20000fd0 . = (. + _Min_Heap_Size) + *fill* 0x20000dd0 0x200 + 0x200013d0 . = (. + _Min_Stack_Size) + *fill* 0x20000fd0 0x400 + 0x200013d0 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o + .ARM.attributes + 0x0000001e 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o + .ARM.attributes + 0x0000004a 0x2c ./Core/Src/adc.o + .ARM.attributes + 0x00000076 0x2c ./Core/Src/can.o + .ARM.attributes + 0x000000a2 0x2c ./Core/Src/dbw.o + .ARM.attributes + 0x000000ce 0x2c ./Core/Src/inputs.o + .ARM.attributes + 0x000000fa 0x2c ./Core/Src/main.o + .ARM.attributes + 0x00000126 0x2c ./Core/Src/mazda_can.o + .ARM.attributes + 0x00000152 0x2c ./Core/Src/outputs.o + .ARM.attributes + 0x0000017e 0x2c ./Core/Src/safety.o + .ARM.attributes + 0x000001aa 0x2c ./Core/Src/stm32f0xx_hal_msp.o + .ARM.attributes + 0x000001d6 0x2c ./Core/Src/stm32f0xx_it.o + .ARM.attributes + 0x00000202 0x2c ./Core/Src/system_stm32f0xx.o + .ARM.attributes + 0x0000022e 0x2c ./Core/Src/ts_comms.o + .ARM.attributes + 0x0000025a 0x21 ./Core/Startup/startup_stm32f072c8tx.o + .ARM.attributes + 0x0000027b 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .ARM.attributes + 0x000002a7 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .ARM.attributes + 0x000002d3 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .ARM.attributes + 0x000002ff 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .ARM.attributes + 0x0000032b 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .ARM.attributes + 0x00000357 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .ARM.attributes + 0x00000383 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .ARM.attributes + 0x000003af 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .ARM.attributes + 0x000003db 0x2c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .ARM.attributes + 0x00000407 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x00000433 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x0000045f 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .ARM.attributes + 0x0000048b 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .ARM.attributes + 0x000004a9 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .ARM.attributes + 0x000004c7 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000004e5 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpsf2.o) + .ARM.attributes + 0x00000503 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + .ARM.attributes + 0x0000052f 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + .ARM.attributes + 0x0000055b 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + .ARM.attributes + 0x00000587 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + .ARM.attributes + 0x000005b3 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + .ARM.attributes + 0x000005df 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + .ARM.attributes + 0x0000060b 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + .ARM.attributes + 0x00000637 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + .ARM.attributes + 0x00000663 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + .ARM.attributes + 0x0000068f 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + .ARM.attributes + 0x000006bb 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + .ARM.attributes + 0x000006e7 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + .ARM.attributes + 0x00000713 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + .ARM.attributes + 0x0000073f 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + .ARM.attributes + 0x0000076b 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + .ARM.attributes + 0x00000797 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + .ARM.attributes + 0x000007c3 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_arm_cmpdf2.o) + .ARM.attributes + 0x000007e1 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o) + .ARM.attributes + 0x000007ff 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + .ARM.attributes + 0x0000082b 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + .ARM.attributes + 0x00000857 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + .ARM.attributes + 0x00000883 0x1e C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(DBW_V2.elf elf32-littlearm) +LOAD linker stubs +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a +LOAD C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a + +.debug_info 0x00000000 0xc9d8 + .debug_info 0x00000000 0x2b0 ./Core/Src/adc.o + .debug_info 0x000002b0 0x993 ./Core/Src/can.o + .debug_info 0x00000c43 0x13d3 ./Core/Src/dbw.o + .debug_info 0x00002016 0x787 ./Core/Src/inputs.o + .debug_info 0x0000279d 0x1ac8 ./Core/Src/main.o + .debug_info 0x00004265 0x353 ./Core/Src/mazda_can.o + .debug_info 0x000045b8 0x624 ./Core/Src/outputs.o + .debug_info 0x00004bdc 0x8a3 ./Core/Src/safety.o + .debug_info 0x0000547f 0xf9f ./Core/Src/stm32f0xx_hal_msp.o + .debug_info 0x0000641e 0x61f ./Core/Src/stm32f0xx_it.o + .debug_info 0x00006a3d 0x242 ./Core/Src/system_stm32f0xx.o + .debug_info 0x00006c7f 0xca9 ./Core/Src/ts_comms.o + .debug_info 0x00007928 0x30 ./Core/Startup/startup_stm32f072c8tx.o + .debug_info 0x00007958 0x6c9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_info 0x00008021 0xc4c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_info 0x00008c6d 0x6c5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_info 0x00009332 0x4f5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_info 0x00009827 0x735 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_info 0x00009f5c 0x5a6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_info 0x0000a502 0x83b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_info 0x0000ad3d 0x61c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_info 0x0000b359 0x167f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_abbrev 0x00000000 0x2cfc + .debug_abbrev 0x00000000 0x155 ./Core/Src/adc.o + .debug_abbrev 0x00000155 0x27a ./Core/Src/can.o + .debug_abbrev 0x000003cf 0x390 ./Core/Src/dbw.o + .debug_abbrev 0x0000075f 0x1ba ./Core/Src/inputs.o + .debug_abbrev 0x00000919 0x359 ./Core/Src/main.o + .debug_abbrev 0x00000c72 0xee ./Core/Src/mazda_can.o + .debug_abbrev 0x00000d60 0x197 ./Core/Src/outputs.o + .debug_abbrev 0x00000ef7 0x26e ./Core/Src/safety.o + .debug_abbrev 0x00001165 0x1e9 ./Core/Src/stm32f0xx_hal_msp.o + .debug_abbrev 0x0000134e 0x133 ./Core/Src/stm32f0xx_it.o + .debug_abbrev 0x00001481 0x11c ./Core/Src/system_stm32f0xx.o + .debug_abbrev 0x0000159d 0x34f ./Core/Src/ts_comms.o + .debug_abbrev 0x000018ec 0x24 ./Core/Startup/startup_stm32f072c8tx.o + .debug_abbrev 0x00001910 0x213 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_abbrev 0x00001b23 0x259 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_abbrev 0x00001d7c 0x28c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_abbrev 0x00002008 0x258 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_abbrev 0x00002260 0x247 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_abbrev 0x000024a7 0x1cb ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_abbrev 0x00002672 0x28c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_abbrev 0x000028fe 0x1a6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_abbrev 0x00002aa4 0x258 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_aranges 0x00000000 0xb28 + .debug_aranges + 0x00000000 0x30 ./Core/Src/adc.o + .debug_aranges + 0x00000030 0x80 ./Core/Src/can.o + .debug_aranges + 0x000000b0 0x90 ./Core/Src/dbw.o + .debug_aranges + 0x00000140 0x40 ./Core/Src/inputs.o + .debug_aranges + 0x00000180 0x50 ./Core/Src/main.o + .debug_aranges + 0x000001d0 0x28 ./Core/Src/mazda_can.o + .debug_aranges + 0x000001f8 0x48 ./Core/Src/outputs.o + .debug_aranges + 0x00000240 0x60 ./Core/Src/safety.o + .debug_aranges + 0x000002a0 0x50 ./Core/Src/stm32f0xx_hal_msp.o + .debug_aranges + 0x000002f0 0x40 ./Core/Src/stm32f0xx_it.o + .debug_aranges + 0x00000330 0x28 ./Core/Src/system_stm32f0xx.o + .debug_aranges + 0x00000358 0x88 ./Core/Src/ts_comms.o + .debug_aranges + 0x000003e0 0x28 ./Core/Startup/startup_stm32f072c8tx.o + .debug_aranges + 0x00000408 0xd0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_aranges + 0x000004d8 0xf8 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_aranges + 0x000005d0 0xc0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_aranges + 0x00000690 0x88 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_aranges + 0x00000718 0x98 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_aranges + 0x000007b0 0x58 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_aranges + 0x00000808 0x80 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_aranges + 0x00000888 0x78 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_aranges + 0x00000900 0x228 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_rnglists + 0x00000000 0x882 + .debug_rnglists + 0x00000000 0x21 ./Core/Src/adc.o + .debug_rnglists + 0x00000021 0x63 ./Core/Src/can.o + .debug_rnglists + 0x00000084 0x72 ./Core/Src/dbw.o + .debug_rnglists + 0x000000f6 0x2e ./Core/Src/inputs.o + .debug_rnglists + 0x00000124 0x3b ./Core/Src/main.o + .debug_rnglists + 0x0000015f 0x1b ./Core/Src/mazda_can.o + .debug_rnglists + 0x0000017a 0x31 ./Core/Src/outputs.o + .debug_rnglists + 0x000001ab 0x46 ./Core/Src/safety.o + .debug_rnglists + 0x000001f1 0x3a ./Core/Src/stm32f0xx_hal_msp.o + .debug_rnglists + 0x0000022b 0x2b ./Core/Src/stm32f0xx_it.o + .debug_rnglists + 0x00000256 0x1a ./Core/Src/system_stm32f0xx.o + .debug_rnglists + 0x00000270 0x66 ./Core/Src/ts_comms.o + .debug_rnglists + 0x000002d6 0x19 ./Core/Startup/startup_stm32f072c8tx.o + .debug_rnglists + 0x000002ef 0x97 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_rnglists + 0x00000386 0xc6 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_rnglists + 0x0000044c 0x8c ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_rnglists + 0x000004d8 0x65 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_rnglists + 0x0000053d 0x76 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_rnglists + 0x000005b3 0x3f ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_rnglists + 0x000005f2 0x61 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_rnglists + 0x00000653 0x5b ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_rnglists + 0x000006ae 0x1d4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_macro 0x00000000 0x1afcf + .debug_macro 0x00000000 0x227 ./Core/Src/adc.o + .debug_macro 0x00000227 0xaae ./Core/Src/adc.o + .debug_macro 0x00000cd5 0x139 ./Core/Src/adc.o + .debug_macro 0x00000e0e 0x2e ./Core/Src/adc.o + .debug_macro 0x00000e3c 0x22 ./Core/Src/adc.o + .debug_macro 0x00000e5e 0x22 ./Core/Src/adc.o + .debug_macro 0x00000e80 0x8e ./Core/Src/adc.o + .debug_macro 0x00000f0e 0x51 ./Core/Src/adc.o + .debug_macro 0x00000f5f 0x103 ./Core/Src/adc.o + .debug_macro 0x00001062 0x6a ./Core/Src/adc.o + .debug_macro 0x000010cc 0x1df ./Core/Src/adc.o + .debug_macro 0x000012ab 0x1c ./Core/Src/adc.o + .debug_macro 0x000012c7 0x22 ./Core/Src/adc.o + .debug_macro 0x000012e9 0xaf ./Core/Src/adc.o + .debug_macro 0x00001398 0x391 ./Core/Src/adc.o + .debug_macro 0x00001729 0xfe50 ./Core/Src/adc.o + .debug_macro 0x00011579 0x3c ./Core/Src/adc.o + .debug_macro 0x000115b5 0x3461 ./Core/Src/adc.o + .debug_macro 0x00014a16 0x190 ./Core/Src/adc.o + .debug_macro 0x00014ba6 0x55 ./Core/Src/adc.o + .debug_macro 0x00014bfb 0x946 ./Core/Src/adc.o + .debug_macro 0x00015541 0x5f3 ./Core/Src/adc.o + .debug_macro 0x00015b34 0x12f ./Core/Src/adc.o + .debug_macro 0x00015c63 0x1a7 ./Core/Src/adc.o + .debug_macro 0x00015e0a 0x1a7 ./Core/Src/adc.o + .debug_macro 0x00015fb1 0x22c ./Core/Src/adc.o + .debug_macro 0x000161dd 0x34 ./Core/Src/adc.o + .debug_macro 0x00016211 0x43 ./Core/Src/adc.o + .debug_macro 0x00016254 0x28 ./Core/Src/adc.o + .debug_macro 0x0001627c 0x33d ./Core/Src/adc.o + .debug_macro 0x000165b9 0xd4 ./Core/Src/adc.o + .debug_macro 0x0001668d 0x408 ./Core/Src/adc.o + .debug_macro 0x00016a95 0xb0 ./Core/Src/adc.o + .debug_macro 0x00016b45 0x217 ./Core/Src/adc.o + .debug_macro 0x00016d5c 0x22c ./Core/Src/adc.o + .debug_macro 0x00016f88 0x60 ./Core/Src/adc.o + .debug_macro 0x00016fe8 0xa5 ./Core/Src/adc.o + .debug_macro 0x0001708d 0x4c ./Core/Src/adc.o + .debug_macro 0x000170d9 0x16d ./Core/Src/adc.o + .debug_macro 0x00017246 0x5a5 ./Core/Src/adc.o + .debug_macro 0x000177eb 0x44 ./Core/Src/adc.o + .debug_macro 0x0001782f 0x130 ./Core/Src/adc.o + .debug_macro 0x0001795f 0xca ./Core/Src/adc.o + .debug_macro 0x00017a29 0x108 ./Core/Src/adc.o + .debug_macro 0x00017b31 0x4c ./Core/Src/adc.o + .debug_macro 0x00017b7d 0x58 ./Core/Src/adc.o + .debug_macro 0x00017bd5 0xd0 ./Core/Src/adc.o + .debug_macro 0x00017ca5 0x22b ./Core/Src/can.o + .debug_macro 0x00017ed0 0x227 ./Core/Src/dbw.o + .debug_macro 0x000180f7 0x227 ./Core/Src/inputs.o + .debug_macro 0x0001831e 0x32f ./Core/Src/main.o + .debug_macro 0x0001864d 0x61 ./Core/Src/main.o + .debug_macro 0x000186ae 0x24 ./Core/Src/main.o + .debug_macro 0x000186d2 0x43 ./Core/Src/main.o + .debug_macro 0x00018715 0x34 ./Core/Src/main.o + .debug_macro 0x00018749 0x16 ./Core/Src/main.o + .debug_macro 0x0001875f 0x3c ./Core/Src/main.o + .debug_macro 0x0001879b 0x364 ./Core/Src/main.o + .debug_macro 0x00018aff 0x10 ./Core/Src/main.o + .debug_macro 0x00018b0f 0x16 ./Core/Src/main.o + .debug_macro 0x00018b25 0x4a ./Core/Src/main.o + .debug_macro 0x00018b6f 0x34 ./Core/Src/main.o + .debug_macro 0x00018ba3 0x10 ./Core/Src/main.o + .debug_macro 0x00018bb3 0x58 ./Core/Src/main.o + .debug_macro 0x00018c0b 0x8e ./Core/Src/main.o + .debug_macro 0x00018c99 0x1c ./Core/Src/main.o + .debug_macro 0x00018cb5 0x17e ./Core/Src/main.o + .debug_macro 0x00018e33 0x16 ./Core/Src/main.o + .debug_macro 0x00018e49 0x16 ./Core/Src/main.o + .debug_macro 0x00018e5f 0x146 ./Core/Src/main.o + .debug_macro 0x00018fa5 0x16 ./Core/Src/main.o + .debug_macro 0x00018fbb 0x20 ./Core/Src/main.o + .debug_macro 0x00018fdb 0x227 ./Core/Src/mazda_can.o + .debug_macro 0x00019202 0x227 ./Core/Src/outputs.o + .debug_macro 0x00019429 0x233 ./Core/Src/safety.o + .debug_macro 0x0001965c 0x227 ./Core/Src/stm32f0xx_hal_msp.o + .debug_macro 0x00019883 0x241 ./Core/Src/stm32f0xx_it.o + .debug_macro 0x00019ac4 0x1cc ./Core/Src/system_stm32f0xx.o + .debug_macro 0x00019c90 0x240 ./Core/Src/ts_comms.o + .debug_macro 0x00019ed0 0x1f0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_macro 0x0001a0c0 0x1f0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_macro 0x0001a2b0 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_macro 0x0001a47c 0x1cc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_macro 0x0001a648 0x1de ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_macro 0x0001a826 0x204 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_macro 0x0001aa2a 0x1de ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_macro 0x0001ac08 0x1de ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_macro 0x0001ade6 0x1e9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_line 0x00000000 0x107b0 + .debug_line 0x00000000 0x8d8 ./Core/Src/adc.o + .debug_line 0x000008d8 0xdfd ./Core/Src/can.o + .debug_line 0x000016d5 0x139a ./Core/Src/dbw.o + .debug_line 0x00002a6f 0x978 ./Core/Src/inputs.o + .debug_line 0x000033e7 0xbf1 ./Core/Src/main.o + .debug_line 0x00003fd8 0x95f ./Core/Src/mazda_can.o + .debug_line 0x00004937 0x8f9 ./Core/Src/outputs.o + .debug_line 0x00005230 0xd04 ./Core/Src/safety.o + .debug_line 0x00005f34 0x8cd ./Core/Src/stm32f0xx_hal_msp.o + .debug_line 0x00006801 0x874 ./Core/Src/stm32f0xx_it.o + .debug_line 0x00007075 0x807 ./Core/Src/system_stm32f0xx.o + .debug_line 0x0000787c 0xcfa ./Core/Src/ts_comms.o + .debug_line 0x00008576 0x7b ./Core/Startup/startup_stm32f072c8tx.o + .debug_line 0x000085f1 0x9ff ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_line 0x00008ff0 0x11ea ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_line 0x0000a1da 0xaa4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_line 0x0000ac7e 0xab5 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_line 0x0000b733 0xbfc ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_line 0x0000c32f 0xb86 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_line 0x0000ceb5 0xf45 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_line 0x0000ddfa 0xcbd ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_line 0x0000eab7 0x1cf9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_str 0x00000000 0x9656c + .debug_str 0x00000000 0x9656c ./Core/Src/adc.o + 0x8f910 (size before relaxing) + .debug_str 0x0009656c 0x8fd94 ./Core/Src/can.o + .debug_str 0x0009656c 0x90339 ./Core/Src/dbw.o + .debug_str 0x0009656c 0x8fcc2 ./Core/Src/inputs.o + .debug_str 0x0009656c 0x9437b ./Core/Src/main.o + .debug_str 0x0009656c 0x8f9e0 ./Core/Src/mazda_can.o + .debug_str 0x0009656c 0x8fc0a ./Core/Src/outputs.o + .debug_str 0x0009656c 0x8fec7 ./Core/Src/safety.o + .debug_str 0x0009656c 0x90179 ./Core/Src/stm32f0xx_hal_msp.o + .debug_str 0x0009656c 0x8fd41 ./Core/Src/stm32f0xx_it.o + .debug_str 0x0009656c 0x8ecda ./Core/Src/system_stm32f0xx.o + .debug_str 0x0009656c 0x8ffed ./Core/Src/ts_comms.o + .debug_str 0x0009656c 0x77 ./Core/Startup/startup_stm32f072c8tx.o + .debug_str 0x0009656c 0x8f2c9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_str 0x0009656c 0x8f3d7 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_str 0x0009656c 0x8f0be ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_str 0x0009656c 0x8ef85 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_str 0x0009656c 0x8f104 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_str 0x0009656c 0x8ef38 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_str 0x0009656c 0x8f121 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_str 0x0009656c 0x8f0d9 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_str 0x0009656c 0x8f9e4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/adc.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/can.o + .comment 0x00000043 0x44 ./Core/Src/dbw.o + .comment 0x00000043 0x44 ./Core/Src/inputs.o + .comment 0x00000043 0x44 ./Core/Src/main.o + .comment 0x00000043 0x44 ./Core/Src/mazda_can.o + .comment 0x00000043 0x44 ./Core/Src/outputs.o + .comment 0x00000043 0x44 ./Core/Src/safety.o + .comment 0x00000043 0x44 ./Core/Src/stm32f0xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32f0xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32f0xx.o + .comment 0x00000043 0x44 ./Core/Src/ts_comms.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .comment 0x00000043 0x44 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + +.debug_frame 0x00000000 0x28b8 + .debug_frame 0x00000000 0x6c ./Core/Src/adc.o + .debug_frame 0x0000006c 0x198 ./Core/Src/can.o + .debug_frame 0x00000204 0x1d8 ./Core/Src/dbw.o + .debug_frame 0x000003dc 0xa0 ./Core/Src/inputs.o + .debug_frame 0x0000047c 0xe4 ./Core/Src/main.o + .debug_frame 0x00000560 0x48 ./Core/Src/mazda_can.o + .debug_frame 0x000005a8 0xc0 ./Core/Src/outputs.o + .debug_frame 0x00000668 0x114 ./Core/Src/safety.o + .debug_frame 0x0000077c 0xf0 ./Core/Src/stm32f0xx_hal_msp.o + .debug_frame 0x0000086c 0x9c ./Core/Src/stm32f0xx_it.o + .debug_frame 0x00000908 0x4c ./Core/Src/system_stm32f0xx.o + .debug_frame 0x00000954 0x1c0 ./Core/Src/ts_comms.o + .debug_frame 0x00000b14 0x2a4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o + .debug_frame 0x00000db8 0x3a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o + .debug_frame 0x00001158 0x2a0 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o + .debug_frame 0x000013f8 0x1c4 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o + .debug_frame 0x000015bc 0x220 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o + .debug_frame 0x000017dc 0x110 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o + .debug_frame 0x000018ec 0x198 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o + .debug_frame 0x00001a84 0x180 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o + .debug_frame 0x00001c04 0x850 ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o + .debug_frame 0x00002454 0x20 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o) + .debug_frame 0x00002474 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-init.o) + .debug_frame 0x000024a0 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x000024c8 0x20 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o) + .debug_frame 0x000024e8 0x20 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o) + .debug_frame 0x00002508 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunssfsi.o) + .debug_frame 0x00002530 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_fixunsdfsi.o) + .debug_frame 0x0000255c 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(addsf3.o) + .debug_frame 0x00002594 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(divsf3.o) + .debug_frame 0x000025cc 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqsf2.o) + .debug_frame 0x000025f8 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gesf2.o) + .debug_frame 0x00002624 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(lesf2.o) + .debug_frame 0x00002650 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(mulsf3.o) + .debug_frame 0x00002688 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subsf3.o) + .debug_frame 0x000026c0 0x20 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixsfsi.o) + .debug_frame 0x000026e0 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsisf.o) + .debug_frame 0x0000270c 0x28 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatunsisf.o) + .debug_frame 0x00002734 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(muldf3.o) + .debug_frame 0x00002770 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(subdf3.o) + .debug_frame 0x000027ac 0x30 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(fixdfsi.o) + .debug_frame 0x000027dc 0x2c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(floatsidf.o) + .debug_frame 0x00002808 0x38 C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(eqdf2.o) + .debug_frame 0x00002840 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(gedf2.o) + .debug_frame 0x0000287c 0x3c C:/ST/STM32CubeIDE_2.0.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(ledf2.o) + +.debug_line_str + 0x00000000 0x5b + .debug_line_str + 0x00000000 0x5b ./Core/Startup/startup_stm32f072c8tx.o diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.cyclo new file mode 100644 index 0000000..fcffaac --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.cyclo @@ -0,0 +1,23 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:141:19:HAL_Init 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:165:19:HAL_DeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:188:13:HAL_MspInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:199:13:HAL_MspDeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:222:26:HAL_InitTick 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:281:13:HAL_IncTick 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:292:17:HAL_GetTick 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:301:10:HAL_GetTickPrio 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:310:19:HAL_SetTickFreq 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:342:21:HAL_GetTickFreq 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:358:13:HAL_Delay 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:384:13:HAL_SuspendTick 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:401:13:HAL_ResumeTick 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:411:10:HAL_GetHalVersion 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:420:10:HAL_GetREVID 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:429:10:HAL_GetDEVID 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:438:10:HAL_GetUIDw0 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:447:10:HAL_GetUIDw1 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:456:10:HAL_GetUIDw2 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:465:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:474:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:483:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:492:6:HAL_DBGMCU_DisableDBGStandbyMode 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d new file mode 100644 index 0000000..22d9676 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o new file mode 100644 index 0000000..1181d22 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su new file mode 100644 index 0000000..d391116 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su @@ -0,0 +1,23 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:141:19:HAL_Init 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:165:19:HAL_DeInit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:188:13:HAL_MspInit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:199:13:HAL_MspDeInit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:222:26:HAL_InitTick 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:281:13:HAL_IncTick 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:292:17:HAL_GetTick 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:301:10:HAL_GetTickPrio 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:310:19:HAL_SetTickFreq 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:342:21:HAL_GetTickFreq 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:358:13:HAL_Delay 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:384:13:HAL_SuspendTick 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:401:13:HAL_ResumeTick 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:411:10:HAL_GetHalVersion 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:420:10:HAL_GetREVID 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:429:10:HAL_GetDEVID 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:438:10:HAL_GetUIDw0 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:447:10:HAL_GetUIDw1 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:456:10:HAL_GetUIDw2 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:465:6:HAL_DBGMCU_EnableDBGStopMode 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:474:6:HAL_DBGMCU_DisableDBGStopMode 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:483:6:HAL_DBGMCU_EnableDBGStandbyMode 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c:492:6:HAL_DBGMCU_DisableDBGStandbyMode 8 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.cyclo new file mode 100644 index 0000000..88e0255 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.cyclo @@ -0,0 +1,28 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:406:19:HAL_ADC_Init 24 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:648:19:HAL_ADC_DeInit 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:774:13:HAL_ADC_MspInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:789:13:HAL_ADC_MspDeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1027:19:HAL_ADC_Start 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1092:19:HAL_ADC_Stop 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1146:19:HAL_ADC_PollForConversion 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1266:19:HAL_ADC_PollForEvent 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1342:19:HAL_ADC_Start_IT 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1423:19:HAL_ADC_Stop_IT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1476:19:HAL_ADC_Start_DMA 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1565:19:HAL_ADC_Stop_DMA 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1650:10:HAL_ADC_GetValue 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1667:6:HAL_ADC_IRQHandler 16 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1792:13:HAL_ADC_ConvCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1807:13:HAL_ADC_ConvHalfCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1822:13:HAL_ADC_LevelOutOfWindowCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1838:13:HAL_ADC_ErrorCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1892:19:HAL_ADC_ConfigChannel 30 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2025:19:HAL_ADC_AnalogWDGConfig 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2147:10:HAL_ADC_GetState 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2161:10:HAL_ADC_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2191:26:ADC_Enable 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2256:26:ADC_Disable 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2313:26:ADC_ConversionStop 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2364:13:ADC_DMAConvCplt 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2429:13:ADC_DMAHalfConvCplt 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2447:13:ADC_DMAError 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d new file mode 100644 index 0000000..c0dbd61 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o new file mode 100644 index 0000000..ca177fb Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su new file mode 100644 index 0000000..f40c29c --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su @@ -0,0 +1,28 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:406:19:HAL_ADC_Init 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:648:19:HAL_ADC_DeInit 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:774:13:HAL_ADC_MspInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:789:13:HAL_ADC_MspDeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1027:19:HAL_ADC_Start 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1092:19:HAL_ADC_Stop 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1146:19:HAL_ADC_PollForConversion 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1266:19:HAL_ADC_PollForEvent 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1342:19:HAL_ADC_Start_IT 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1423:19:HAL_ADC_Stop_IT 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1476:19:HAL_ADC_Start_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1565:19:HAL_ADC_Stop_DMA 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1650:10:HAL_ADC_GetValue 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1667:6:HAL_ADC_IRQHandler 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1792:13:HAL_ADC_ConvCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1807:13:HAL_ADC_ConvHalfCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1822:13:HAL_ADC_LevelOutOfWindowCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1838:13:HAL_ADC_ErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:1892:19:HAL_ADC_ConfigChannel 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2025:19:HAL_ADC_AnalogWDGConfig 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2147:10:HAL_ADC_GetState 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2161:10:HAL_ADC_GetError 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2191:26:ADC_Enable 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2256:26:ADC_Disable 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2313:26:ADC_ConversionStop 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2364:13:ADC_DMAConvCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2429:13:ADC_DMAHalfConvCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c:2447:13:ADC_DMAError 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.cyclo new file mode 100644 index 0000000..17edad4 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.cyclo @@ -0,0 +1 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c:97:19:HAL_ADCEx_Calibration_Start 8 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d new file mode 100644 index 0000000..47db663 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o new file mode 100644 index 0000000..58f8f9e Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su new file mode 100644 index 0000000..20a9a94 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su @@ -0,0 +1 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c:97:19:HAL_ADCEx_Calibration_Start 32 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.cyclo new file mode 100644 index 0000000..db73b02 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.cyclo @@ -0,0 +1,36 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:274:19:HAL_CAN_Init 13 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:459:19:HAL_CAN_DeInit 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:506:13:HAL_CAN_MspInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:522:13:HAL_CAN_MspDeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:838:19:HAL_CAN_ConfigFilter 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:988:19:HAL_CAN_Start 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1040:19:HAL_CAN_Stop 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1095:19:HAL_CAN_RequestSleep 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1126:19:HAL_CAN_WakeUp 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1175:10:HAL_CAN_IsSleepActive 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1206:19:HAL_CAN_AddTxMessage 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1314:19:HAL_CAN_AbortTxRequest 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1363:10:HAL_CAN_GetTxMailboxesFreeLevel 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1406:10:HAL_CAN_IsTxMessagePending 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1438:10:HAL_CAN_GetTxTimestamp 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1484:19:HAL_CAN_GetRxMessage 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1574:10:HAL_CAN_GetRxFifoFillLevel 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1627:19:HAL_CAN_ActivateNotification 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1660:19:HAL_CAN_DeactivateNotification 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1691:6:HAL_CAN_IRQHandler 51 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2102:13:HAL_CAN_TxMailbox0CompleteCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2119:13:HAL_CAN_TxMailbox1CompleteCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2136:13:HAL_CAN_TxMailbox2CompleteCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2153:13:HAL_CAN_TxMailbox0AbortCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2170:13:HAL_CAN_TxMailbox1AbortCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2187:13:HAL_CAN_TxMailbox2AbortCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2204:13:HAL_CAN_RxFifo0MsgPendingCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2221:13:HAL_CAN_RxFifo0FullCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2238:13:HAL_CAN_RxFifo1MsgPendingCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2255:13:HAL_CAN_RxFifo1FullCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2272:13:HAL_CAN_SleepCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2288:13:HAL_CAN_WakeUpFromRxMsgCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2305:13:HAL_CAN_ErrorCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2342:22:HAL_CAN_GetState 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2377:10:HAL_CAN_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2389:19:HAL_CAN_ResetError 3 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.d new file mode 100644 index 0000000..1d0793f --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o new file mode 100644 index 0000000..ea23a4e Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.su new file mode 100644 index 0000000..4ba3826 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.su @@ -0,0 +1,36 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:274:19:HAL_CAN_Init 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:459:19:HAL_CAN_DeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:506:13:HAL_CAN_MspInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:522:13:HAL_CAN_MspDeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:838:19:HAL_CAN_ConfigFilter 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:988:19:HAL_CAN_Start 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1040:19:HAL_CAN_Stop 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1095:19:HAL_CAN_RequestSleep 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1126:19:HAL_CAN_WakeUp 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1175:10:HAL_CAN_IsSleepActive 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1206:19:HAL_CAN_AddTxMessage 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1314:19:HAL_CAN_AbortTxRequest 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1363:10:HAL_CAN_GetTxMailboxesFreeLevel 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1406:10:HAL_CAN_IsTxMessagePending 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1438:10:HAL_CAN_GetTxTimestamp 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1484:19:HAL_CAN_GetRxMessage 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1574:10:HAL_CAN_GetRxFifoFillLevel 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1627:19:HAL_CAN_ActivateNotification 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1660:19:HAL_CAN_DeactivateNotification 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:1691:6:HAL_CAN_IRQHandler 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2102:13:HAL_CAN_TxMailbox0CompleteCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2119:13:HAL_CAN_TxMailbox1CompleteCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2136:13:HAL_CAN_TxMailbox2CompleteCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2153:13:HAL_CAN_TxMailbox0AbortCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2170:13:HAL_CAN_TxMailbox1AbortCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2187:13:HAL_CAN_TxMailbox2AbortCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2204:13:HAL_CAN_RxFifo0MsgPendingCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2221:13:HAL_CAN_RxFifo0FullCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2238:13:HAL_CAN_RxFifo1MsgPendingCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2255:13:HAL_CAN_RxFifo1FullCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2272:13:HAL_CAN_SleepCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2288:13:HAL_CAN_WakeUpFromRxMsgCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2305:13:HAL_CAN_ErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2342:22:HAL_CAN_GetState 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2377:10:HAL_CAN_GetError 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c:2389:19:HAL_CAN_ResetError 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.cyclo new file mode 100644 index 0000000..9ad522c --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.cyclo @@ -0,0 +1,21 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:659:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:678:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:697:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:712:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm0.h:730:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm0.h:754:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm0.h:856:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm0.h:920:26:SysTick_Config 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:136:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:152:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:168:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:181:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:194:10:HAL_SYSTICK_Config 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:226:10:HAL_NVIC_GetPriority 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:239:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:273:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:290:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:308:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:317:13:HAL_SYSTICK_Callback 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d new file mode 100644 index 0000000..c4d25f3 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o new file mode 100644 index 0000000..7d47a60 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su new file mode 100644 index 0000000..c848dac --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su @@ -0,0 +1,21 @@ +../Drivers/CMSIS/Include/core_cm0.h:623:22:__NVIC_EnableIRQ 16 static +../Drivers/CMSIS/Include/core_cm0.h:659:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm0.h:678:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0.h:697:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0.h:712:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm0.h:730:22:__NVIC_SetPriority 24 static +../Drivers/CMSIS/Include/core_cm0.h:754:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm0.h:856:34:__NVIC_SystemReset 8 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm0.h:920:26:SysTick_Config 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:136:6:HAL_NVIC_SetPriority 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:152:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:168:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:181:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:194:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:226:10:HAL_NVIC_GetPriority 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:239:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:273:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:290:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:308:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c:317:13:HAL_SYSTICK_Callback 8 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.cyclo new file mode 100644 index 0000000..7a70538 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:138:19:HAL_DMA_Init 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:200:19:HAL_DMA_DeInit 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:282:19:HAL_DMA_Start 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:329:19:HAL_DMA_Start_IT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:385:19:HAL_DMA_Abort 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:423:19:HAL_DMA_Abort_IT 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:469:19:HAL_DMA_PollForTransfer 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:570:6:HAL_DMA_IRQHandler 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:662:19:HAL_DMA_RegisterCallback 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:713:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:789:22:HAL_DMA_GetState 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:800:10:HAL_DMA_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:826:13:DMA_SetConfig 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:860:13:DMA_CalcBaseAndBitshift 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d new file mode 100644 index 0000000..be83786 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o new file mode 100644 index 0000000..7e2d756 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su new file mode 100644 index 0000000..87adb12 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su @@ -0,0 +1,14 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:138:19:HAL_DMA_Init 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:200:19:HAL_DMA_DeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:282:19:HAL_DMA_Start 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:329:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:385:19:HAL_DMA_Abort 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:423:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:469:19:HAL_DMA_PollForTransfer 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:570:6:HAL_DMA_IRQHandler 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:662:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:713:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:789:22:HAL_DMA_GetState 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:800:10:HAL_DMA_GetError 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:826:13:DMA_SetConfig 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c:860:13:DMA_CalcBaseAndBitshift 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.cyclo new file mode 100644 index 0000000..b1550d6 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:327:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:380:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:405:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:445:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:477:10:HAL_EXTI_GetPending 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:506:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:527:6:HAL_EXTI_GenerateSWI 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d new file mode 100644 index 0000000..2732b69 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o new file mode 100644 index 0000000..8ea1c6d Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su new file mode 100644 index 0000000..9823a30 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:327:19:HAL_EXTI_ClearConfigLine 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:380:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:405:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:445:6:HAL_EXTI_IRQHandler 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:477:10:HAL_EXTI_GetPending 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:506:6:HAL_EXTI_ClearPending 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c:527:6:HAL_EXTI_GenerateSWI 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.cyclo new file mode 100644 index 0000000..fec8f0f --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:167:19:HAL_FLASH_Program 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:239:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:285:6:HAL_FLASH_IRQHandler 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:446:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:479:19:HAL_FLASH_Unlock 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:503:19:HAL_FLASH_Lock 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:515:19:HAL_FLASH_OB_Unlock 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:535:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:548:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:580:10:HAL_FLASH_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:603:13:FLASH_Program_HalfWord 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:620:19:FLASH_WaitForLastOperation 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:663:13:FLASH_SetErrorCode 3 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d new file mode 100644 index 0000000..11d6546 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o new file mode 100644 index 0000000..cb6581e Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su new file mode 100644 index 0000000..4099893 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su @@ -0,0 +1,14 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:167:19:HAL_FLASH_Program 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:239:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:285:6:HAL_FLASH_IRQHandler 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:446:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:479:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:503:19:HAL_FLASH_Lock 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:515:19:HAL_FLASH_OB_Unlock 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:535:19:HAL_FLASH_OB_Lock 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:548:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:580:10:HAL_FLASH_GetError 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:603:13:FLASH_Program_HalfWord 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:620:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c:663:13:FLASH_SetErrorCode 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.cyclo new file mode 100644 index 0000000..7bffd27 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.cyclo @@ -0,0 +1,16 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:240:19:HAL_FLASHEx_Erase_IT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:313:19:HAL_FLASHEx_OBErase 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:362:19:HAL_FLASHEx_OBProgram 11 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:443:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:465:10:HAL_FLASHEx_OBGetUserData 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:500:13:FLASH_MassErase 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:521:26:FLASH_OB_EnableWRP 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:637:26:FLASH_OB_DisableWRP 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:751:26:FLASH_OB_RDP_LevelConfig 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:802:26:FLASH_OB_UserConfig 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:857:26:FLASH_OB_ProgramData 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:890:17:FLASH_OB_GetWRP 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:904:17:FLASH_OB_GetRDP 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:931:16:FLASH_OB_GetUser 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:960:6:FLASH_PageErase 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d new file mode 100644 index 0000000..bc35103 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o new file mode 100644 index 0000000..b0bb23f Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su new file mode 100644 index 0000000..914c6c0 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su @@ -0,0 +1,16 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:240:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:313:19:HAL_FLASHEx_OBErase 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:362:19:HAL_FLASHEx_OBProgram 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:443:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:465:10:HAL_FLASHEx_OBGetUserData 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:500:13:FLASH_MassErase 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:521:26:FLASH_OB_EnableWRP 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:637:26:FLASH_OB_DisableWRP 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:751:26:FLASH_OB_RDP_LevelConfig 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:802:26:FLASH_OB_UserConfig 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:857:26:FLASH_OB_ProgramData 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:890:17:FLASH_OB_GetWRP 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:904:17:FLASH_OB_GetRDP 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:931:16:FLASH_OB_GetUser 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c:960:6:FLASH_PageErase 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.cyclo new file mode 100644 index 0000000..6b62279 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:177:6:HAL_GPIO_Init 19 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:302:6:HAL_GPIO_DeInit 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:385:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:418:6:HAL_GPIO_WritePin 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:440:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:465:19:HAL_GPIO_LockPin 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:500:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:515:13:HAL_GPIO_EXTI_Callback 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d new file mode 100644 index 0000000..5953b11 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o new file mode 100644 index 0000000..2ff51b8 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su new file mode 100644 index 0000000..19fbb88 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:177:6:HAL_GPIO_Init 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:302:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:385:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:418:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:440:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:465:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:500:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c:515:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.cyclo new file mode 100644 index 0000000..476f50a --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.cyclo @@ -0,0 +1,79 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:476:19:HAL_I2C_Init 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:585:19:HAL_I2C_DeInit 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:631:13:HAL_I2C_MspInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:647:13:HAL_I2C_MspDeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1068:19:HAL_I2C_Master_Transmit 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1183:19:HAL_I2C_Master_Receive 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1297:19:HAL_I2C_Slave_Transmit 14 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1434:19:HAL_I2C_Slave_Receive 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1560:19:HAL_I2C_Master_Transmit_IT 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1630:19:HAL_I2C_Master_Receive_IT 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1697:19:HAL_I2C_Slave_Transmit_IT 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1746:19:HAL_I2C_Slave_Receive_IT 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1797:19:HAL_I2C_Master_Transmit_DMA 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1941:19:HAL_I2C_Master_Receive_DMA 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2083:19:HAL_I2C_Slave_Transmit_DMA 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2186:19:HAL_I2C_Slave_Receive_DMA 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2293:19:HAL_I2C_Mem_Write 15 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2428:19:HAL_I2C_Mem_Read 15 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2561:19:HAL_I2C_Mem_Write_IT 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2653:19:HAL_I2C_Mem_Read_IT 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2744:19:HAL_I2C_Mem_Write_DMA 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2889:19:HAL_I2C_Mem_Read_DMA 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3031:19:HAL_I2C_IsDeviceReady 16 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3172:19:HAL_I2C_Master_Seq_Transmit_IT 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3257:19:HAL_I2C_Master_Seq_Transmit_DMA 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3420:19:HAL_I2C_Master_Seq_Receive_IT 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3505:19:HAL_I2C_Master_Seq_Receive_DMA 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3666:19:HAL_I2C_Slave_Seq_Transmit_IT 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3762:19:HAL_I2C_Slave_Seq_Transmit_DMA 16 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3942:19:HAL_I2C_Slave_Seq_Receive_IT 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4038:19:HAL_I2C_Slave_Seq_Receive_DMA 16 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4214:19:HAL_I2C_EnableListen_IT 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4238:19:HAL_I2C_DisableListen_IT 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4271:19:HAL_I2C_Master_Abort_IT 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4333:6:HAL_I2C_EV_IRQHandler 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4352:6:HAL_I2C_ER_IRQHandler 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4401:13:HAL_I2C_MasterTxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4417:13:HAL_I2C_MasterRxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4432:13:HAL_I2C_SlaveTxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4448:13:HAL_I2C_SlaveRxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4466:13:HAL_I2C_AddrCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4484:13:HAL_I2C_ListenCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4500:13:HAL_I2C_MemTxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4516:13:HAL_I2C_MemRxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4532:13:HAL_I2C_ErrorCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4548:13:HAL_I2C_AbortCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4583:22:HAL_I2C_GetState 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4595:21:HAL_I2C_GetMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4606:10:HAL_I2C_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4631:26:I2C_Master_ISR_IT 22 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4768:26:I2C_Slave_ISR_IT 25 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4903:26:I2C_Master_ISR_DMA 18 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5038:26:I2C_Slave_ISR_DMA 27 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5178:26:I2C_RequestMemoryWrite 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5232:26:I2C_RequestMemoryRead 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5280:13:I2C_ITAddrCplt 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5375:13:I2C_ITMasterSeqCplt 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5428:13:I2C_ITSlaveSeqCplt 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5502:13:I2C_ITMasterCplt 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5645:13:I2C_ITSlaveCplt 16 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5804:13:I2C_ITListenCplt 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5855:13:I2C_ITError 17 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5967:13:I2C_TreatErrorCallback 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6005:13:I2C_Flush_TXDR 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6026:13:I2C_DMAMasterTransmitCplt 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6074:13:I2C_DMASlaveTransmitCplt 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6101:13:I2C_DMAMasterReceiveCplt 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6149:13:I2C_DMASlaveReceiveCplt 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6176:13:I2C_DMAError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6193:13:I2C_DMAAbort 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6220:26:I2C_WaitOnFlagUntilTimeout 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6251:26:I2C_WaitOnTXISFlagUntilTimeout 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6288:26:I2C_WaitOnSTOPFlagUntilTimeout 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6322:26:I2C_WaitOnRXNEFlagUntilTimeout 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6385:26:I2C_IsAcknowledgeFailed 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6453:13:I2C_TransferConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6476:13:I2C_Enable_IRQ 11 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6547:13:I2C_Disable_IRQ 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6610:13:I2C_ConvertOtherXferOptions 3 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d new file mode 100644 index 0000000..8c567d4 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o new file mode 100644 index 0000000..4b960b3 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su new file mode 100644 index 0000000..035a6f5 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su @@ -0,0 +1,79 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:476:19:HAL_I2C_Init 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:585:19:HAL_I2C_DeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:631:13:HAL_I2C_MspInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:647:13:HAL_I2C_MspDeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1068:19:HAL_I2C_Master_Transmit 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1183:19:HAL_I2C_Master_Receive 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1297:19:HAL_I2C_Slave_Transmit 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1434:19:HAL_I2C_Slave_Receive 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1560:19:HAL_I2C_Master_Transmit_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1630:19:HAL_I2C_Master_Receive_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1697:19:HAL_I2C_Slave_Transmit_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1746:19:HAL_I2C_Slave_Receive_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1797:19:HAL_I2C_Master_Transmit_DMA 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:1941:19:HAL_I2C_Master_Receive_DMA 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2083:19:HAL_I2C_Slave_Transmit_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2186:19:HAL_I2C_Slave_Receive_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2293:19:HAL_I2C_Mem_Write 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2428:19:HAL_I2C_Mem_Read 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2561:19:HAL_I2C_Mem_Write_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2653:19:HAL_I2C_Mem_Read_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2744:19:HAL_I2C_Mem_Write_DMA 56 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:2889:19:HAL_I2C_Mem_Read_DMA 56 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3031:19:HAL_I2C_IsDeviceReady 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3172:19:HAL_I2C_Master_Seq_Transmit_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3257:19:HAL_I2C_Master_Seq_Transmit_DMA 56 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3420:19:HAL_I2C_Master_Seq_Receive_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3505:19:HAL_I2C_Master_Seq_Receive_DMA 56 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3666:19:HAL_I2C_Slave_Seq_Transmit_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3762:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:3942:19:HAL_I2C_Slave_Seq_Receive_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4038:19:HAL_I2C_Slave_Seq_Receive_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4214:19:HAL_I2C_EnableListen_IT 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4238:19:HAL_I2C_DisableListen_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4271:19:HAL_I2C_Master_Abort_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4333:6:HAL_I2C_EV_IRQHandler 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4352:6:HAL_I2C_ER_IRQHandler 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4401:13:HAL_I2C_MasterTxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4417:13:HAL_I2C_MasterRxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4432:13:HAL_I2C_SlaveTxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4448:13:HAL_I2C_SlaveRxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4466:13:HAL_I2C_AddrCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4484:13:HAL_I2C_ListenCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4500:13:HAL_I2C_MemTxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4516:13:HAL_I2C_MemRxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4532:13:HAL_I2C_ErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4548:13:HAL_I2C_AbortCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4583:22:HAL_I2C_GetState 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4595:21:HAL_I2C_GetMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4606:10:HAL_I2C_GetError 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4631:26:I2C_Master_ISR_IT 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4768:26:I2C_Slave_ISR_IT 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:4903:26:I2C_Master_ISR_DMA 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5038:26:I2C_Slave_ISR_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5178:26:I2C_RequestMemoryWrite 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5232:26:I2C_RequestMemoryRead 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5280:13:I2C_ITAddrCplt 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5375:13:I2C_ITMasterSeqCplt 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5428:13:I2C_ITSlaveSeqCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5502:13:I2C_ITMasterCplt 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5645:13:I2C_ITSlaveCplt 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5804:13:I2C_ITListenCplt 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5855:13:I2C_ITError 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:5967:13:I2C_TreatErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6005:13:I2C_Flush_TXDR 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6026:13:I2C_DMAMasterTransmitCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6074:13:I2C_DMASlaveTransmitCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6101:13:I2C_DMAMasterReceiveCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6149:13:I2C_DMASlaveReceiveCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6176:13:I2C_DMAError 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6193:13:I2C_DMAAbort 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6220:26:I2C_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6251:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6288:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6322:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6385:26:I2C_IsAcknowledgeFailed 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6453:13:I2C_TransferConfig 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6476:13:I2C_Enable_IRQ 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6547:13:I2C_Disable_IRQ 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c:6610:13:I2C_ConvertOtherXferOptions 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.cyclo new file mode 100644 index 0000000..fafe5c2 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:193:19:HAL_I2CEx_EnableWakeUp 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:232:19:HAL_I2CEx_DisableWakeUp 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:279:6:HAL_I2CEx_EnableFastModePlus 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:304:6:HAL_I2CEx_DisableFastModePlus 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d new file mode 100644 index 0000000..4835680 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o new file mode 100644 index 0000000..c025d85 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su new file mode 100644 index 0000000..668f686 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:193:19:HAL_I2CEx_EnableWakeUp 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:232:19:HAL_I2CEx_DisableWakeUp 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:279:6:HAL_I2CEx_EnableFastModePlus 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c:304:6:HAL_I2CEx_DisableFastModePlus 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.cyclo new file mode 100644 index 0000000..7158713 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.cyclo @@ -0,0 +1,12 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:75:6:HAL_PWR_DeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:88:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:100:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:231:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:246:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:269:6:HAL_PWR_EnterSLEEPMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:312:6:HAL_PWR_EnterSTOPMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:367:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:391:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:404:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:418:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:431:6:HAL_PWR_DisableSEVOnPend 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d new file mode 100644 index 0000000..34c3b00 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o new file mode 100644 index 0000000..2ad6e42 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su new file mode 100644 index 0000000..a7ff3ff --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su @@ -0,0 +1,12 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:75:6:HAL_PWR_DeInit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:88:6:HAL_PWR_EnableBkUpAccess 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:100:6:HAL_PWR_DisableBkUpAccess 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:231:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:246:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:269:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:312:6:HAL_PWR_EnterSTOPMode 24 static,ignoring_inline_asm +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:367:6:HAL_PWR_EnterSTANDBYMode 8 static,ignoring_inline_asm +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:391:6:HAL_PWR_EnableSleepOnExit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:404:6:HAL_PWR_DisableSleepOnExit 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:418:6:HAL_PWR_EnableSEVOnPend 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c:431:6:HAL_PWR_DisableSEVOnPend 8 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..66ae804 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:108:6:HAL_PWR_ConfigPVD 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:150:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:159:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:169:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:186:13:HAL_PWR_PVDCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:207:6:HAL_PWREx_EnableVddio2Monitor 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:217:6:HAL_PWREx_DisableVddio2Monitor 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:229:6:HAL_PWREx_Vddio2Monitor_IRQHandler 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:246:13:HAL_PWREx_Vddio2MonitorCallback 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d new file mode 100644 index 0000000..7d1e7d6 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o new file mode 100644 index 0000000..26e618b Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su new file mode 100644 index 0000000..7f9012d --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su @@ -0,0 +1,9 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:108:6:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:150:6:HAL_PWR_EnablePVD 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:159:6:HAL_PWR_DisablePVD 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:169:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:186:13:HAL_PWR_PVDCallback 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:207:6:HAL_PWREx_EnableVddio2Monitor 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:217:6:HAL_PWREx_DisableVddio2Monitor 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:229:6:HAL_PWREx_Vddio2Monitor_IRQHandler 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c:246:13:HAL_PWREx_Vddio2MonitorCallback 8 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.cyclo new file mode 100644 index 0000000..5760b86 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.cyclo @@ -0,0 +1,13 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:210:19:HAL_RCC_DeInit 8 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:300:19:HAL_RCC_OscConfig 78 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:779:19:HAL_RCC_ClockConfig 19 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1018:6:HAL_RCC_MCOConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1052:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1061:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1097:10:HAL_RCC_GetSysClockFreq 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1172:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1183:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1196:6:HAL_RCC_GetOscConfig 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1298:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1324:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1341:13:HAL_RCC_CSSCallback 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d new file mode 100644 index 0000000..54dc410 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o new file mode 100644 index 0000000..82f928b Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su new file mode 100644 index 0000000..ba07469 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su @@ -0,0 +1,13 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:210:19:HAL_RCC_DeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:300:19:HAL_RCC_OscConfig 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:779:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1018:6:HAL_RCC_MCOConfig 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1052:6:HAL_RCC_EnableCSS 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1061:6:HAL_RCC_DisableCSS 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1097:10:HAL_RCC_GetSysClockFreq 72 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1172:10:HAL_RCC_GetHCLKFreq 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1183:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1196:6:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1298:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1324:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c:1341:13:HAL_RCC_CSSCallback 8 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..3f3016f --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.cyclo @@ -0,0 +1,12 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:104:19:HAL_RCCEx_PeriphCLKConfig 17 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:270:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:370:10:HAL_RCCEx_GetPeriphCLKFreq 42 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:659:6:HAL_RCCEx_CRSConfig 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:701:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:711:6:HAL_RCCEx_CRSGetSynchronizationInfo 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:744:10:HAL_RCCEx_CRSWaitSynchronization 11 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:827:6:HAL_RCCEx_CRS_IRQHandler 12 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:892:13:HAL_RCCEx_CRS_SyncOkCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:903:13:HAL_RCCEx_CRS_SyncWarnCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:914:13:HAL_RCCEx_CRS_ExpectedSyncCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:930:13:HAL_RCCEx_CRS_ErrorCallback 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d new file mode 100644 index 0000000..6a5c98e --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o new file mode 100644 index 0000000..0d5ea89 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su new file mode 100644 index 0000000..904d7c0 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su @@ -0,0 +1,12 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:104:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:270:6:HAL_RCCEx_GetPeriphCLKConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:370:10:HAL_RCCEx_GetPeriphCLKFreq 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:659:6:HAL_RCCEx_CRSConfig 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:701:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:711:6:HAL_RCCEx_CRSGetSynchronizationInfo 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:744:10:HAL_RCCEx_CRSWaitSynchronization 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:827:6:HAL_RCCEx_CRS_IRQHandler 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:892:13:HAL_RCCEx_CRS_SyncOkCallback 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:903:13:HAL_RCCEx_CRS_SyncWarnCallback 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:914:13:HAL_RCCEx_CRS_ExpectedSyncCallback 8 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c:930:13:HAL_RCCEx_CRS_ErrorCallback 16 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d new file mode 100644 index 0000000..25a7e48 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o new file mode 100644 index 0000000..8feadc1 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.su new file mode 100644 index 0000000..e69de29 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d new file mode 100644 index 0000000..3600600 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o new file mode 100644 index 0000000..9e92a6c Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.cyclo new file mode 100644 index 0000000..d5dd327 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.cyclo @@ -0,0 +1,66 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:288:19:HAL_UART_Init 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:377:19:HAL_HalfDuplex_Init 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:465:19:HAL_LIN_Init 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:575:19:HAL_MultiProcessor_Init 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:665:19:HAL_UART_DeInit 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:711:13:HAL_UART_MspInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:726:13:HAL_UART_MspDeInit 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1145:19:HAL_UART_Transmit 14 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1246:19:HAL_UART_Receive 19 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1348:19:HAL_UART_Transmit_IT 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1417:19:HAL_UART_Receive_IT 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1473:19:HAL_UART_Transmit_DMA 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1565:19:HAL_UART_Receive_DMA 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1611:19:HAL_UART_DMAPause 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1645:19:HAL_UART_DMAResume 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1677:19:HAL_UART_DMAStop 11 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1752:19:HAL_UART_Abort 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1847:19:HAL_UART_AbortTransmit 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1899:19:HAL_UART_AbortReceive 6 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1966:19:HAL_UART_Abort_IT 13 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2112:19:HAL_UART_AbortTransmit_IT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2196:19:HAL_UART_AbortReceive_IT 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2288:6:HAL_UART_IRQHandler 44 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2581:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2596:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2611:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2626:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2641:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2656:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2671:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2686:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2703:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2751:6:HAL_UART_ReceiverTimeout_Config 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2763:19:HAL_UART_EnableReceiverTimeout 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2794:19:HAL_UART_DisableReceiverTimeout 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2825:19:HAL_MultiProcessor_EnableMuteMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2845:19:HAL_MultiProcessor_DisableMuteMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2865:6:HAL_MultiProcessor_EnterMuteMode 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2875:19:HAL_HalfDuplex_EnableTransmitter 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2923:19:HAL_LIN_SendBreak 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2969:23:HAL_UART_GetState 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2985:10:HAL_UART_GetError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3031:19:UART_SetConfig 36 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3169:6:UART_AdvFeatureConfig 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3243:19:UART_CheckIdleState 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3294:19:UART_WaitOnFlagUntilTimeout 7 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3356:19:UART_Start_Receive_IT 9 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3400:19:UART_Start_Receive_DMA 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3457:13:UART_EndTxTransfer 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3472:13:UART_EndRxTransfer 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3498:13:UART_DMATransmitCplt 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3532:13:UART_DMATxHalfCplt 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3550:13:UART_DMAReceiveCplt 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3607:13:UART_DMARxHalfCplt 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3641:13:UART_DMAError 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3681:13:UART_DMAAbortOnError 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3704:13:UART_DMATxAbortCallback 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3754:13:UART_DMARxAbortCallback 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3806:13:UART_DMATxOnlyAbortCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3834:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3867:13:UART_TxISR_8BIT 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3896:13:UART_TxISR_16BIT 3 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3928:13:UART_EndTransmit_IT 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3953:13:UART_RxISR_8BIT 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:4023:13:UART_RxISR_16BIT 4 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.d new file mode 100644 index 0000000..6f53bef --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o new file mode 100644 index 0000000..b9d7041 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.su new file mode 100644 index 0000000..e9e5e3f --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.su @@ -0,0 +1,66 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:288:19:HAL_UART_Init 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:377:19:HAL_HalfDuplex_Init 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:465:19:HAL_LIN_Init 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:575:19:HAL_MultiProcessor_Init 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:665:19:HAL_UART_DeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:711:13:HAL_UART_MspInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:726:13:HAL_UART_MspDeInit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1145:19:HAL_UART_Transmit 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1246:19:HAL_UART_Receive 48 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1348:19:HAL_UART_Transmit_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1417:19:HAL_UART_Receive_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1473:19:HAL_UART_Transmit_DMA 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1565:19:HAL_UART_Receive_DMA 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1611:19:HAL_UART_DMAPause 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1645:19:HAL_UART_DMAResume 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1677:19:HAL_UART_DMAStop 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1752:19:HAL_UART_Abort 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1847:19:HAL_UART_AbortTransmit 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1899:19:HAL_UART_AbortReceive 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:1966:19:HAL_UART_Abort_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2112:19:HAL_UART_AbortTransmit_IT 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2196:19:HAL_UART_AbortReceive_IT 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2288:6:HAL_UART_IRQHandler 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2581:13:HAL_UART_TxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2596:13:HAL_UART_TxHalfCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2611:13:HAL_UART_RxCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2626:13:HAL_UART_RxHalfCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2641:13:HAL_UART_ErrorCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2656:13:HAL_UART_AbortCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2671:13:HAL_UART_AbortTransmitCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2686:13:HAL_UART_AbortReceiveCpltCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2703:13:HAL_UARTEx_RxEventCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2751:6:HAL_UART_ReceiverTimeout_Config 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2763:19:HAL_UART_EnableReceiverTimeout 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2794:19:HAL_UART_DisableReceiverTimeout 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2825:19:HAL_MultiProcessor_EnableMuteMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2845:19:HAL_MultiProcessor_DisableMuteMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2865:6:HAL_MultiProcessor_EnterMuteMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2875:19:HAL_HalfDuplex_EnableTransmitter 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2898:19:HAL_HalfDuplex_EnableReceiver 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2923:19:HAL_LIN_SendBreak 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2969:23:HAL_UART_GetState 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:2985:10:HAL_UART_GetError 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3031:19:UART_SetConfig 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3169:6:UART_AdvFeatureConfig 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3243:19:UART_CheckIdleState 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3294:19:UART_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3356:19:UART_Start_Receive_IT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3400:19:UART_Start_Receive_DMA 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3457:13:UART_EndTxTransfer 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3472:13:UART_EndRxTransfer 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3498:13:UART_DMATransmitCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3532:13:UART_DMATxHalfCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3550:13:UART_DMAReceiveCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3607:13:UART_DMARxHalfCplt 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3641:13:UART_DMAError 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3681:13:UART_DMAAbortOnError 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3704:13:UART_DMATxAbortCallback 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3754:13:UART_DMARxAbortCallback 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3806:13:UART_DMATxOnlyAbortCallback 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3834:13:UART_DMARxOnlyAbortCallback 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3867:13:UART_TxISR_8BIT 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3896:13:UART_TxISR_16BIT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3928:13:UART_EndTransmit_IT 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:3953:13:UART_RxISR_8BIT 24 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c:4023:13:UART_RxISR_16BIT 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.cyclo b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.cyclo new file mode 100644 index 0000000..3d68485 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.cyclo @@ -0,0 +1,10 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:150:19:HAL_RS485Ex_Init 5 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:255:13:HAL_UARTEx_WakeupCallback 1 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:340:19:HAL_MultiProcessorEx_AddressLength_Set 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:379:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:434:19:HAL_UARTEx_EnableStopMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:453:19:HAL_UARTEx_DisableStopMode 2 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:487:19:HAL_UARTEx_ReceiveToIdle 24 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:625:19:HAL_UARTEx_ReceiveToIdle_IT 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:701:19:HAL_UARTEx_ReceiveToIdle_DMA 10 +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:776:13:UARTEx_Wakeup_AddressConfig 1 diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.d b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.d new file mode 100644 index 0000000..5aefa7b --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o: \ + ../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h \ + ../Core/Inc/stm32f0xx_hal_conf.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h \ + ../Drivers/CMSIS/Include/core_cm0.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h \ + ../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h: +../Core/Inc/stm32f0xx_hal_conf.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h: +../Drivers/CMSIS/Include/core_cm0.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h: +../Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h: diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o new file mode 100644 index 0000000..a232373 Binary files /dev/null and b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o differ diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.su b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.su new file mode 100644 index 0000000..3d7f9da --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.su @@ -0,0 +1,10 @@ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:150:19:HAL_RS485Ex_Init 32 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:255:13:HAL_UARTEx_WakeupCallback 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:340:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:379:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:434:19:HAL_UARTEx_EnableStopMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:453:19:HAL_UARTEx_DisableStopMode 16 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:487:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:625:19:HAL_UARTEx_ReceiveToIdle_IT 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:701:19:HAL_UARTEx_ReceiveToIdle_DMA 40 static +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c:776:13:UARTEx_Wakeup_AddressConfig 24 static diff --git a/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..819f6b2 --- /dev/null +++ b/DBW_V2/Debug/Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,84 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c \ +../Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c + +C_DEPS += \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.d \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.d + +OBJS += \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o \ +./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F0xx_HAL_Driver/Src/%.o Drivers/STM32F0xx_HAL_Driver/Src/%.su Drivers/STM32F0xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F0xx_HAL_Driver/Src/%.c Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F072xB -DDEBUG -c -I../Drivers/STM32F0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Include -I../Core/Inc -I../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F0xx/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32F0xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32F0xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.su ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.cyclo ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.d ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o ./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.su + +.PHONY: clean-Drivers-2f-STM32F0xx_HAL_Driver-2f-Src + diff --git a/DBW_V2/Debug/makefile b/DBW_V2/Debug/makefile new file mode 100644 index 0000000..676e441 --- /dev/null +++ b/DBW_V2/Debug/makefile @@ -0,0 +1,118 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32F0xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(CCM_DEPS)),) +-include $(CCM_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CXXM_DEPS)),) +-include $(CXXM_DEPS) +endif +ifneq ($(strip $(C++M_DEPS)),) +-include $(C++M_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := DBW_V2 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +DBW_V2.elf \ + +MAP_FILES += \ +DBW_V2.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +DBW_V2.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: DBW_V2.elf secondary-outputs + +# Tool invocations +DBW_V2.elf DBW_V2.map: $(OBJS) $(USER_OBJS) Z:\STM32\STM32CubeIDE\workspace_1.9.0\DBW_v2\STM32F072C8TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-g++ -o "DBW_V2.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0 -T"Z:\STM32\STM32CubeIDE\workspace_1.9.0\DBW_v2\STM32F072C8TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="DBW_V2.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +DBW_V2.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "DBW_V2.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) DBW_V2.elf DBW_V2.list DBW_V2.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/DBW_V2/Debug/objects.list b/DBW_V2/Debug/objects.list new file mode 100644 index 0000000..6e4404c --- /dev/null +++ b/DBW_V2/Debug/objects.list @@ -0,0 +1,35 @@ +"./Core/Src/adc.o" +"./Core/Src/can.o" +"./Core/Src/dbw.o" +"./Core/Src/inputs.o" +"./Core/Src/main.o" +"./Core/Src/mazda_can.o" +"./Core/Src/outputs.o" +"./Core/Src/safety.o" +"./Core/Src/stm32f0xx_hal_msp.o" +"./Core/Src/stm32f0xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32f0xx.o" +"./Core/Src/ts_comms.o" +"./Core/Startup/startup_stm32f072c8tx.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.o" +"./Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.o" diff --git a/DBW_V2/Debug/objects.mk b/DBW_V2/Debug/objects.mk new file mode 100644 index 0000000..aa49a8e --- /dev/null +++ b/DBW_V2/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/DBW_V2/Debug/sources.mk b/DBW_V2/Debug/sources.mk new file mode 100644 index 0000000..11f1e69 --- /dev/null +++ b/DBW_V2/Debug/sources.mk @@ -0,0 +1,44 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (14.3.rel1) +################################################################################ + +C++M_SRCS := +CPP_SRCS := +S_UPPER_SRCS := +O_SRCS := +ELF_SRCS := +C_UPPER_SRCS := +CXX_SRCS := +CCM_SRCS := +C++_SRCS := +OBJ_SRCS := +S_SRCS := +CC_SRCS := +C_SRCS := +CXXM_SRCS := +CYCLO_FILES := +OBJDUMP_LIST := +CCM_DEPS := +C_UPPER_DEPS := +S_DEPS := +CXXM_DEPS := +C_DEPS := +CC_DEPS := +SIZE_OUTPUT := +C++_DEPS := +SU_FILES := +EXECUTABLES := +OBJS := +CXX_DEPS := +MAP_FILES := +S_UPPER_DEPS := +C++M_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F0xx_HAL_Driver/Src \ + diff --git a/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h b/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h new file mode 100644 index 0000000..f6e8fd5 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h @@ -0,0 +1,11293 @@ +/** + ****************************************************************************** + * @file stm32f072xb.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F0xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f072xb + * @{ + */ + +#ifndef __STM32F072xB_H +#define __STM32F072xB_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F0 specific Interrupt Numbers ******************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ + TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupt */ + ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +}CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +}CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +}CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +}CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/* Legacy defines */ +typedef struct +{ + __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */ +}COMP1_2_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +}CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/** Uncomment the line below according to the target STM32 device used in your application. + * stm32f0xxxx.h file contains: + * - All the peripheral register's definitions, bits definitions and memory mapping for STM32F0xxxx devices + * - IRQ channel definition + * - Peripheral memory mapping and physical registers address definition + * - Peripheral pointer declaration and driver header file inclusion + * - Product miscellaneous configuration: assert macros… + * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family’s superset. + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048xx */ /*!< STM32F048xx Devices (STM32F048xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif +/* Legacy aliases */ +#if defined (STM32F048x6) + #define STM32F048xx +#endif /* STM32F048x6 */ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.5 + */ +#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F0_DEVICE_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F0_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F0_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F0_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h new file mode 100644 index 0000000..fafabf4 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h @@ -0,0 +1,105 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_armcc.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..7d751fb --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_armclang.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..d8031b0 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_compiler.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..79a2cac --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_gcc.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..1bd41a4 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_iccarm.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..3c90a2c --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/DBW_V2/Drivers/CMSIS/Include/cmsis_version.h b/DBW_V2/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..ae3f2e3 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/DBW_V2/Drivers/CMSIS/Include/core_armv8mbl.h b/DBW_V2/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..ec76ab2 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_armv8mml.h b/DBW_V2/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..2d0f106 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm0.h b/DBW_V2/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..6f82227 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm0plus.h b/DBW_V2/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b9377e8 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm1.h b/DBW_V2/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..fd1c407 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm23.h b/DBW_V2/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..8202a8d --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm3.h b/DBW_V2/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b0dfbd3 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm33.h b/DBW_V2/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..02f82e2 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm4.h b/DBW_V2/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..308b868 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_cm7.h b/DBW_V2/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..ada6c2a --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_sc000.h b/DBW_V2/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9086c64 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/core_sc300.h b/DBW_V2/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..665822d --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/DBW_V2/Drivers/CMSIS/Include/mpu_armv7.h b/DBW_V2/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..7d4b600 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/DBW_V2/Drivers/CMSIS/Include/mpu_armv8.h b/DBW_V2/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..99ee9f9 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/DBW_V2/Drivers/CMSIS/Include/tz_context.h b/DBW_V2/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/DBW_V2/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..43cafcb --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3783 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h new file mode 100644 index 0000000..a100055 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h @@ -0,0 +1,585 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_H +#define __STM32F0xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_conf.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Macros + * @{ + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#else +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) +#endif +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; + +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remapping HAL Pin remapping + * @{ + */ +#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). + 0: No remap (pin pair PA9/10 mapped on the pins) + 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ + +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection + * @note Applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ +#endif +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ + +/** + * @} + */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @note applicable on STM32F09x + * @{ + */ +#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */ + +#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ +#if defined(STM32F091xC) +#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ +#endif +#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ +#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ +#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ +#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ +#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ +#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ +#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ +#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ +#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ +#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ +#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ +#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ +#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ +#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ +#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ +#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ +#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ +#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ +#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ +#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ +#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ +#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ +#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ +#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ +#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ +#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ +#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ +#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ +#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ +#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ +#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ +#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ +#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ +#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) +#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ + +#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ + +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup Memory_Mapping_Selection Memory Mapping Selection + * @{ + */ +#if defined(SYSCFG_CFGR1_MEM_MODE) +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#endif /* SYSCFG_CFGR1_MEM_MODE */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 */ + +#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ + SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ + }while(0) +#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ +/** + * @} + */ + + +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +/** @defgroup HAL_Pin_remap HAL Pin remap + * @brief Pin remapping enable/disable macros + * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping + * @{ + */ +#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 |= (__PIN_REMAP__); \ + }while(0) +#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * That you can find above these macros. + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ + +#if defined(SYSCFG_CFGR2_PVD_LOCK) +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_PVD_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +/** @defgroup SRAM_Parity_Lock SRAM Parity Lock + * @{ + */ +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ + +#if defined(SYSCFG_CFGR2_SRAM_PEF) +/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM + * @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + * @{ + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) +/** + * @} + */ +#endif /* SYSCFG_CFGR2_SRAM_PEF */ + + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check + * @brief ISR wrapper check + * @note This feature is applicable on STM32F09x + * @note Allow to determine interrupt source per line. + * @{ + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +#if defined(STM32F091xC) || defined (STM32F098xx) +/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection + * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register + * @note This feature is applicable on STM32F09x + * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL + * @{ + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ + SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ + SYSCFG->CFGR1 |= (__SOURCE__); \ + }while(0) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) +/** + * @} + */ +#endif /* (STM32F091xC) || defined (STM32F098xx)*/ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h new file mode 100644 index 0000000..31771b1 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h @@ -0,0 +1,1019 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc.h + * @author MCD Application Team + * @brief Header file containing functions prototypes of ADC HAL library. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_ADC_H +#define STM32F0xx_HAL_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC initialization and regular group + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') + * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. + This parameter can be a value of @ref ADC_ClockPrescaler + Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if the ADC is disabled */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_Data_align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): + If only 1 channel is set: Conversion is performed in single mode. + If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). + This parameter can be a value of @ref ADC_Scan_mode */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. */ + FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous + conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). + This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ + FunctionalState LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. + Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE + Note: Number of discontinuous ranks increment is fixed to one-by-one. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + This parameter can be a value of @ref ADC_External_trigger_source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten + This parameter has an effect on regular group only, including in DMA mode. + This parameter can be a value of @ref ADC_Overrun */ + uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_sampling_times + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ +}ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled or enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. + On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. + Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_rank */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. + Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. + If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ +}ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. + This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. + This parameter can be a value of @ref ADC_channels. */ + FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + * @note ADC state machine is managed by bitfields, state must be compared + * with bit by bit. + * For example: + * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " + * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +}ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler + * @{ + */ +#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ + +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ + +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ +/** + * @} + */ + +/** @defgroup ADC_Data_align ADC Data_align + * @{ + */ +#define ADC_DATAALIGN_RIGHT (0x00000000U) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC Scan mode + * @{ + */ +/* Note: Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE (0x00000000U) */ +/* ADC_SCAN_ENABLE (0x00000001U) */ +/* Scan direction forward is considered as default setting equivalent */ +/* to scan enable. */ +/* Scan direction backward is considered as additional setting. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +#define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ + +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC EOCSelection + * @{ + */ +#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) +#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) +/** + * @} + */ + +/** @defgroup ADC_Overrun ADC Overrun + * @{ + */ +#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) +#define ADC_OVR_DATA_PRESERVED (0x00000001U) +/** + * @} + */ + +/** @defgroup ADC_rank ADC rank + * @{ + */ +#define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC sampling times + * @{ + */ +/* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ +/* to distinguish this parameter versus reset value 0x00000000, */ +/* in the context of management of parameters "SamplingTimeCommon" */ +/* and "SamplingTime" (obsolete)). */ +#define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ +#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ +#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ +#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ +#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ +#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular + * @{ + */ + +/* List of external triggers of regular group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ +#define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) +#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) +#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) +#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) +/** + * @} + */ + +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Enable the ADC peripheral + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) + +/** + * @brief Disable the ADC peripheral + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ + __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ + } while(0) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval State ofinterruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag + * @arg ADC_FLAG_RDY: ADC Ready flag + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the ADC's pending flags + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag + * @arg ADC_FLAG_RDY: ADC Ready flag + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** @brief Reset ADC handle state + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif + +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + + +/** + * @brief Verification of hardware constraints before ADC can be enabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) + */ +#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ + ) == RESET \ + ) ? SET : RESET) + +/** + * @brief Verification of hardware constraints before ADC can be disabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) + */ +#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ + ) ? SET : RESET) + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ +/* performed automatically by hardware and flag ADC_FLAG_RDY is not */ +/* set. */ +#define ADC_IS_ENABLE(__HANDLE__) \ + (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ + (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ + ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) + +/** + * @brief Check if no conversion on going on regular group + * @param __HANDLE__ ADC handle + * @retval SET (conversion is on going) or RESET (no conversion is on going) + */ +#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ + (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ + ) ? RESET : SET) + +/** + * @brief Returns resolution bits in CFGR1 register: RES[1:0]. + * Returned value is among parameters to @ref ADC_Resolution. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) + +/** + * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. + * Returned value is among parameters to @ref ADC_Resolution. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_GET_SAMPLINGTIME(__HANDLE__) \ + (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + + +/** + * @brief Configure the channel number into channel selection register + * @param _CHANNEL_ ADC Channel + * @retval None + */ +/* This function converts ADC channels from numbers (see defgroup ADC_channels) + to bitfields, to get the equivalence of CMSIS channels: + ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) + ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) + ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) + ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) + ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) + ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) + ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) + ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) + ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) + ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) + ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) + ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) + ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) + ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) + ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) + ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) + ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) + ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) + ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) +*/ +#define ADC_CHSELR_CHANNEL(_CHANNEL_) \ + ( 1U << (_CHANNEL_)) + +/** + * @brief Set the ADC's sample time + * @param _SAMPLETIME_ Sample time parameter. + * @retval None + */ +/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ +/* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ +/* distinguish this parameter versus reset value 0x00000000, */ +/* in the context of management of parameters "SamplingTimeCommon" */ +/* and "SamplingTime" (obsolete)). */ +#define ADC_SMPR_SET(_SAMPLETIME_) \ + ((_SAMPLETIME_) & (ADC_SMPR_SMP)) + +/** + * @brief Set the Analog Watchdog 1 channel. + * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. + * @retval None + */ +#define ADC_CFGR_AWDCH(_CHANNEL_) \ + ((_CHANNEL_) << 26U) + +/** + * @brief Enable ADC discontinuous conversion mode for regular group + * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. + * @retval None + */ +#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ + ((_REG_DISCONTINUOUS_MODE_) << 16U) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_ Auto off bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15U) + +/** + * @brief Enable the ADC auto delay mode. + * @param _AUTOWAIT_ Auto delay bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ + ((_AUTOWAIT_) << 14U) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << 13U) + +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. + * @retval Overun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ + ) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_ Scan conversion mode. + * @retval None + */ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: to avoid any */ +/* unwanted setting, the exact parameter corresponding to the device */ +/* must be passed to this macro. */ +#define ADC_SCANDIR(_SCAN_MODE_) \ + ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ + )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ + ) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_ DMA continuous request mode. + * @retval None + */ +#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << 1U) + +/** + * @brief Configure the analog watchdog high threshold into register TR. + * @param _Threshold_ Threshold value + * @retval None + */ +#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ + ((_Threshold_) << 16U) + +/** + * @brief Shift the AWD threshold in function of the selected ADC resolution. + * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted + * @retval None + */ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) + + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ + ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) + +#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ + ((WATCHDOG) == ADC_RANK_NONE) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT) ) + +/** @defgroup ADC_range_verification ADC range verification + * in function of ADC resolution selected (12, 10, 8 or 6 bits) + * @{ + */ +#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) +/** + * @} + */ + +/** @defgroup ADC_regular_rank_verification ADC regular rank verification + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f0xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ + + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* IO operation functions *****************************************************/ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ + + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/* Peripheral Control functions ***********************************************/ +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F0xx_HAL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h new file mode 100644 index 0000000..96e74cc --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_ADC_EX_H +#define __STM32F0xx_HAL_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CCR_ALL (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN) +#else +#define ADC_CCR_ALL (ADC_CCR_TSEN | ADC_CCR_VREFEN) +#endif + +/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular + * @{ + */ +/* List of external triggers with generic trigger name, sorted by trigger */ +/* name: */ + +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO +#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 +#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO +#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + 1U) + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO +#endif + +#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6) +#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO +#endif + +/** + * @} + */ + + +/** @defgroup ADC_channels ADC channels + * @{ + */ +/* Note: Depending on devices, some channels may not be available on package */ +/* pins. Refer to device datasheet for channels availability. */ +/* Note: Channels are used by bitfields for setting of channel selection */ +/* (register ADC_CHSELR) and used by number for setting of analog */ +/* watchdog channel (bits AWDCH in register ADC_CFGR1). */ +/* Channels are defined with decimal numbers and converted them to */ +/* bitfields when needed. */ +#define ADC_CHANNEL_0 ( 0x00000000U) +#define ADC_CHANNEL_1 ( 0x00000001U) +#define ADC_CHANNEL_2 ( 0x00000002U) +#define ADC_CHANNEL_3 ( 0x00000003U) +#define ADC_CHANNEL_4 ( 0x00000004U) +#define ADC_CHANNEL_5 ( 0x00000005U) +#define ADC_CHANNEL_6 ( 0x00000006U) +#define ADC_CHANNEL_7 ( 0x00000007U) +#define ADC_CHANNEL_8 ( 0x00000008U) +#define ADC_CHANNEL_9 ( 0x00000009U) +#define ADC_CHANNEL_10 ( 0x0000000AU) +#define ADC_CHANNEL_11 ( 0x0000000BU) +#define ADC_CHANNEL_12 ( 0x0000000CU) +#define ADC_CHANNEL_13 ( 0x0000000DU) +#define ADC_CHANNEL_14 ( 0x0000000EU) +#define ADC_CHANNEL_15 ( 0x0000000FU) +#define ADC_CHANNEL_16 ( 0x00000010U) +#define ADC_CHANNEL_17 ( 0x00000011U) + +#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CHANNEL_18 ( 0x00000012U) +#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macros ADCEx Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if the selected ADC channel is an internal channel + * VrefInt/TempSensor/Vbat + * Note: On STM32F0, availability of internal channel Vbat depends on + * devices lines. + * @param __CHANNEL__ ADC channel + * @retval None + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) \ + ) +#else +#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) \ + ) +#endif + +/** + * @brief Select the internal measurement path to be enabled/disabled + * corresponding to the selected ADC internal channel + * VrefInt/TempSensor/Vbat. + * Note: On STM32F0, availability of internal channel Vbat depends on + * devices lines. + * @param __CHANNEL__ ADC channel + * @retval Bit of register ADC_CCR + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ + (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ + )? \ + (ADC_CCR_TSEN) \ + : \ + ( \ + ( (__CHANNEL__) == ADC_CHANNEL_VREFINT \ + )? \ + (ADC_CCR_VREFEN) \ + : \ + (ADC_CCR_VBATEN) \ + ) \ + ) +#else +#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ + (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ + )? \ + (ADC_CCR_TSEN) \ + : \ + (ADC_CCR_VREFEN) \ + ) +#endif + + +#if defined (STM32F030x6) || defined (STM32F070x6) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#elif defined (STM32F042x6) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) + +#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#else +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) ) +#else +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) ) +#endif + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_ADC_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h new file mode 100644 index 0000000..66817b1 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_can.h @@ -0,0 +1,842 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_CAN_H +#define STM32F0xx_HAL_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#if defined (CAN) +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + This parameter mus be a number between Min_Data = 0 and Max_Data = 13. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + STM32F0xx devices don't support slave CAN instance (dual CAN). Therefore + this parameter is meaningless but it has been kept for compatibility accross + STM32 families. */ + +} CAN_FilterTypeDef; + +/** + * @brief CAN Tx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ + + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct __CAN_HandleTypeDef +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +} CAN_HandleTypeDef; + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number + * @{ + */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + + +#endif /* CAN */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_CAN_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h new file mode 100644 index 0000000..e471200 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CORTEX_H +#define __STM32F0xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ +/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *******************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h new file mode 100644 index 0000000..b2f6105 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h @@ -0,0 +1,178 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DEF +#define __STM32F0xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5*/ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h new file mode 100644 index 0000000..db71942 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_H +#define __STM32F0xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ +} DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ +#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ +#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ +#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ +#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ +#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ +#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ +#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ +#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ +#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ +#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ +#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ +#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ +#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ +#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ +#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ +#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ +#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ +#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ +#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ +#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ +#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ +#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ +#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ +#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ +#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ +#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ +#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ + +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ +#if defined (STM32F070xB) +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. + 0: Disabled, need to remap before use + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ + +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif + +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_DMA_RMP */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + + +/* Interrupt & Flag management */ + +/** + * @brief Enables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping + */ +#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +#endif /* SYSCFG_CFGR1_DMA_RMP */ + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32f0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* Input and Output operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#if defined(SYSCFG_CFGR1_DMA_RMP) + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ + ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ + ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ + ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) +#elif defined (STM32F070xB) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#else +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#endif + +#endif /* SYSCFG_CFGR1_DMA_RMP */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h new file mode 100644 index 0000000..185f833 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h @@ -0,0 +1,811 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_DMA_EX_H +#define __STM32F0xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ +#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#if !defined(STM32F030xC) +#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */ +#endif /* !defined(STM32F030xC) */ + +/****************** DMA1 remap bit field definition********************/ +/* DMA1 - Channel 1 */ +#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ +#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ +#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ +#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 2 */ +#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ +#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ +#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ +#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 3 */ +#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ +#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ +#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 4 */ +#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ +#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ +#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ +#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ +#endif /* !defined(STM32F030xC) */ + +/* DMA1 - Channel 5 */ +#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ +#if !defined(STM32F030xC) +#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ +#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if !defined(STM32F030xC) +/* DMA1 - Channel 6 */ +#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ +#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ +#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ +/* DMA1 - Channel 7 */ +#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */ +#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ +#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ +#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ + +/****************** DMA2 remap bit field definition********************/ +/* DMA2 - Channel 1 */ +#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ +#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ +/* DMA2 - Channel 2 */ +#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ +#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ +/* DMA2 - Channel 3 */ +#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ +#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ +#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ +#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ +/* DMA2 - Channel 4 */ +#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ +#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ +#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ +#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ +/* DMA2 - Channel 5 */ +#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */ +#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ +#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ +#endif /* !defined(STM32F030xC) */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ + ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ + ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) + +#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ + ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ + ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ + ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ + ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ + ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ + ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ + ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ + ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ + ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ + ((REQUEST) == HAL_DMA1_CH5_USART6_RX)) +#endif /* STM32F030xC */ + +/** + * @} + */ +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros + * @{ + */ +/* Interrupt & Flag management */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#elif defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ + (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ + (DMA1->IFCR = (__FLAG__))) + +#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */ +/** + * @brief Returns the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) + +/** + * @brief Returns the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) + +/** + * @brief Returns the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ + +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clears the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * Where x can be 1_5 to select the DMA Channel flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif + + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define __HAL_DMA1_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ + DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define __HAL_DMA2_REMAP(__REQUEST__) \ + do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ + DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \ + DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \ + }while(0) +#endif /* STM32F091xC || STM32F098xx */ + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h new file mode 100644 index 0000000..7dc4823 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h @@ -0,0 +1,375 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_EXTI_H +#define STM32F0xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ + +/** + * @brief HAL EXTI common Callback ID enumeration definition + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ + +#if defined (EXTI_IMR_MR16) +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#else +#define EXTI_LINE_16 (EXTI_RESERVED | 0x10u) +#endif /* EXTI_IMR_MR16 */ + +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ + +#if defined (EXTI_IMR_MR18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#else +#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) +#endif /* EXTI_IMR_MR18 */ + +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#if defined (EXTI_IMR_MR20) +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#else +#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) +#endif /* EXTI_IMR_MR20 */ + +#if defined (EXTI_IMR_MR21) +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */ +#else +#define EXTI_LINE_21 (EXTI_RESERVED | 0x15u) +#endif /* EXTI_IMR_MR21 */ + +#if defined (EXTI_IMR_MR22) +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */ +#else +#define EXTI_LINE_22 (EXTI_RESERVED | 0x16u) +#endif /* EXTI_IMR_MR22 */ + +#if defined (EXTI_IMR_MR23) +#define EXTI_LINE_23 (EXTI_DIRECT | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */ +#else +#define EXTI_LINE_23 (EXTI_RESERVED | 0x17u) +#endif /* EXTI_IMR_MR23 */ + +#define EXTI_LINE_24 (EXTI_RESERVED | 0x18u) + +#if defined (EXTI_IMR_MR25) +#define EXTI_LINE_25 (EXTI_CONFIG | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */ +#else +#define EXTI_LINE_25 (EXTI_RESERVED | 0x19u) +#endif /* EXTI_IMR_MR25 */ + +#if defined (EXTI_IMR_MR26) +#define EXTI_LINE_26 (EXTI_CONFIG | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */ +#else +#define EXTI_LINE_26 (EXTI_RESERVED | 0x1Au) +#endif /* EXTI_IMR_MR26 */ + +#if defined (EXTI_IMR_MR27) +#define EXTI_LINE_27 (EXTI_CONFIG | 0x1Bu) /*!< External interrupt line 27 Connected to the internal CEC wakeup event */ +#else +#define EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu) +#endif /* EXTI_IMR_MR27 */ + +#if defined (EXTI_IMR_MR28) +#define EXTI_LINE_28 (EXTI_CONFIG | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */ +#else +#define EXTI_LINE_28 (EXTI_RESERVED | 0x1Cu) +#endif /* EXTI_IMR_MR28 */ + +#define EXTI_LINE_29 (EXTI_RESERVED | 0x1Du) +#define EXTI_LINE_30 (EXTI_RESERVED | 0x1Eu) + +#if defined (EXTI_IMR_MR31) +#define EXTI_LINE_31 (EXTI_CONFIG | 0x1Fu) /*!< External interrupt line 31 Connected to the VDDIO2 supply comparator output */ +#else +#define EXTI_LINE_31 (EXTI_RESERVED | 0x1Fu) +#endif /* EXTI_IMR_MR31 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined (GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 32uL + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#elif defined (GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOF)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOF)) +#endif /* GPIOE */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h new file mode 100644 index 0000000..ecce5da --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_H +#define __STM32F0xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @} + */ + +/** @defgroup FLASH_Prefetch FLASH Prefetch + * @brief macros to handle FLASH Prefetch buffer + * @{ + */ +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32f0xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h new file mode 100644 index 0000000..a4c79d8 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_FLASH_EX_H +#define __STM32F0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1))/*||\ + ((LEVEL) == OB_RDP_LEVEL_2))*/ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) + +#if defined(FLASH_OBR_BOOT_SEL) +#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) +#endif /* FLASH_OBR_BOOT_SEL */ + + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) + +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY + This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and + @ref FLASHEx_OB_RAM_Parity_Check_Enable */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Page_Size FLASHEx Page Size + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ + || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) +#define FLASH_PAGE_SIZE 0x400U +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#define FLASH_PAGE_SIZE 0x800U +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ +/** + * @} + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES (0x00U) /*!
© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_H +#define __STM32F0xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32f0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h new file mode 100644 index 0000000..33b27e3 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h @@ -0,0 +1,800 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_GPIO_EX_H +#define __STM32F0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined (STM32F030x6) +/*------------------------- STM32F030x6---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x6 */ + +/*---------------------------------- STM32F030x8 -------------------------------------------*/ +#if defined (STM32F030x8) +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030x8 */ + +#if defined (STM32F031x6) || defined (STM32F038xx) +/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F031x6 || STM32F038xx */ + +#if defined (STM32F051x8) || defined (STM32F058xx) +/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F051x8/STM32F058xx */ + +#if defined (STM32F071xB) +/*--------------------------- STM32F071xB ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F071xB */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */ +#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */ +#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */ +#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ +#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */ +#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030xC) +/*--------------------------- STM32F030xC ----------------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */ +#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F030xC */ + +#if defined (STM32F072xB) || defined (STM32F078xx) +/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ +#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +/* AF 7 */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined (STM32F070xB) +/*---------------------------------- STM32F070xB ---------------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070xB */ + +#if defined (STM32F042x6) || defined (STM32F048xx) +/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */ +#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined (STM32F070x6) +/*--------------------------------------- STM32F070x6 ----------------------------------------*/ +/* AF 0 */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */ + +/* AF 1 */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */ + +/* AF 2 */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */ + +/* AF 3 */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */ + +/* AF 4 */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */ + +/* AF 5 */ +#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */ +#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */ +#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */ + +/* AF 6 */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U) + +#endif /* STM32F070x6 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index +* @{ + */ +#if defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif + +#if !defined(GPIOD) && defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if !defined(GPIOD) && !defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 5U) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h new file mode 100644 index 0000000..3df3fc0 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h @@ -0,0 +1,809 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_I2C_H +#define STM32F0xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f0xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F0xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h new file mode 100644 index 0000000..8679506 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h @@ -0,0 +1,174 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_I2C_EX_H +#define STM32F0xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#else +#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ +#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ +#endif +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, + uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, + uint32_t DigitalFilter); +#if defined(I2C_CR1_WUPEN) +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +#endif +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h new file mode 100644 index 0000000..e716606 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_H +#define __STM32F0xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * Warning: this Flag is not available on STM32F030x8 products + * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference + * voltage VREFINT is ready. + * Warning: this Flag is not available on STM32F030x8 products + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h new file mode 100644 index 0000000..a9ed6eb --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_PWR_EX_H +#define __STM32F0xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + This parameter can be a value of @ref PWREx_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVD_Mode */ +}PWR_PVDTypeDef; + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) +#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7) || \ + ((PIN) == PWR_WAKEUP_PIN8)) + +#elif defined(STM32F030xC) || defined (STM32F070xB) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN5) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#elif defined(STM32F042x6) || defined (STM32F048xx) +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) +#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) +#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) +#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN4) || \ + ((PIN) == PWR_WAKEUP_PIN6) || \ + ((PIN) == PWR_WAKEUP_PIN7)) + +#else +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) + + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) + +#endif + +/** + * @} + */ + +/** @defgroup PWREx_EXTI_Line PWREx EXTI Line + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + +#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ +/** + * @} + */ + +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/** + * @} + */ + +/** @defgroup PWREx_PVD_Mode PWREx PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +/** + * @} + */ +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +/** @defgroup PWREx_Flag PWREx Flag + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) + +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#else +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWREx Exported Macros + * @{ + */ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ + do{ \ + EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ + } while(0) + +/** + * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) + +/** + * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. + * @retval EXTI VDDIO2 Monitor Line Status. + */ +#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Clear the VDDIO2 Monitor EXTI flag. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) + + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +/* I/O operation functions ***************************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_Vddio2Monitor_IRQHandler(void); +void HAL_PWREx_Vddio2MonitorCallback(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/* Peripheral Control functions **********************************************/ +#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F072xB) || \ + defined (STM32F091xC) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); +#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F072xB) || */ + /* defined (STM32F091xC) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +void HAL_PWREx_EnableVddio2Monitor(void); +void HAL_PWREx_DisableVddio2Monitor(void); +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h new file mode 100644 index 0000000..4239c51 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h @@ -0,0 +1,1686 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_H +#define __STM32F0xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 + +/** + * @} + */ + + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1U) +#define CR2_REG_INDEX ((uint8_t)2U) +#define BDCR_REG_INDEX ((uint8_t)3U) +#define CSR_REG_INDEX ((uint8_t)4U) + +/* Bits position in in the CFGR register */ +#define RCC_CFGR_PLLMUL_BITNUMBER 18U +#define RCC_CFGR_HPRE_BITNUMBER 4U +#define RCC_CFGR_PPRE_BITNUMBER 8U +/* Flags in the CFGR2 register */ +#define RCC_CFGR2_PREDIV_BITNUMBER 0 +/* Flags in the CR register */ +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 +/* Flags in the CR2 register */ +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 +/* Flags in the BDCR register */ +#define RCC_BDCR_LSERDY_BitNumber 1 +/* Flags in the CSR register */ +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 +/* Flags in the HSITRIM register */ +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_HSI14TRIM_BIT_NUMBER 3 +#define RCC_FLAG_MASK ((uint8_t)0x1FU) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ + ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ + ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ + ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ + ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ + ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ + ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ + ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t HSI14State; /*!< The new state of the HSI14. + This parameter can be a value of @ref RCC_HSI14_Config */ + + uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_HSI48_SUPPORT) + uint32_t HSI48State; /*!< The new state of the HSI48. + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_HSI48_SUPPORT */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) +#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U) +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ +#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Config RCC HSI14 Config + * @{ + */ +#define RCC_HSI14_OFF (0x00000000U) +#define RCC_HSI14_ON RCC_CR2_HSI14ON +#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) + +#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00U) +#define RCC_HSI48_ON ((uint8_t)0x01U) + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ +#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 +#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 + +/** + * @} + */ + +/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor + * @{ + */ + +#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +/** + * @} + */ + + +/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK + +/** + * @} + */ +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL +#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14 + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ +#if defined(RCC_CIR_HSI48RDYF) +#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */ +#endif +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: CR2 register + * - 011: BDCR register + * - 0100: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber)) +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber)) +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber)) +/* Flags in the CR2 register */ +#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber)) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber)) +#if defined(RCC_CSR_V18PWRRSTF) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber)) +#endif +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber)) +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + + +/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) +/** + * @} + */ +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration + * @{ + */ + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14). + * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software + * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be + * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used. + * clock cycles. + */ +#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14). + * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI14 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON) + +/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC. + */ +#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS) + +/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI14 RC. + * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSI14CALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \ + MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER) +/** + * @} + */ + +/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) + +/** + * @} + */ + +/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ + } while(0U) + + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif +#if defined(RCC_CFGR_MCOPRE) +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#else + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + +#endif + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, + * the RTC cannot be used in STOP and STANDBY modes. + * @note The system must always be configured so as to get a PCLK frequency greater than or + * equal to the RTCCLK frequency for a proper operation of the RTC. + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable + @if STM32F042x6 + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F048xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F071xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F072xB + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F078xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F091xC + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @elseif STM32F098xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt + @endif + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready + @if STM32F038xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F042x6 + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F048xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F058xx + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F071xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F072xB + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F078xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @elseif STM32F091xC + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + @elseif STM32F098xx + * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \ + (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h new file mode 100644 index 0000000..e599e97 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h @@ -0,0 +1,2085 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_RCC_EX_H +#define __STM32F0xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#else + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI14)) + +#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV + +/** + * @} + */ + +/** @addtogroup RCC_Interrupt + * @{ + */ +#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source_Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 +/** + * @} + */ + +#else +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ + +#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#else +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 +#endif + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @addtogroup RCC_MCO_Clock_Source + * @{ + */ + +#if defined(RCC_CFGR_PLLNODIV) + +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#endif /* RCC_CFGR_PLLNODIV */ + +#if defined(RCC_CFGR_MCO_HSI48) + +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 + +#endif /* SRCC_CFGR_MCO_HSI48 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Private Constants -------------------------------------------------------------*/ +#if defined(CRS) +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL)) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(RCC_CFGR_MCOPRE) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ + ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) +#else + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) + +#endif /* RCC_CFGR_MCOPRE */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) +#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) +#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) +#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ + ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +#endif /* CRS */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t UsbClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F072xB || STM32F078xx */ + + +#if defined(STM32F091xC) || defined(STM32F098xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCC_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +}RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x3FU */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFFU */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +}RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USART3 (0x00040000U) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source + * @{ + */ +#define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ +#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ + +/** + * @} + */ + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK +#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE +#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI + +/** + * @} + */ + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK +#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE +#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI + +/** + * @} + */ + +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 +#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) + +#define RCC_MCODIV_1 (0x00000000U) +#define RCC_MCODIV_2 (0x10000000U) +#define RCC_MCODIV_4 (0x20000000U) +#define RCC_MCODIV_8 (0x30000000U) +#define RCC_MCODIV_16 (0x40000000U) +#define RCC_MCODIV_32 (0x50000000U) +#define RCC_MCODIV_64 (0x60000000U) +#define RCC_MCODIV_128 (0x70000000U) + +#else + +#define RCC_MCODIV_1 (0x00000000U) + +#endif /* RCC_CFGR_MCOPRE */ + +/** + * @} + */ + +/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration + * @{ + */ + +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE (0x00000000U) +#define RCC_CRS_TIMEOUT (0x00000001U) +#define RCC_CRS_SYNCOK (0x00000002U) +#define RCC_CRS_SYNCWARN (0x00000004U) +#define RCC_CRS_SYNCERR (0x00000008U) +#define RCC_CRS_SYNCMISS (0x00000010U) +#define RCC_CRS_TRIMOVF (0x00000020U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. + The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) +#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases peripheral reset. + * @{ + */ + +/** @brief Force or release AHB peripheral reset. + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) + +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @brief Force or release APB1 peripheral reset. + */ +#if defined(STM32F030x8) \ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) + +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) + +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) + +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) + +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) + +#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + + +/** @brief Force or release APB2 peripheral reset. + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) + +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) + +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) + +#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) + +#endif /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** @brief AHB Peripheral Clock Enable Disable Status + */ +#if defined(GPIOD) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) + +#endif /* GPIOD */ + +#if defined(GPIOE) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) + +#endif /* GPIOE */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(CRS) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) + +#endif /* CRS */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) +#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) +#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) +#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable + * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI48 can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI14. + * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software + * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be + * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. + * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator + * clock cycles. + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) + +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) + +/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HSI48_ON HSI48 enabled + * @arg @ref RCC_HSI48_OFF HSI48 disabled + */ +#define __HAL_RCC_GET_HSI48_STATE() \ + (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) + +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F070x6) || defined(STM32F070xB) + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSOURCE__ specifies the USB clock source. + * This parameter can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: +@if STM32F070xB +@elseif STM32F070x6 +@else + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock +@endif + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F072xB || STM32F078xx || */ + /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @brief Macro to configure the CEC clock. + * @param __CECCLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) + +/** @brief Macro to get the HDMI CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || defined(STM32F098xx) */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ + +#if defined(STM32F091xC) || defined(STM32F098xx) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ + RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag + * @{ + */ +/* Interrupt & Flag management */ + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0U) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0U) + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h new file mode 100644 index 0000000..0f57c73 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h @@ -0,0 +1,2125 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_TIM_H +#define STM32F0xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h new file mode 100644 index 0000000..23f6642 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_TIM_EX_H +#define STM32F0xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ +#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h new file mode 100644 index 0000000..2344a5d --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h @@ -0,0 +1,1595 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_UART_H +#define STM32F0xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck is the UART input clock */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#if defined(USART_CR1_UESM) +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#endif /* USART_CR1_UESM */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#if defined(USART_CR1_UESM) +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#endif /* USART_CR1_UESM */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#if defined(USART_CR1_UESM) +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* USART_CR1_UESM */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag +#if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + #endif + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) + + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +#if defined(USART_CR1_UESM) +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +#endif /* USART_CR1_UESM */ +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +#if defined(USART_CR1_UESM) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* USART_CR1_UESM */ + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32f0xx_hal_uart_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +#if defined(USART_CR2_LINEN) +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +#endif /* USART_CR2_LINEN */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +#if defined(USART_CR2_LINEN) +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +#endif /* USART_CR2_LINEN */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h new file mode 100644 index 0000000..127f13f --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h @@ -0,0 +1,591 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F0xx_HAL_UART_EX_H +#define STM32F0xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +#if defined(USART_CR1_UESM) +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#if defined(USART_CR1_M1) +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#endif /* USART_CR1_M1 */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#if defined (USART_CR1_M0) +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#else +#define UART_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long UART frame */ +#endif /* USART_CR1_M0 */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +#if defined(USART_CR1_UESM) +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +#if defined(USART_CR1_UESM) +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +#endif/* USART_CR1_UESM */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } while(0) +#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F070xB) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F091xC) || defined (STM32F098xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART7) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART8) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#elif defined(STM32F030xC) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) + +#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#if defined (USART_CR1_M1) +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +#else +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +#endif /* USART_CR1_M1 */ + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#if defined (USART_CR1_M1) +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) +#else +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) +#endif /* USART_CR1_M1 */ + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F0xx_HAL_UART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c new file mode 100644 index 0000000..94a482a --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c @@ -0,0 +1,514 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) HAL Initialization and de-initialization functions + (+) HAL Control functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32F0xx HAL Driver version number V1.7.5 + */ +#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F0xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK (0x00000FFFU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on HSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initialize common part of the HAL and stops the SysTick + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note ThiS function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the HAL revision + * @retval version 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c new file mode 100644 index 0000000..e64aa66 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc.c @@ -0,0 +1,2479 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on regular group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * Other functions (extended functions) are available in file + * "stm32f0xx_hal_adc_ex.c". + * + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + + (+) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (common for all channels) + + (+) ADC conversion of regular group. + + (+) External trigger (timer or EXTI) with configurable polarity + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) ADC calibration + + (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32F0, ADC clock frequency max is 14MHz (refer + to device datasheet). + Therefore, ADC clock prescaler must be configured in + function of ADC clock source frequency to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Two possible clock sources: synchronous clock derived from APB clock + or asynchronous clock derived from ADC dedicated HSI RC oscillator + 14MHz. + If asynchronous clock is selected, parameter "HSI14State" must be set either: + - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control + the HSI14 oscillator enable/disable (if not used to supply the main + system clock): feature used if ADC mode LowPowerAutoPowerOff is + enabled. + - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator + always enabled: can be used to supply the main system clock. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) + + HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) + (+++) RCC_OscInitTypeDef RCC_OscInitStructure; + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; + (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_DisableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_DeInit(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + + /* Fixed timeout values for ADC calibration, enable settling time, disable */ + /* settling time. */ + /* Values defined to be higher than worst cases: low clock frequency, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ + /* Unit: ms */ + #define ADC_ENABLE_TIMEOUT ( 2U) + #define ADC_DISABLE_TIMEOUT ( 2U) + #define ADC_STOP_CONVERSION_TIMEOUT ( 2U) + + /* Delay for ADC stabilization time. */ + /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ + /* Unit: us */ + #define ADC_STAB_DELAY_US ( 1U) + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US ( 10U) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); +static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * depending on both possible clock sources: APB clock of HSI clock. + * See commented example code below that can be copied and uncommented + * into HAL_ADC_MspInit(). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpCFGR1 = 0U; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + + /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ + /* at RCC top level depending on both possible clock sources: */ + /* APB clock or HSI clock. */ + /* Refer to header of this file for more details on clock enabling procedure*/ + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + /* - ADC voltage regulator enable */ + if (hadc->State == HAL_ADC_STATE_RESET) + { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + /* and if there is no conversion on going on regular group (ADC can be */ + /* enabled anyway, in case of call of this function to update a parameter */ + /* on the fly). */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && + (tmp_hal_status == HAL_OK) && + (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - ADC clock mode */ + /* - ADC clock prescaler */ + /* - ADC resolution */ + if (ADC_IS_ENABLE(hadc) == RESET) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES , + hadc->Init.Resolution ); + + /* Configuration of ADC clock mode: clock source AHB or HSI with */ + /* selectable prescaler */ + MODIFY_REG(hadc->Instance->CFGR2 , + ADC_CFGR2_CKMODE , + hadc->Init.ClockPrescaler ); + } + + /* Configuration of ADC: */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_AUTDLY | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG ); + + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCANDIR(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); + + /* Enable discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | + hadc->Init.ExternalTrigConvEdge ); + } + + /* Update ADC configuration register with previous settings */ + hadc->Instance->CFGR1 |= tmpCFGR1; + + /* Channel sampling time configuration */ + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function if parameter */ + /* "SamplingTimeCommon" has been set to a valid sampling time. */ + /* Otherwise, sampling time is set into ADC channel initialization */ + /* structure with parameter "SamplingTime" (obsolete). */ + if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core IP clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmpCFGR1'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) + == tmpCFGR1) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behaviour in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status != HAL_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + } + + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (tmp_hal_status != HAL_ERROR) + { + + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOSMP | ADC_IT_RDY ) ); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP; + + /* Reset register TR1 */ + hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | + ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | + ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | + ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | + ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable*/ + + /* Reset register CCR */ + ADC->CCR &= ~(ADC_CCR_ALL); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ + /* */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @brief Initializes the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of regular group. + * Interruptions enabled in this function: None. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmp_hal_status = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_EOC; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_Flag_EOC = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of each conversion */ + else /* ADC_EOC_SINGLE_CONV */ + { + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + else + { + tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + } + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until End of Conversion flag is raised */ + while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Clear end of conversion flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event. + * @param hadc ADC handle + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg ADC_AWD_EVENT: ADC Analog watchdog event + * @arg ADC_OVR_EVENT: ADC Overrun event + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart=0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + switch(EventType) + { + /* Analog watchdog (level out of window) event */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + + /* Clear ADC Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + break; + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Enables ADC, starts conversion of regular group with interruption. + * Interruptions enabled in this function: + * - EOC (end of conversion of regular group) or EOS (end of + * sequence of regular group) depending on ADC initialization + * parameter "EOCSelection" + * - overrun (if available) + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmp_hal_status = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable ADC end of conversion interrupt */ + /* Enable ADC overrun interrupt */ + switch(hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + break; + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @brief Stop ADC conversion of regular group, disable interruption of + * end-of-conversion, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enables ADC, starts conversion of regular group and transfers result + * through DMA. + * Interruptions enabled in this function: + * - DMA transfer complete + * - DMA half transfer + * - overrun + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval None + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmp_hal_status = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable + * ADC peripheral. + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ + hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* while DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ + /* in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Handles ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Conversion flag for regular group ========== */ + if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || + (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Note: into callback, to determine if conversion has been triggered */ + /* from EOC or EOS, possibility to use: */ + /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + } + + /* ========== Check Analog watchdog flags ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC Analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + + } + + + /* ========== Check Overrun flag ========== */ + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || + HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) + { + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + +} + + +/** + * @brief Conversion complete callback in non blocking mode + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non blocking mode + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non blocking mode + * (ADC conversion with interruption or transfer by DMA) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the regular + * group. + * @note In case of usage of internal measurement channels: + * VrefInt/Vbat/TempSensor. + * Sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values, parameters TS_vrefint, + * TS_vbat, TS_temp (values rough order: 5us to 17us). + * These internal paths can be be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into regular group, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_ChannelConfTypeDef". + * @param hadc ADC handle + * @param sConfig Structure of ADC channel for regular group. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t wait_loop_index = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_RANK(sConfig->Rank)); + + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + { + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC conversion sequencer. */ + if (sConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Set the channel selection register from the selected channel */ + hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); + + /* Channel sampling time configuration */ + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function with */ + /* parameter "SamplingTime" (obsolete) only if not already set into */ + /* ADC initialization structure with parameter "SamplingTimeCommon". */ + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + { + /* Modify sampling time if needed (not needed in case of reoccurrence */ + /* for several channels programmed consecutively into the sequencer) */ + if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); + } + } + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + /* If Channel_16 is selected, enable Temp. sensor measurement path. */ + /* If Channel_17 is selected, enable VREFINT measurement path. */ + /* If Channel_18 is selected, enable VBAT measurement path. */ + ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); + + /* If Temp. sensor is selected, wait for stabilization delay */ + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + } + } + } + else + { + /* Regular sequence configuration */ + /* Reset the channel selection register from the selected channel */ + hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths disable: If internal channel selected, */ + /* disable dedicated internal buffers and path. */ + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + /* If Channel_16 is selected, disable Temp. sensor measurement path. */ + /* If Channel_17 is selected, disable VREFINT measurement path. */ + /* If Channel_18 is selected, disable VBAT measurement path. */ + ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); + } + } + + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @brief Configures the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + + /* Verify if threshold is within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + + if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Analog watchdog channels */ + /* - Analog watchdog thresholds */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels. */ + /* - Set the Analog watchdog channel (is not used if watchdog */ + /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ + hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | + ADC_CFGR1_AWDEN | + ADC_CFGR1_AWDCH ); + + hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | + ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); + + /* Shift the offset in function of the selected ADC resolution: Thresholds*/ + /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + + /* Set the high and low thresholds */ + hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); + hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | + tmpAWDLowThresholdShifted ); + + /* Clear the ADC Analog watchdog flag (in case of left enabled by */ + /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ + /* or HAL_ADC_PollForEvent(). */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); + + /* Configure ADC Analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + } + /* If a conversion is on going on regular group, no update could be done */ + /* on neither of the AWD configuration structure parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @} + */ + + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the ADC state + * @note ADC state machine is managed by bitfields, ADC status must be + * compared with states bits. + * For example: + * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " + * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " + * @param hadc ADC handle + * @retval HAL state + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc ADC handle + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @note If low power mode AutoPowerOff is enabled, power-on/off phases are + * performed automatically by hardware. + * In this mode, this function is useless and must not be called because + * flag ADC_FLAG_RDY is not usable. + * Therefore, this function must be called under condition of + * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". + * @param hadc ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0U; + __IO uint32_t wait_loop_index = 0U; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (ADC_IS_ENABLE(hadc) == RESET) + { + /* Check if conditions to enable the ADC are fulfilled */ + if (ADC_ENABLING_CONDITIONS(hadc) == RESET) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) + { + wait_loop_index--; + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait for ADC effectively enabled */ + while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0U; + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if (ADC_IS_ENABLE(hadc) != RESET) + { + /* Check if conditions to disable the ADC are fulfilled */ + if (ADC_DISABLING_CONDITIONS(hadc) != RESET) + { + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) + { + if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief Stop ADC conversion. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc ADC handle + * @retval HAL status. + */ +static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + { + + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && + HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) + { + /* Stop conversions on regular group */ + hadc->Instance->CR |= ADC_CR_ADSTP; + } + + /* Wait for conversion effectively stopped */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) + { + if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c new file mode 100644 index 0000000..da68cbb --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_adc_ex.c @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Operation functions + * ++ Calibration (ADC automatic self-calibration) + * Other functions (generic functions) are available in file + * "stm32f0xx_hal_adc.c". + * + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32l1xx_hal_adc.c". + [..] + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADCEx Private Constants + * @{ + */ + +/* Fixed timeout values for ADC calibration, enable settling time, disable */ + /* settling time. */ + /* Values defined to be higher than worst cases: low clock frequency, */ + /* maximum prescaler. */ + /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ + /* prescaler 4. */ + /* Unit: ms */ + #define ADC_DISABLE_TIMEOUT 2 + #define ADC_CALIBRATION_TIMEOUT 2U +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Perform the ADC calibration. +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @note Calibration factor can be read after calibration, using function + * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tickstart = 0U; + uint32_t backup_setting_adc_dma_transfer = 0; /* Note: Variable not declared as volatile because register read is already declared as volatile */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + if (ADC_IS_ENABLE(hadc) == RESET) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 serie: Calibration factor is */ + /* available in data register and also transfered by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + + /* Start ADC calibration */ + hadc->Instance->CR |= ADC_CR_ADCAL; + + tickstart = HAL_GetTick(); + + /* Wait for calibration completion */ + while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) + { + if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + /* Restore ADC DMA transfer request after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c new file mode 100644 index 0000000..c2fe2fe --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_can.c @@ -0,0 +1,2432 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example @ref HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() + or @ref HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#if defined(CAN) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callabck is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + + /* CAN is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + /* Select the Tx mailbox */ + if (TxMailbox == CAN_TX_MAILBOX0) + { + transmitmailbox = 0U; + } + else if (TxMailbox == CAN_TX_MAILBOX1) + { + transmitmailbox = 1U; + } + else /* (TxMailbox == CAN_TX_MAILBOX2) */ + { + transmitmailbox = 2U; + } + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 mesage pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c new file mode 100644 index 0000000..cbe3f5b --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M0 exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32f0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0 based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK) functionalities. + + +@endverbatim + * @{ + */ + + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c new file mode 100644 index 0000000..b7f91a4 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c @@ -0,0 +1,901 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialize DmaBaseAddress and ChannelIndex parameters used + by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + +/* Get DMA Base Address */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete, & transfer error interrupts */ + /* Half transfer interrupt is optional: enable it only if associated callback is available */ + if(NULL != hdma->XferHalfCpltCallback ) + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + } + else + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + } + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Abort the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + { + if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + + /* DMA peripheral state is not updated in Half Transfer */ + /* State is updated only in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete & transfer error interrupts */ + /* if the DMA mode is not CIRCULAR */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management ***************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Then, disable all DMA interrupts */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameters. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief set the DMA base address and channel index depending on DMA instance + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c new file mode 100644 index 0000000..1adb8f7 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c new file mode 100644 index 0000000..94ad6e9 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c @@ -0,0 +1,694 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F0xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programming (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0U; + uint8_t nbiterations = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + /* In case of error, stop programming procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + flags |= FLASH_FLAG_PGERR; + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c new file mode 100644 index 0000000..7c30632 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c @@ -0,0 +1,984 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F0xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT 8U +#define FLASH_POSITION_OB_USERDATA0_BIT 16U +#define FLASH_POSITION_OB_USERDATA1_BIT 24U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(void); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) @ref HAL_FLASHEx_Erase: return only when erase has been done + (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0U; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#elif defined(OB_WRP_PAGES0TO31MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#elif defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); +#if defined(FLASH_OBR_BOOT_SEL) + assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); + assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); +#endif /* FLASH_OBR_BOOT_SEL */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_OBR_BOOT_SEL) + OB->USER = UserConfig; +#else + OB->USER = (UserConfig | 0x88U); +#endif + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t tmp_reg; + + /* Read RDP level bits */ + tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)); + + if (tmp_reg == 0U) + { + return OB_RDP_LEVEL_0; + } + else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2) + { + return OB_RDP_LEVEL_2; + } + else + { + return OB_RDP_LEVEL_1; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c new file mode 100644 index 0000000..2c43ff5 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c @@ -0,0 +1,543 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also + recommended to use it to unconfigure pin which was used as an external interrupt + or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG + registers. + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines + * @{ + */ +#define GPIO_MODE (0x00000003U) +#define EXTI_MODE (0x10000000U) +#define GPIO_MODE_IT (0x00010000U) +#define GPIO_MODE_EVT (0x00020000U) +#define RISING_EDGE (0x00100000U) +#define FALLING_EDGE (0x00200000U) +#define GPIO_OUTPUT_TYPE (0x00000010U) + +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); + GPIOx->PUPDR = temp; + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + SYSCFG->EXTICR[position >> 2u] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (4u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; + } + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin specifies the port bits to be locked. +* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c new file mode 100644 index 0000000..3523403 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c @@ -0,0 +1,6646 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_ERROR; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c new file mode 100644 index 0000000..a1e3f60 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c @@ -0,0 +1,333 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F0xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + (+) Configure Wake Up Feature + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#if defined(I2C_CR1_WUPEN) + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c new file mode 100644 index 0000000..558d869 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c @@ -0,0 +1,454 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization function + * + Peripheral Control function + * + @verbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + PWR->CR |= (uint32_t)PWR_CR_DBP; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers when present). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. + (++)WakeUp Pin 1 on PA.00. + (++)WakeUp Pin 2 on PC.13. + (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) + (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) + (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) + (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) + (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + when programmed in wakeup mode (the peripheral must be + programmed in wakeup mode and the corresponding interrupt vector + must be enabled in the NVIC) + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. + The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers and Standby circuitry. + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. +@endverbatim + * @{ + */ + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be value of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be values of : + * @ref PWREx_WakeUp_Pins + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator Specifies the regulator state in SLEEP mode. + * On STM32F0 devices, this parameter is a dummy value and it is ignored + * as regulator can't be modified in this mode. Parameter is kept for platform + * compatibility. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC alternate function pins if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pins if enabled. + * STM32F0x8 devices, the Stop mode is available, but it is + * aningless to distinguish between voltage regulator in Low power + * mode and voltage regulator in Run mode because the regulator + * not used and the core is supplied directly from an external source. + * Consequently, the Standby mode is not available on those devices. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= (uint32_t)PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c new file mode 100644 index 0000000..c14370b --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c @@ -0,0 +1,274 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWREx HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @brief Extended Peripheral Control functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. + (+) The PVD is stopped in Standby mode. + -@- PVD is not available on STM32F030x4/x6/x8 + + *** VDDIO2 Monitor Configuration *** + ==================================== + [..] + (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it + to VREFInt Voltage + (+) This monitor is internally connected to the EXTI line31 + and can generate an interrupt if enabled. This is done through + HAL_PWREx_EnableVddio2Monitor() function. + -@- VDDIO2 is available on STM32F07x/09x/04x + +@endverbatim + * @{ + */ + +#if defined (STM32F031x6) || defined (STM32F051x8) || \ + defined (STM32F071xB) || defined (STM32F091xC) || \ + defined (STM32F042x6) || defined (STM32F072xB) +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + PWR->CR |= (uint32_t)PWR_CR_PVDE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + PWR->CR &= ~((uint32_t)PWR_CR_PVDE); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ + /* defined (STM32F071xB) || defined (STM32F091xC) || */ + /* defined (STM32F042x6) || defined (STM32F072xB) */ + +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +/** + * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. + * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, + an interrupt is generated Irq line 1. + NVIS has to be enable by user. + * @retval None + */ +void HAL_PWREx_EnableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); +} + +/** + * @brief Disable the Vddio2 Monitor. + * @retval None + */ +void HAL_PWREx_DisableVddio2Monitor(void) +{ + __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); + __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); + +} + +/** + * @brief This function handles the PWR Vddio2 monitor interrupt request. + * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). + * @retval None + */ +void HAL_PWREx_Vddio2Monitor_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) + { + /* PWR Vddio2 monitor interrupt user callback */ + HAL_PWREx_Vddio2MonitorCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR Vddio2 Monitor interrupt callback + * @retval None + */ +__weak void HAL_PWREx_Vddio2MonitorCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file + */ +} + +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c new file mode 100644 index 0000000..fbe2bf5 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c @@ -0,0 +1,1365 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, + AHB and APB1). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + The HSI clock can be used also to clock the USART and I2C peripherals. + + (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock + the ADC peripheral. + + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 48 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the TIM, I2C and USART + peripherals (up to 48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. + + (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * - All interrupt and reset flags cleared + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO); + + /* Wait till HSI as SYSCLK status is enabled */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable for HSI as system clock source */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLLRDY is cleared */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + + /* Reset CFGR3 register */ + CLEAR_REG(RCC->CFGR3); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + /* Clear all reset flags */ + __HAL_RCC_CLEAR_RESET_FLAGS(); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + uint32_t pll_config2; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(RCC_HSI48_SUPPORT) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Check the HSI48 State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } +#endif /* RCC_HSI48_SUPPORT */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + pll_config2 = RCC->CFGR2; + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) || + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(RCC_CFGR_SWS_HSI48) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* RCC_CFGR_SWS_HSI48 */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + @if STM32F042x6 + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F048xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F071xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F072xB + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F078xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F091xC + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elseif STM32F098xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F030xC + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F031x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F038xx + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070x6 + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @elif STM32F070xB + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + @endif + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @retval None + */ +#else +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +#endif +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based + * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the + * PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } +#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } +#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */ + else + { +#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); +#endif + } + sysclockfreq = pllclk; + break; + } +#if defined(RCC_CFGR_SWS_HSI48) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + { + sysclockfreq = HSI48_VALUE; + break; + } +#endif /* RCC_CFGR_SWS_HSI48 */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif /* RCC_HSI48_SUPPORT */ + + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI14 configuration -----------------------------------------------*/ + if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) + { + RCC_OscInitStruct->HSI14State = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSI14State = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER); + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration if any-----------------------------------------*/ + RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = __HAL_FLASH_GET_LATENCY(); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c new file mode 100644 index 0000000..7771bce --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c @@ -0,0 +1,964 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(CRS) +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/* Bit position in register */ +#define CRS_CFGR_FELIM_BITNUMBER 16 +#define CRS_CR_TRIM_BITNUMBER 8 +#define CRS_ISR_FECAP_BITNUMBER 16 +/** + * @} + */ +#endif /* CRS */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t temp_reg = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + /*----------------------------- USART3 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* STM32F091xC || STM32F098xx */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks + * (USART, RTC, I2C, CEC and USB). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + /* Common part first */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + /* Get the RTC configuration --------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USART1 clock configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + /* Get the USB clock source ---------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + @if STM32F042x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F048xx + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F051x8 + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F058xx + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F070x6 + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F070xB + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + @endif + @if STM32F071xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F072xB + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F078xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F091xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F098xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* frequency == 0 : means that no available frequency for the peripheral */ + uint32_t frequency = 0U; + + uint32_t srcclk = 0U; +#if defined(USB) + uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U; +#endif /* USB */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 32U; + } + break; + } + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + /* Check if USART1 clock selection is PCLK1 */ + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART1 clock selection is HSI */ + else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART1 clock selection is SYSCLK */ + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART1 clock selection is LSE */ + else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#if defined(RCC_CFGR3_USART2SW) + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + /* Check if USART2 clock selection is PCLK1 */ + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART2 clock selection is HSI */ + else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART2 clock selection is SYSCLK */ + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART2 clock selection is LSE */ + else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + case RCC_PERIPHCLK_USART3: + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + /* Check if USART3 clock selection is PCLK1 */ + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART3 clock selection is HSI */ + else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART3 clock selection is SYSCLK */ + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART3 clock selection is LSE */ + else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART3SW */ + case RCC_PERIPHCLK_I2C1: + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Check if HSI is ready and if I2C1 clock selection is HSI */ + if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C1 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#if defined(USB) + case RCC_PERIPHCLK_USB: + { + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + /* Check if PLL is ready and if USB clock selection is PLL */ + if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ + frequency = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(RCC_CR2_HSI48ON) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ + frequency = (HSI48_VALUE / predivfactor) * pllmull; + } +#endif /* RCC_CR2_HSI48ON */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) + /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ + frequency = (HSI_VALUE / predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */ + frequency = (HSI_VALUE >> 1U) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ + } + } +#if defined(RCC_CR2_HSI48ON) + /* Check if HSI48 is ready and if USB clock selection is HSI48 */ + else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) + { + frequency = HSI48_VALUE; + } +#endif /* RCC_CR2_HSI48ON */ + break; + } +#endif /* USB */ +#if defined(CEC) + case RCC_PERIPHCLK_CEC: + { + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + /* Check if HSI is ready and if CEC clock selection is HSI */ + if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if LSE is ready and if CEC clock selection is LSE */ + else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* CEC */ + default: + { + break; + } + } + return(frequency); +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function @ref HAL_RCCEx_CRSConfig which + (+++) Reset CRS registers to their default values. + (+++) Configure CRS registers with synchronization configuration + (+++) Enable automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function @ref HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + @ref HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (RCC_IRQn/RCC_IRQHandler) + (++) Call function @ref HAL_RCCEx_CRSConfig() + (++) Enable RCC_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (@ref __HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) @ref HAL_RCCEx_CRS_SyncOkCallback() + (+++) @ref HAL_RCCEx_CRS_SyncWarnCallback() + (+++) @ref HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) @ref HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function @ref HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling @ref HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the timeout +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart = 0U; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while(RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) + { + if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) + { + crserror |= RCC_CRS_SYNCERR; + } + if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) + { + crserror |= RCC_CRS_SYNCMISS; + } + if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c new file mode 100644 index 0000000..4ecd84b --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c @@ -0,0 +1,7433 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + } + break; + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c new file mode 100644 index 0000000..fe9102a --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c @@ -0,0 +1,2308 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM14, the parameter can have the following values: + * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock + * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c new file mode 100644 index 0000000..d9a0b1d --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c @@ -0,0 +1,4102 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register, + - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/ +#if defined (USART_CR2_LINEN) + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +#else + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); +#endif /* USART_CR2_LINEN */ +#if defined (USART_CR3_SCEN) +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); +#endif /* USART_CR3_IREN */ +#else +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL); +#endif /* USART_CR3_IREN*/ +#endif /* USART_CR3_SCEN */ + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register, + - SCEN (if Smartcard is supported) and IREN (if IrDA is supported) bits in the USART_CR3 register.*/ +#if defined (USART_CR2_LINEN) + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +#else + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); +#endif /* USART_CR2_LINEN */ +#if defined (USART_CR3_SCEN) +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); +#else + CLEAR_BIT(huart->Instance->CR3, USART_CR3_SCEN); +#endif /* USART_CR3_IREN */ +#else +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, USART_CR3_IREN); +#endif /* USART_CR3_IREN */ +#endif /* USART_CR3_SCEN */ + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +#if defined(USART_CR2_LINEN) +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN(if Smartcard is supported) and IREN(if IrDA is supported) bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +#if defined (USART_CR3_SCEN) +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); +#endif /* USART_CR3_IREN */ +#else +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL); +#endif /* USART_CR3_IREN*/ +#endif /* USART_CR3_SCEN */ + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} +#endif /* USART_CR2_LINEN */ + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register, + - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */ +#if defined (USART_CR2_LINEN) + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +#else + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); +#endif /* USART_CR2_LINEN */ +#if defined (USART_CR3_SCEN) +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); +#endif /* USART_CR3_IREN */ +#else +#if defined (USART_CR3_IREN) + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); +#else + CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL); +#endif /* USART_CR3_IREN */ +#endif /* USART_CR3_SCEN */ + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + +#if defined(USART_CR1_UESM) + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#endif /* USART_CR1_UESM */ + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return(UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return(UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + __HAL_LOCK(huart); + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + &&((isrflags & USART_ISR_IDLE) != 0U) + &&((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ( (nb_remaining_rx_data > 0U) + &&(nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ( (huart->RxXferCount > 0U) + &&(nb_rx_data > 0U) ) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif + } + return; + } + } +#if defined(USART_CR1_UESM) + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +#endif /* USART_CR1_UESM */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +#if defined(USART_CR2_LINEN) +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} +#endif /* USART_CR2_LINEN */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_UESM) + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#endif /* USART_CR1_UESM */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + tmpreg |= huart->Init.OneBitSampling; + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Handle UART Communication Timeout. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize/2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c new file mode 100644 index 0000000..19e5888 --- /dev/null +++ b/DBW_V2/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c @@ -0,0 +1,802 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +#if defined(USART_CR1_UESM) +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + +#if defined(USART_CR1_UESM) + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + +#endif +@endverbatim + * @{ + */ + +#if defined(USART_CR1_UESM) +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#endif /* USART_CR1_UESM */ + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. +#if defined(USART_CR1_UESM) + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality +#endif + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +#if defined(USART_CR1_UESM) +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR1_UESM */ +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data copy from RDR will be + handled by DMA from a uint16_t frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ +#if defined(USART_CR1_UESM) + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} +#endif /* USART_CR1_UESM */ + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/DBW_V2/STM32F072C8TX_FLASH.ld b/DBW_V2/STM32F072C8TX_FLASH.ld new file mode 100644 index 0000000..b80ca77 --- /dev/null +++ b/DBW_V2/STM32F072C8TX_FLASH.ld @@ -0,0 +1,210 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for STM32F072C8Tx Device from stm32f0 series +** 64Kbytes FLASH +** 16Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2021 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200 ; /* required amount of heap */ +_Min_Stack_Size = 0x400 ; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 56K +CONST (rx) : ORIGIN = 0x0800E000, LENGTH = 4K +CONFIG(rx) : ORIGIN = 0x0800F000, LENGTH = 4K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /*Config section*/ + .config : ALIGN(4) + { + *(.config .config.*) + } >CONFIG + + /*>CONFIG AT> CONST */ + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/DBW_V2/TunerStudioAppDebug.txt b/DBW_V2/TunerStudioAppDebug.txt new file mode 100644 index 0000000..701440e --- /dev/null +++ b/DBW_V2/TunerStudioAppDebug.txt @@ -0,0 +1,43335 @@ +Starting on DESKTOP-MVON5FO +TunerStudio 3.1.08 started on Sun Feb 27 18:50:09 CET 2022 +JRE 1.8.0_66, Windows 10 10.0, x86 +java.library.path=./lib +TunerStudioMS.jar +Look:Metal, ClassName:'javax.swing.plaf.metal.MetalLookAndFeel' +Look:Nimbus, ClassName:'javax.swing.plaf.nimbus.NimbusLookAndFeel' +Look:CDE/Motif, ClassName:'com.sun.java.swing.plaf.motif.MotifLookAndFeel' +Look:Windows, ClassName:'com.sun.java.swing.plaf.windows.WindowsLookAndFeel' +Look:Windows Classic, ClassName:'com.sun.java.swing.plaf.windows.WindowsClassicLookAndFeel' +Look:Night Shade, ClassName:'de.muntjak.tinylookandfeel.TinyLookAndFeel' +Setting Look & Feel to:javax.swing.plaf.metal.MetalLookAndFeel +ScrollBar.width +2/27/22 6:50:09 PM :Debug: no update:defaultFont +2/27/22 6:50:09 PM :Info: Initializing File Dialogs. +2/27/22 6:50:09 PM :Debug: hid: 548.822 +2/27/22 6:50:10 PM :Info: Loading Language Content. +2/27/22 6:50:12 PM :Debug: Command Non-VolatileBytes for F resolved to: x46 F +2/27/22 6:50:12 PM :Debug: Command Non-VolatileBytes for I resolved to: x49 I +2/27/22 6:50:12 PM :Debug: Command Non-VolatileBytes for f resolved to: x66 f +2/27/22 6:50:12 PM :Info: Initializing Help. +2/27/22 6:50:12 PM :Info: Initializing Edition Features. +2/27/22 6:50:12 PM :Info: Initializing App Events. +2/27/22 6:50:12 PM :Debug: App Name:TunerStudio, appEdition:MS Lite! +2/27/22 6:50:12 PM :Debug: Dummy Function Factory Created. +2/27/22 6:50:12 PM :Info: Initializing User Interface +2/27/22 6:50:14 PM :Info: Loading Font list. +2/27/22 6:50:14 PM :Debug: Time to retreive font name list: 16 ms. +2/27/22 6:50:14 PM :Info: +2/27/22 6:50:14 PM :Info: Initializing UI Components. +2/27/22 6:50:14 PM :Info: Ready +MSmain: No check, last update check=Sun Feb 27 18:14:34 CET 2022 +2/27/22 6:50:16 PM :Info: Opening Project ... +2/27/22 6:50:16 PM :Debug: Opening project: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021 +2/27/22 6:50:16 PM :Debug: Reading translation file as plain text +2/27/22 6:50:16 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 6:50:16 PM :Debug: Filtered ConfigurationOptionGroup in 2ms. +2/27/22 6:50:16 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 6:50:16 PM :Info: Read file canPcVariables.ini: 1.4379ms +2/27/22 6:50:16 PM :Info: Filtered ini: 0.0474ms +2/27/22 6:50:16 PM :Info: No iniVersion defined +2/27/22 6:50:16 PM :Info: Loading Trigger Wheels +2/27/22 6:50:16 PM :Info: Loaded All known ini sections +2/27/22 6:50:16 PM :Info: Parsed and validated ini "canPcVariables.ini" in : 13ms. +2/27/22 6:50:16 PM :Info: Read file mainController.ini: 0.8097ms +2/27/22 6:50:16 PM :Info: Filtered ini: 0.1017ms +2/27/22 6:50:16 PM :Info: No iniVersion defined +2/27/22 6:50:16 PM :Debug: ini signature: speeduino DBW 2.0.0 +2/27/22 6:50:16 PM :Info: Set Write Blocks on = true +2/27/22 6:50:16 PM :Info: Loading Trigger Wheels +2/27/22 6:50:16 PM :Info: Loading Depricated ini section [UserDefined], use [UiDialogs] +2/27/22 6:50:16 PM :Info: Loaded All known ini sections +2/27/22 6:50:16 PM :Info: Parsed and validated ini "mainController.ini" in : 10ms. +2/27/22 6:50:16 PM :Info: Not Loading default Tools because non are defined for signature: speeduino DBW 2.0.0 +2/27/22 6:50:16 PM :Info: Time to load primary config: 49.0774ms. used cached config: false +SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder". +SLF4J: Defaulting to no-operation (NOP) logger implementation +SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details. +2/27/22 6:50:16 PM :Debug: set baud to 115200 +2/27/22 6:50:16 PM :Debug: Adding Configuration: DBW_code_26.10.2021 +2/27/22 6:50:16 PM :Debug: controllerOnline = 0.0 +2/27/22 6:50:16 PM :Info: No secl OutputChannel, och sync monitor disabled. +2/27/22 6:50:16 PM :Debug: Fill Constants: 1 +2/27/22 6:50:16 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 6:50:16 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 6:50:16 PM :Info: dirtyData.size(): 0 +2/27/22 6:50:16 PM :Info: dirtyData.size(): 0 +2/27/22 6:50:16 PM :Debug: Flush lasted: 82ms. +2/27/22 6:50:16 PM :Info: dirtyData.size(): 0 +2/27/22 6:50:16 PM :Info: dirtyData.size(): 0 +2/27/22 6:50:16 PM :Debug: Flush lasted: 78ms. +2/27/22 6:50:16 PM :Debug: Skip Burn, last write page: -2 +2/27/22 6:50:16 PM :Info: !!! Loaded config in 287 +2/27/22 6:50:17 PM :Info: !!! Activated Project 441 +2/27/22 6:50:17 PM :Info: Opening Gauge Cluster.. +2/27/22 6:50:17 PM :Debug: High Speed Paint: true +2/27/22 6:50:17 PM :Info: +2/27/22 6:50:17 PM :Info: Com Thread created: COMM Thread53583.00833055951 +2/27/22 6:50:17 PM :Info: endModalBlock called, but Root Pane is not a ProgressPane. +2/27/22 6:50:17 PM :Debug: !!! Opened Dash 671 +2/27/22 6:50:17 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread53583.00833055951 +2/27/22 6:50:17 PM :Info: DBW_code_26.10.2021 Ready +2/27/22 6:50:17 PM :Debug: Tuning View Files loaded in 0.167ms. +2/27/22 6:50:17 PM :Info: Comm Read Thread Change! Old Thread:null, new Thread:COMM Thread53583.00833055951 +2/27/22 6:50:17 PM :Info: No Persistor set, not activating persisted triggers. +MSad: No check, last update check=Sun Feb 27 18:14:37 CET 2022 +2/27/22 6:50:22 PM :Debug: goOffline Starting, Time:0 +2/27/22 6:50:22 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 6:50:22 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 6:50:22 PM :Debug: goOffline closed port, Time:0 +2/27/22 6:50:22 PM :Debug: goOffline Starting, Time:0 +2/27/22 6:50:22 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 6:50:22 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 6:50:22 PM :Debug: goOffline closed port, Time:1 +2/27/22 6:50:22 PM :Debug: set baud to 115200 +2/27/22 6:50:22 PM :Debug: set baud to 115200 +2/27/22 6:50:22 PM :Debug: goOffline comm thread stopped, Time:502 +2/27/22 6:50:22 PM :Debug: No Remaining Queue Write instructions +2/27/22 6:50:23 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread53583.00833055951 +2/27/22 6:50:23 PM :Debug: goOffline comm thread stopped, Time:993 +2/27/22 6:50:23 PM :Debug: No Remaining Queue Write instructions +2/27/22 6:50:23 PM :Debug: set baud to 115200 +2/27/22 6:50:23 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:50:23 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread53583.00833055951, new Thread:Thread-23 +Feb 27, 2022 6:50:24 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:50:25 PM :Debug: set baud to 115200 +2/27/22 6:50:25 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:50:25 PM :Info: Comm Read Thread Change! Old Thread:Thread-23, new Thread:Thread-26 +Feb 27, 2022 6:50:26 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:50:39 PM :Debug: set baud to 115200 +2/27/22 6:50:39 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:50:39 PM :Info: Comm Read Thread Change! Old Thread:Thread-26, new Thread:Thread-29 +Feb 27, 2022 6:50:40 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:50:40 PM :Debug: set baud to 115200 +2/27/22 6:50:40 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:50:40 PM :Info: Comm Read Thread Change! Old Thread:Thread-29, new Thread:Thread-32 +Feb 27, 2022 6:50:41 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:30 PM :Debug: set baud to 115200 +2/27/22 6:51:30 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:30 PM :Info: Comm Read Thread Change! Old Thread:Thread-32, new Thread:Thread-35 +Feb 27, 2022 6:51:30 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:34 PM :Debug: set baud to 150000 +2/27/22 6:51:34 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:34 PM :Info: Comm Read Thread Change! Old Thread:Thread-35, new Thread:Thread-38 +Feb 27, 2022 6:51:34 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:39 PM :Debug: set baud to 230400 +2/27/22 6:51:39 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:39 PM :Info: Comm Read Thread Change! Old Thread:Thread-38, new Thread:Thread-41 +Feb 27, 2022 6:51:39 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:44 PM :Debug: set baud to 250000 +2/27/22 6:51:44 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:44 PM :Info: Comm Read Thread Change! Old Thread:Thread-41, new Thread:Thread-44 +Feb 27, 2022 6:51:44 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:47 PM :Debug: set baud to 460800 +2/27/22 6:51:47 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:47 PM :Info: Comm Read Thread Change! Old Thread:Thread-44, new Thread:Thread-47 +Feb 27, 2022 6:51:47 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:50 PM :Debug: set baud to 500000 +2/27/22 6:51:50 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:50 PM :Info: Comm Read Thread Change! Old Thread:Thread-47, new Thread:Thread-50 +Feb 27, 2022 6:51:51 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:57 PM :Debug: set baud to 9600 +2/27/22 6:51:57 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:51:57 PM :Info: Comm Read Thread Change! Old Thread:Thread-50, new Thread:Thread-53 +Feb 27, 2022 6:51:57 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:51:59 PM :Debug: set baud to 14400 +2/27/22 6:51:59 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:00 PM :Info: Comm Read Thread Change! Old Thread:Thread-53, new Thread:Thread-56 +Feb 27, 2022 6:52:00 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:03 PM :Debug: set baud to 19200 +2/27/22 6:52:03 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:03 PM :Info: Comm Read Thread Change! Old Thread:Thread-56, new Thread:Thread-59 +Feb 27, 2022 6:52:03 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:06 PM :Debug: set baud to 28800 +2/27/22 6:52:06 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:06 PM :Info: Comm Read Thread Change! Old Thread:Thread-59, new Thread:Thread-62 +Feb 27, 2022 6:52:06 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:11 PM :Debug: set baud to 57600 +2/27/22 6:52:11 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:11 PM :Info: Comm Read Thread Change! Old Thread:Thread-62, new Thread:Thread-65 +Feb 27, 2022 6:52:12 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:14 PM :Debug: set baud to 115200 +2/27/22 6:52:14 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:14 PM :Info: Comm Read Thread Change! Old Thread:Thread-65, new Thread:Thread-68 +Feb 27, 2022 6:52:15 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:16 PM :Debug: set baud to 115200 +2/27/22 6:52:16 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:16 PM :Info: Comm Read Thread Change! Old Thread:Thread-68, new Thread:Thread-71 +Feb 27, 2022 6:52:17 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:22 PM :Debug: set baud to 115200 +2/27/22 6:52:22 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:23 PM :Info: Comm Read Thread Change! Old Thread:Thread-71, new Thread:Thread-74 +Feb 27, 2022 6:52:23 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:24 PM :Debug: set baud to 115200 +2/27/22 6:52:24 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:52:24 PM :Info: Comm Read Thread Change! Old Thread:Thread-74, new Thread:Thread-77 +Feb 27, 2022 6:52:25 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:44 PM :Debug: set baud to 115200 +2/27/22 6:52:44 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 6:52:44 PM y.t a +SEVERE: null +F.l: Unable to open port: COM5 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:44 PM :Debug: set baud to 115200 +2/27/22 6:52:44 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 6:52:44 PM y.t a +SEVERE: null +F.l: Unable to open port: COM5 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:49 PM :Debug: set baud to 115200 +2/27/22 6:52:49 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 6:52:49 PM y.t a +SEVERE: null +F.l: Unable to open port: COM6 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:52:50 PM :Debug: set baud to 115200 +2/27/22 6:52:50 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 6:52:50 PM y.t a +SEVERE: null +F.l: Unable to open port: COM6 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:22 PM :Debug: set baud to 115200 +2/27/22 6:53:22 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:22 PM :Info: Comm Read Thread Change! Old Thread:Thread-77, new Thread:Thread-84 +Feb 27, 2022 6:53:22 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:23 PM :Debug: set baud to 115200 +2/27/22 6:53:23 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:23 PM :Info: Comm Read Thread Change! Old Thread:Thread-84, new Thread:Thread-87 +Feb 27, 2022 6:53:24 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:33 PM :Debug: set baud to 115200 +2/27/22 6:53:33 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:33 PM :Info: Comm Read Thread Change! Old Thread:Thread-87, new Thread:Thread-90 +Feb 27, 2022 6:53:34 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:35 PM :Debug: set baud to 115200 +2/27/22 6:53:35 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:35 PM :Info: Comm Read Thread Change! Old Thread:Thread-90, new Thread:Thread-93 +Feb 27, 2022 6:53:35 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:49 PM :Debug: set baud to 115200 +2/27/22 6:53:49 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:49 PM :Info: Comm Read Thread Change! Old Thread:Thread-93, new Thread:Thread-96 +Feb 27, 2022 6:53:50 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:53:55 PM :Debug: set baud to 115200 +2/27/22 6:53:55 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:53:55 PM :Info: Comm Read Thread Change! Old Thread:Thread-96, new Thread:Thread-99 +2/27/22 6:53:56 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xFF .. +2/27/22 6:54:02 PM :Info: Com Thread created: COMM Thread26972.84513724123 +2/27/22 6:54:02 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread26972.84513724123 +2/27/22 6:54:03 PM :Info: Comm Read Thread Change! Old Thread:Thread-99, new Thread:COMM Thread26972.84513724123 +2/27/22 6:54:04 PM :Debug: set baud to 115200 +2/27/22 6:54:04 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:54:04 PM :Warning: COM6 port instance already found, trying to close. +Feb 27, 2022 6:54:04 PM aw.d available +SEVERE: null +jssc.SerialPortException: Port name - COM6; Method name - getInputBufferBytesCount(); Exception type - Port not opened. + at jssc.SerialPort.checkPortOpened(SerialPort.java:951) + at jssc.SerialPort.getInputBufferBytesCount(SerialPort.java:873) + at aw.d.available(Unknown Source) + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.M.a(Unknown Source) + at I.d.a(Unknown Source) + at F.J.d(Unknown Source) + at y.t.a(Unknown Source) + at y.u.run(Unknown Source) + +2/27/22 6:54:04 PM :Error: connection lost serialPort COM6 not open +2/27/22 6:54:04 PM :Info: Error: connection lost serialPort COM6 not open +Feb 27, 2022 6:54:04 PM aw.d available +SEVERE: null +jssc.SerialPortException: Port name - COM6; Method name - getInputBufferBytesCount(); Exception type - Port not opened. + at jssc.SerialPort.checkPortOpened(SerialPort.java:951) + at jssc.SerialPort.getInputBufferBytesCount(SerialPort.java:873) + at aw.d.available(Unknown Source) + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at F.J.d(Unknown Source) + at y.t.a(Unknown Source) + at y.u.run(Unknown Source) + +2/27/22 6:54:04 PM :Error: Exception during synchronous write +2/27/22 6:54:04 PM :Info: Error: Exception during synchronous write +Feb 27, 2022 6:54:04 PM y.t a +SEVERE: null +F.l: Unable to open port: COM6 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:54:05 PM :Debug: set baud to 115200 +2/27/22 6:54:05 PM :Info: Com Thread created: COMM Thread3486.739884091683 +2/27/22 6:54:05 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread3486.739884091683 +2/27/22 6:54:06 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread26972.84513724123, new Thread:COMM Thread3486.739884091683 +2/27/22 6:54:06 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread26972.84513724123 +2/27/22 6:54:06 PM :Warning: Unsupported Controller Firmware: ?? +2/27/22 6:54:08 PM :Warning: Unsupported Controller Firmware: ?? +2/27/22 6:54:10 PM :Debug: goOffline Starting, Time:0 +2/27/22 6:54:10 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 6:54:10 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 6:54:10 PM :Debug: goOffline closed port, Time:1 +2/27/22 6:54:11 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread3486.739884091683 +2/27/22 6:54:11 PM :Debug: goOffline comm thread stopped, Time:1360 +2/27/22 6:54:11 PM :Debug: No Remaining Queue Write instructions +2/27/22 6:57:58 PM :Info: Com Thread created: COMM Thread56244.994526562696 +2/27/22 6:57:58 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread56244.994526562696 +2/27/22 6:57:59 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread3486.739884091683, new Thread:COMM Thread56244.994526562696 +2/27/22 6:58:00 PM :Debug: goOffline Starting, Time:0 +2/27/22 6:58:00 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 6:58:00 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 6:58:00 PM :Debug: goOffline closed port, Time:1 +2/27/22 6:58:00 PM :Debug: goOffline Starting, Time:0 +2/27/22 6:58:00 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 6:58:00 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 6:58:00 PM :Debug: goOffline closed port, Time:1 +2/27/22 6:58:00 PM :Debug: set baud to 115200 +2/27/22 6:58:00 PM :Debug: set baud to 115200 +2/27/22 6:58:00 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread56244.994526562696 +2/27/22 6:58:01 PM :Debug: goOffline comm thread stopped, Time:152 +2/27/22 6:58:01 PM :Debug: No Remaining Queue Write instructions +2/27/22 6:58:01 PM :Debug: goOffline comm thread stopped, Time:502 +2/27/22 6:58:01 PM :Debug: No Remaining Queue Write instructions +2/27/22 6:58:02 PM :Debug: set baud to 115200 +2/27/22 6:58:02 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:02 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread56244.994526562696, new Thread:Thread-112 +Feb 27, 2022 6:58:03 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:04 PM :Debug: set baud to 115200 +2/27/22 6:58:04 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:04 PM :Info: Comm Read Thread Change! Old Thread:Thread-112, new Thread:Thread-115 +Feb 27, 2022 6:58:05 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:05 PM :Debug: set baud to 115200 +2/27/22 6:58:05 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:05 PM :Info: Comm Read Thread Change! Old Thread:Thread-115, new Thread:Thread-118 +Feb 27, 2022 6:58:06 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:11 PM :Debug: set baud to 115200 +2/27/22 6:58:11 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:11 PM :Info: Comm Read Thread Change! Old Thread:Thread-118, new Thread:Thread-121 +Feb 27, 2022 6:58:11 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:12 PM :Debug: set baud to 115200 +2/27/22 6:58:12 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:12 PM :Info: Comm Read Thread Change! Old Thread:Thread-121, new Thread:Thread-124 +Feb 27, 2022 6:58:13 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:14 PM :Debug: set baud to 115200 +2/27/22 6:58:14 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:14 PM :Info: Comm Read Thread Change! Old Thread:Thread-124, new Thread:Thread-127 +Feb 27, 2022 6:58:15 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 6:58:16 PM :Debug: set baud to 115200 +2/27/22 6:58:16 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 6:58:16 PM :Info: Comm Read Thread Change! Old Thread:Thread-127, new Thread:Thread-130 +Feb 27, 2022 6:58:16 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:01:02 PM :Debug: set baud to 115200 +2/27/22 7:01:02 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:02 PM :Info: Comm Read Thread Change! Old Thread:Thread-130, new Thread:Thread-133 +2/27/22 7:01:02 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xDF .. +2/27/22 7:01:03 PM :Debug: set baud to 115200 +2/27/22 7:01:03 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:03 PM :Info: Comm Read Thread Change! Old Thread:Thread-133, new Thread:Thread-136 +2/27/22 7:01:04 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF . +2/27/22 7:01:05 PM :Debug: set baud to 115200 +2/27/22 7:01:05 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:05 PM :Info: Comm Read Thread Change! Old Thread:Thread-136, new Thread:Thread-139 +2/27/22 7:01:06 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF . +2/27/22 7:01:23 PM :Debug: set baud to 115200 +2/27/22 7:01:23 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:24 PM :Info: Comm Read Thread Change! Old Thread:Thread-139, new Thread:Thread-142 +Feb 27, 2022 7:01:24 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:01:25 PM :Debug: set baud to 115200 +2/27/22 7:01:25 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:26 PM :Info: Comm Read Thread Change! Old Thread:Thread-142, new Thread:Thread-145 +Feb 27, 2022 7:01:26 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:01:46 PM :Debug: set baud to 115200 +2/27/22 7:01:46 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:46 PM :Info: Comm Read Thread Change! Old Thread:Thread-145, new Thread:Thread-148 +Feb 27, 2022 7:01:47 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:01:47 PM :Debug: set baud to 115200 +2/27/22 7:01:47 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:01:48 PM :Info: Comm Read Thread Change! Old Thread:Thread-148, new Thread:Thread-151 +Feb 27, 2022 7:01:48 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:02:58 PM :Debug: set baud to 115200 +2/27/22 7:02:58 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:02:58 PM :Info: Comm Read Thread Change! Old Thread:Thread-151, new Thread:Thread-154 +Feb 27, 2022 7:02:59 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:02:59 PM :Debug: set baud to 115200 +2/27/22 7:02:59 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:02:59 PM :Info: Comm Read Thread Change! Old Thread:Thread-154, new Thread:Thread-157 +Feb 27, 2022 7:03:00 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:03:01 PM :Debug: set baud to 115200 +2/27/22 7:03:01 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:03:01 PM :Info: Comm Read Thread Change! Old Thread:Thread-157, new Thread:Thread-160 +Feb 27, 2022 7:03:02 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:03:06 PM :Debug: set baud to 115200 +2/27/22 7:03:06 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:03:06 PM :Info: Comm Read Thread Change! Old Thread:Thread-160, new Thread:Thread-163 +Feb 27, 2022 7:03:07 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:03:26 PM :Debug: set baud to 115200 +2/27/22 7:03:26 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:03:26 PM :Info: Comm Read Thread Change! Old Thread:Thread-163, new Thread:Thread-166 +Feb 27, 2022 7:03:27 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:03:27 PM :Debug: set baud to 115200 +2/27/22 7:03:27 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:03:28 PM :Info: Comm Read Thread Change! Old Thread:Thread-166, new Thread:Thread-169 +Feb 27, 2022 7:03:28 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:03:29 PM :Debug: set baud to 115200 +2/27/22 7:03:29 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:03:29 PM :Info: Comm Read Thread Change! Old Thread:Thread-169, new Thread:Thread-172 +Feb 27, 2022 7:03:30 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:04:19 PM :Debug: set baud to 115200 +2/27/22 7:04:19 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:04:19 PM :Info: Comm Read Thread Change! Old Thread:Thread-172, new Thread:Thread-175 +Feb 27, 2022 7:04:20 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:04:20 PM :Debug: set baud to 115200 +2/27/22 7:04:20 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:04:20 PM :Info: Comm Read Thread Change! Old Thread:Thread-175, new Thread:Thread-178 +Feb 27, 2022 7:04:21 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:04:22 PM :Debug: set baud to 115200 +2/27/22 7:04:22 PM :Info: Com Thread created: COMM Thread14885.22442301773 +2/27/22 7:04:22 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread14885.22442301773 +2/27/22 7:04:22 PM :Info: Comm Read Thread Change! Old Thread:Thread-178, new Thread:COMM Thread14885.22442301773 +2/27/22 7:04:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:04:23 PM :Info: Time to save msq: 23.5604 +2/27/22 7:04:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:04:23 PM :Info: closeApp Called +2/27/22 7:04:23 PM :Debug: TuneLog Editor set text +2/27/22 7:04:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:04:23 PM :Info: Time to save msq: 3.7469 +2/27/22 7:04:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:04:23 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:04:23 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:04:23 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:04:23 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:04:24 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread14885.22442301773 +2/27/22 7:04:24 PM :Debug: goOffline comm thread stopped, Time:657 +2/27/22 7:04:24 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:04:24 PM :Debug: removing Configuration: DBW_code_26.10.2021 +2/27/22 7:04:24 PM :Info: No Persistor set, not saving active triggers. +2/27/22 7:04:24 PM :Debug: ############################################# Save Project Backup ########################################## +2/27/22 7:04:24 PM :Info: Finalizing Sensors +Saved user properties successfully +Starting on DESKTOP-MVON5FO +TunerStudio 3.1.08 started on Sun Feb 27 19:04:38 CET 2022 +JRE 1.8.0_66, Windows 10 10.0, x86 +java.library.path=./lib +TunerStudioMS.jar +Look:Metal, ClassName:'javax.swing.plaf.metal.MetalLookAndFeel' +Look:Nimbus, ClassName:'javax.swing.plaf.nimbus.NimbusLookAndFeel' +Look:CDE/Motif, ClassName:'com.sun.java.swing.plaf.motif.MotifLookAndFeel' +Look:Windows, ClassName:'com.sun.java.swing.plaf.windows.WindowsLookAndFeel' +Look:Windows Classic, ClassName:'com.sun.java.swing.plaf.windows.WindowsClassicLookAndFeel' +Look:Night Shade, ClassName:'de.muntjak.tinylookandfeel.TinyLookAndFeel' +Setting Look & Feel to:javax.swing.plaf.metal.MetalLookAndFeel +ScrollBar.width +2/27/22 7:04:38 PM :Debug: no update:defaultFont +2/27/22 7:04:38 PM :Info: Initializing File Dialogs. +2/27/22 7:04:39 PM :Debug: hid: 572.78455 +2/27/22 7:04:39 PM :Info: Loading Language Content. +2/27/22 7:04:41 PM :Debug: Command Non-VolatileBytes for F resolved to: x46 F +2/27/22 7:04:41 PM :Debug: Command Non-VolatileBytes for I resolved to: x49 I +2/27/22 7:04:41 PM :Debug: Command Non-VolatileBytes for f resolved to: x66 f +2/27/22 7:04:41 PM :Info: Initializing Help. +2/27/22 7:04:41 PM :Info: Initializing Edition Features. +2/27/22 7:04:41 PM :Info: Initializing App Events. +2/27/22 7:04:41 PM :Debug: App Name:TunerStudio, appEdition:MS Lite! +2/27/22 7:04:41 PM :Debug: Dummy Function Factory Created. +2/27/22 7:04:41 PM :Info: Initializing User Interface +2/27/22 7:04:43 PM :Info: Loading Font list. +2/27/22 7:04:43 PM :Debug: Time to retreive font name list: 16 ms. +2/27/22 7:04:43 PM :Info: +2/27/22 7:04:43 PM :Info: Initializing UI Components. +2/27/22 7:04:43 PM :Info: Ready +2/27/22 7:04:44 PM :Info: Opening Project ... +2/27/22 7:04:44 PM :Debug: Opening project: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021 +2/27/22 7:04:44 PM :Debug: Reading translation file as plain text +2/27/22 7:04:44 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:04:44 PM :Debug: Filtered ConfigurationOptionGroup in 1ms. +2/27/22 7:04:44 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:04:44 PM :Info: Read file canPcVariables.ini: 1.3477ms +2/27/22 7:04:44 PM :Info: Filtered ini: 0.0284ms +2/27/22 7:04:44 PM :Info: No iniVersion defined +2/27/22 7:04:44 PM :Info: Loading Trigger Wheels +2/27/22 7:04:44 PM :Info: Loaded All known ini sections +2/27/22 7:04:44 PM :Info: Parsed and validated ini "canPcVariables.ini" in : 13ms. +2/27/22 7:04:44 PM :Info: Read file mainController.ini: 1.1138ms +2/27/22 7:04:44 PM :Info: Filtered ini: 0.1141ms +2/27/22 7:04:44 PM :Info: No iniVersion defined +2/27/22 7:04:44 PM :Debug: ini signature: speeduino DBW 2.0.0 +2/27/22 7:04:44 PM :Info: Set Write Blocks on = true +2/27/22 7:04:44 PM :Info: Loading Trigger Wheels +2/27/22 7:04:44 PM :Info: Loading Depricated ini section [UserDefined], use [UiDialogs] +2/27/22 7:04:44 PM :Info: Loaded All known ini sections +2/27/22 7:04:44 PM :Info: Parsed and validated ini "mainController.ini" in : 10ms. +2/27/22 7:04:44 PM :Info: Not Loading default Tools because non are defined for signature: speeduino DBW 2.0.0 +2/27/22 7:04:44 PM :Info: Time to load primary config: 48.3113ms. used cached config: false +SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder". +SLF4J: Defaulting to no-operation (NOP) logger implementation +SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details. +2/27/22 7:04:44 PM :Debug: set baud to 115200 +2/27/22 7:04:44 PM :Debug: Adding Configuration: DBW_code_26.10.2021 +2/27/22 7:04:44 PM :Debug: controllerOnline = 0.0 +2/27/22 7:04:44 PM :Info: No secl OutputChannel, och sync monitor disabled. +2/27/22 7:04:44 PM :Debug: Fill Constants: 0 +2/27/22 7:04:44 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:04:44 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:04:44 PM :Info: dirtyData.size(): 0 +2/27/22 7:04:44 PM :Info: dirtyData.size(): 0 +2/27/22 7:04:44 PM :Debug: Flush lasted: 72ms. +2/27/22 7:04:44 PM :Info: dirtyData.size(): 0 +2/27/22 7:04:44 PM :Info: dirtyData.size(): 0 +2/27/22 7:04:44 PM :Debug: Flush lasted: 77ms. +2/27/22 7:04:44 PM :Debug: Skip Burn, last write page: -2 +2/27/22 7:04:44 PM :Info: !!! Loaded config in 313 +2/27/22 7:04:44 PM :Info: !!! Activated Project 486 +2/27/22 7:04:44 PM :Info: Opening Gauge Cluster.. +2/27/22 7:04:44 PM :Debug: High Speed Paint: true +2/27/22 7:04:44 PM :Info: +2/27/22 7:04:44 PM :Info: Com Thread created: COMM Thread11667.498411430932 +2/27/22 7:04:44 PM :Info: endModalBlock called, but Root Pane is not a ProgressPane. +2/27/22 7:04:44 PM :Debug: !!! Opened Dash 721 +2/27/22 7:04:44 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread11667.498411430932 +2/27/22 7:04:44 PM :Info: DBW_code_26.10.2021 Ready +2/27/22 7:04:44 PM :Debug: Tuning View Files loaded in 0.1556ms. +2/27/22 7:04:45 PM :Info: Comm Read Thread Change! Old Thread:null, new Thread:COMM Thread11667.498411430932 +MSmain: No check, last update check=Sun Feb 27 18:14:34 CET 2022 +2/27/22 7:04:45 PM :Info: No Persistor set, not activating persisted triggers. +2/27/22 7:04:45 PM :Debug: Running speed test +2/27/22 7:04:46 PM :Debug: Processor Score:441530 +MSad: No check, last update check=Sun Feb 27 18:14:37 CET 2022 +2/27/22 7:04:48 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:04:48 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:04:48 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:04:48 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:04:48 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:04:48 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:04:48 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:04:48 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:04:49 PM :Debug: set baud to 115200 +2/27/22 7:04:49 PM :Debug: set baud to 115200 +2/27/22 7:04:49 PM :Debug: goOffline comm thread stopped, Time:514 +2/27/22 7:04:49 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:04:49 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread11667.498411430932 +2/27/22 7:04:49 PM :Debug: goOffline comm thread stopped, Time:778 +2/27/22 7:04:49 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:04:50 PM :Debug: set baud to 115200 +2/27/22 7:04:50 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:04:51 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread11667.498411430932, new Thread:Thread-24 +Feb 27, 2022 7:04:51 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:04:53 PM :Debug: set baud to 115200 +2/27/22 7:04:53 PM :Info: Com Thread created: COMM Thread24568.11311790118 +2/27/22 7:04:53 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread24568.11311790118 +2/27/22 7:04:53 PM :Info: Comm Read Thread Change! Old Thread:Thread-24, new Thread:COMM Thread24568.11311790118 +2/27/22 7:06:26 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:06:26 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:06:26 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:06:26 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:06:26 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:06:26 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:06:26 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:06:26 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:06:26 PM :Debug: set baud to 115200 +2/27/22 7:06:26 PM :Debug: set baud to 115200 +2/27/22 7:06:27 PM :Debug: goOffline comm thread stopped, Time:502 +2/27/22 7:06:27 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:06:27 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread24568.11311790118 +2/27/22 7:06:27 PM :Debug: goOffline comm thread stopped, Time:864 +2/27/22 7:06:27 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:06:27 PM :Debug: set baud to 115200 +2/27/22 7:06:27 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:27 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread24568.11311790118, new Thread:Thread-31 +Feb 27, 2022 7:06:28 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:29 PM :Debug: set baud to 115200 +2/27/22 7:06:29 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:29 PM :Info: Comm Read Thread Change! Old Thread:Thread-31, new Thread:Thread-34 +Feb 27, 2022 7:06:30 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:32 PM :Debug: set baud to 115200 +2/27/22 7:06:32 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:32 PM :Info: Comm Read Thread Change! Old Thread:Thread-34, new Thread:Thread-37 +Feb 27, 2022 7:06:33 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:34 PM :Debug: set baud to 115200 +2/27/22 7:06:34 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:34 PM :Info: Comm Read Thread Change! Old Thread:Thread-37, new Thread:Thread-40 +Feb 27, 2022 7:06:34 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:36 PM :Debug: set baud to 115200 +2/27/22 7:06:36 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:36 PM :Info: Comm Read Thread Change! Old Thread:Thread-40, new Thread:Thread-43 +Feb 27, 2022 7:06:37 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:39 PM :Debug: set baud to 115200 +2/27/22 7:06:39 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:39 PM :Info: Comm Read Thread Change! Old Thread:Thread-43, new Thread:Thread-46 +Feb 27, 2022 7:06:40 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:06:41 PM :Debug: set baud to 115200 +2/27/22 7:06:41 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:06:41 PM :Info: Comm Read Thread Change! Old Thread:Thread-46, new Thread:Thread-49 +Feb 27, 2022 7:06:41 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:20:50 PM :Debug: set baud to 115200 +2/27/22 7:20:50 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:20:50 PM :Info: Comm Read Thread Change! Old Thread:Thread-49, new Thread:Thread-52 +Feb 27, 2022 7:20:51 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:20:52 PM :Debug: set baud to 115200 +2/27/22 7:20:52 PM :Info: Com Thread created: COMM Thread59538.77638449372 +2/27/22 7:20:52 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread59538.77638449372 +2/27/22 7:20:52 PM :Info: Comm Read Thread Change! Old Thread:Thread-52, new Thread:COMM Thread59538.77638449372 +2/27/22 7:20:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:20:54 PM :Info: Time to save msq: 25.4093 +2/27/22 7:20:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:20:54 PM :Info: closeApp Called +2/27/22 7:20:54 PM :Debug: TuneLog Editor set text +2/27/22 7:20:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:20:54 PM :Info: Time to save msq: 3.5612 +2/27/22 7:20:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:20:54 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:20:54 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:20:54 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:20:54 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:20:54 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread59538.77638449372 +2/27/22 7:20:54 PM :Debug: goOffline comm thread stopped, Time:759 +2/27/22 7:20:54 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:20:54 PM :Debug: removing Configuration: DBW_code_26.10.2021 +2/27/22 7:20:54 PM :Info: No Persistor set, not saving active triggers. +2/27/22 7:20:54 PM :Debug: ############################################# Save Project Backup ########################################## +2/27/22 7:20:54 PM :Info: Finalizing Sensors +Saved user properties successfully +Starting on DESKTOP-MVON5FO +TunerStudio 3.1.08 started on Sun Feb 27 19:23:22 CET 2022 +JRE 1.8.0_66, Windows 10 10.0, x86 +java.library.path=./lib +TunerStudioMS.jar +Look:Metal, ClassName:'javax.swing.plaf.metal.MetalLookAndFeel' +Look:Nimbus, ClassName:'javax.swing.plaf.nimbus.NimbusLookAndFeel' +Look:CDE/Motif, ClassName:'com.sun.java.swing.plaf.motif.MotifLookAndFeel' +Look:Windows, ClassName:'com.sun.java.swing.plaf.windows.WindowsLookAndFeel' +Look:Windows Classic, ClassName:'com.sun.java.swing.plaf.windows.WindowsClassicLookAndFeel' +Look:Night Shade, ClassName:'de.muntjak.tinylookandfeel.TinyLookAndFeel' +Setting Look & Feel to:javax.swing.plaf.metal.MetalLookAndFeel +ScrollBar.width +2/27/22 7:23:22 PM :Debug: no update:defaultFont +2/27/22 7:23:23 PM :Info: Initializing File Dialogs. +2/27/22 7:23:23 PM :Debug: hid: 513.6715 +2/27/22 7:23:24 PM :Info: Loading Language Content. +2/27/22 7:23:26 PM :Debug: Command Non-VolatileBytes for F resolved to: x46 F +2/27/22 7:23:26 PM :Debug: Command Non-VolatileBytes for I resolved to: x49 I +2/27/22 7:23:26 PM :Debug: Command Non-VolatileBytes for f resolved to: x66 f +2/27/22 7:23:26 PM :Info: Initializing Help. +2/27/22 7:23:26 PM :Info: Initializing Edition Features. +2/27/22 7:23:26 PM :Info: Initializing App Events. +2/27/22 7:23:26 PM :Debug: App Name:TunerStudio, appEdition:MS Lite! +2/27/22 7:23:26 PM :Debug: Dummy Function Factory Created. +2/27/22 7:23:26 PM :Info: Initializing User Interface +2/27/22 7:23:28 PM :Info: Loading Font list. +2/27/22 7:23:28 PM :Debug: Time to retreive font name list: 23 ms. +2/27/22 7:23:28 PM :Info: +2/27/22 7:23:28 PM :Info: Initializing UI Components. +2/27/22 7:23:28 PM :Info: Ready +MSmain: No check, last update check=Sun Feb 27 18:14:34 CET 2022 +MSad: No check, last update check=Sun Feb 27 18:14:37 CET 2022 +2/27/22 7:23:41 PM :Info: Opening Project ... +2/27/22 7:23:41 PM :Debug: Opening project: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021 +2/27/22 7:23:41 PM :Debug: Reading translation file as plain text +2/27/22 7:23:41 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:23:41 PM :Debug: Filtered ConfigurationOptionGroup in 2ms. +2/27/22 7:23:41 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:23:41 PM :Info: Read file canPcVariables.ini: 1.8045ms +2/27/22 7:23:41 PM :Info: Filtered ini: 0.0303ms +2/27/22 7:23:41 PM :Info: No iniVersion defined +2/27/22 7:23:41 PM :Info: Loading Trigger Wheels +2/27/22 7:23:41 PM :Info: Loaded All known ini sections +2/27/22 7:23:41 PM :Info: Parsed and validated ini "canPcVariables.ini" in : 23ms. +2/27/22 7:23:41 PM :Info: Read file mainController.ini: 1.5727ms +2/27/22 7:23:41 PM :Info: Filtered ini: 0.1131ms +2/27/22 7:23:41 PM :Info: No iniVersion defined +2/27/22 7:23:41 PM :Debug: ini signature: speeduino DBW 2.0.0 +2/27/22 7:23:41 PM :Info: Set Write Blocks on = true +2/27/22 7:23:41 PM :Info: Loading Trigger Wheels +2/27/22 7:23:41 PM :Info: Loading Depricated ini section [UserDefined], use [UiDialogs] +2/27/22 7:23:41 PM :Info: Loaded All known ini sections +2/27/22 7:23:41 PM :Info: Parsed and validated ini "mainController.ini" in : 18ms. +2/27/22 7:23:41 PM :Info: Not Loading default Tools because non are defined for signature: speeduino DBW 2.0.0 +2/27/22 7:23:41 PM :Info: Time to load primary config: 91.1326ms. used cached config: false +SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder". +SLF4J: Defaulting to no-operation (NOP) logger implementation +SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details. +2/27/22 7:23:41 PM :Debug: set baud to 115200 +2/27/22 7:23:41 PM :Debug: Adding Configuration: DBW_code_26.10.2021 +2/27/22 7:23:41 PM :Debug: controllerOnline = 0.0 +2/27/22 7:23:41 PM :Info: No secl OutputChannel, och sync monitor disabled. +2/27/22 7:23:41 PM :Debug: Fill Constants: 2 +2/27/22 7:23:41 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:23:41 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:23:41 PM :Info: dirtyData.size(): 0 +2/27/22 7:23:42 PM :Info: dirtyData.size(): 0 +2/27/22 7:23:42 PM :Debug: Flush lasted: 73ms. +2/27/22 7:23:42 PM :Info: dirtyData.size(): 0 +2/27/22 7:23:42 PM :Info: dirtyData.size(): 0 +2/27/22 7:23:42 PM :Debug: Flush lasted: 78ms. +2/27/22 7:23:42 PM :Debug: Skip Burn, last write page: -2 +2/27/22 7:23:42 PM :Info: !!! Loaded config in 363 +2/27/22 7:23:42 PM :Info: !!! Activated Project 555 +2/27/22 7:23:42 PM :Info: Opening Gauge Cluster.. +2/27/22 7:23:42 PM :Debug: High Speed Paint: true +2/27/22 7:23:42 PM :Info: +2/27/22 7:23:42 PM :Info: Com Thread created: COMM Thread45327.883014414205 +2/27/22 7:23:42 PM :Info: endModalBlock called, but Root Pane is not a ProgressPane. +2/27/22 7:23:42 PM :Debug: !!! Opened Dash 899 +2/27/22 7:23:42 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread45327.883014414205 +2/27/22 7:23:42 PM :Info: DBW_code_26.10.2021 Ready +2/27/22 7:23:42 PM :Debug: Tuning View Files loaded in 0.1584ms. +2/27/22 7:23:42 PM :Info: Comm Read Thread Change! Old Thread:null, new Thread:COMM Thread45327.883014414205 +2/27/22 7:23:43 PM :Info: No Persistor set, not activating persisted triggers. +2/27/22 7:23:50 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:23:50 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:23:50 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:23:50 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:23:50 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:23:50 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:23:50 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:23:50 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:23:50 PM :Debug: set baud to 115200 +2/27/22 7:23:50 PM :Debug: set baud to 115200 +2/27/22 7:23:51 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:23:51 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:23:51 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread45327.883014414205 +2/27/22 7:23:51 PM :Debug: goOffline comm thread stopped, Time:660 +2/27/22 7:23:51 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:23:53 PM :Debug: set baud to 115200 +2/27/22 7:23:53 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:23:53 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread45327.883014414205, new Thread:Thread-23 +Feb 27, 2022 7:23:53 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:23:58 PM :Debug: set baud to 115200 +2/27/22 7:23:58 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:23:58 PM :Info: Comm Read Thread Change! Old Thread:Thread-23, new Thread:Thread-26 +2/27/22 7:23:59 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xFF .. +2/27/22 7:24:08 PM :Debug: set baud to 115200 +2/27/22 7:24:08 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:24:08 PM :Info: Comm Read Thread Change! Old Thread:Thread-26, new Thread:Thread-29 +2/27/22 7:24:09 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xFF .. +2/27/22 7:24:52 PM :Debug: set baud to 115200 +2/27/22 7:24:52 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:24:52 PM :Info: Comm Read Thread Change! Old Thread:Thread-29, new Thread:Thread-32 +2/27/22 7:24:53 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xFF .. +2/27/22 7:24:54 PM :Debug: set baud to 115200 +2/27/22 7:24:54 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:24:54 PM :Info: Comm Read Thread Change! Old Thread:Thread-32, new Thread:Thread-35 +2/27/22 7:24:55 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF . +Feb 27, 2022 7:24:57 PM com.ftdi.FTDevice getDevices +INFO: Found devs: 0 (All:0) +Feb 27, 2022 7:24:58 PM com.ftdi.FTDevice getDevices +INFO: Found devs: 0 (All:0) +2/27/22 7:24:58 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:24:58 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:24:58 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:24:58 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:24:58 PM :Debug: goOffline comm thread stopped, Time:500 +2/27/22 7:24:58 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:24:58 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 7:24:58 PM com.ftdi.FTDevice getDevices +INFO: Found devs: 0 (All:0) +Feb 27, 2022 7:24:58 PM y.t a +SEVERE: null +F.l: Did not find any supported FTDI Device or it is already in use. + at au.b.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +Feb 27, 2022 7:24:59 PM com.ftdi.FTDevice getDevices +INFO: Found devs: 0 (All:0) +2/27/22 7:24:59 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 7:24:59 PM com.ftdi.FTDevice getDevices +INFO: Found devs: 0 (All:0) +Feb 27, 2022 7:24:59 PM y.t a +SEVERE: null +F.l: Did not find any supported FTDI Device or it is already in use. + at au.b.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:04 PM :Debug: set baud to 115200 +2/27/22 7:25:04 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:25:04 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:25:04 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:25:04 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:25:05 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:25:05 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:25:05 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:05 PM :Info: Comm Read Thread Change! Old Thread:Thread-35, new Thread:Thread-41 +2/27/22 7:25:06 PM :Debug: Read from RS232: Port:COM6, Baud:115200, signature:xFF xFF .. +2/27/22 7:25:18 PM :Debug: set baud to 115200 +2/27/22 7:25:18 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:18 PM :Info: Comm Read Thread Change! Old Thread:Thread-41, new Thread:Thread-44 +Feb 27, 2022 7:25:19 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:20 PM :Debug: set baud to 115200 +2/27/22 7:25:20 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:20 PM :Info: Comm Read Thread Change! Old Thread:Thread-44, new Thread:Thread-47 +Feb 27, 2022 7:25:21 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:27 PM :Debug: set baud to 115200 +2/27/22 7:25:27 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:27 PM :Info: Comm Read Thread Change! Old Thread:Thread-47, new Thread:Thread-50 +Feb 27, 2022 7:25:28 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:53 PM :Debug: set baud to 115200 +2/27/22 7:25:53 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:53 PM :Info: Comm Read Thread Change! Old Thread:Thread-50, new Thread:Thread-53 +Feb 27, 2022 7:25:54 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:54 PM :Debug: set baud to 115200 +2/27/22 7:25:54 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:54 PM :Info: Comm Read Thread Change! Old Thread:Thread-53, new Thread:Thread-56 +Feb 27, 2022 7:25:55 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:25:59 PM :Debug: set baud to 115200 +2/27/22 7:25:59 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:25:59 PM :Info: Comm Read Thread Change! Old Thread:Thread-56, new Thread:Thread-59 +Feb 27, 2022 7:25:59 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:26:00 PM :Debug: set baud to 115200 +2/27/22 7:26:00 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:26:00 PM :Info: Comm Read Thread Change! Old Thread:Thread-59, new Thread:Thread-62 +Feb 27, 2022 7:26:01 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:27:43 PM :Debug: set baud to 115200 +2/27/22 7:27:43 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:27:44 PM :Info: Comm Read Thread Change! Old Thread:Thread-62, new Thread:Thread-65 +Feb 27, 2022 7:27:44 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:27:45 PM :Debug: set baud to 115200 +2/27/22 7:27:45 PM :Info: Com Thread created: COMM Thread51154.386207734824 +2/27/22 7:27:45 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread51154.386207734824 +2/27/22 7:27:45 PM :Info: Comm Read Thread Change! Old Thread:Thread-65, new Thread:COMM Thread51154.386207734824 +2/27/22 7:30:00 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:30:00 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:30:00 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:30:00 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:30:00 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:30:00 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:30:00 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:30:00 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:30:00 PM :Debug: set baud to 115200 +2/27/22 7:30:00 PM :Debug: set baud to 115200 +2/27/22 7:30:00 PM :Debug: goOffline comm thread stopped, Time:505 +2/27/22 7:30:00 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:30:00 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread51154.386207734824 +2/27/22 7:30:00 PM :Debug: goOffline comm thread stopped, Time:883 +2/27/22 7:30:00 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:30:01 PM :Debug: set baud to 115200 +2/27/22 7:30:01 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:30:01 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread51154.386207734824, new Thread:Thread-72 +Feb 27, 2022 7:30:02 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:30:02 PM :Debug: set baud to 115200 +2/27/22 7:30:02 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:30:02 PM :Info: Comm Read Thread Change! Old Thread:Thread-72, new Thread:Thread-75 +Feb 27, 2022 7:30:03 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:30:05 PM :Debug: set baud to 115200 +2/27/22 7:30:05 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:30:05 PM :Info: Comm Read Thread Change! Old Thread:Thread-75, new Thread:Thread-78 +Feb 27, 2022 7:30:05 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:31:34 PM :Debug: ############################################# Save Project Backup ########################################## +Starting on DESKTOP-MVON5FO +TunerStudio 3.1.08 started on Sun Feb 27 19:48:49 CET 2022 +JRE 1.8.0_66, Windows 10 10.0, x86 +java.library.path=./lib +TunerStudioMS.jar +Look:Metal, ClassName:'javax.swing.plaf.metal.MetalLookAndFeel' +Look:Nimbus, ClassName:'javax.swing.plaf.nimbus.NimbusLookAndFeel' +Look:CDE/Motif, ClassName:'com.sun.java.swing.plaf.motif.MotifLookAndFeel' +Look:Windows, ClassName:'com.sun.java.swing.plaf.windows.WindowsLookAndFeel' +Look:Windows Classic, ClassName:'com.sun.java.swing.plaf.windows.WindowsClassicLookAndFeel' +Look:Night Shade, ClassName:'de.muntjak.tinylookandfeel.TinyLookAndFeel' +Setting Look & Feel to:javax.swing.plaf.metal.MetalLookAndFeel +ScrollBar.width +2/27/22 7:48:49 PM :Debug: no update:defaultFont +2/27/22 7:48:49 PM :Info: Initializing File Dialogs. +2/27/22 7:48:49 PM :Debug: hid: 518.5734 +2/27/22 7:48:51 PM :Info: Loading Language Content. +2/27/22 7:48:53 PM :Debug: Command Non-VolatileBytes for F resolved to: x46 F +2/27/22 7:48:53 PM :Debug: Command Non-VolatileBytes for I resolved to: x49 I +2/27/22 7:48:53 PM :Debug: Command Non-VolatileBytes for f resolved to: x66 f +2/27/22 7:48:53 PM :Info: Initializing Help. +2/27/22 7:48:53 PM :Info: Initializing Edition Features. +2/27/22 7:48:53 PM :Info: Initializing App Events. +2/27/22 7:48:53 PM :Debug: App Name:TunerStudio, appEdition:MS Lite! +2/27/22 7:48:53 PM :Debug: Dummy Function Factory Created. +2/27/22 7:48:53 PM :Info: Initializing User Interface +2/27/22 7:48:55 PM :Info: Loading Font list. +2/27/22 7:48:55 PM :Debug: Time to retreive font name list: 15 ms. +2/27/22 7:48:55 PM :Info: +2/27/22 7:48:55 PM :Info: Initializing UI Components. +2/27/22 7:48:55 PM :Info: Ready +2/27/22 7:48:55 PM :Info: Opening Project ... +2/27/22 7:48:55 PM :Debug: Opening project: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021 +2/27/22 7:48:55 PM :Debug: Reading translation file as plain text +2/27/22 7:48:55 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:48:55 PM :Debug: Filtered ConfigurationOptionGroup in 4ms. +2/27/22 7:48:55 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 7:48:55 PM :Info: Read file canPcVariables.ini: 1.1243ms +2/27/22 7:48:55 PM :Info: Filtered ini: 0.0285ms +2/27/22 7:48:55 PM :Info: No iniVersion defined +2/27/22 7:48:55 PM :Info: Loading Trigger Wheels +2/27/22 7:48:55 PM :Info: Loaded All known ini sections +2/27/22 7:48:55 PM :Info: Parsed and validated ini "canPcVariables.ini" in : 16ms. +2/27/22 7:48:55 PM :Info: Read file mainController.ini: 2.9556ms +2/27/22 7:48:55 PM :Info: Filtered ini: 0.1115ms +2/27/22 7:48:55 PM :Info: No iniVersion defined +2/27/22 7:48:55 PM :Debug: ini signature: speeduino DBW 2.0.0 +2/27/22 7:48:55 PM :Info: Set Write Blocks on = true +2/27/22 7:48:55 PM :Info: Loading Trigger Wheels +2/27/22 7:48:55 PM :Info: Loading Depricated ini section [UserDefined], use [UiDialogs] +2/27/22 7:48:55 PM :Info: Loaded All known ini sections +2/27/22 7:48:55 PM :Info: Parsed and validated ini "mainController.ini" in : 0ms. +2/27/22 7:48:55 PM :Info: Not Loading default Tools because non are defined for signature: speeduino DBW 2.0.0 +2/27/22 7:48:55 PM :Info: Time to load primary config: 51.7803ms. used cached config: false +SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder". +SLF4J: Defaulting to no-operation (NOP) logger implementation +SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details. +2/27/22 7:48:55 PM :Debug: set baud to 115200 +2/27/22 7:48:55 PM :Debug: Adding Configuration: DBW_code_26.10.2021 +2/27/22 7:48:55 PM :Debug: controllerOnline = 0.0 +2/27/22 7:48:55 PM :Info: No secl OutputChannel, och sync monitor disabled. +2/27/22 7:48:55 PM :Debug: Fill Constants: 0 +2/27/22 7:48:55 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:48:55 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 7:48:55 PM :Info: dirtyData.size(): 0 +2/27/22 7:48:56 PM :Info: dirtyData.size(): 0 +2/27/22 7:48:56 PM :Debug: Flush lasted: 78ms. +2/27/22 7:48:56 PM :Info: dirtyData.size(): 0 +2/27/22 7:48:56 PM :Info: dirtyData.size(): 0 +2/27/22 7:48:56 PM :Debug: Flush lasted: 79ms. +2/27/22 7:48:56 PM :Debug: Skip Burn, last write page: -2 +2/27/22 7:48:56 PM :Info: !!! Loaded config in 324 +2/27/22 7:48:56 PM :Info: !!! Activated Project 487 +2/27/22 7:48:56 PM :Info: Opening Gauge Cluster.. +2/27/22 7:48:56 PM :Debug: High Speed Paint: true +2/27/22 7:48:56 PM :Info: +2/27/22 7:48:56 PM :Info: Com Thread created: COMM Thread34028.783909446625 +2/27/22 7:48:56 PM :Info: endModalBlock called, but Root Pane is not a ProgressPane. +2/27/22 7:48:56 PM :Debug: !!! Opened Dash 706 +2/27/22 7:48:56 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread34028.783909446625 +2/27/22 7:48:56 PM :Info: DBW_code_26.10.2021 Ready +2/27/22 7:48:56 PM :Debug: Port not valid: Unable to open port: COM6 +Please check your Communications Settings. +2/27/22 7:48:56 PM :Debug: Tuning View Files loaded in 0.1399ms. +2/27/22 7:48:57 PM :Info: No Persistor set, not activating persisted triggers. +MSmain: No check, last update check=Sun Feb 27 18:14:34 CET 2022 +MSad: No check, last update check=Sun Feb 27 18:14:37 CET 2022 +2/27/22 7:49:01 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:49:01 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:49:01 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:49:01 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:49:01 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:49:01 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:49:01 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:49:01 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:49:01 PM :Debug: set baud to 115200 +2/27/22 7:49:01 PM :Debug: set baud to 115200 +2/27/22 7:49:01 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread34028.783909446625 +2/27/22 7:49:01 PM :Debug: goOffline comm thread stopped, Time:125 +2/27/22 7:49:01 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:49:02 PM :Debug: goOffline comm thread stopped, Time:504 +2/27/22 7:49:02 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:49:04 PM :Debug: set baud to 115200 +2/27/22 7:49:04 PM :Debug: Received Instruction: Test Connection, Page: 0 +Feb 27, 2022 7:49:04 PM y.t a +SEVERE: null +F.l: Unable to open port: COM6 +Please check your Communications Settings. + at aw.a.f(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:49:06 PM :Debug: set baud to 115200 +2/27/22 7:49:06 PM :Info: Com Thread created: COMM Thread90564.12199534128 +2/27/22 7:49:06 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread90564.12199534128 +2/27/22 7:49:06 PM :Debug: Port not valid: Unable to open port: COM6 +Please check your Communications Settings. +2/27/22 7:50:54 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:50:54 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:50:54 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:50:54 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:50:54 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:50:54 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:50:54 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:50:54 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:50:54 PM :Debug: set baud to 115200 +2/27/22 7:50:54 PM :Debug: set baud to 115200 +2/27/22 7:50:54 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread90564.12199534128 +2/27/22 7:50:54 PM :Debug: goOffline comm thread stopped, Time:103 +2/27/22 7:50:54 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:50:54 PM :Debug: goOffline comm thread stopped, Time:502 +2/27/22 7:50:54 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:51:03 PM :Debug: set baud to 115200 +2/27/22 7:51:03 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:51:03 PM :Info: Comm Read Thread Change! Old Thread:null, new Thread:Thread-24 +Feb 27, 2022 7:51:04 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:51:07 PM :Debug: set baud to 115200 +2/27/22 7:51:07 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:51:07 PM :Info: Comm Read Thread Change! Old Thread:Thread-24, new Thread:Thread-27 +2/27/22 7:51:07 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:xFF xFE .. +2/27/22 7:51:08 PM :Debug: set baud to 115200 +2/27/22 7:51:08 PM :Info: Com Thread created: COMM Thread58411.45338286851 +2/27/22 7:51:08 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread58411.45338286851 +2/27/22 7:51:08 PM :Info: Comm Read Thread Change! Old Thread:Thread-27, new Thread:COMM Thread58411.45338286851 +2/27/22 7:51:09 PM :Warning: Unsupported Controller Firmware: ? +2/27/22 7:51:11 PM :Warning: Unsupported Controller Firmware: ~? +2/27/22 7:51:13 PM :Warning: Unsupported Controller Firmware: ~? +2/27/22 7:51:16 PM :Warning: Unsupported Controller Firmware: ? +2/27/22 7:51:18 PM :Warning: Unsupported Controller Firmware: ? +2/27/22 7:51:23 PM :Warning: Unsupported Controller Firmware: ~? +2/27/22 7:51:24 PM :Warning: Unsupported Controller Firmware: ? +2/27/22 7:53:22 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:53:22 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:53:22 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:53:22 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:53:22 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread58411.45338286851 +2/27/22 7:53:22 PM :Debug: goOffline comm thread stopped, Time:203 +2/27/22 7:53:22 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:54:02 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:54:02 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:54:02 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:54:02 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:54:02 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:54:02 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:54:02 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:54:02 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:54:02 PM :Debug: set baud to 115200 +2/27/22 7:54:02 PM :Debug: set baud to 115200 +2/27/22 7:54:03 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:54:03 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:54:03 PM :Debug: goOffline comm thread stopped, Time:502 +2/27/22 7:54:03 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:54:05 PM :Debug: set baud to 115200 +2/27/22 7:54:05 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:05 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread58411.45338286851, new Thread:Thread-35 +Feb 27, 2022 7:54:06 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:54:06 PM :Debug: set baud to 115200 +2/27/22 7:54:06 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:06 PM :Info: Comm Read Thread Change! Old Thread:Thread-35, new Thread:Thread-38 +Feb 27, 2022 7:54:07 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:54:08 PM :Debug: set baud to 115200 +2/27/22 7:54:08 PM :Info: Com Thread created: COMM Thread68250.1161199374 +2/27/22 7:54:08 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread68250.1161199374 +2/27/22 7:54:08 PM :Info: Comm Read Thread Change! Old Thread:Thread-38, new Thread:COMM Thread68250.1161199374 +2/27/22 7:54:30 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:54:30 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:54:30 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:54:30 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:54:30 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:54:30 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:54:30 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:54:30 PM :Debug: goOffline closed port, Time:0 +2/27/22 7:54:30 PM :Debug: set baud to 115200 +2/27/22 7:54:30 PM :Debug: set baud to 115200 +2/27/22 7:54:31 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread68250.1161199374 +2/27/22 7:54:31 PM :Debug: goOffline comm thread stopped, Time:373 +2/27/22 7:54:31 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:54:31 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:54:31 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:54:33 PM :Debug: set baud to 115200 +2/27/22 7:54:33 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:33 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread68250.1161199374, new Thread:Thread-45 +Feb 27, 2022 7:54:34 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:54:35 PM :Debug: set baud to 115200 +2/27/22 7:54:35 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:35 PM :Info: Comm Read Thread Change! Old Thread:Thread-45, new Thread:Thread-48 +Feb 27, 2022 7:54:35 PM y.t a +SEVERE: null +U.b: No bytes found on unknown read size. timeout x2: 600 + at y.t.a(Unknown Source) + at F.J.a(Unknown Source) + at F.J.b(Unknown Source) + at y.t.a(Unknown Source) + at F.J.q(Unknown Source) + at F.J.c(Unknown Source) + at F.J.b(Unknown Source) + at aJ.aa.o(Unknown Source) + at aJ.aa.b(Unknown Source) + at aJ.am.run(Unknown Source) + +2/27/22 7:54:38 PM :Debug: set baud to 115200 +2/27/22 7:54:38 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:38 PM :Info: Comm Read Thread Change! Old Thread:Thread-48, new Thread:Thread-51 +2/27/22 7:54:38 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:xFF xFF .. +2/27/22 7:54:39 PM :Debug: set baud to 115200 +2/27/22 7:54:39 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:39 PM :Info: Comm Read Thread Change! Old Thread:Thread-51, new Thread:Thread-54 +2/27/22 7:54:40 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:xFF xFE .. +2/27/22 7:54:58 PM :Debug: set baud to 115200 +2/27/22 7:54:58 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:54:58 PM :Info: Comm Read Thread Change! Old Thread:Thread-54, new Thread:Thread-57 +2/27/22 7:54:59 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:01 PM :Debug: set baud to 115200 +2/27/22 7:55:01 PM :Info: Com Thread created: COMM Thread96853.57914539523 +2/27/22 7:55:01 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread96853.57914539523 +2/27/22 7:55:01 PM :Info: Comm Read Thread Change! Old Thread:Thread-57, new Thread:COMM Thread96853.57914539523 +2/27/22 7:55:02 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:02 PM :Info: Communicating with sig:speeduino dbw_v0.80, speeduino dbw_v0.80 +2/27/22 7:55:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:02 PM :Info: Looks like Speeduino +2/27/22 7:55:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:02 PM :Info: Looks like Speeduino +2/27/22 7:55:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:02 PM :Info: Looks like Speeduino +2/27/22 7:55:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:02 PM :Info: Looks like Speeduino +2/27/22 7:55:09 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:09 PM :Info: Looks like Speeduino +2/27/22 7:55:11 PM :Info: Could not get ECU Definition for signature: Signature:speeduino dbw_v0.80, firmware:speeduino dbw_v0.80, Error: The correct ECU Definition not availble. +2/27/22 7:55:15 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:15 PM :Debug: controllerOnline = 1.0 +2/27/22 7:55:15 PM :Warning: COM8 port instance already found, trying to close. +2/27/22 7:55:16 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:17 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:17 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:18 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:19 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:19 PM :Info: Timeout reading page 1, increased blockReadTimeout to 651, trying once more. +2/27/22 7:55:20 PM :Debug: Read All Data +2/27/22 7:55:20 PM :Debug: result.FAILED: 1 tryCount +2/27/22 7:55:21 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:55:22 PM :Info: Communicating with sig:speeduino dbw_v0.80, speeduino dbw_v0.80 +2/27/22 7:55:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:22 PM :Info: Looks like Speeduino +2/27/22 7:55:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:22 PM :Info: Looks like Speeduino +2/27/22 7:55:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:22 PM :Info: Looks like Speeduino +2/27/22 7:55:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:22 PM :Info: Looks like Speeduino +2/27/22 7:55:22 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:33 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:33 PM :Debug: controllerOnline = 1.0 +2/27/22 7:55:33 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:33 PM :Info: CRC from controller page 1:x5C xC9 xCE xEC \... +2/27/22 7:55:33 PM :Info: Local Data CRC for page 1: xF6 xEF xD3 x26 ...& +2/27/22 7:55:33 PM :Debug: Read page time: 171ms. +2/27/22 7:55:33 PM :Info: Checksum page 1 data read: xE6 x92 x25 x02 ..%. +2/27/22 7:55:33 PM :Debug: Read All Data +2/27/22 7:55:33 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:55:33 PM :Debug: DiffTime: 4 ms. +2/27/22 7:55:33 PM :Debug: Time to get Panels = 0ms. +2/27/22 7:55:33 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:33 PM :Info: CRC from controller page 1:x5C xC9 xCE xEC \... +2/27/22 7:55:33 PM :Info: Local Data CRC for page 1: xE6 x92 x25 x02 ..%. +2/27/22 7:55:33 PM :Debug: Read page time: 171ms. +2/27/22 7:55:33 PM :Info: Checksum page 1 data read: x6D x39 x81 xCF m9.. +2/27/22 7:55:33 PM :Debug: Read All Data +2/27/22 7:55:33 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:55:33 PM :Debug: DiffTime: 3 ms. +2/27/22 7:55:33 PM :Debug: Time to get Panels = 0ms. + +2/27/22 7:55:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:33 PM :Debug: Time:398.044s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:33 PM :Debug: Time:398.044s. + +2/27/22 7:55:33 PM :Debug: Time:398.044s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.111s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.111s. + +2/27/22 7:55:34 PM :Debug: Time:398.111s. ' . . . . . . . . . . . . . . . +2/27/22 7:55:34 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:55:34 PM :Info: Looks like Speeduino + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.18s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.18s. + +2/27/22 7:55:34 PM :Debug: Time:398.18s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.248s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.248s. + +2/27/22 7:55:34 PM :Debug: Time:398.248s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.313s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.313s. + +2/27/22 7:55:34 PM :Debug: Time:398.313s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.38s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.38s. + +2/27/22 7:55:34 PM :Debug: Time:398.38s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.447s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.447s. + +2/27/22 7:55:34 PM :Debug: Time:398.447s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.515s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.515s. + +2/27/22 7:55:34 PM :Debug: Time:398.515s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.582s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.582s. + +2/27/22 7:55:34 PM :Debug: Time:398.582s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.648s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.648s. + +2/27/22 7:55:34 PM :Debug: Time:398.648s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.711s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.711s. + +2/27/22 7:55:34 PM :Debug: Time:398.711s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.78s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.78s. + +2/27/22 7:55:34 PM :Debug: Time:398.78s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.849s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.849s. + +2/27/22 7:55:34 PM :Debug: Time:398.849s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.914s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.914s. + +2/27/22 7:55:34 PM :Debug: Time:398.915s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:398.976s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:398.976s. + +2/27/22 7:55:34 PM :Debug: Time:398.976s. ' . . . . . . . . . . . . . . . + +2/27/22 7:55:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:34 PM :Debug: Time:399.047s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:34 PM :Debug: Time:399.047s. + +2/27/22 7:55:34 PM :Debug: Time:399.047s. ' . . . . . . . . . . . . . . . +2/27/22 7:55:35 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. + +2/27/22 7:55:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:35 PM :Debug: Time:399.128s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:35 PM :Debug: Time:399.128s. + +2/27/22 7:55:35 PM :Debug: Time:399.128s. ' . . . . . . . . . . . . . . . +2/27/22 7:55:35 PM :Info: Time to save msq: 65.9357 +2/27/22 7:55:35 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:55:35 PM :Info: dirtyData.size(): 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 + +2/27/22 7:55:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:55:35 PM :Debug: Time:399.234s. 0x27 0xF8 0xFF 0xFF 0x0 0x0 0xFE 0x1 0x0 0x0 0xC4 0xFF 0x0 0x0 0x0 0x0 +2/27/22 7:55:35 PM :Debug: Time:399.234s. + +2/27/22 7:55:35 PM :Debug: Time:399.234s. ' . . . . . . . . . . . . . . . +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:35 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:35 PM :Debug: Flush lasted: 129ms. +2/27/22 7:55:35 PM :Debug: Burn Page anonymous: 1 +2/27/22 7:55:35 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:35 PM :Info: Queueing burn to page:1 +2/27/22 7:55:35 PM :Info: Sending, 76 bytes. +2/27/22 7:55:35 PM :Info: Loaded Restore point C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq + Sending, 76 bytes. +2/27/22 7:55:35 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:35 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:35 PM :Debug: Flush lasted: 1ms. +2/27/22 7:55:35 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:55:35 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:35 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:55:35 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:55:37 PM :Info: Time to save msq: 5.3615 +2/27/22 7:55:37 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:55:37 PM :Info: dirtyData.size(): 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:37 PM :Debug: removed expired instruction +2/27/22 7:55:37 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:37 PM :Debug: Flush lasted: 59ms. +2/27/22 7:55:37 PM :Debug: Burn Page anonymous: 1 +2/27/22 7:55:37 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:37 PM :Info: Queueing burn to page:1 +2/27/22 7:55:37 PM :Info: Sending, 76 bytes. +2/27/22 7:55:37 PM :Info: Loaded Restore point C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq + Sending, 76 bytes. +2/27/22 7:55:37 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:37 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:37 PM :Debug: Flush lasted: 1ms. +2/27/22 7:55:37 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:55:37 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:37 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:55:37 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:37 PM :Debug: Burn time:257ms. +2/27/22 7:55:37 PM :Debug: burned page 1 +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:37 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:37 PM :Info: Local Data CRC for page 1: xA0 x75 xEB xE3 .u.. +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Info: Retrying CRC call to see if it agrees after read: +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:37 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:37 PM :Info: Local Data CRC for page 1: xFE xC4 xBF x54 ...T +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:37 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:38 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:38 PM :Info: Local Data CRC for page 1: xFE xC4 xBF x54 ...T +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:38 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:854 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Read page time: 170ms. +2/27/22 7:55:39 PM :Info: Checksum page 1 data read: xB6 x2C x77 x0A .,w. +2/27/22 7:55:39 PM :Debug: Read All Data +2/27/22 7:55:39 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:55:39 PM :Debug: DiffTime: 1 ms. +2/27/22 7:55:39 PM :Debug: Time to get Panels = 0ms. +2/27/22 7:55:39 PM :Debug: Queued Write instructions:853 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:852 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:851 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:851 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:850 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:850 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:849 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:849 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:848 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:848 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:847 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:846 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:845 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:845 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:844 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:844 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:843 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:843 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:842 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:842 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:841 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:840 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:839 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:839 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:838 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:838 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:837 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:837 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:836 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:836 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:835 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:834 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:833 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:833 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:832 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:832 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:831 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:831 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:830 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:830 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:829 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:828 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:827 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:827 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:826 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:826 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:825 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:825 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:824 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:824 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:823 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:822 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:821 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:821 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:820 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:820 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:819 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:819 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:818 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:818 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:817 to page(s) 1, +2/27/22 7:55:39 PM :Debug: Queued Write instructions:817 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:815 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:815 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:814 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:814 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:813 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:813 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:812 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:812 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:811 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:811 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:809 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:809 to page(s) 1, +2/27/22 7:55:40 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:55:40 PM :Debug: Queued Write instructions:808 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:808 to page(s) 1, +2/27/22 7:55:40 PM :Info: Time to save msq: 10.2945 +2/27/22 7:55:40 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:55:40 PM :Info: dirtyData.size(): 1 +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Queued Write instructions:807 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Queued Write instructions:807 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:40 PM :Debug: removed expired instruction +2/27/22 7:55:40 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:40 PM :Debug: Flush lasted: 40ms. +2/27/22 7:55:40 PM :Debug: Burn Page anonymous: 1 +2/27/22 7:55:40 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:40 PM :Info: Queueing burn to page:1 +2/27/22 7:55:40 PM :Info: Sending, 88 bytes. +2/27/22 7:55:40 PM :Info: Loaded Restore point C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq + Sending, 88 bytes. +2/27/22 7:55:40 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:40 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:40 PM :Debug: Flush lasted: 0ms. +2/27/22 7:55:40 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:55:40 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:40 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:55:40 PM :Debug: Queued Write instructions:806 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:806 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:40 PM :Debug: Queued Write instructions:805 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:805 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:803 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:803 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:802 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:802 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:801 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:801 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:800 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:800 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:799 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:799 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:798 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:798 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:796 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:796 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:795 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:795 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:794 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:794 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:793 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:793 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:792 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:792 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:790 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:790 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:789 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:789 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:788 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:788 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:787 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:787 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:786 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:786 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:784 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:784 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:783 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:783 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:782 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:782 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:781 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:781 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:40 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Burn time:257ms. +2/27/22 7:55:41 PM :Debug: burned page 1 +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:41 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:41 PM :Info: Local Data CRC for page 1: xA0 x75 xEB xE3 .u.. +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Info: Retrying CRC call to see if it agrees after read: +2/27/22 7:55:41 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:41 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:41 PM :Info: Local Data CRC for page 1: x00 xC2 x3E x4E ..>N +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:41 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:42 PM :Info: CRC from controller page 1:x4C xD7 xB3 xAC L... +2/27/22 7:55:42 PM :Info: Local Data CRC for page 1: x00 xC2 x3E x4E ..>N +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:42 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Read page time: 171ms. +2/27/22 7:55:43 PM :Info: Checksum page 1 data read: xAC x7F x08 xD9 .... +2/27/22 7:55:43 PM :Debug: Read All Data +2/27/22 7:55:43 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:55:43 PM :Debug: DiffTime: 1 ms. +2/27/22 7:55:43 PM :Debug: Time to get Panels = 0ms. +2/27/22 7:55:43 PM :Debug: Queued Write instructions:779 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:779 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:778 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:769 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:769 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:769 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:763 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:763 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:763 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:757 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:757 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:757 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:754 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:754 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:753 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:751 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:751 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:751 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:748 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:748 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:747 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:43 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:739 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:739 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:739 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:732 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:732 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:732 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:729 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:726 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:726 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:726 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:723 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:720 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:720 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:720 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:715 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:715 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:715 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:714 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:714 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:714 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:713 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:713 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:713 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:712 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:712 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:712 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:711 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:711 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:711 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:710 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:709 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:709 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:708 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:708 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:708 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:707 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:707 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:707 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:706 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:706 to page(s) 1, +2/27/22 7:55:44 PM :Debug: Queued Write instructions:706 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:705 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:705 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:705 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:704 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:703 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:703 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:702 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:702 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:702 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:701 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:701 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:701 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:700 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:700 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:700 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:699 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:699 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:699 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:698 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:698 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:697 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:696 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:696 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:696 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:695 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:695 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:695 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:694 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:694 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:694 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:693 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:693 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:693 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:692 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:692 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:691 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:690 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:690 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:690 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:689 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:689 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:689 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:688 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:688 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:688 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:687 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:687 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:687 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:686 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:686 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:685 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:684 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:684 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:684 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:683 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:683 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:683 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:682 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:682 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:682 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:681 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:681 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:681 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:680 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:680 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:679 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:679 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:678 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:678 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:677 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:677 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:677 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:676 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:676 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:676 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:675 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:675 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:675 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:674 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:674 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:674 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:673 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:673 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:672 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:671 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:671 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:671 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:670 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:670 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:670 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:669 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:669 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:669 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:668 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:668 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:668 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:667 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:667 to page(s) 1, +2/27/22 7:55:45 PM :Debug: Queued Write instructions:666 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:666 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:665 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:665 to page(s) 1, +2/27/22 7:55:46 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:55:46 PM :Debug: Queued Write instructions:664 to page(s) 1, +2/27/22 7:55:46 PM :Info: Time to save msq: 6.5159 +2/27/22 7:55:46 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:55:46 PM :Debug: Queued Write instructions:664 to page(s) 1, +2/27/22 7:55:46 PM :Info: dirtyData.size(): 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 7:55:46 PM :Debug: removed expired instruction +2/27/22 7:55:46 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:46 PM :Debug: Flush lasted: 36ms. +2/27/22 7:55:46 PM :Debug: Burn Page anonymous: 1 +2/27/22 7:55:46 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:46 PM :Info: Queueing burn to page:1 +2/27/22 7:55:46 PM :Info: Sending, 88 bytes. +2/27/22 7:55:46 PM :Info: Loaded Restore point C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq + Sending, 88 bytes. +2/27/22 7:55:46 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:46 PM :Debug: Flush lasted: 70ms. +2/27/22 7:55:46 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:55:46 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:46 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:55:46 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Burn time:258ms. +2/27/22 7:55:46 PM :Debug: burned page 1 +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:46 PM :Info: CRC from controller page 1:x3F xAB x2E x2D ?..- +2/27/22 7:55:46 PM :Info: Local Data CRC for page 1: xA0 x75 xEB xE3 .u.. +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Info: Retrying CRC call to see if it agrees after read: +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:46 PM :Info: CRC from controller page 1:x3F xAB x2E x2D ?..- +2/27/22 7:55:46 PM :Info: Local Data CRC for page 1: xFB xBE x0E x24 ...$ +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:46 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:55:47 PM :Info: CRC from controller page 1:x3F xAB x2E x2D ?..- +2/27/22 7:55:47 PM :Info: Local Data CRC for page 1: xFB xBE x0E x24 ...$ +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:47 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:780 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Read page time: 171ms. +2/27/22 7:55:48 PM :Info: Checksum page 1 data read: xC0 xCC xF1 x96 .... +2/27/22 7:55:48 PM :Debug: Read All Data +2/27/22 7:55:48 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:55:48 PM :Debug: DiffTime: 1 ms. +2/27/22 7:55:48 PM :Debug: Time to get Panels = 0ms. +2/27/22 7:55:48 PM :Debug: Queued Write instructions:779 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:779 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:779 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:778 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:778 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:778 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:778 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:777 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:776 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:775 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:774 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:773 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:772 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:772 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:772 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:772 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:771 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:770 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:769 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:769 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:768 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:767 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:766 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:766 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:766 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:766 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:765 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:764 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:763 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:763 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:762 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:761 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:760 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:760 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:760 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:759 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:758 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:757 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:757 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:756 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:755 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:754 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:754 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:754 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:753 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:753 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:753 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:753 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:752 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:751 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:751 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:750 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:749 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:748 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:748 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:748 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:747 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:747 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:747 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:747 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:746 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:745 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:48 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:744 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:743 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:742 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:741 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:741 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:741 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:741 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:740 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:739 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:739 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:738 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:737 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:736 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:735 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:735 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:735 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:734 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:733 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:732 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:732 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:731 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:730 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:729 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:729 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:729 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:728 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:727 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:726 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:725 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:724 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:723 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:723 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:723 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:722 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:721 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:720 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:720 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:719 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:718 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:717 to page(s) 1, +2/27/22 7:55:49 PM :Debug: Queued Write instructions:716 to page(s) 1, +2/27/22 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instructions:630 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:629 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:629 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:629 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:628 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:628 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:628 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:628 to page(s) 1, +2/27/22 7:55:51 PM :Debug: Queued Write instructions:627 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:627 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:627 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:627 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:626 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:626 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:625 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:625 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:625 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:624 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:624 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:624 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:624 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:623 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:623 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:623 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:623 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:622 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:622 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:622 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:621 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:621 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:621 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:621 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:620 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:620 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:619 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:619 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:619 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:618 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:618 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:618 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:618 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:617 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:617 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:617 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:616 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:616 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:616 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:616 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:615 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:615 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:615 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:615 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:614 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:614 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:613 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:613 to page(s) 1, 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page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:609 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:609 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:608 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:608 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:608 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:608 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:607 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:606 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:606 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:606 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:606 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:605 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:605 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:605 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:605 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:604 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:604 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:604 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:603 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:603 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:603 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:603 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:602 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:602 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:602 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:602 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:601 to page(s) 1, +2/27/22 7:55:52 PM :Debug: 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:Debug: Queued Write instructions:597 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:596 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:596 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:596 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:596 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:595 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:595 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:594 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:594 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:594 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:593 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:593 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:593 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:593 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:592 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:592 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:592 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:591 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:591 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:591 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:591 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:590 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:590 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:590 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:590 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:589 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:589 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:588 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:588 to page(s) 1, +2/27/22 7:55:52 PM :Debug: Queued Write instructions:588 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 7:55:53 PM :Info: Initiating read page 1 : 826:2 +2/27/22 7:55:53 PM :Debug: Queued Write instructions:587 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:587 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:587 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:587 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:586 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:586 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:586 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:586 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:585 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:585 to page(s) 1, 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page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:580 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:580 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:580 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:580 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:579 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:579 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:579 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:578 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:578 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:578 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:578 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:577 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:577 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write 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:Debug: Queued Write instructions:568 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:568 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:568 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:567 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:567 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:567 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:566 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:566 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:566 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:566 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:565 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:565 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:565 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:565 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:564 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:564 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:564 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:564 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:563 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:562 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:562 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:562 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:562 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:561 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:561 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:561 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:561 to page(s) 1, +2/27/22 7:55:53 PM :Debug: Queued Write instructions:560 to page(s) 1, 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:Debug: Queued Write instructions:543 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:543 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:543 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:543 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:542 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:542 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:542 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:541 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:541 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:541 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:541 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:540 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:539 to page(s) 1, +2/27/22 7:55:54 PM :Debug: Queued Write instructions:539 to page(s) 1, +2/27/22 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:Debug: Queued Write instructions:494 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:493 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:493 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:493 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:493 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:492 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:492 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:492 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:492 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:491 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:491 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:491 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:490 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:490 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:489 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:489 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:489 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:489 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:488 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:488 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:488 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:487 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:487 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:487 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:487 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:486 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:486 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:486 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:486 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:485 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:485 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:485 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:484 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:484 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:483 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:483 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:483 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:483 to page(s) 1, +2/27/22 7:55:55 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:55 PM :Debug: Queued Write instructions:482 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:482 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:482 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:481 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:481 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:481 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:481 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:480 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:480 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:480 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:480 to page(s) 1, +2/27/22 7:55:55 PM :Info: dirtyData.size(): 0 +2/27/22 7:55:55 PM :Debug: Flush lasted: 70ms. +2/27/22 7:55:55 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:55:55 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:55:55 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:55:55 PM :Debug: Queued Write instructions:479 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:479 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:479 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:478 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:478 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:477 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:477 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:477 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:477 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:476 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:476 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:476 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:475 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:475 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:475 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:475 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:474 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:474 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:474 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:474 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:473 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:473 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:473 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:472 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:472 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:471 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:471 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:471 to page(s) 1, +2/27/22 7:55:55 PM :Debug: Queued Write instructions:471 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:470 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:470 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:470 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:469 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:469 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:469 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:469 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:468 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:468 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:468 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:468 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:467 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:467 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:467 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:466 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:466 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:466 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:465 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:465 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:465 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:464 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:464 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:464 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:463 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:463 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:463 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:463 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:462 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:462 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:462 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:462 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:461 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:461 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:461 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:461 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:460 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:460 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:460 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:459 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:459 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:458 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:458 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:458 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:458 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:457 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:457 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:457 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:456 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:456 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:456 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:456 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:455 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:455 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:455 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:455 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:454 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:454 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:454 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:453 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:453 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:453 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:452 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:452 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:452 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:451 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:451 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:451 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:450 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:450 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:450 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:450 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:449 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:449 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:449 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:449 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:448 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:448 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:448 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:448 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:447 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:447 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:447 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:446 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:446 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:445 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:445 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:445 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:445 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:444 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:444 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:444 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:443 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:443 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:443 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:443 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:442 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:442 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:442 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:442 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:441 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:441 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:441 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:440 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:440 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:439 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:439 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:439 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:439 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:438 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:438 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:438 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:437 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:437 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:437 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:437 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:436 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:436 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:436 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:436 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:435 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:435 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:435 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:434 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:434 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:433 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:433 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:433 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:433 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:432 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:432 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:432 to page(s) 1, +2/27/22 7:55:56 PM :Debug: Queued Write instructions:431 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:431 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:431 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:431 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:430 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:430 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:430 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:430 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:429 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:429 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:429 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:429 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:428 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:427 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:427 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:427 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:427 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:426 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:426 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:426 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:425 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:425 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:425 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:425 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:424 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:424 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:424 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:424 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:423 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:423 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:423 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:423 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:422 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:422 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:421 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:421 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:421 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:420 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:420 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:420 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:420 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:419 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:419 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:419 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:418 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:418 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:418 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:418 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:417 to page(s) 1, +2/27/22 7:55:57 PM :Debug: Queued Write instructions:417 to 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:Debug: Queued Write instructions:157 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:157 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:156 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:156 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:156 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:156 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:155 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:155 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:155 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:154 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:154 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:154 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:154 to page(s) 1, +2/27/22 7:56:04 PM :Debug: Queued Write instructions:153 to page(s) 1, +2/27/22 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+2/27/22 7:56:07 PM :Debug: Queued Write instructions:28 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:27 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:27 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:27 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:27 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:26 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:26 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:26 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:26 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:25 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:25 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:25 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:25 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:24 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:24 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:23 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:23 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:22 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:22 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:22 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:22 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:21 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:21 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:21 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:21 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:20 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:20 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:20 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:20 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:19 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:19 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:19 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:19 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:18 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:18 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:17 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:17 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:16 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:16 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:16 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:16 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:15 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:15 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:15 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:15 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:14 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:14 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:14 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:14 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:13 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:13 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:13 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:13 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:12 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:12 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:12 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:12 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:11 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:11 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:10 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:10 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:9 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:9 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:9 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:9 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:8 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:8 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:8 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:8 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:7 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:7 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:7 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:7 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:6 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:6 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:6 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:6 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:5 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:5 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:4 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:4 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:3 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:3 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:3 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:3 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:2 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:2 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:2 to page(s) 1, +2/27/22 7:56:07 PM :Debug: Queued Write instructions:2 to page(s) 1, +2/27/22 7:56:08 PM :Debug: Queued Write instructions:1 to page(s) 1, +2/27/22 7:56:08 PM :Debug: Queued Write instructions:1 to page(s) 1, +2/27/22 7:56:08 PM :Debug: Queued Write instructions:1 to page(s) 1, +2/27/22 7:56:08 PM :Debug: Queued Write instructions:1 to page(s) 1, +2/27/22 7:56:08 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:08 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:08 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:08 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:08 PM :Debug: Burn time:257ms. +2/27/22 7:56:08 PM :Debug: burned page 1 +2/27/22 7:56:08 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 7:56:09 PM :Info: Time to save msq: 2.9581 +2/27/22 7:56:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 7:56:10 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:56:10 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:56:10 PM :Debug: Burn Page anonymous: -1 +2/27/22 7:56:10 PM :Debug: Received Instruction: , Page: 1 +2/27/22 7:56:10 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 7:56:10 PM :Debug: goOffline about to stopProcessing, Time:251 +2/27/22 7:56:10 PM :Debug: controllerOnline = 0.0 +2/27/22 7:56:10 PM :Debug: goOffline Notified offline, Time:253 +2/27/22 7:56:10 PM :Debug: goOffline closed port, Time:253 +2/27/22 7:56:10 PM :Debug: Deactivated fast paint Main Dashboard +2/27/22 7:56:11 PM :Debug: goOffline comm thread stopped, Time:753 +2/27/22 7:56:11 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:11 PM :Debug: can not close Port: jssc.SerialPort@165f580, message: Port name - COM8; Method name - setEventsMask(); Exception type - Can't set mask. +2/27/22 7:56:11 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread96853.57914539523 +2/27/22 7:56:29 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:56:29 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:56:29 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 7:56:29 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:56:29 PM :Debug: goOffline Starting, Time:0 +2/27/22 7:56:29 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 7:56:29 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 7:56:29 PM :Debug: goOffline closed port, Time:1 +2/27/22 7:56:29 PM :Debug: set baud to 115200 +2/27/22 7:56:29 PM :Debug: set baud to 115200 +2/27/22 7:56:30 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:56:30 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:30 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 7:56:30 PM :Debug: No Remaining Queue Write instructions +2/27/22 7:56:32 PM :Debug: set baud to 115200 +2/27/22 7:56:32 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 7:56:32 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread96853.57914539523, new Thread:Thread-80 +2/27/22 7:56:33 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:56:34 PM :Debug: set baud to 115200 +2/27/22 7:56:34 PM :Info: Com Thread created: COMM Thread58384.68729449401 +2/27/22 7:56:34 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread58384.68729449401 +2/27/22 7:56:34 PM :Info: Comm Read Thread Change! Old Thread:Thread-80, new Thread:COMM Thread58384.68729449401 +2/27/22 7:56:34 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:56:35 PM :Info: Communicating with sig:speeduino dbw_v0.80, speeduino dbw_v0.80 +2/27/22 7:56:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:35 PM :Info: Looks like Speeduino +2/27/22 7:56:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:35 PM :Info: Looks like Speeduino +2/27/22 7:56:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:35 PM :Info: Looks like Speeduino +2/27/22 7:56:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:35 PM :Info: Looks like Speeduino +2/27/22 7:56:37 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:56:37 PM :Debug: controllerOnline = 1.0 +2/27/22 7:56:37 PM :Warning: COM8 port instance already found, trying to close. +2/27/22 7:56:38 PM :Debug: Read from RS232: Port:COM8, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:56:38 PM :Info: Timeout reading page 1, increased blockReadTimeout to 1051, trying once more. +2/27/22 7:56:40 PM :Debug: Read All Data +2/27/22 7:56:40 PM :Debug: result.FAILED: 1 tryCount +2/27/22 7:56:41 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x64 x62 x77 x5F x76 x30 speeduino.dbw_v0 +x2E x38 x30 x00 .80. +2/27/22 7:56:41 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:56:42 PM :Info: Communicating with sig:speeduino dbw_v0.80, speeduino dbw_v0.80 +2/27/22 7:56:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:42 PM :Info: Looks like Speeduino +2/27/22 7:56:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:42 PM :Info: Looks like Speeduino +2/27/22 7:56:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:42 PM :Info: Looks like Speeduino +2/27/22 7:56:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:42 PM :Info: Looks like Speeduino +2/27/22 7:56:43 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 7:56:43 PM :Debug: controllerOnline = 1.0 +2/27/22 7:56:43 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:56:43 PM :Info: CRC from controller page 1:x3F xAB x2E x2D ?..- +2/27/22 7:56:43 PM :Info: Local Data CRC for page 1: xC0 xCC xF1 x96 .... +2/27/22 7:56:43 PM :Debug: Read page time: 172ms. +2/27/22 7:56:43 PM :Info: Checksum page 1 data read: xF5 xC2 x75 x09 ..u. +2/27/22 7:56:43 PM :Debug: Read All Data +2/27/22 7:56:43 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:56:43 PM :Debug: DiffTime: 1 ms. +2/27/22 7:56:43 PM :Debug: Time to get Panels = 0ms. +2/27/22 7:56:44 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 7:56:44 PM :Info: CRC from controller page 1:x3F xAB x2E x2D ?..- +2/27/22 7:56:44 PM :Info: Local Data CRC for page 1: xF5 xC2 x75 x09 ..u. +2/27/22 7:56:44 PM :Debug: Read page time: 171ms. +2/27/22 7:56:44 PM :Info: Checksum page 1 data read: x68 x94 x16 x43 h..C +2/27/22 7:56:44 PM :Debug: Read All Data +2/27/22 7:56:44 PM :Debug: isBlank Time: 0 ms. +2/27/22 7:56:44 PM :Debug: DiffTime: 2 ms. +2/27/22 7:56:44 PM :Debug: Time to get Panels = 0ms. + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.56s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.56s. + +2/27/22 7:56:44 PM :Debug: Time:468.56s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.623s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF8 0x0 0x0 0x0 0x1A 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.623s. + +2/27/22 7:56:44 PM :Debug: Time:468.623s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.703s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.703s. + +2/27/22 7:56:44 PM :Debug: Time:468.703s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0xA 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.772s. + +2/27/22 7:56:44 PM :Debug: Time:468.772s. . & . . . . . . + . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.839s. + +2/27/22 7:56:44 PM :Debug: Time:468.839s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.905s. + +2/27/22 7:56:44 PM :Debug: Time:468.905s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:468.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:468.973s. + +2/27/22 7:56:44 PM :Debug: Time:468.973s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:44 PM :Debug: Time:469.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:44 PM :Debug: Time:469.037s. + +2/27/22 7:56:44 PM :Debug: Time:469.037s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.104s. + +2/27/22 7:56:45 PM :Debug: Time:469.104s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.172s. + +2/27/22 7:56:45 PM :Debug: Time:469.172s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.236s. + +2/27/22 7:56:45 PM :Debug: Time:469.236s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.303s. + +2/27/22 7:56:45 PM :Debug: Time:469.303s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.372s. + +2/27/22 7:56:45 PM :Debug: Time:469.372s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.438s. + +2/27/22 7:56:45 PM :Debug: Time:469.438s. . & . . . . . . . . . . . . . . +2/27/22 7:56:45 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:45 PM :Info: Looks like Speeduino + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.506s. + +2/27/22 7:56:45 PM :Debug: Time:469.506s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.566s. + +2/27/22 7:56:45 PM :Debug: Time:469.566s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.629s. + +2/27/22 7:56:45 PM :Debug: Time:469.629s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.706s. + +2/27/22 7:56:45 PM :Debug: Time:469.706s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF9 0x0 0x14 0x0 0x19 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.774s. + +2/27/22 7:56:45 PM :Debug: Time:469.774s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.84s. + +2/27/22 7:56:45 PM :Debug: Time:469.84s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.907s. + +2/27/22 7:56:45 PM :Debug: Time:469.907s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:469.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:469.974s. + +2/27/22 7:56:45 PM :Debug: Time:469.974s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:45 PM :Debug: Time:470.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:45 PM :Debug: Time:470.041s. + +2/27/22 7:56:45 PM :Debug: Time:470.041s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.108s. + +2/27/22 7:56:46 PM :Debug: Time:470.108s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.176s. + +2/27/22 7:56:46 PM :Debug: Time:470.176s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.24s. + +2/27/22 7:56:46 PM :Debug: Time:470.24s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.302s. + +2/27/22 7:56:46 PM :Debug: Time:470.302s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.374s. + +2/27/22 7:56:46 PM :Debug: Time:470.374s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.44s. + +2/27/22 7:56:46 PM :Debug: Time:470.44s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.507s. + +2/27/22 7:56:46 PM :Debug: Time:470.507s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.574s. + +2/27/22 7:56:46 PM :Debug: Time:470.574s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.639s. + +2/27/22 7:56:46 PM :Debug: Time:470.639s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.707s. + +2/27/22 7:56:46 PM :Debug: Time:470.707s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.773s. + +2/27/22 7:56:46 PM :Debug: Time:470.773s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.84s. + +2/27/22 7:56:46 PM :Debug: Time:470.84s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.908s. + +2/27/22 7:56:46 PM :Debug: Time:470.908s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:470.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:470.975s. + +2/27/22 7:56:46 PM :Debug: Time:470.975s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:46 PM :Debug: Time:471.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:46 PM :Debug: Time:471.036s. + +2/27/22 7:56:46 PM :Debug: Time:471.036s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.107s. + +2/27/22 7:56:47 PM :Debug: Time:471.107s. . & . . . . . . . . . . . . . . +2/27/22 7:56:47 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:47 PM :Info: Looks like Speeduino + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.174s. + +2/27/22 7:56:47 PM :Debug: Time:471.174s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.24s. + +2/27/22 7:56:47 PM :Debug: Time:471.24s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.308s. + +2/27/22 7:56:47 PM :Debug: Time:471.308s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.377s. + +2/27/22 7:56:47 PM :Debug: Time:471.377s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.441s. + +2/27/22 7:56:47 PM :Debug: Time:471.441s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.51s. + +2/27/22 7:56:47 PM :Debug: Time:471.51s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.578s. + +2/27/22 7:56:47 PM :Debug: Time:471.578s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.642s. + +2/27/22 7:56:47 PM :Debug: Time:471.642s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.711s. + +2/27/22 7:56:47 PM :Debug: Time:471.711s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.778s. + +2/27/22 7:56:47 PM :Debug: Time:471.778s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.842s. + +2/27/22 7:56:47 PM :Debug: Time:471.842s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.91s. + +2/27/22 7:56:47 PM :Debug: Time:471.91s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:471.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:471.976s. + +2/27/22 7:56:47 PM :Debug: Time:471.976s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:47 PM :Debug: Time:472.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0xA 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:47 PM :Debug: Time:472.041s. + +2/27/22 7:56:47 PM :Debug: Time:472.041s. . & . . . . . . + . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.109s. + +2/27/22 7:56:48 PM :Debug: Time:472.109s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.176s. + +2/27/22 7:56:48 PM :Debug: Time:472.176s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.242s. + +2/27/22 7:56:48 PM :Debug: Time:472.242s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xFB 0x0 0x32 0x0 0x17 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.309s. + +2/27/22 7:56:48 PM :Debug: Time:472.309s. . & . . . . . . 2 . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.378s. + +2/27/22 7:56:48 PM :Debug: Time:472.378s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF7 0x0 0x0 0x0 0x1B 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.443s. + +2/27/22 7:56:48 PM :Debug: Time:472.443s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.51s. + +2/27/22 7:56:48 PM :Debug: Time:472.51s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.577s. + +2/27/22 7:56:48 PM :Debug: Time:472.577s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.642s. + +2/27/22 7:56:48 PM :Debug: Time:472.642s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.709s. + +2/27/22 7:56:48 PM :Debug: Time:472.709s. . & . . . . . . . . . . . . . . +2/27/22 7:56:48 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:48 PM :Info: Looks like Speeduino + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.778s. + +2/27/22 7:56:48 PM :Debug: Time:472.778s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.843s. + +2/27/22 7:56:48 PM :Debug: Time:472.843s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.911s. + +2/27/22 7:56:48 PM :Debug: Time:472.911s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:472.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:472.978s. + +2/27/22 7:56:48 PM :Debug: Time:472.978s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:48 PM :Debug: Time:473.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:48 PM :Debug: Time:473.042s. + +2/27/22 7:56:48 PM :Debug: Time:473.042s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.11s. + +2/27/22 7:56:49 PM :Debug: Time:473.11s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.178s. + +2/27/22 7:56:49 PM :Debug: Time:473.178s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.246s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.246s. + +2/27/22 7:56:49 PM :Debug: Time:473.246s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0xA 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.312s. + +2/27/22 7:56:49 PM :Debug: Time:473.312s. . & . . . . . . + . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.379s. + +2/27/22 7:56:49 PM :Debug: Time:473.379s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.443s. + +2/27/22 7:56:49 PM :Debug: Time:473.443s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.512s. + +2/27/22 7:56:49 PM :Debug: Time:473.512s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0xF6 0xFF 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.579s. + +2/27/22 7:56:49 PM :Debug: Time:473.579s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.645s. + +2/27/22 7:56:49 PM :Debug: Time:473.645s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.715s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.715s. + +2/27/22 7:56:49 PM :Debug: Time:473.715s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.778s. + +2/27/22 7:56:49 PM :Debug: Time:473.778s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.846s. + +2/27/22 7:56:49 PM :Debug: Time:473.846s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.913s. + +2/27/22 7:56:49 PM :Debug: Time:473.913s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:473.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:473.974s. + +2/27/22 7:56:49 PM :Debug: Time:473.974s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:49 PM :Debug: Time:474.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:49 PM :Debug: Time:474.044s. + +2/27/22 7:56:49 PM :Debug: Time:474.044s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.116s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.116s. + +2/27/22 7:56:50 PM :Debug: Time:474.116s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.183s. + +2/27/22 7:56:50 PM :Debug: Time:474.183s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.244s. + +2/27/22 7:56:50 PM :Debug: Time:474.244s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.313s. + +2/27/22 7:56:50 PM :Debug: Time:474.313s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.381s. + +2/27/22 7:56:50 PM :Debug: Time:474.381s. . & . . . . . . . . . . . . . . +2/27/22 7:56:50 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:50 PM :Info: Looks like Speeduino + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.447s. + +2/27/22 7:56:50 PM :Debug: Time:474.447s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.513s. + +2/27/22 7:56:50 PM :Debug: Time:474.513s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.58s. + +2/27/22 7:56:50 PM :Debug: Time:474.58s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0 0x12 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.646s. + +2/27/22 7:56:50 PM :Debug: Time:474.646s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF8 0x0 0x0 0x0 0x1A 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.714s. + +2/27/22 7:56:50 PM :Debug: Time:474.714s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.781s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF6 0x0 0x0 0x0 0x1C 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.781s. + +2/27/22 7:56:50 PM :Debug: Time:474.781s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.846s. + +2/27/22 7:56:50 PM :Debug: Time:474.846s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.913s. + +2/27/22 7:56:50 PM :Debug: Time:474.913s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:474.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:474.981s. + +2/27/22 7:56:50 PM :Debug: Time:474.981s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:50 PM :Debug: Time:475.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:50 PM :Debug: Time:475.046s. + +2/27/22 7:56:50 PM :Debug: Time:475.046s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0xF6 0xFF 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.114s. + +2/27/22 7:56:51 PM :Debug: Time:475.115s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.175s. + +2/27/22 7:56:51 PM :Debug: Time:475.175s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.238s. + +2/27/22 7:56:51 PM :Debug: Time:475.238s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.315s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.315s. + +2/27/22 7:56:51 PM :Debug: Time:475.315s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.383s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.383s. + +2/27/22 7:56:51 PM :Debug: Time:475.383s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.452s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.452s. + +2/27/22 7:56:51 PM :Debug: Time:475.452s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.518s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.518s. + +2/27/22 7:56:51 PM :Debug: Time:475.518s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.586s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.586s. + +2/27/22 7:56:51 PM :Debug: Time:475.586s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.65s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.65s. + +2/27/22 7:56:51 PM :Debug: Time:475.65s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.719s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.719s. + +2/27/22 7:56:51 PM :Debug: Time:475.719s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.786s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.786s. + +2/27/22 7:56:51 PM :Debug: Time:475.786s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.851s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0xA 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.851s. + +2/27/22 7:56:51 PM :Debug: Time:475.851s. . & . . . . . . + . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.917s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.917s. + +2/27/22 7:56:51 PM :Debug: Time:475.917s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:475.985s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:475.985s. + +2/27/22 7:56:51 PM :Debug: Time:475.985s. . & . . . . . . . . . . . . . . +2/27/22 7:56:51 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:51 PM :Info: Looks like Speeduino + +2/27/22 7:56:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:51 PM :Debug: Time:476.051s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:51 PM :Debug: Time:476.051s. + +2/27/22 7:56:51 PM :Debug: Time:476.051s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.119s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.119s. + +2/27/22 7:56:52 PM :Debug: Time:476.119s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.18s. + +2/27/22 7:56:52 PM :Debug: Time:476.18s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.243s. + +2/27/22 7:56:52 PM :Debug: Time:476.243s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.32s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.32s. + +2/27/22 7:56:52 PM :Debug: Time:476.32s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.388s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.388s. + +2/27/22 7:56:52 PM :Debug: Time:476.388s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.457s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.457s. + +2/27/22 7:56:52 PM :Debug: Time:476.457s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.523s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.523s. + +2/27/22 7:56:52 PM :Debug: Time:476.523s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.591s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0xF6 0xFF 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.591s. + +2/27/22 7:56:52 PM :Debug: Time:476.591s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.655s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.655s. + +2/27/22 7:56:52 PM :Debug: Time:476.655s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.722s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.722s. + +2/27/22 7:56:52 PM :Debug: Time:476.722s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.79s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.79s. + +2/27/22 7:56:52 PM :Debug: Time:476.79s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.854s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0xF6 0xFF 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.854s. + +2/27/22 7:56:52 PM :Debug: Time:476.854s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.922s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0x0 0x0 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.922s. + +2/27/22 7:56:52 PM :Debug: Time:476.922s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:476.99s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:476.99s. + +2/27/22 7:56:52 PM :Debug: Time:476.99s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:52 PM :Debug: Time:477.056s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:52 PM :Debug: Time:477.056s. + +2/27/22 7:56:52 PM :Debug: Time:477.056s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.123s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.123s. + +2/27/22 7:56:53 PM :Debug: Time:477.123s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.184s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.184s. + +2/27/22 7:56:53 PM :Debug: Time:477.184s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.248s. + +2/27/22 7:56:53 PM :Debug: Time:477.248s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.326s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.326s. + +2/27/22 7:56:53 PM :Debug: Time:477.326s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.395s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.395s. + +2/27/22 7:56:53 PM :Debug: Time:477.395s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.462s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.462s. + +2/27/22 7:56:53 PM :Debug: Time:477.462s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.529s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.529s. + +2/27/22 7:56:53 PM :Debug: Time:477.529s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.596s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.596s. + +2/27/22 7:56:53 PM :Debug: Time:477.596s. . & . . . . . . . . . . . . . . +2/27/22 7:56:53 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:53 PM :Info: Looks like Speeduino + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.661s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.661s. + +2/27/22 7:56:53 PM :Debug: Time:477.661s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.729s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.729s. + +2/27/22 7:56:53 PM :Debug: Time:477.729s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.798s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.798s. + +2/27/22 7:56:53 PM :Debug: Time:477.798s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.861s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.861s. + +2/27/22 7:56:53 PM :Debug: Time:477.861s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.929s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.929s. + +2/27/22 7:56:53 PM :Debug: Time:477.929s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:477.996s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:477.996s. + +2/27/22 7:56:53 PM :Debug: Time:477.996s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:53 PM :Debug: Time:478.061s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:53 PM :Debug: Time:478.061s. + +2/27/22 7:56:53 PM :Debug: Time:478.061s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.129s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.129s. + +2/27/22 7:56:54 PM :Debug: Time:478.129s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.19s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.19s. + +2/27/22 7:56:54 PM :Debug: Time:478.19s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.254s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.254s. + +2/27/22 7:56:54 PM :Debug: Time:478.254s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.329s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.329s. + +2/27/22 7:56:54 PM :Debug: Time:478.329s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.398s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.398s. + +2/27/22 7:56:54 PM :Debug: Time:478.398s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.463s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.463s. + +2/27/22 7:56:54 PM :Debug: Time:478.463s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.53s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.53s. + +2/27/22 7:56:54 PM :Debug: Time:478.53s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.597s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.597s. + +2/27/22 7:56:54 PM :Debug: Time:478.597s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.665s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.665s. + +2/27/22 7:56:54 PM :Debug: Time:478.665s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.732s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.732s. + +2/27/22 7:56:54 PM :Debug: Time:478.732s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.799s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.799s. + +2/27/22 7:56:54 PM :Debug: Time:478.799s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.862s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.862s. + +2/27/22 7:56:54 PM :Debug: Time:478.862s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:478.931s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:478.931s. + +2/27/22 7:56:54 PM :Debug: Time:478.931s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:54 PM :Debug: Time:479.01s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:54 PM :Debug: Time:479.01s. + +2/27/22 7:56:54 PM :Debug: Time:479.01s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.075s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.075s. + +2/27/22 7:56:55 PM :Debug: Time:479.075s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.144s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.144s. + +2/27/22 7:56:55 PM :Debug: Time:479.144s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.208s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.208s. + +2/27/22 7:56:55 PM :Debug: Time:479.208s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.278s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.278s. + +2/27/22 7:56:55 PM :Debug: Time:479.278s. . & . . . . . . . . . . . . . . +2/27/22 7:56:55 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:55 PM :Info: Looks like Speeduino + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.345s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x0 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.345s. + +2/27/22 7:56:55 PM :Debug: Time:479.345s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.411s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.411s. + +2/27/22 7:56:55 PM :Debug: Time:479.411s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.479s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.479s. + +2/27/22 7:56:55 PM :Debug: Time:479.479s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.546s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0xF6 0xFF 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.546s. + +2/27/22 7:56:55 PM :Debug: Time:479.546s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.613s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.613s. + +2/27/22 7:56:55 PM :Debug: Time:479.613s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.678s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.678s. + +2/27/22 7:56:55 PM :Debug: Time:479.678s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.748s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.748s. + +2/27/22 7:56:55 PM :Debug: Time:479.748s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.815s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.815s. + +2/27/22 7:56:55 PM :Debug: Time:479.815s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.883s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.883s. + +2/27/22 7:56:55 PM :Debug: Time:479.883s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:479.95s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:479.95s. + +2/27/22 7:56:55 PM :Debug: Time:479.95s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:55 PM :Debug: Time:480.018s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:55 PM :Debug: Time:480.018s. + +2/27/22 7:56:55 PM :Debug: Time:480.018s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.082s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.082s. + +2/27/22 7:56:56 PM :Debug: Time:480.082s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.15s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.15s. + +2/27/22 7:56:56 PM :Debug: Time:480.15s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.218s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.218s. + +2/27/22 7:56:56 PM :Debug: Time:480.218s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.282s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.282s. + +2/27/22 7:56:56 PM :Debug: Time:480.282s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.35s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.35s. + +2/27/22 7:56:56 PM :Debug: Time:480.35s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.418s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.418s. + +2/27/22 7:56:56 PM :Debug: Time:480.418s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.483s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.483s. + +2/27/22 7:56:56 PM :Debug: Time:480.483s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.55s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.55s. + +2/27/22 7:56:56 PM :Debug: Time:480.55s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.617s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.617s. + +2/27/22 7:56:56 PM :Debug: Time:480.617s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.682s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.682s. + +2/27/22 7:56:56 PM :Debug: Time:480.682s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.749s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.749s. + +2/27/22 7:56:56 PM :Debug: Time:480.749s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.817s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.817s. + +2/27/22 7:56:56 PM :Debug: Time:480.817s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.877s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.877s. + +2/27/22 7:56:56 PM :Debug: Time:480.877s. . & . . . . . . . . . . . . . . +2/27/22 7:56:56 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:56 PM :Info: Looks like Speeduino + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:480.949s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:480.949s. + +2/27/22 7:56:56 PM :Debug: Time:480.949s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:56 PM :Debug: Time:481.017s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:56 PM :Debug: Time:481.017s. + +2/27/22 7:56:56 PM :Debug: Time:481.017s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.083s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.083s. + +2/27/22 7:56:57 PM :Debug: Time:481.083s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.15s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.15s. + +2/27/22 7:56:57 PM :Debug: Time:481.15s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.218s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.218s. + +2/27/22 7:56:57 PM :Debug: Time:481.218s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.284s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.284s. + +2/27/22 7:56:57 PM :Debug: Time:481.284s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.351s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.351s. + +2/27/22 7:56:57 PM :Debug: Time:481.351s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.419s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.419s. + +2/27/22 7:56:57 PM :Debug: Time:481.419s. . & . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.483s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.483s. + +2/27/22 7:56:57 PM :Debug: Time:481.483s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.552s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.552s. + +2/27/22 7:56:57 PM :Debug: Time:481.552s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.619s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.619s. + +2/27/22 7:56:57 PM :Debug: Time:481.619s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.685s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.685s. + +2/27/22 7:56:57 PM :Debug: Time:481.685s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.752s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.752s. + +2/27/22 7:56:57 PM :Debug: Time:481.752s. . & . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.82s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.82s. + +2/27/22 7:56:57 PM :Debug: Time:481.82s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.886s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.886s. + +2/27/22 7:56:57 PM :Debug: Time:481.886s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:481.953s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:481.953s. + +2/27/22 7:56:57 PM :Debug: Time:481.953s. . & . . . . . . . . . . . . . + +2/27/22 7:56:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:57 PM :Debug: Time:482.02s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:57 PM :Debug: Time:482.02s. + +2/27/22 7:56:57 PM :Debug: Time:482.02s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.085s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.085s. + +2/27/22 7:56:58 PM :Debug: Time:482.085s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.153s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.153s. + +2/27/22 7:56:58 PM :Debug: Time:482.153s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.23s. + +2/27/22 7:56:58 PM :Debug: Time:482.23s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0xF6 0xFF 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.3s. + +2/27/22 7:56:58 PM :Debug: Time:482.3s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.368s. + +2/27/22 7:56:58 PM :Debug: Time:482.368s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.435s. + +2/27/22 7:56:58 PM :Debug: Time:482.435s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.501s. + +2/27/22 7:56:58 PM :Debug: Time:482.501s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.568s. + +2/27/22 7:56:58 PM :Debug: Time:482.568s. . & . . . . . . . . . . . . . +2/27/22 7:56:58 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:56:58 PM :Info: Looks like Speeduino + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.635s. + +2/27/22 7:56:58 PM :Debug: Time:482.635s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.702s. + +2/27/22 7:56:58 PM :Debug: Time:482.702s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.77s. + +2/27/22 7:56:58 PM :Debug: Time:482.77s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.832s. + +2/27/22 7:56:58 PM :Debug: Time:482.832s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.902s. + +2/27/22 7:56:58 PM :Debug: Time:482.902s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:482.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:482.969s. + +2/27/22 7:56:58 PM :Debug: Time:482.969s. . & . . . . . . . . . . . . . + +2/27/22 7:56:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:58 PM :Debug: Time:483.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:58 PM :Debug: Time:483.036s. + +2/27/22 7:56:58 PM :Debug: Time:483.036s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.104s. + +2/27/22 7:56:59 PM :Debug: Time:483.104s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.171s. + +2/27/22 7:56:59 PM :Debug: Time:483.171s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.243s. + +2/27/22 7:56:59 PM :Debug: Time:483.243s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.302s. + +2/27/22 7:56:59 PM :Debug: Time:483.302s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.371s. + +2/27/22 7:56:59 PM :Debug: Time:483.371s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.44s. + +2/27/22 7:56:59 PM :Debug: Time:483.44s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.508s. + +2/27/22 7:56:59 PM :Debug: Time:483.508s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.572s. + +2/27/22 7:56:59 PM :Debug: Time:483.572s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.64s. + +2/27/22 7:56:59 PM :Debug: Time:483.64s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF4 0x0 0x14 0x0 0x1E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.709s. + +2/27/22 7:56:59 PM :Debug: Time:483.709s. . & . . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0xEC 0xFF 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.77s. + +2/27/22 7:56:59 PM :Debug: Time:483.77s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.84s. + +2/27/22 7:56:59 PM :Debug: Time:483.84s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.907s. + +2/27/22 7:56:59 PM :Debug: Time:483.907s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:483.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:483.973s. + +2/27/22 7:56:59 PM :Debug: Time:483.973s. . & . . . . . . . . . . . . . + +2/27/22 7:56:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:56:59 PM :Debug: Time:484.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:56:59 PM :Debug: Time:484.036s. + +2/27/22 7:56:59 PM :Debug: Time:484.036s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.106s. + +2/27/22 7:57:00 PM :Debug: Time:484.106s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.173s. + +2/27/22 7:57:00 PM :Debug: Time:484.173s. . & . . . . . . . . . . . . . +2/27/22 7:57:00 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:00 PM :Info: Looks like Speeduino + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.241s. + +2/27/22 7:57:00 PM :Debug: Time:484.241s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.303s. + +2/27/22 7:57:00 PM :Debug: Time:484.303s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.366s. + +2/27/22 7:57:00 PM :Debug: Time:484.366s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.438s. + +2/27/22 7:57:00 PM :Debug: Time:484.438s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.505s. + +2/27/22 7:57:00 PM :Debug: Time:484.505s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.573s. + +2/27/22 7:57:00 PM :Debug: Time:484.573s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.639s. + +2/27/22 7:57:00 PM :Debug: Time:484.639s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.707s. + +2/27/22 7:57:00 PM :Debug: Time:484.707s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.775s. + +2/27/22 7:57:00 PM :Debug: Time:484.775s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.835s. + +2/27/22 7:57:00 PM :Debug: Time:484.835s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.904s. + +2/27/22 7:57:00 PM :Debug: Time:484.904s. . & . . . . . . . . . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:484.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:484.967s. + +2/27/22 7:57:00 PM :Debug: Time:484.967s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:00 PM :Debug: Time:485.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0xF6 0xFF 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:00 PM :Debug: Time:485.038s. + +2/27/22 7:57:00 PM :Debug: Time:485.038s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.107s. + +2/27/22 7:57:01 PM :Debug: Time:485.107s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.176s. + +2/27/22 7:57:01 PM :Debug: Time:485.176s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.244s. + +2/27/22 7:57:01 PM :Debug: Time:485.244s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.306s. + +2/27/22 7:57:01 PM :Debug: Time:485.306s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.377s. + +2/27/22 7:57:01 PM :Debug: Time:485.377s. . & . . . . . . . . . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.445s. + +2/27/22 7:57:01 PM :Debug: Time:485.445s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.512s. + +2/27/22 7:57:01 PM :Debug: Time:485.512s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.581s. + +2/27/22 7:57:01 PM :Debug: Time:485.581s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.659s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.659s. + +2/27/22 7:57:01 PM :Debug: Time:485.659s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.726s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.726s. + +2/27/22 7:57:01 PM :Debug: Time:485.726s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.792s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.792s. + +2/27/22 7:57:01 PM :Debug: Time:485.792s. . & . . . . . . . . ! . . . . . +2/27/22 7:57:01 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:01 PM :Info: Looks like Speeduino + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.861s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.861s. + +2/27/22 7:57:01 PM :Debug: Time:485.861s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:485.928s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:485.928s. + +2/27/22 7:57:01 PM :Debug: Time:485.928s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:486.002s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:486.002s. + +2/27/22 7:57:01 PM :Debug: Time:486.002s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:01 PM :Debug: Time:486.07s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:01 PM :Debug: Time:486.07s. + +2/27/22 7:57:01 PM :Debug: Time:486.07s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.138s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.138s. + +2/27/22 7:57:02 PM :Debug: Time:486.138s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.198s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.198s. + +2/27/22 7:57:02 PM :Debug: Time:486.198s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.267s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.267s. + +2/27/22 7:57:02 PM :Debug: Time:486.267s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.335s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.335s. + +2/27/22 7:57:02 PM :Debug: Time:486.335s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.399s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.399s. + +2/27/22 7:57:02 PM :Debug: Time:486.399s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.466s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.466s. + +2/27/22 7:57:02 PM :Debug: Time:486.466s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.529s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.529s. + +2/27/22 7:57:02 PM :Debug: Time:486.529s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.599s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.599s. + +2/27/22 7:57:02 PM :Debug: Time:486.599s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.666s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.666s. + +2/27/22 7:57:02 PM :Debug: Time:486.666s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.734s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.734s. + +2/27/22 7:57:02 PM :Debug: Time:486.734s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.801s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.801s. + +2/27/22 7:57:02 PM :Debug: Time:486.801s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.866s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.866s. + +2/27/22 7:57:02 PM :Debug: Time:486.866s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.934s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.934s. + +2/27/22 7:57:02 PM :Debug: Time:486.934s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:486.999s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:486.999s. + +2/27/22 7:57:02 PM :Debug: Time:486.999s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:02 PM :Debug: Time:487.066s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:02 PM :Debug: Time:487.066s. + +2/27/22 7:57:02 PM :Debug: Time:487.066s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.133s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.133s. + +2/27/22 7:57:03 PM :Debug: Time:487.133s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.198s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.198s. + +2/27/22 7:57:03 PM :Debug: Time:487.198s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.266s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.266s. + +2/27/22 7:57:03 PM :Debug: Time:487.266s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.335s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.335s. + +2/27/22 7:57:03 PM :Debug: Time:487.335s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.399s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF2 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.399s. + +2/27/22 7:57:03 PM :Debug: Time:487.399s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.466s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.466s. + +2/27/22 7:57:03 PM :Debug: Time:487.466s. . & . . . . . . . . ! . . . . . +2/27/22 7:57:03 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:03 PM :Info: Looks like Speeduino + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.531s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.531s. + +2/27/22 7:57:03 PM :Debug: Time:487.531s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.598s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.598s. + +2/27/22 7:57:03 PM :Debug: Time:487.598s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.665s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.665s. + +2/27/22 7:57:03 PM :Debug: Time:487.665s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.734s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0xF6 0xFF 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.735s. + +2/27/22 7:57:03 PM :Debug: Time:487.735s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.795s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.795s. + +2/27/22 7:57:03 PM :Debug: Time:487.795s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.866s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.866s. + +2/27/22 7:57:03 PM :Debug: Time:487.866s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.933s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x20 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.933s. + +2/27/22 7:57:03 PM :Debug: Time:487.933s. . & . . . . . . . . . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:487.999s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:487.999s. + +2/27/22 7:57:03 PM :Debug: Time:487.999s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:03 PM :Debug: Time:488.067s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:03 PM :Debug: Time:488.067s. + +2/27/22 7:57:03 PM :Debug: Time:488.067s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.134s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.134s. + +2/27/22 7:57:04 PM :Debug: Time:488.134s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.201s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.201s. + +2/27/22 7:57:04 PM :Debug: Time:488.201s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.269s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.269s. + +2/27/22 7:57:04 PM :Debug: Time:488.269s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.337s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.337s. + +2/27/22 7:57:04 PM :Debug: Time:488.337s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.401s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.401s. + +2/27/22 7:57:04 PM :Debug: Time:488.401s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.468s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0xF6 0xFF 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.468s. + +2/27/22 7:57:04 PM :Debug: Time:488.468s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.536s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.536s. + +2/27/22 7:57:04 PM :Debug: Time:488.536s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.601s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.601s. + +2/27/22 7:57:04 PM :Debug: Time:488.601s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.669s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.669s. + +2/27/22 7:57:04 PM :Debug: Time:488.669s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.732s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.732s. + +2/27/22 7:57:04 PM :Debug: Time:488.732s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.795s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.795s. + +2/27/22 7:57:04 PM :Debug: Time:488.795s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.868s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.868s. + +2/27/22 7:57:04 PM :Debug: Time:488.868s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:488.935s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:488.935s. + +2/27/22 7:57:04 PM :Debug: Time:488.935s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:489.001s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:489.001s. + +2/27/22 7:57:04 PM :Debug: Time:489.001s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:04 PM :Debug: Time:489.069s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:04 PM :Debug: Time:489.069s. + +2/27/22 7:57:04 PM :Debug: Time:489.069s. . & . . . . . . . . " . . . . . +2/27/22 7:57:05 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:05 PM :Info: Looks like Speeduino + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.135s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.135s. + +2/27/22 7:57:05 PM :Debug: Time:489.135s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.201s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.201s. + +2/27/22 7:57:05 PM :Debug: Time:489.201s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.269s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.269s. + +2/27/22 7:57:05 PM :Debug: Time:489.269s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.329s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.329s. + +2/27/22 7:57:05 PM :Debug: Time:489.329s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.393s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.393s. + +2/27/22 7:57:05 PM :Debug: Time:489.393s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.47s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.47s. + +2/27/22 7:57:05 PM :Debug: Time:489.47s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.537s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.537s. + +2/27/22 7:57:05 PM :Debug: Time:489.537s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.603s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.603s. + +2/27/22 7:57:05 PM :Debug: Time:489.603s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.672s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.672s. + +2/27/22 7:57:05 PM :Debug: Time:489.672s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.738s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.738s. + +2/27/22 7:57:05 PM :Debug: Time:489.738s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.803s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.803s. + +2/27/22 7:57:05 PM :Debug: Time:489.803s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.864s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.864s. + +2/27/22 7:57:05 PM :Debug: Time:489.864s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:489.935s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:489.935s. + +2/27/22 7:57:05 PM :Debug: Time:489.935s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:05 PM :Debug: Time:490.002s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:05 PM :Debug: Time:490.002s. + +2/27/22 7:57:05 PM :Debug: Time:490.002s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.075s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.075s. + +2/27/22 7:57:06 PM :Debug: Time:490.075s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.134s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.134s. + +2/27/22 7:57:06 PM :Debug: Time:490.134s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.204s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.204s. + +2/27/22 7:57:06 PM :Debug: Time:490.204s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.272s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.272s. + +2/27/22 7:57:06 PM :Debug: Time:490.272s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.34s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.34s. + +2/27/22 7:57:06 PM :Debug: Time:490.34s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.408s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.408s. + +2/27/22 7:57:06 PM :Debug: Time:490.408s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.474s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.474s. + +2/27/22 7:57:06 PM :Debug: Time:490.474s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.542s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.542s. + +2/27/22 7:57:06 PM :Debug: Time:490.542s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.605s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.605s. + +2/27/22 7:57:06 PM :Debug: Time:490.605s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.673s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.673s. + +2/27/22 7:57:06 PM :Debug: Time:490.673s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.741s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.741s. + +2/27/22 7:57:06 PM :Debug: Time:490.741s. . & . . . . . . . . " . . . . . +2/27/22 7:57:06 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:06 PM :Info: Looks like Speeduino + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.805s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.805s. + +2/27/22 7:57:06 PM :Debug: Time:490.805s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.868s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.868s. + +2/27/22 7:57:06 PM :Debug: Time:490.868s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:490.938s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:490.938s. + +2/27/22 7:57:06 PM :Debug: Time:490.938s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:06 PM :Debug: Time:491.006s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:06 PM :Debug: Time:491.006s. + +2/27/22 7:57:06 PM :Debug: Time:491.006s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.074s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.074s. + +2/27/22 7:57:07 PM :Debug: Time:491.074s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.142s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.142s. + +2/27/22 7:57:07 PM :Debug: Time:491.142s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.207s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0xF6 0xFF 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.207s. + +2/27/22 7:57:07 PM :Debug: Time:491.207s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.275s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.275s. + +2/27/22 7:57:07 PM :Debug: Time:491.275s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.342s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.342s. + +2/27/22 7:57:07 PM :Debug: Time:491.342s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.402s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.402s. + +2/27/22 7:57:07 PM :Debug: Time:491.402s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.475s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.475s. + +2/27/22 7:57:07 PM :Debug: Time:491.475s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.541s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.541s. + +2/27/22 7:57:07 PM :Debug: Time:491.541s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.608s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.608s. + +2/27/22 7:57:07 PM :Debug: Time:491.608s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.674s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.674s. + +2/27/22 7:57:07 PM :Debug: Time:491.674s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.742s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.742s. + +2/27/22 7:57:07 PM :Debug: Time:491.742s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.807s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.807s. + +2/27/22 7:57:07 PM :Debug: Time:491.807s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.874s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.874s. + +2/27/22 7:57:07 PM :Debug: Time:491.874s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:491.942s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:491.942s. + +2/27/22 7:57:07 PM :Debug: Time:491.942s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:07 PM :Debug: Time:492.007s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:07 PM :Debug: Time:492.007s. + +2/27/22 7:57:07 PM :Debug: Time:492.007s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.075s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.075s. + +2/27/22 7:57:08 PM :Debug: Time:492.075s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.141s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.141s. + +2/27/22 7:57:08 PM :Debug: Time:492.141s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.206s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.206s. + +2/27/22 7:57:08 PM :Debug: Time:492.206s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.281s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.281s. + +2/27/22 7:57:08 PM :Debug: Time:492.281s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.346s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.346s. + +2/27/22 7:57:08 PM :Debug: Time:492.347s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.407s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.407s. + +2/27/22 7:57:08 PM :Debug: Time:492.407s. . & . . . . . . . . # . . . . . +2/27/22 7:57:08 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:08 PM :Info: Looks like Speeduino + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.479s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.479s. + +2/27/22 7:57:08 PM :Debug: Time:492.479s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.547s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.547s. + +2/27/22 7:57:08 PM :Debug: Time:492.547s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.613s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.613s. + +2/27/22 7:57:08 PM :Debug: Time:492.613s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.68s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.68s. + +2/27/22 7:57:08 PM :Debug: Time:492.68s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.749s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.749s. + +2/27/22 7:57:08 PM :Debug: Time:492.749s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.813s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.813s. + +2/27/22 7:57:08 PM :Debug: Time:492.813s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.882s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.882s. + +2/27/22 7:57:08 PM :Debug: Time:492.882s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:492.948s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:492.948s. + +2/27/22 7:57:08 PM :Debug: Time:492.948s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:08 PM :Debug: Time:493.012s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:08 PM :Debug: Time:493.012s. + +2/27/22 7:57:08 PM :Debug: Time:493.012s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.079s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.079s. + +2/27/22 7:57:09 PM :Debug: Time:493.079s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.146s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.146s. + +2/27/22 7:57:09 PM :Debug: Time:493.146s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.214s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.214s. + +2/27/22 7:57:09 PM :Debug: Time:493.214s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.28s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.28s. + +2/27/22 7:57:09 PM :Debug: Time:493.28s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.347s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.348s. + +2/27/22 7:57:09 PM :Debug: Time:493.348s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.408s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.408s. + +2/27/22 7:57:09 PM :Debug: Time:493.408s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.482s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.482s. + +2/27/22 7:57:09 PM :Debug: Time:493.482s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.549s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.549s. + +2/27/22 7:57:09 PM :Debug: Time:493.549s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.614s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.614s. + +2/27/22 7:57:09 PM :Debug: Time:493.614s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.682s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.682s. + +2/27/22 7:57:09 PM :Debug: Time:493.682s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.749s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.749s. + +2/27/22 7:57:09 PM :Debug: Time:493.749s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.828s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.828s. + +2/27/22 7:57:09 PM :Debug: Time:493.828s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.897s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.897s. + +2/27/22 7:57:09 PM :Debug: Time:493.897s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:493.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:493.965s. + +2/27/22 7:57:09 PM :Debug: Time:493.965s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:09 PM :Debug: Time:494.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:09 PM :Debug: Time:494.033s. + +2/27/22 7:57:09 PM :Debug: Time:494.033s. . & . . . . . . . . # . . . . . +2/27/22 7:57:10 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:10 PM :Info: Looks like Speeduino + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.099s. + +2/27/22 7:57:10 PM :Debug: Time:494.099s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.163s. + +2/27/22 7:57:10 PM :Debug: Time:494.163s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.232s. + +2/27/22 7:57:10 PM :Debug: Time:494.232s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.299s. + +2/27/22 7:57:10 PM :Debug: Time:494.299s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.367s. + +2/27/22 7:57:10 PM :Debug: Time:494.367s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF0 0x0 0x14 0x0 0x22 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.428s. + +2/27/22 7:57:10 PM :Debug: Time:494.428s. . & . . . . . . . . " . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.492s. + +2/27/22 7:57:10 PM :Debug: Time:494.492s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.563s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.563s. + +2/27/22 7:57:10 PM :Debug: Time:494.563s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.631s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.631s. + +2/27/22 7:57:10 PM :Debug: Time:494.631s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.699s. + +2/27/22 7:57:10 PM :Debug: Time:494.699s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.766s. + +2/27/22 7:57:10 PM :Debug: Time:494.766s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.833s. + +2/27/22 7:57:10 PM :Debug: Time:494.833s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.9s. + +2/27/22 7:57:10 PM :Debug: Time:494.9s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:494.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:494.964s. + +2/27/22 7:57:10 PM :Debug: Time:494.964s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:10 PM :Debug: Time:495.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:10 PM :Debug: Time:495.033s. + +2/27/22 7:57:10 PM :Debug: Time:495.033s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.1s. + +2/27/22 7:57:11 PM :Debug: Time:495.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.17s. + +2/27/22 7:57:11 PM :Debug: Time:495.17s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.231s. + +2/27/22 7:57:11 PM :Debug: Time:495.231s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.294s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.294s. + +2/27/22 7:57:11 PM :Debug: Time:495.294s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.365s. + +2/27/22 7:57:11 PM :Debug: Time:495.365s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.433s. + +2/27/22 7:57:11 PM :Debug: Time:495.433s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.502s. + +2/27/22 7:57:11 PM :Debug: Time:495.502s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.569s. + +2/27/22 7:57:11 PM :Debug: Time:495.569s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.636s. + +2/27/22 7:57:11 PM :Debug: Time:495.636s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:11 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:11 PM :Info: Looks like Speeduino + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0xF6 0xFF 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.702s. + +2/27/22 7:57:11 PM :Debug: Time:495.702s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.77s. + +2/27/22 7:57:11 PM :Debug: Time:495.77s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.837s. + +2/27/22 7:57:11 PM :Debug: Time:495.837s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.902s. + +2/27/22 7:57:11 PM :Debug: Time:495.902s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:495.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:495.967s. + +2/27/22 7:57:11 PM :Debug: Time:495.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:11 PM :Debug: Time:496.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:11 PM :Debug: Time:496.036s. + +2/27/22 7:57:11 PM :Debug: Time:496.036s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.104s. + +2/27/22 7:57:12 PM :Debug: Time:496.104s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.172s. + +2/27/22 7:57:12 PM :Debug: Time:496.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.233s. + +2/27/22 7:57:12 PM :Debug: Time:496.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.297s. + +2/27/22 7:57:12 PM :Debug: Time:496.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.368s. + +2/27/22 7:57:12 PM :Debug: Time:496.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.436s. + +2/27/22 7:57:12 PM :Debug: Time:496.436s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.516s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.516s. + +2/27/22 7:57:12 PM :Debug: Time:496.516s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.59s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.59s. + +2/27/22 7:57:12 PM :Debug: Time:496.59s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.657s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.657s. + +2/27/22 7:57:12 PM :Debug: Time:496.657s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.724s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEE 0x0 0x0 0x0 0x24 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.724s. + +2/27/22 7:57:12 PM :Debug: Time:496.724s. . & . . . . . . . . $ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.79s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.79s. + +2/27/22 7:57:12 PM :Debug: Time:496.79s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.857s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.857s. + +2/27/22 7:57:12 PM :Debug: Time:496.857s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.922s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.922s. + +2/27/22 7:57:12 PM :Debug: Time:496.922s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:496.992s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:496.992s. + +2/27/22 7:57:12 PM :Debug: Time:496.992s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:12 PM :Debug: Time:497.06s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:12 PM :Debug: Time:497.06s. + +2/27/22 7:57:12 PM :Debug: Time:497.06s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.125s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.125s. + +2/27/22 7:57:13 PM :Debug: Time:497.125s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.193s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.193s. + +2/27/22 7:57:13 PM :Debug: Time:497.193s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.258s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.258s. + +2/27/22 7:57:13 PM :Debug: Time:497.258s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:13 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:13 PM :Info: Looks like Speeduino + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.325s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.325s. + +2/27/22 7:57:13 PM :Debug: Time:497.325s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.385s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.385s. + +2/27/22 7:57:13 PM :Debug: Time:497.385s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.455s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.455s. + +2/27/22 7:57:13 PM :Debug: Time:497.455s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.524s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.524s. + +2/27/22 7:57:13 PM :Debug: Time:497.524s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.593s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.593s. + +2/27/22 7:57:13 PM :Debug: Time:497.593s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.66s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.66s. + +2/27/22 7:57:13 PM :Debug: Time:497.66s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.725s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.725s. + +2/27/22 7:57:13 PM :Debug: Time:497.725s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.794s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.794s. + +2/27/22 7:57:13 PM :Debug: Time:497.794s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.861s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.861s. + +2/27/22 7:57:13 PM :Debug: Time:497.861s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.925s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.925s. + +2/27/22 7:57:13 PM :Debug: Time:497.925s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:497.99s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:497.99s. + +2/27/22 7:57:13 PM :Debug: Time:497.99s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:13 PM :Debug: Time:498.06s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:13 PM :Debug: Time:498.06s. + +2/27/22 7:57:13 PM :Debug: Time:498.06s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.127s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF5 0x0 0xCA 0x3 0x1D 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.127s. + +2/27/22 7:57:14 PM :Debug: Time:498.127s. . & . . . . . . . . . . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.194s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.194s. + +2/27/22 7:57:14 PM :Debug: Time:498.194s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.267s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.267s. + +2/27/22 7:57:14 PM :Debug: Time:498.267s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.327s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.327s. + +2/27/22 7:57:14 PM :Debug: Time:498.327s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.396s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.396s. + +2/27/22 7:57:14 PM :Debug: Time:498.396s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.463s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.463s. + +2/27/22 7:57:14 PM :Debug: Time:498.463s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.526s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.526s. + +2/27/22 7:57:14 PM :Debug: Time:498.526s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.588s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.588s. + +2/27/22 7:57:14 PM :Debug: Time:498.588s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.656s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.656s. + +2/27/22 7:57:14 PM :Debug: Time:498.656s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.722s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.722s. + +2/27/22 7:57:14 PM :Debug: Time:498.722s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.794s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.794s. + +2/27/22 7:57:14 PM :Debug: Time:498.794s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.861s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.861s. + +2/27/22 7:57:14 PM :Debug: Time:498.861s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.926s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.926s. + +2/27/22 7:57:14 PM :Debug: Time:498.926s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:14 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:14 PM :Info: Looks like Speeduino + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:498.991s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:498.991s. + +2/27/22 7:57:14 PM :Debug: Time:498.991s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:14 PM :Debug: Time:499.054s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:14 PM :Debug: Time:499.054s. + +2/27/22 7:57:14 PM :Debug: Time:499.054s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.127s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.127s. + +2/27/22 7:57:15 PM :Debug: Time:499.127s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.195s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.195s. + +2/27/22 7:57:15 PM :Debug: Time:499.195s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.26s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.26s. + +2/27/22 7:57:15 PM :Debug: Time:499.26s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.337s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.337s. + +2/27/22 7:57:15 PM :Debug: Time:499.337s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.401s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.401s. + +2/27/22 7:57:15 PM :Debug: Time:499.401s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.461s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.461s. + +2/27/22 7:57:15 PM :Debug: Time:499.461s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.525s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.525s. + +2/27/22 7:57:15 PM :Debug: Time:499.525s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.591s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.591s. + +2/27/22 7:57:15 PM :Debug: Time:499.591s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.659s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.659s. + +2/27/22 7:57:15 PM :Debug: Time:499.659s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.725s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.725s. + +2/27/22 7:57:15 PM :Debug: Time:499.725s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.788s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.788s. + +2/27/22 7:57:15 PM :Debug: Time:499.788s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.852s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.852s. + +2/27/22 7:57:15 PM :Debug: Time:499.852s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.924s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.924s. + +2/27/22 7:57:15 PM :Debug: Time:499.924s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:499.99s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:499.99s. + +2/27/22 7:57:15 PM :Debug: Time:499.99s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:15 PM :Debug: Time:500.06s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:15 PM :Debug: Time:500.06s. + +2/27/22 7:57:15 PM :Debug: Time:500.06s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.129s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.129s. + +2/27/22 7:57:16 PM :Debug: Time:500.129s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.193s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.193s. + +2/27/22 7:57:16 PM :Debug: Time:500.194s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.258s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.258s. + +2/27/22 7:57:16 PM :Debug: Time:500.258s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.322s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.322s. + +2/27/22 7:57:16 PM :Debug: Time:500.322s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.393s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.393s. + +2/27/22 7:57:16 PM :Debug: Time:500.393s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.457s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.457s. + +2/27/22 7:57:16 PM :Debug: Time:500.457s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.523s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.524s. + +2/27/22 7:57:16 PM :Debug: Time:500.524s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.588s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.588s. + +2/27/22 7:57:16 PM :Debug: Time:500.588s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:16 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:16 PM :Info: Looks like Speeduino + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.652s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.652s. + +2/27/22 7:57:16 PM :Debug: Time:500.652s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.718s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.718s. + +2/27/22 7:57:16 PM :Debug: Time:500.718s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.791s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.792s. + +2/27/22 7:57:16 PM :Debug: Time:500.792s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.856s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.856s. + +2/27/22 7:57:16 PM :Debug: Time:500.856s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.92s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.92s. + +2/27/22 7:57:16 PM :Debug: Time:500.92s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:500.991s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:500.991s. + +2/27/22 7:57:16 PM :Debug: Time:500.991s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:16 PM :Debug: Time:501.057s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:16 PM :Debug: Time:501.057s. + +2/27/22 7:57:16 PM :Debug: Time:501.057s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.12s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.12s. + +2/27/22 7:57:17 PM :Debug: Time:501.121s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.185s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.185s. + +2/27/22 7:57:17 PM :Debug: Time:501.185s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.257s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.257s. + +2/27/22 7:57:17 PM :Debug: Time:501.257s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.322s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.322s. + +2/27/22 7:57:17 PM :Debug: Time:501.323s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.386s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.386s. + +2/27/22 7:57:17 PM :Debug: Time:501.386s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.459s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.459s. + +2/27/22 7:57:17 PM :Debug: Time:501.46s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.527s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.527s. + +2/27/22 7:57:17 PM :Debug: Time:501.527s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.592s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.592s. + +2/27/22 7:57:17 PM :Debug: Time:501.592s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.656s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.657s. + +2/27/22 7:57:17 PM :Debug: Time:501.657s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.726s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.726s. + +2/27/22 7:57:17 PM :Debug: Time:501.726s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.794s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.794s. + +2/27/22 7:57:17 PM :Debug: Time:501.794s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.857s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.857s. + +2/27/22 7:57:17 PM :Debug: Time:501.857s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.924s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.924s. + +2/27/22 7:57:17 PM :Debug: Time:501.924s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:501.988s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:501.988s. + +2/27/22 7:57:17 PM :Debug: Time:501.988s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:17 PM :Debug: Time:502.06s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:17 PM :Debug: Time:502.06s. + +2/27/22 7:57:17 PM :Debug: Time:502.06s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.125s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.125s. + +2/27/22 7:57:18 PM :Debug: Time:502.125s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.189s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.189s. + +2/27/22 7:57:18 PM :Debug: Time:502.189s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:18 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:18 PM :Info: Looks like Speeduino + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.253s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.253s. + +2/27/22 7:57:18 PM :Debug: Time:502.254s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.327s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.327s. + +2/27/22 7:57:18 PM :Debug: Time:502.327s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.39s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xEF 0x0 0x0 0x0 0x23 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.391s. + +2/27/22 7:57:18 PM :Debug: Time:502.391s. . & . . . . . . . . # . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.46s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.46s. + +2/27/22 7:57:18 PM :Debug: Time:502.46s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.528s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.528s. + +2/27/22 7:57:18 PM :Debug: Time:502.528s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.593s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.593s. + +2/27/22 7:57:18 PM :Debug: Time:502.593s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.658s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.658s. + +2/27/22 7:57:18 PM :Debug: Time:502.658s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.723s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.723s. + +2/27/22 7:57:18 PM :Debug: Time:502.723s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.789s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.789s. + +2/27/22 7:57:18 PM :Debug: Time:502.789s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.859s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.86s. + +2/27/22 7:57:18 PM :Debug: Time:502.86s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.924s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.925s. + +2/27/22 7:57:18 PM :Debug: Time:502.925s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:502.989s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:502.989s. + +2/27/22 7:57:18 PM :Debug: Time:502.989s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:18 PM :Debug: Time:503.054s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:18 PM :Debug: Time:503.054s. + +2/27/22 7:57:18 PM :Debug: Time:503.054s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.12s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.12s. + +2/27/22 7:57:19 PM :Debug: Time:503.12s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.185s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.185s. + +2/27/22 7:57:19 PM :Debug: Time:503.185s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.251s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.251s. + +2/27/22 7:57:19 PM :Debug: Time:503.251s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.327s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF3 0x0 0x0 0x0 0x1F 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.328s. + +2/27/22 7:57:19 PM :Debug: Time:503.328s. . & . . . . . . . . . . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.394s. 0xF5 0x26 0x0 0x0 0x0 0x0 0xF1 0x0 0x0 0x0 0x21 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.395s. + +2/27/22 7:57:19 PM :Debug: Time:503.395s. . & . . . . . . . . ! . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.46s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.46s. + +2/27/22 7:57:19 PM :Debug: Time:503.46s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.525s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.525s. + +2/27/22 7:57:19 PM :Debug: Time:503.525s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.59s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.59s. + +2/27/22 7:57:19 PM :Debug: Time:503.59s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.653s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.653s. + +2/27/22 7:57:19 PM :Debug: Time:503.653s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.717s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.717s. + +2/27/22 7:57:19 PM :Debug: Time:503.717s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.788s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.789s. + +2/27/22 7:57:19 PM :Debug: Time:503.789s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.854s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.854s. + +2/27/22 7:57:19 PM :Debug: Time:503.854s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:19 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:19 PM :Info: Looks like Speeduino + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.919s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.919s. + +2/27/22 7:57:19 PM :Debug: Time:503.919s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:503.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:503.984s. + +2/27/22 7:57:19 PM :Debug: Time:503.984s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:19 PM :Debug: Time:504.05s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:19 PM :Debug: Time:504.05s. + +2/27/22 7:57:19 PM :Debug: Time:504.05s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.122s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.123s. + +2/27/22 7:57:20 PM :Debug: Time:504.123s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.187s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.187s. + +2/27/22 7:57:20 PM :Debug: Time:504.187s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.259s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.259s. + +2/27/22 7:57:20 PM :Debug: Time:504.259s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.326s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.326s. + +2/27/22 7:57:20 PM :Debug: Time:504.326s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.39s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.391s. + +2/27/22 7:57:20 PM :Debug: Time:504.391s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.455s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.455s. + +2/27/22 7:57:20 PM :Debug: Time:504.455s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.519s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.519s. + +2/27/22 7:57:20 PM :Debug: Time:504.519s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.586s. + +2/27/22 7:57:20 PM :Debug: Time:504.586s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.648s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.648s. + +2/27/22 7:57:20 PM :Debug: Time:504.648s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.714s. + +2/27/22 7:57:20 PM :Debug: Time:504.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.783s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.783s. + +2/27/22 7:57:20 PM :Debug: Time:504.784s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.85s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.85s. + +2/27/22 7:57:20 PM :Debug: Time:504.85s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.916s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.916s. + +2/27/22 7:57:20 PM :Debug: Time:504.916s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:504.987s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:504.987s. + +2/27/22 7:57:20 PM :Debug: Time:504.987s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:20 PM :Debug: Time:505.051s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:20 PM :Debug: Time:505.051s. + +2/27/22 7:57:20 PM :Debug: Time:505.051s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.116s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.116s. + +2/27/22 7:57:21 PM :Debug: Time:505.116s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.185s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.185s. + +2/27/22 7:57:21 PM :Debug: Time:505.185s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.254s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.254s. + +2/27/22 7:57:21 PM :Debug: Time:505.254s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.318s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.318s. + +2/27/22 7:57:21 PM :Debug: Time:505.318s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.382s. + +2/27/22 7:57:21 PM :Debug: Time:505.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.446s. + +2/27/22 7:57:21 PM :Debug: Time:505.446s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:21 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:21 PM :Info: Looks like Speeduino + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.512s. + +2/27/22 7:57:21 PM :Debug: Time:505.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.583s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.583s. + +2/27/22 7:57:21 PM :Debug: Time:505.583s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.649s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.649s. + +2/27/22 7:57:21 PM :Debug: Time:505.649s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.714s. + +2/27/22 7:57:21 PM :Debug: Time:505.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.786s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.786s. + +2/27/22 7:57:21 PM :Debug: Time:505.786s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.851s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.851s. + +2/27/22 7:57:21 PM :Debug: Time:505.851s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.914s. + +2/27/22 7:57:21 PM :Debug: Time:505.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:505.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:505.978s. + +2/27/22 7:57:21 PM :Debug: Time:505.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:21 PM :Debug: Time:506.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:21 PM :Debug: Time:506.044s. + +2/27/22 7:57:21 PM :Debug: Time:506.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.11s. + +2/27/22 7:57:22 PM :Debug: Time:506.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.182s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.182s. + +2/27/22 7:57:22 PM :Debug: Time:506.182s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.247s. + +2/27/22 7:57:22 PM :Debug: Time:506.247s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.311s. + +2/27/22 7:57:22 PM :Debug: Time:506.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.384s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.384s. + +2/27/22 7:57:22 PM :Debug: Time:506.384s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.445s. + +2/27/22 7:57:22 PM :Debug: Time:506.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.513s. + +2/27/22 7:57:22 PM :Debug: Time:506.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x7C 0xFC 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.577s. + +2/27/22 7:57:22 PM :Debug: Time:506.577s. . & . . . . . . | . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.649s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.649s. + +2/27/22 7:57:22 PM :Debug: Time:506.649s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.714s. + +2/27/22 7:57:22 PM :Debug: Time:506.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.778s. + +2/27/22 7:57:22 PM :Debug: Time:506.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.844s. + +2/27/22 7:57:22 PM :Debug: Time:506.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.917s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.917s. + +2/27/22 7:57:22 PM :Debug: Time:506.917s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:506.982s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:506.982s. + +2/27/22 7:57:22 PM :Debug: Time:506.982s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:22 PM :Debug: Time:507.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:22 PM :Debug: Time:507.047s. + +2/27/22 7:57:22 PM :Debug: Time:507.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.112s. + +2/27/22 7:57:23 PM :Debug: Time:507.112s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:23 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:23 PM :Info: Looks like Speeduino + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.178s. + +2/27/22 7:57:23 PM :Debug: Time:507.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.249s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.25s. + +2/27/22 7:57:23 PM :Debug: Time:507.25s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.321s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.321s. + +2/27/22 7:57:23 PM :Debug: Time:507.321s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.388s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.389s. + +2/27/22 7:57:23 PM :Debug: Time:507.389s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.451s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.451s. + +2/27/22 7:57:23 PM :Debug: Time:507.451s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.517s. + +2/27/22 7:57:23 PM :Debug: Time:507.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.587s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.588s. + +2/27/22 7:57:23 PM :Debug: Time:507.588s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.651s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.651s. + +2/27/22 7:57:23 PM :Debug: Time:507.651s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.722s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.722s. + +2/27/22 7:57:23 PM :Debug: Time:507.722s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.785s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.785s. + +2/27/22 7:57:23 PM :Debug: Time:507.785s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.849s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.849s. + +2/27/22 7:57:23 PM :Debug: Time:507.849s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.916s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.916s. + +2/27/22 7:57:23 PM :Debug: Time:507.916s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:507.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:507.981s. + +2/27/22 7:57:23 PM :Debug: Time:507.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:23 PM :Debug: Time:508.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:23 PM :Debug: Time:508.045s. + +2/27/22 7:57:23 PM :Debug: Time:508.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.11s. + +2/27/22 7:57:24 PM :Debug: Time:508.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.181s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.181s. + +2/27/22 7:57:24 PM :Debug: Time:508.181s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.252s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.252s. + +2/27/22 7:57:24 PM :Debug: Time:508.253s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.321s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.321s. + +2/27/22 7:57:24 PM :Debug: Time:508.321s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.386s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.386s. + +2/27/22 7:57:24 PM :Debug: Time:508.386s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.45s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.451s. + +2/27/22 7:57:24 PM :Debug: Time:508.451s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.515s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.515s. + +2/27/22 7:57:24 PM :Debug: Time:508.515s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.579s. + +2/27/22 7:57:24 PM :Debug: Time:508.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.644s. + +2/27/22 7:57:24 PM :Debug: Time:508.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.709s. + +2/27/22 7:57:24 PM :Debug: Time:508.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.783s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.783s. + +2/27/22 7:57:24 PM :Debug: Time:508.783s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:24 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:24 PM :Info: Looks like Speeduino + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.848s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.848s. + +2/27/22 7:57:24 PM :Debug: Time:508.848s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.918s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.918s. + +2/27/22 7:57:24 PM :Debug: Time:508.918s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:508.986s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:508.987s. + +2/27/22 7:57:24 PM :Debug: Time:508.987s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:24 PM :Debug: Time:509.05s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:24 PM :Debug: Time:509.05s. + +2/27/22 7:57:24 PM :Debug: Time:509.05s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.12s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.12s. + +2/27/22 7:57:25 PM :Debug: Time:509.12s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.187s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.187s. + +2/27/22 7:57:25 PM :Debug: Time:509.187s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.248s. + +2/27/22 7:57:25 PM :Debug: Time:509.248s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.315s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.315s. + +2/27/22 7:57:25 PM :Debug: Time:509.315s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.38s. + +2/27/22 7:57:25 PM :Debug: Time:509.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.445s. + +2/27/22 7:57:25 PM :Debug: Time:509.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.509s. + +2/27/22 7:57:25 PM :Debug: Time:509.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.583s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.583s. + +2/27/22 7:57:25 PM :Debug: Time:509.583s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.653s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.654s. + +2/27/22 7:57:25 PM :Debug: Time:509.654s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.721s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.721s. + +2/27/22 7:57:25 PM :Debug: Time:509.721s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.785s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.785s. + +2/27/22 7:57:25 PM :Debug: Time:509.785s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.85s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.85s. + +2/27/22 7:57:25 PM :Debug: Time:509.85s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.914s. + +2/27/22 7:57:25 PM :Debug: Time:509.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:509.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:509.978s. + +2/27/22 7:57:25 PM :Debug: Time:509.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:25 PM :Debug: Time:510.05s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:25 PM :Debug: Time:510.05s. + +2/27/22 7:57:25 PM :Debug: Time:510.05s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.115s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.115s. + +2/27/22 7:57:26 PM :Debug: Time:510.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.187s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.187s. + +2/27/22 7:57:26 PM :Debug: Time:510.187s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.255s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.256s. + +2/27/22 7:57:26 PM :Debug: Time:510.256s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.319s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.32s. + +2/27/22 7:57:26 PM :Debug: Time:510.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.384s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.384s. + +2/27/22 7:57:26 PM :Debug: Time:510.384s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:26 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:26 PM :Info: Looks like Speeduino + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.446s. + +2/27/22 7:57:26 PM :Debug: Time:510.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.513s. + +2/27/22 7:57:26 PM :Debug: Time:510.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.586s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.586s. + +2/27/22 7:57:26 PM :Debug: Time:510.586s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.652s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.652s. + +2/27/22 7:57:26 PM :Debug: Time:510.652s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.716s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.716s. + +2/27/22 7:57:26 PM :Debug: Time:510.716s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.786s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.786s. + +2/27/22 7:57:26 PM :Debug: Time:510.786s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.855s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.855s. + +2/27/22 7:57:26 PM :Debug: Time:510.855s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.917s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.917s. + +2/27/22 7:57:26 PM :Debug: Time:510.917s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:510.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:510.981s. + +2/27/22 7:57:26 PM :Debug: Time:510.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:26 PM :Debug: Time:511.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:26 PM :Debug: Time:511.046s. + +2/27/22 7:57:26 PM :Debug: Time:511.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.111s. + +2/27/22 7:57:27 PM :Debug: Time:511.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.184s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.184s. + +2/27/22 7:57:27 PM :Debug: Time:511.184s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.248s. + +2/27/22 7:57:27 PM :Debug: Time:511.248s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.314s. + +2/27/22 7:57:27 PM :Debug: Time:511.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.38s. + +2/27/22 7:57:27 PM :Debug: Time:511.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.453s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.453s. + +2/27/22 7:57:27 PM :Debug: Time:511.453s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.518s. + +2/27/22 7:57:27 PM :Debug: Time:511.518s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.58s. + +2/27/22 7:57:27 PM :Debug: Time:511.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.648s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.648s. + +2/27/22 7:57:27 PM :Debug: Time:511.648s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.714s. + +2/27/22 7:57:27 PM :Debug: Time:511.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.779s. + +2/27/22 7:57:27 PM :Debug: Time:511.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.844s. + +2/27/22 7:57:27 PM :Debug: Time:511.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.909s. + +2/27/22 7:57:27 PM :Debug: Time:511.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:511.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:511.983s. + +2/27/22 7:57:27 PM :Debug: Time:511.983s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:27 PM :Debug: Time:512.048s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:27 PM :Debug: Time:512.048s. + +2/27/22 7:57:27 PM :Debug: Time:512.048s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:28 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:28 PM :Info: Looks like Speeduino + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.112s. + +2/27/22 7:57:28 PM :Debug: Time:512.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.179s. + +2/27/22 7:57:28 PM :Debug: Time:512.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.251s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.251s. + +2/27/22 7:57:28 PM :Debug: Time:512.252s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.315s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.315s. + +2/27/22 7:57:28 PM :Debug: Time:512.315s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.38s. + +2/27/22 7:57:28 PM :Debug: Time:512.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.445s. + +2/27/22 7:57:28 PM :Debug: Time:512.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.517s. + +2/27/22 7:57:28 PM :Debug: Time:512.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.58s. + +2/27/22 7:57:28 PM :Debug: Time:512.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.646s. + +2/27/22 7:57:28 PM :Debug: Time:512.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.718s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.718s. + +2/27/22 7:57:28 PM :Debug: Time:512.718s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.783s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.783s. + +2/27/22 7:57:28 PM :Debug: Time:512.783s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.852s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.852s. + +2/27/22 7:57:28 PM :Debug: Time:512.852s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.92s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.92s. + +2/27/22 7:57:28 PM :Debug: Time:512.92s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:512.986s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:512.986s. + +2/27/22 7:57:28 PM :Debug: Time:512.986s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:28 PM :Debug: Time:513.051s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:28 PM :Debug: Time:513.051s. + +2/27/22 7:57:28 PM :Debug: Time:513.051s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.122s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.122s. + +2/27/22 7:57:29 PM :Debug: Time:513.122s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.183s. + +2/27/22 7:57:29 PM :Debug: Time:513.183s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.252s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.253s. + +2/27/22 7:57:29 PM :Debug: Time:513.253s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.317s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.317s. + +2/27/22 7:57:29 PM :Debug: Time:513.317s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.382s. + +2/27/22 7:57:29 PM :Debug: Time:513.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.446s. + +2/27/22 7:57:29 PM :Debug: Time:513.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.513s. + +2/27/22 7:57:29 PM :Debug: Time:513.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.578s. + +2/27/22 7:57:29 PM :Debug: Time:513.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.65s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.65s. + +2/27/22 7:57:29 PM :Debug: Time:513.65s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:29 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:29 PM :Info: Looks like Speeduino + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.714s. + +2/27/22 7:57:29 PM :Debug: Time:513.715s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.787s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.787s. + +2/27/22 7:57:29 PM :Debug: Time:513.787s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.856s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.856s. + +2/27/22 7:57:29 PM :Debug: Time:513.856s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.92s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.921s. + +2/27/22 7:57:29 PM :Debug: Time:513.921s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:513.991s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:513.991s. + +2/27/22 7:57:29 PM :Debug: Time:513.991s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:29 PM :Debug: Time:514.059s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:29 PM :Debug: Time:514.059s. + +2/27/22 7:57:29 PM :Debug: Time:514.059s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.123s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.123s. + +2/27/22 7:57:30 PM :Debug: Time:514.123s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.188s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.188s. + +2/27/22 7:57:30 PM :Debug: Time:514.188s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.249s. + +2/27/22 7:57:30 PM :Debug: Time:514.249s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.316s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.316s. + +2/27/22 7:57:30 PM :Debug: Time:514.316s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.38s. + +2/27/22 7:57:30 PM :Debug: Time:514.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.446s. + +2/27/22 7:57:30 PM :Debug: Time:514.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.518s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.518s. + +2/27/22 7:57:30 PM :Debug: Time:514.518s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.584s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.584s. + +2/27/22 7:57:30 PM :Debug: Time:514.584s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.655s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.655s. + +2/27/22 7:57:30 PM :Debug: Time:514.655s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.721s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.721s. + +2/27/22 7:57:30 PM :Debug: Time:514.721s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.785s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.786s. + +2/27/22 7:57:30 PM :Debug: Time:514.786s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.85s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.85s. + +2/27/22 7:57:30 PM :Debug: Time:514.85s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.92s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.92s. + +2/27/22 7:57:30 PM :Debug: Time:514.92s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:514.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:514.983s. + +2/27/22 7:57:30 PM :Debug: Time:514.983s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:30 PM :Debug: Time:515.051s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:30 PM :Debug: Time:515.051s. + +2/27/22 7:57:30 PM :Debug: Time:515.051s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.116s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.116s. + +2/27/22 7:57:31 PM :Debug: Time:515.116s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.18s. + +2/27/22 7:57:31 PM :Debug: Time:515.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.245s. + +2/27/22 7:57:31 PM :Debug: Time:515.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.317s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.317s. + +2/27/22 7:57:31 PM :Debug: Time:515.317s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:31 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:31 PM :Info: Looks like Speeduino + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.381s. + +2/27/22 7:57:31 PM :Debug: Time:515.381s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.453s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.453s. + +2/27/22 7:57:31 PM :Debug: Time:515.453s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.522s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.522s. + +2/27/22 7:57:31 PM :Debug: Time:515.522s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.587s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.587s. + +2/27/22 7:57:31 PM :Debug: Time:515.587s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.651s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.651s. + +2/27/22 7:57:31 PM :Debug: Time:515.651s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.716s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.716s. + +2/27/22 7:57:31 PM :Debug: Time:515.716s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.782s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.783s. + +2/27/22 7:57:31 PM :Debug: Time:515.783s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.847s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.847s. + +2/27/22 7:57:31 PM :Debug: Time:515.847s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.91s. + +2/27/22 7:57:31 PM :Debug: Time:515.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:515.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:515.976s. + +2/27/22 7:57:31 PM :Debug: Time:515.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:31 PM :Debug: Time:516.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:31 PM :Debug: Time:516.049s. + +2/27/22 7:57:31 PM :Debug: Time:516.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.114s. + +2/27/22 7:57:32 PM :Debug: Time:516.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.179s. + +2/27/22 7:57:32 PM :Debug: Time:516.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.25s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.25s. + +2/27/22 7:57:32 PM :Debug: Time:516.25s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.315s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.315s. + +2/27/22 7:57:32 PM :Debug: Time:516.315s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.387s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.387s. + +2/27/22 7:57:32 PM :Debug: Time:516.388s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.452s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.452s. + +2/27/22 7:57:32 PM :Debug: Time:516.452s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.517s. + +2/27/22 7:57:32 PM :Debug: Time:516.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.589s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.589s. + +2/27/22 7:57:32 PM :Debug: Time:516.589s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.657s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.657s. + +2/27/22 7:57:32 PM :Debug: Time:516.657s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.721s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.721s. + +2/27/22 7:57:32 PM :Debug: Time:516.721s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.785s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.785s. + +2/27/22 7:57:32 PM :Debug: Time:516.785s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.854s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.854s. + +2/27/22 7:57:32 PM :Debug: Time:516.854s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.918s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.918s. + +2/27/22 7:57:32 PM :Debug: Time:516.918s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:32 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:32 PM :Info: Looks like Speeduino + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:516.984s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:516.984s. + +2/27/22 7:57:32 PM :Debug: Time:516.985s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:32 PM :Debug: Time:517.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:32 PM :Debug: Time:517.049s. + +2/27/22 7:57:32 PM :Debug: Time:517.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.114s. + +2/27/22 7:57:33 PM :Debug: Time:517.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.18s. + +2/27/22 7:57:33 PM :Debug: Time:517.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.244s. + +2/27/22 7:57:33 PM :Debug: Time:517.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.317s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.317s. + +2/27/22 7:57:33 PM :Debug: Time:517.317s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.383s. + +2/27/22 7:57:33 PM :Debug: Time:517.383s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.448s. + +2/27/22 7:57:33 PM :Debug: Time:517.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.513s. + +2/27/22 7:57:33 PM :Debug: Time:517.514s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.588s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.588s. + +2/27/22 7:57:33 PM :Debug: Time:517.588s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.653s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.653s. + +2/27/22 7:57:33 PM :Debug: Time:517.654s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.717s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.717s. + +2/27/22 7:57:33 PM :Debug: Time:517.717s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.78s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.78s. + +2/27/22 7:57:33 PM :Debug: Time:517.78s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.848s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.848s. + +2/27/22 7:57:33 PM :Debug: Time:517.848s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.913s. + +2/27/22 7:57:33 PM :Debug: Time:517.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:517.986s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:517.986s. + +2/27/22 7:57:33 PM :Debug: Time:517.986s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:33 PM :Debug: Time:518.05s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:33 PM :Debug: Time:518.05s. + +2/27/22 7:57:33 PM :Debug: Time:518.05s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.121s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.122s. + +2/27/22 7:57:34 PM :Debug: Time:518.122s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.189s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.189s. + +2/27/22 7:57:34 PM :Debug: Time:518.19s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.251s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.251s. + +2/27/22 7:57:34 PM :Debug: Time:518.251s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.317s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.317s. + +2/27/22 7:57:34 PM :Debug: Time:518.318s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.386s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.386s. + +2/27/22 7:57:34 PM :Debug: Time:518.386s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.455s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.455s. + +2/27/22 7:57:34 PM :Debug: Time:518.455s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.519s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.519s. + +2/27/22 7:57:34 PM :Debug: Time:518.519s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.589s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.589s. + +2/27/22 7:57:34 PM :Debug: Time:518.589s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:34 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:34 PM :Info: Looks like Speeduino + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.657s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.657s. + +2/27/22 7:57:34 PM :Debug: Time:518.657s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.722s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.722s. + +2/27/22 7:57:34 PM :Debug: Time:518.722s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.785s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.785s. + +2/27/22 7:57:34 PM :Debug: Time:518.785s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.85s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.85s. + +2/27/22 7:57:34 PM :Debug: Time:518.85s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.915s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.915s. + +2/27/22 7:57:34 PM :Debug: Time:518.915s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:518.979s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:518.979s. + +2/27/22 7:57:34 PM :Debug: Time:518.979s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:34 PM :Debug: Time:519.052s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:34 PM :Debug: Time:519.052s. + +2/27/22 7:57:34 PM :Debug: Time:519.052s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.117s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.117s. + +2/27/22 7:57:35 PM :Debug: Time:519.117s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.183s. + +2/27/22 7:57:35 PM :Debug: Time:519.184s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.254s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.255s. + +2/27/22 7:57:35 PM :Debug: Time:519.255s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.322s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.322s. + +2/27/22 7:57:35 PM :Debug: Time:519.322s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.385s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.385s. + +2/27/22 7:57:35 PM :Debug: Time:519.385s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.451s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.451s. + +2/27/22 7:57:35 PM :Debug: Time:519.451s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.515s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.516s. + +2/27/22 7:57:35 PM :Debug: Time:519.516s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.581s. + +2/27/22 7:57:35 PM :Debug: Time:519.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.654s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.654s. + +2/27/22 7:57:35 PM :Debug: Time:519.654s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.718s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.718s. + +2/27/22 7:57:35 PM :Debug: Time:519.718s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.783s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.783s. + +2/27/22 7:57:35 PM :Debug: Time:519.783s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.847s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.847s. + +2/27/22 7:57:35 PM :Debug: Time:519.847s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.913s. + +2/27/22 7:57:35 PM :Debug: Time:519.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:519.985s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:519.985s. + +2/27/22 7:57:35 PM :Debug: Time:519.985s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:35 PM :Debug: Time:520.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:35 PM :Debug: Time:520.047s. + +2/27/22 7:57:35 PM :Debug: Time:520.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.115s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.115s. + +2/27/22 7:57:36 PM :Debug: Time:520.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.18s. + +2/27/22 7:57:36 PM :Debug: Time:520.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.244s. + +2/27/22 7:57:36 PM :Debug: Time:520.244s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:36 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:36 PM :Info: Looks like Speeduino + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.311s. + +2/27/22 7:57:36 PM :Debug: Time:520.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.382s. + +2/27/22 7:57:36 PM :Debug: Time:520.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.448s. + +2/27/22 7:57:36 PM :Debug: Time:520.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.52s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.52s. + +2/27/22 7:57:36 PM :Debug: Time:520.52s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.584s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.585s. + +2/27/22 7:57:36 PM :Debug: Time:520.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.649s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.649s. + +2/27/22 7:57:36 PM :Debug: Time:520.649s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.719s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.719s. + +2/27/22 7:57:36 PM :Debug: Time:520.719s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.782s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.782s. + +2/27/22 7:57:36 PM :Debug: Time:520.782s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.853s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.853s. + +2/27/22 7:57:36 PM :Debug: Time:520.853s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.919s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.919s. + +2/27/22 7:57:36 PM :Debug: Time:520.919s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:520.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:520.984s. + +2/27/22 7:57:36 PM :Debug: Time:520.984s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:36 PM :Debug: Time:521.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:36 PM :Debug: Time:521.047s. + +2/27/22 7:57:36 PM :Debug: Time:521.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.112s. + +2/27/22 7:57:37 PM :Debug: Time:521.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.184s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.185s. + +2/27/22 7:57:37 PM :Debug: Time:521.185s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.252s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.252s. + +2/27/22 7:57:37 PM :Debug: Time:521.252s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.316s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.316s. + +2/27/22 7:57:37 PM :Debug: Time:521.316s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.38s. + +2/27/22 7:57:37 PM :Debug: Time:521.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.445s. + +2/27/22 7:57:37 PM :Debug: Time:521.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.51s. + +2/27/22 7:57:37 PM :Debug: Time:521.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.582s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.582s. + +2/27/22 7:57:37 PM :Debug: Time:521.582s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.647s. + +2/27/22 7:57:37 PM :Debug: Time:521.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.711s. + +2/27/22 7:57:37 PM :Debug: Time:521.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.776s. + +2/27/22 7:57:37 PM :Debug: Time:521.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.849s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.849s. + +2/27/22 7:57:37 PM :Debug: Time:521.849s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:37 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:37 PM :Info: Looks like Speeduino + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.914s. + +2/27/22 7:57:37 PM :Debug: Time:521.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:521.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:521.983s. + +2/27/22 7:57:37 PM :Debug: Time:521.984s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:37 PM :Debug: Time:522.053s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:37 PM :Debug: Time:522.053s. + +2/27/22 7:57:37 PM :Debug: Time:522.053s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.117s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.117s. + +2/27/22 7:57:38 PM :Debug: Time:522.117s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.182s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.182s. + +2/27/22 7:57:38 PM :Debug: Time:522.182s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.247s. + +2/27/22 7:57:38 PM :Debug: Time:522.247s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.319s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.32s. + +2/27/22 7:57:38 PM :Debug: Time:522.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.387s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.387s. + +2/27/22 7:57:38 PM :Debug: Time:522.387s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.452s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.452s. + +2/27/22 7:57:38 PM :Debug: Time:522.452s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.516s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.516s. + +2/27/22 7:57:38 PM :Debug: Time:522.516s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.581s. + +2/27/22 7:57:38 PM :Debug: Time:522.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.646s. + +2/27/22 7:57:38 PM :Debug: Time:522.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.712s. + +2/27/22 7:57:38 PM :Debug: Time:522.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.779s. + +2/27/22 7:57:38 PM :Debug: Time:522.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.849s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.849s. + +2/27/22 7:57:38 PM :Debug: Time:522.849s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.914s. + +2/27/22 7:57:38 PM :Debug: Time:522.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:522.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:522.978s. + +2/27/22 7:57:38 PM :Debug: Time:522.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:38 PM :Debug: Time:523.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:38 PM :Debug: Time:523.049s. + +2/27/22 7:57:38 PM :Debug: Time:523.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.117s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.117s. + +2/27/22 7:57:39 PM :Debug: Time:523.117s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.182s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.182s. + +2/27/22 7:57:39 PM :Debug: Time:523.182s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.249s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.249s. + +2/27/22 7:57:39 PM :Debug: Time:523.249s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.314s. + +2/27/22 7:57:39 PM :Debug: Time:523.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.379s. + +2/27/22 7:57:39 PM :Debug: Time:523.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.444s. + +2/27/22 7:57:39 PM :Debug: Time:523.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.509s. + +2/27/22 7:57:39 PM :Debug: Time:523.509s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:39 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:39 PM :Info: Looks like Speeduino + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.575s. + +2/27/22 7:57:39 PM :Debug: Time:523.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.639s. + +2/27/22 7:57:39 PM :Debug: Time:523.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.706s. + +2/27/22 7:57:39 PM :Debug: Time:523.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.779s. + +2/27/22 7:57:39 PM :Debug: Time:523.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.843s. + +2/27/22 7:57:39 PM :Debug: Time:523.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.907s. + +2/27/22 7:57:39 PM :Debug: Time:523.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:523.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:523.973s. + +2/27/22 7:57:39 PM :Debug: Time:523.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:39 PM :Debug: Time:524.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:39 PM :Debug: Time:524.044s. + +2/27/22 7:57:39 PM :Debug: Time:524.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.11s. + +2/27/22 7:57:40 PM :Debug: Time:524.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.174s. + +2/27/22 7:57:40 PM :Debug: Time:524.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.24s. + +2/27/22 7:57:40 PM :Debug: Time:524.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.311s. + +2/27/22 7:57:40 PM :Debug: Time:524.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.375s. + +2/27/22 7:57:40 PM :Debug: Time:524.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.441s. + +2/27/22 7:57:40 PM :Debug: Time:524.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.506s. + +2/27/22 7:57:40 PM :Debug: Time:524.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.571s. + +2/27/22 7:57:40 PM :Debug: Time:524.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.643s. + +2/27/22 7:57:40 PM :Debug: Time:524.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.712s. + +2/27/22 7:57:40 PM :Debug: Time:524.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.779s. + +2/27/22 7:57:40 PM :Debug: Time:524.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.845s. + +2/27/22 7:57:40 PM :Debug: Time:524.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.908s. + +2/27/22 7:57:40 PM :Debug: Time:524.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:524.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:524.974s. + +2/27/22 7:57:40 PM :Debug: Time:524.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:40 PM :Debug: Time:525.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:40 PM :Debug: Time:525.039s. + +2/27/22 7:57:40 PM :Debug: Time:525.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.112s. + +2/27/22 7:57:41 PM :Debug: Time:525.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.175s. + +2/27/22 7:57:41 PM :Debug: Time:525.175s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:41 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:41 PM :Info: Looks like Speeduino + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.24s. + +2/27/22 7:57:41 PM :Debug: Time:525.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.305s. + +2/27/22 7:57:41 PM :Debug: Time:525.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.378s. + +2/27/22 7:57:41 PM :Debug: Time:525.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.441s. + +2/27/22 7:57:41 PM :Debug: Time:525.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.505s. + +2/27/22 7:57:41 PM :Debug: Time:525.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.578s. + +2/27/22 7:57:41 PM :Debug: Time:525.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.643s. + +2/27/22 7:57:41 PM :Debug: Time:525.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.708s. + +2/27/22 7:57:41 PM :Debug: Time:525.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.772s. + +2/27/22 7:57:41 PM :Debug: Time:525.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.845s. + +2/27/22 7:57:41 PM :Debug: Time:525.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.91s. + +2/27/22 7:57:41 PM :Debug: Time:525.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:525.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:525.974s. + +2/27/22 7:57:41 PM :Debug: Time:525.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:41 PM :Debug: Time:526.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:41 PM :Debug: Time:526.038s. + +2/27/22 7:57:41 PM :Debug: Time:526.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.104s. + +2/27/22 7:57:42 PM :Debug: Time:526.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.171s. + +2/27/22 7:57:42 PM :Debug: Time:526.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.242s. + +2/27/22 7:57:42 PM :Debug: Time:526.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.313s. + +2/27/22 7:57:42 PM :Debug: Time:526.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.382s. + +2/27/22 7:57:42 PM :Debug: Time:526.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.447s. + +2/27/22 7:57:42 PM :Debug: Time:526.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.512s. + +2/27/22 7:57:42 PM :Debug: Time:526.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.582s. + +2/27/22 7:57:42 PM :Debug: Time:526.582s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.643s. + +2/27/22 7:57:42 PM :Debug: Time:526.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.713s. + +2/27/22 7:57:42 PM :Debug: Time:526.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.779s. + +2/27/22 7:57:42 PM :Debug: Time:526.779s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:42 PM :Info: Looks like Speeduino + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.845s. + +2/27/22 7:57:42 PM :Debug: Time:526.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.909s. + +2/27/22 7:57:42 PM :Debug: Time:526.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:526.98s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:526.98s. + +2/27/22 7:57:42 PM :Debug: Time:526.98s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:42 PM :Debug: Time:527.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:42 PM :Debug: Time:527.049s. + +2/27/22 7:57:42 PM :Debug: Time:527.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.113s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.113s. + +2/27/22 7:57:43 PM :Debug: Time:527.113s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.177s. + +2/27/22 7:57:43 PM :Debug: Time:527.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.243s. + +2/27/22 7:57:43 PM :Debug: Time:527.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.307s. + +2/27/22 7:57:43 PM :Debug: Time:527.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.379s. + +2/27/22 7:57:43 PM :Debug: Time:527.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.444s. + +2/27/22 7:57:43 PM :Debug: Time:527.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.508s. + +2/27/22 7:57:43 PM :Debug: Time:527.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.572s. + +2/27/22 7:57:43 PM :Debug: Time:527.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.644s. + +2/27/22 7:57:43 PM :Debug: Time:527.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.714s. + +2/27/22 7:57:43 PM :Debug: Time:527.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.776s. + +2/27/22 7:57:43 PM :Debug: Time:527.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.847s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.847s. + +2/27/22 7:57:43 PM :Debug: Time:527.847s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.911s. + +2/27/22 7:57:43 PM :Debug: Time:527.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:527.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:527.977s. + +2/27/22 7:57:43 PM :Debug: Time:527.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:43 PM :Debug: Time:528.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:43 PM :Debug: Time:528.047s. + +2/27/22 7:57:43 PM :Debug: Time:528.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.116s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.116s. + +2/27/22 7:57:44 PM :Debug: Time:528.116s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.18s. + +2/27/22 7:57:44 PM :Debug: Time:528.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.245s. + +2/27/22 7:57:44 PM :Debug: Time:528.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.31s. + +2/27/22 7:57:44 PM :Debug: Time:528.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.376s. + +2/27/22 7:57:44 PM :Debug: Time:528.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.441s. + +2/27/22 7:57:44 PM :Debug: Time:528.441s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:44 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:44 PM :Info: Looks like Speeduino + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.506s. + +2/27/22 7:57:44 PM :Debug: Time:528.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.578s. + +2/27/22 7:57:44 PM :Debug: Time:528.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.645s. + +2/27/22 7:57:44 PM :Debug: Time:528.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.709s. + +2/27/22 7:57:44 PM :Debug: Time:528.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.774s. + +2/27/22 7:57:44 PM :Debug: Time:528.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.846s. + +2/27/22 7:57:44 PM :Debug: Time:528.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.907s. + +2/27/22 7:57:44 PM :Debug: Time:528.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:528.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:528.977s. + +2/27/22 7:57:44 PM :Debug: Time:528.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:44 PM :Debug: Time:529.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:44 PM :Debug: Time:529.046s. + +2/27/22 7:57:44 PM :Debug: Time:529.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.112s. + +2/27/22 7:57:45 PM :Debug: Time:529.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.177s. + +2/27/22 7:57:45 PM :Debug: Time:529.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.247s. + +2/27/22 7:57:45 PM :Debug: Time:529.247s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.308s. + +2/27/22 7:57:45 PM :Debug: Time:529.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.379s. + +2/27/22 7:57:45 PM :Debug: Time:529.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.443s. + +2/27/22 7:57:45 PM :Debug: Time:529.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.514s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.514s. + +2/27/22 7:57:45 PM :Debug: Time:529.514s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.576s. + +2/27/22 7:57:45 PM :Debug: Time:529.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.646s. + +2/27/22 7:57:45 PM :Debug: Time:529.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.711s. + +2/27/22 7:57:45 PM :Debug: Time:529.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.777s. + +2/27/22 7:57:45 PM :Debug: Time:529.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.84s. + +2/27/22 7:57:45 PM :Debug: Time:529.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.907s. + +2/27/22 7:57:45 PM :Debug: Time:529.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:529.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:529.978s. + +2/27/22 7:57:45 PM :Debug: Time:529.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:45 PM :Debug: Time:530.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:45 PM :Debug: Time:530.043s. + +2/27/22 7:57:45 PM :Debug: Time:530.043s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:46 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:46 PM :Info: Looks like Speeduino + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.106s. + +2/27/22 7:57:46 PM :Debug: Time:530.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.171s. + +2/27/22 7:57:46 PM :Debug: Time:530.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.243s. + +2/27/22 7:57:46 PM :Debug: Time:530.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.313s. + +2/27/22 7:57:46 PM :Debug: Time:530.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.381s. + +2/27/22 7:57:46 PM :Debug: Time:530.381s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.445s. + +2/27/22 7:57:46 PM :Debug: Time:530.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.509s. + +2/27/22 7:57:46 PM :Debug: Time:530.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.58s. + +2/27/22 7:57:46 PM :Debug: Time:530.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.647s. + +2/27/22 7:57:46 PM :Debug: Time:530.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.713s. + +2/27/22 7:57:46 PM :Debug: Time:530.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.777s. + +2/27/22 7:57:46 PM :Debug: Time:530.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.847s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.847s. + +2/27/22 7:57:46 PM :Debug: Time:530.847s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.914s. + +2/27/22 7:57:46 PM :Debug: Time:530.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:530.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:530.978s. + +2/27/22 7:57:46 PM :Debug: Time:530.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:46 PM :Debug: Time:531.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:46 PM :Debug: Time:531.042s. + +2/27/22 7:57:46 PM :Debug: Time:531.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.107s. + +2/27/22 7:57:47 PM :Debug: Time:531.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.179s. + +2/27/22 7:57:47 PM :Debug: Time:531.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.244s. + +2/27/22 7:57:47 PM :Debug: Time:531.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.307s. + +2/27/22 7:57:47 PM :Debug: Time:531.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.372s. + +2/27/22 7:57:47 PM :Debug: Time:531.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.443s. + +2/27/22 7:57:47 PM :Debug: Time:531.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.509s. + +2/27/22 7:57:47 PM :Debug: Time:531.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.573s. + +2/27/22 7:57:47 PM :Debug: Time:531.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.638s. + +2/27/22 7:57:47 PM :Debug: Time:531.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.704s. + +2/27/22 7:57:47 PM :Debug: Time:531.704s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:47 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:47 PM :Info: Looks like Speeduino + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.776s. + +2/27/22 7:57:47 PM :Debug: Time:531.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.841s. + +2/27/22 7:57:47 PM :Debug: Time:531.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.905s. + +2/27/22 7:57:47 PM :Debug: Time:531.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:531.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:531.971s. + +2/27/22 7:57:47 PM :Debug: Time:531.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:47 PM :Debug: Time:532.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:47 PM :Debug: Time:532.043s. + +2/27/22 7:57:47 PM :Debug: Time:532.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.107s. + +2/27/22 7:57:48 PM :Debug: Time:532.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.172s. + +2/27/22 7:57:48 PM :Debug: Time:532.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.239s. + +2/27/22 7:57:48 PM :Debug: Time:532.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.309s. + +2/27/22 7:57:48 PM :Debug: Time:532.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.374s. + +2/27/22 7:57:48 PM :Debug: Time:532.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.44s. + +2/27/22 7:57:48 PM :Debug: Time:532.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.51s. + +2/27/22 7:57:48 PM :Debug: Time:532.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.575s. + +2/27/22 7:57:48 PM :Debug: Time:532.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.64s. + +2/27/22 7:57:48 PM :Debug: Time:532.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.711s. + +2/27/22 7:57:48 PM :Debug: Time:532.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.772s. + +2/27/22 7:57:48 PM :Debug: Time:532.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.843s. + +2/27/22 7:57:48 PM :Debug: Time:532.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.908s. + +2/27/22 7:57:48 PM :Debug: Time:532.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:532.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:532.973s. + +2/27/22 7:57:48 PM :Debug: Time:532.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:48 PM :Debug: Time:533.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:48 PM :Debug: Time:533.037s. + +2/27/22 7:57:48 PM :Debug: Time:533.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.102s. + +2/27/22 7:57:49 PM :Debug: Time:533.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.175s. + +2/27/22 7:57:49 PM :Debug: Time:533.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.241s. + +2/27/22 7:57:49 PM :Debug: Time:533.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.305s. + +2/27/22 7:57:49 PM :Debug: Time:533.305s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:49 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:49 PM :Info: Looks like Speeduino + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.369s. + +2/27/22 7:57:49 PM :Debug: Time:533.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.436s. + +2/27/22 7:57:49 PM :Debug: Time:533.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.502s. + +2/27/22 7:57:49 PM :Debug: Time:533.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.578s. + +2/27/22 7:57:49 PM :Debug: Time:533.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.645s. + +2/27/22 7:57:49 PM :Debug: Time:533.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.715s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.715s. + +2/27/22 7:57:49 PM :Debug: Time:533.715s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.775s. + +2/27/22 7:57:49 PM :Debug: Time:533.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.84s. + +2/27/22 7:57:49 PM :Debug: Time:533.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.905s. + +2/27/22 7:57:49 PM :Debug: Time:533.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:533.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:533.969s. + +2/27/22 7:57:49 PM :Debug: Time:533.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:49 PM :Debug: Time:534.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:49 PM :Debug: Time:534.035s. + +2/27/22 7:57:49 PM :Debug: Time:534.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.107s. + +2/27/22 7:57:50 PM :Debug: Time:534.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.172s. + +2/27/22 7:57:50 PM :Debug: Time:534.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.238s. + +2/27/22 7:57:50 PM :Debug: Time:534.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.31s. + +2/27/22 7:57:50 PM :Debug: Time:534.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.373s. + +2/27/22 7:57:50 PM :Debug: Time:534.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.436s. + +2/27/22 7:57:50 PM :Debug: Time:534.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.502s. + +2/27/22 7:57:50 PM :Debug: Time:534.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.567s. + +2/27/22 7:57:50 PM :Debug: Time:534.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.641s. + +2/27/22 7:57:50 PM :Debug: Time:534.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.706s. + +2/27/22 7:57:50 PM :Debug: Time:534.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.777s. + +2/27/22 7:57:50 PM :Debug: Time:534.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.841s. + +2/27/22 7:57:50 PM :Debug: Time:534.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.911s. + +2/27/22 7:57:50 PM :Debug: Time:534.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:534.979s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:534.979s. + +2/27/22 7:57:50 PM :Debug: Time:534.979s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:50 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:50 PM :Info: Looks like Speeduino + +2/27/22 7:57:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:50 PM :Debug: Time:535.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:50 PM :Debug: Time:535.045s. + +2/27/22 7:57:50 PM :Debug: Time:535.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.107s. + +2/27/22 7:57:51 PM :Debug: Time:535.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.179s. + +2/27/22 7:57:51 PM :Debug: Time:535.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.247s. + +2/27/22 7:57:51 PM :Debug: Time:535.247s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.312s. + +2/27/22 7:57:51 PM :Debug: Time:535.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.376s. + +2/27/22 7:57:51 PM :Debug: Time:535.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.441s. + +2/27/22 7:57:51 PM :Debug: Time:535.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.507s. + +2/27/22 7:57:51 PM :Debug: Time:535.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.572s. + +2/27/22 7:57:51 PM :Debug: Time:535.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.637s. + +2/27/22 7:57:51 PM :Debug: Time:535.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.702s. + +2/27/22 7:57:51 PM :Debug: Time:535.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.774s. + +2/27/22 7:57:51 PM :Debug: Time:535.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.845s. + +2/27/22 7:57:51 PM :Debug: Time:535.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.913s. + +2/27/22 7:57:51 PM :Debug: Time:535.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:535.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:535.978s. + +2/27/22 7:57:51 PM :Debug: Time:535.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:51 PM :Debug: Time:536.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:51 PM :Debug: Time:536.039s. + +2/27/22 7:57:51 PM :Debug: Time:536.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.107s. + +2/27/22 7:57:52 PM :Debug: Time:536.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.178s. + +2/27/22 7:57:52 PM :Debug: Time:536.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.246s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.246s. + +2/27/22 7:57:52 PM :Debug: Time:536.246s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.312s. + +2/27/22 7:57:52 PM :Debug: Time:536.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.377s. + +2/27/22 7:57:52 PM :Debug: Time:536.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.442s. + +2/27/22 7:57:52 PM :Debug: Time:536.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.507s. + +2/27/22 7:57:52 PM :Debug: Time:536.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.572s. + +2/27/22 7:57:52 PM :Debug: Time:536.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.638s. + +2/27/22 7:57:52 PM :Debug: Time:536.638s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:52 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:52 PM :Info: Looks like Speeduino + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.703s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.703s. + +2/27/22 7:57:52 PM :Debug: Time:536.703s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.776s. + +2/27/22 7:57:52 PM :Debug: Time:536.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.841s. + +2/27/22 7:57:52 PM :Debug: Time:536.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.911s. + +2/27/22 7:57:52 PM :Debug: Time:536.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:536.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:536.981s. + +2/27/22 7:57:52 PM :Debug: Time:536.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:52 PM :Debug: Time:537.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:52 PM :Debug: Time:537.045s. + +2/27/22 7:57:52 PM :Debug: Time:537.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.111s. + +2/27/22 7:57:53 PM :Debug: Time:537.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.176s. + +2/27/22 7:57:53 PM :Debug: Time:537.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.239s. + +2/27/22 7:57:53 PM :Debug: Time:537.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.304s. + +2/27/22 7:57:53 PM :Debug: Time:537.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.371s. + +2/27/22 7:57:53 PM :Debug: Time:537.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.438s. + +2/27/22 7:57:53 PM :Debug: Time:537.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.503s. + +2/27/22 7:57:53 PM :Debug: Time:537.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.572s. + +2/27/22 7:57:53 PM :Debug: Time:537.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.642s. + +2/27/22 7:57:53 PM :Debug: Time:537.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.708s. + +2/27/22 7:57:53 PM :Debug: Time:537.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.772s. + +2/27/22 7:57:53 PM :Debug: Time:537.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.843s. + +2/27/22 7:57:53 PM :Debug: Time:537.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.911s. + +2/27/22 7:57:53 PM :Debug: Time:537.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:537.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:537.974s. + +2/27/22 7:57:53 PM :Debug: Time:537.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:53 PM :Debug: Time:538.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:53 PM :Debug: Time:538.04s. + +2/27/22 7:57:53 PM :Debug: Time:538.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.109s. + +2/27/22 7:57:54 PM :Debug: Time:538.109s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.17s. + +2/27/22 7:57:54 PM :Debug: Time:538.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.24s. + +2/27/22 7:57:54 PM :Debug: Time:538.24s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:54 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:54 PM :Info: Looks like Speeduino + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.304s. + +2/27/22 7:57:54 PM :Debug: Time:538.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.369s. + +2/27/22 7:57:54 PM :Debug: Time:538.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.432s. + +2/27/22 7:57:54 PM :Debug: Time:538.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.499s. + +2/27/22 7:57:54 PM :Debug: Time:538.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.572s. + +2/27/22 7:57:54 PM :Debug: Time:538.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.637s. + +2/27/22 7:57:54 PM :Debug: Time:538.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.708s. + +2/27/22 7:57:54 PM :Debug: Time:538.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.773s. + +2/27/22 7:57:54 PM :Debug: Time:538.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.837s. + +2/27/22 7:57:54 PM :Debug: Time:538.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.901s. + +2/27/22 7:57:54 PM :Debug: Time:538.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:538.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:538.968s. + +2/27/22 7:57:54 PM :Debug: Time:538.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:54 PM :Debug: Time:539.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:54 PM :Debug: Time:539.04s. + +2/27/22 7:57:54 PM :Debug: Time:539.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.102s. + +2/27/22 7:57:55 PM :Debug: Time:539.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.17s. + +2/27/22 7:57:55 PM :Debug: Time:539.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.24s. + +2/27/22 7:57:55 PM :Debug: Time:539.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.305s. + +2/27/22 7:57:55 PM :Debug: Time:539.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.371s. + +2/27/22 7:57:55 PM :Debug: Time:539.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.435s. + +2/27/22 7:57:55 PM :Debug: Time:539.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.499s. + +2/27/22 7:57:55 PM :Debug: Time:539.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.572s. + +2/27/22 7:57:55 PM :Debug: Time:539.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.642s. + +2/27/22 7:57:55 PM :Debug: Time:539.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.71s. + +2/27/22 7:57:55 PM :Debug: Time:539.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.775s. + +2/27/22 7:57:55 PM :Debug: Time:539.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.84s. + +2/27/22 7:57:55 PM :Debug: Time:539.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.909s. + +2/27/22 7:57:55 PM :Debug: Time:539.909s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:55 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:55 PM :Info: Looks like Speeduino + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:539.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:539.977s. + +2/27/22 7:57:55 PM :Debug: Time:539.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:55 PM :Debug: Time:540.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:55 PM :Debug: Time:540.042s. + +2/27/22 7:57:55 PM :Debug: Time:540.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.107s. + +2/27/22 7:57:56 PM :Debug: Time:540.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.171s. + +2/27/22 7:57:56 PM :Debug: Time:540.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.237s. + +2/27/22 7:57:56 PM :Debug: Time:540.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.303s. + +2/27/22 7:57:56 PM :Debug: Time:540.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.367s. + +2/27/22 7:57:56 PM :Debug: Time:540.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.44s. + +2/27/22 7:57:56 PM :Debug: Time:540.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.509s. + +2/27/22 7:57:56 PM :Debug: Time:540.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.577s. + +2/27/22 7:57:56 PM :Debug: Time:540.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.64s. + +2/27/22 7:57:56 PM :Debug: Time:540.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.705s. + +2/27/22 7:57:56 PM :Debug: Time:540.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.769s. + +2/27/22 7:57:56 PM :Debug: Time:540.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.834s. + +2/27/22 7:57:56 PM :Debug: Time:540.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.907s. + +2/27/22 7:57:56 PM :Debug: Time:540.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:540.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:540.971s. + +2/27/22 7:57:56 PM :Debug: Time:540.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:56 PM :Debug: Time:541.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:56 PM :Debug: Time:541.042s. + +2/27/22 7:57:56 PM :Debug: Time:541.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.111s. + +2/27/22 7:57:57 PM :Debug: Time:541.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.174s. + +2/27/22 7:57:57 PM :Debug: Time:541.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.238s. + +2/27/22 7:57:57 PM :Debug: Time:541.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.304s. + +2/27/22 7:57:57 PM :Debug: Time:541.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.375s. + +2/27/22 7:57:57 PM :Debug: Time:541.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.439s. + +2/27/22 7:57:57 PM :Debug: Time:541.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.504s. + +2/27/22 7:57:57 PM :Debug: Time:541.504s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:57 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:57 PM :Info: Looks like Speeduino + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.57s. + +2/27/22 7:57:57 PM :Debug: Time:541.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.635s. + +2/27/22 7:57:57 PM :Debug: Time:541.635s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.704s. + +2/27/22 7:57:57 PM :Debug: Time:541.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.769s. + +2/27/22 7:57:57 PM :Debug: Time:541.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.84s. + +2/27/22 7:57:57 PM :Debug: Time:541.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.902s. + +2/27/22 7:57:57 PM :Debug: Time:541.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:541.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:541.972s. + +2/27/22 7:57:57 PM :Debug: Time:541.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:57 PM :Debug: Time:542.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:57 PM :Debug: Time:542.037s. + +2/27/22 7:57:57 PM :Debug: Time:542.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.106s. + +2/27/22 7:57:58 PM :Debug: Time:542.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.169s. + +2/27/22 7:57:58 PM :Debug: Time:542.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.239s. + +2/27/22 7:57:58 PM :Debug: Time:542.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.304s. + +2/27/22 7:57:58 PM :Debug: Time:542.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.368s. + +2/27/22 7:57:58 PM :Debug: Time:542.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.431s. + +2/27/22 7:57:58 PM :Debug: Time:542.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.497s. + +2/27/22 7:57:58 PM :Debug: Time:542.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.57s. + +2/27/22 7:57:58 PM :Debug: Time:542.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.634s. + +2/27/22 7:57:58 PM :Debug: Time:542.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.699s. + +2/27/22 7:57:58 PM :Debug: Time:542.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.77s. + +2/27/22 7:57:58 PM :Debug: Time:542.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.836s. + +2/27/22 7:57:58 PM :Debug: Time:542.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.902s. + +2/27/22 7:57:58 PM :Debug: Time:542.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:542.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:542.967s. + +2/27/22 7:57:58 PM :Debug: Time:542.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:58 PM :Debug: Time:543.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:58 PM :Debug: Time:543.031s. + +2/27/22 7:57:58 PM :Debug: Time:543.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.096s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.096s. + +2/27/22 7:57:59 PM :Debug: Time:543.096s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.169s. + +2/27/22 7:57:59 PM :Debug: Time:543.169s. . & . . . . . . . . ~ . . . . . +2/27/22 7:57:59 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:57:59 PM :Info: Looks like Speeduino + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.235s. + +2/27/22 7:57:59 PM :Debug: Time:543.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.3s. + +2/27/22 7:57:59 PM :Debug: Time:543.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.363s. + +2/27/22 7:57:59 PM :Debug: Time:543.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.429s. + +2/27/22 7:57:59 PM :Debug: Time:543.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.503s. + +2/27/22 7:57:59 PM :Debug: Time:543.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.57s. + +2/27/22 7:57:59 PM :Debug: Time:543.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.634s. + +2/27/22 7:57:59 PM :Debug: Time:543.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.705s. + +2/27/22 7:57:59 PM :Debug: Time:543.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.768s. + +2/27/22 7:57:59 PM :Debug: Time:543.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.837s. + +2/27/22 7:57:59 PM :Debug: Time:543.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.906s. + +2/27/22 7:57:59 PM :Debug: Time:543.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:543.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:543.975s. + +2/27/22 7:57:59 PM :Debug: Time:543.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:57:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:57:59 PM :Debug: Time:544.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:57:59 PM :Debug: Time:544.039s. + +2/27/22 7:57:59 PM :Debug: Time:544.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.104s. + +2/27/22 7:58:00 PM :Debug: Time:544.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.168s. + +2/27/22 7:58:00 PM :Debug: Time:544.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.233s. + +2/27/22 7:58:00 PM :Debug: Time:544.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.298s. + +2/27/22 7:58:00 PM :Debug: Time:544.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.37s. + +2/27/22 7:58:00 PM :Debug: Time:544.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.435s. + +2/27/22 7:58:00 PM :Debug: Time:544.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.5s. + +2/27/22 7:58:00 PM :Debug: Time:544.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.564s. + +2/27/22 7:58:00 PM :Debug: Time:544.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.63s. + +2/27/22 7:58:00 PM :Debug: Time:544.63s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.695s. + +2/27/22 7:58:00 PM :Debug: Time:544.695s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.768s. + +2/27/22 7:58:00 PM :Debug: Time:544.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.834s. + +2/27/22 7:58:00 PM :Debug: Time:544.834s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:00 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:00 PM :Info: Looks like Speeduino + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.899s. + +2/27/22 7:58:00 PM :Debug: Time:544.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:544.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:544.965s. + +2/27/22 7:58:00 PM :Debug: Time:544.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:00 PM :Debug: Time:545.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:00 PM :Debug: Time:545.037s. + +2/27/22 7:58:00 PM :Debug: Time:545.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.101s. + +2/27/22 7:58:01 PM :Debug: Time:545.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.165s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.165s. + +2/27/22 7:58:01 PM :Debug: Time:545.165s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.23s. + +2/27/22 7:58:01 PM :Debug: Time:545.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.296s. + +2/27/22 7:58:01 PM :Debug: Time:545.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.369s. + +2/27/22 7:58:01 PM :Debug: Time:545.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.434s. + +2/27/22 7:58:01 PM :Debug: Time:545.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.498s. + +2/27/22 7:58:01 PM :Debug: Time:545.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.57s. + +2/27/22 7:58:01 PM :Debug: Time:545.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.634s. + +2/27/22 7:58:01 PM :Debug: Time:545.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.699s. + +2/27/22 7:58:01 PM :Debug: Time:545.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.763s. + +2/27/22 7:58:01 PM :Debug: Time:545.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.829s. + +2/27/22 7:58:01 PM :Debug: Time:545.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.902s. + +2/27/22 7:58:01 PM :Debug: Time:545.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:545.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:545.964s. + +2/27/22 7:58:01 PM :Debug: Time:545.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:01 PM :Debug: Time:546.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:01 PM :Debug: Time:546.031s. + +2/27/22 7:58:01 PM :Debug: Time:546.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.103s. + +2/27/22 7:58:02 PM :Debug: Time:546.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.169s. + +2/27/22 7:58:02 PM :Debug: Time:546.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.233s. + +2/27/22 7:58:02 PM :Debug: Time:546.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.304s. + +2/27/22 7:58:02 PM :Debug: Time:546.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.369s. + +2/27/22 7:58:02 PM :Debug: Time:546.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.433s. + +2/27/22 7:58:02 PM :Debug: Time:546.433s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:02 PM :Info: Looks like Speeduino + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.503s. + +2/27/22 7:58:02 PM :Debug: Time:546.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.571s. + +2/27/22 7:58:02 PM :Debug: Time:546.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.635s. + +2/27/22 7:58:02 PM :Debug: Time:546.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.701s. + +2/27/22 7:58:02 PM :Debug: Time:546.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.77s. + +2/27/22 7:58:02 PM :Debug: Time:546.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.832s. + +2/27/22 7:58:02 PM :Debug: Time:546.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.903s. + +2/27/22 7:58:02 PM :Debug: Time:546.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:546.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:546.968s. + +2/27/22 7:58:02 PM :Debug: Time:546.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:02 PM :Debug: Time:547.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:02 PM :Debug: Time:547.032s. + +2/27/22 7:58:02 PM :Debug: Time:547.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.103s. + +2/27/22 7:58:03 PM :Debug: Time:547.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.173s. + +2/27/22 7:58:03 PM :Debug: Time:547.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.237s. + +2/27/22 7:58:03 PM :Debug: Time:547.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.302s. + +2/27/22 7:58:03 PM :Debug: Time:547.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.368s. + +2/27/22 7:58:03 PM :Debug: Time:547.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.434s. + +2/27/22 7:58:03 PM :Debug: Time:547.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.496s. + +2/27/22 7:58:03 PM :Debug: Time:547.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.562s. + +2/27/22 7:58:03 PM :Debug: Time:547.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.634s. + +2/27/22 7:58:03 PM :Debug: Time:547.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.7s. + +2/27/22 7:58:03 PM :Debug: Time:547.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.763s. + +2/27/22 7:58:03 PM :Debug: Time:547.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.836s. + +2/27/22 7:58:03 PM :Debug: Time:547.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.901s. + +2/27/22 7:58:03 PM :Debug: Time:547.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:547.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:547.965s. + +2/27/22 7:58:03 PM :Debug: Time:547.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:03 PM :Debug: Time:548.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:03 PM :Debug: Time:548.03s. + +2/27/22 7:58:03 PM :Debug: Time:548.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.102s. + +2/27/22 7:58:04 PM :Debug: Time:548.102s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:04 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:04 PM :Info: Looks like Speeduino + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.168s. + +2/27/22 7:58:04 PM :Debug: Time:548.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.234s. + +2/27/22 7:58:04 PM :Debug: Time:548.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.299s. + +2/27/22 7:58:04 PM :Debug: Time:548.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.363s. + +2/27/22 7:58:04 PM :Debug: Time:548.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.428s. + +2/27/22 7:58:04 PM :Debug: Time:548.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.494s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.494s. + +2/27/22 7:58:04 PM :Debug: Time:548.494s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.567s. + +2/27/22 7:58:04 PM :Debug: Time:548.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.637s. + +2/27/22 7:58:04 PM :Debug: Time:548.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.709s. + +2/27/22 7:58:04 PM :Debug: Time:548.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.77s. + +2/27/22 7:58:04 PM :Debug: Time:548.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.837s. + +2/27/22 7:58:04 PM :Debug: Time:548.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.903s. + +2/27/22 7:58:04 PM :Debug: Time:548.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:548.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:548.967s. + +2/27/22 7:58:04 PM :Debug: Time:548.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:04 PM :Debug: Time:549.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:04 PM :Debug: Time:549.029s. + +2/27/22 7:58:04 PM :Debug: Time:549.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.103s. + +2/27/22 7:58:05 PM :Debug: Time:549.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.172s. + +2/27/22 7:58:05 PM :Debug: Time:549.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.236s. + +2/27/22 7:58:05 PM :Debug: Time:549.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.302s. + +2/27/22 7:58:05 PM :Debug: Time:549.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.366s. + +2/27/22 7:58:05 PM :Debug: Time:549.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.43s. + +2/27/22 7:58:05 PM :Debug: Time:549.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.496s. + +2/27/22 7:58:05 PM :Debug: Time:549.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.568s. + +2/27/22 7:58:05 PM :Debug: Time:549.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.635s. + +2/27/22 7:58:05 PM :Debug: Time:549.635s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.699s. + +2/27/22 7:58:05 PM :Debug: Time:549.699s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:05 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:05 PM :Info: Looks like Speeduino + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.763s. + +2/27/22 7:58:05 PM :Debug: Time:549.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.837s. + +2/27/22 7:58:05 PM :Debug: Time:549.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.901s. + +2/27/22 7:58:05 PM :Debug: Time:549.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:549.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:549.964s. + +2/27/22 7:58:05 PM :Debug: Time:549.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:05 PM :Debug: Time:550.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:05 PM :Debug: Time:550.03s. + +2/27/22 7:58:05 PM :Debug: Time:550.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.103s. + +2/27/22 7:58:06 PM :Debug: Time:550.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.167s. + +2/27/22 7:58:06 PM :Debug: Time:550.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.237s. + +2/27/22 7:58:06 PM :Debug: Time:550.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.305s. + +2/27/22 7:58:06 PM :Debug: Time:550.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.37s. + +2/27/22 7:58:06 PM :Debug: Time:550.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.435s. + +2/27/22 7:58:06 PM :Debug: Time:550.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.504s. + +2/27/22 7:58:06 PM :Debug: Time:550.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.572s. + +2/27/22 7:58:06 PM :Debug: Time:550.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.636s. + +2/27/22 7:58:06 PM :Debug: Time:550.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.701s. + +2/27/22 7:58:06 PM :Debug: Time:550.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.771s. + +2/27/22 7:58:06 PM :Debug: Time:550.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.84s. + +2/27/22 7:58:06 PM :Debug: Time:550.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.905s. + +2/27/22 7:58:06 PM :Debug: Time:550.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:550.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:550.969s. + +2/27/22 7:58:06 PM :Debug: Time:550.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:06 PM :Debug: Time:551.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:06 PM :Debug: Time:551.033s. + +2/27/22 7:58:06 PM :Debug: Time:551.033s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.097s. + +2/27/22 7:58:07 PM :Debug: Time:551.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.169s. + +2/27/22 7:58:07 PM :Debug: Time:551.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.234s. + +2/27/22 7:58:07 PM :Debug: Time:551.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.297s. + +2/27/22 7:58:07 PM :Debug: Time:551.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.362s. + +2/27/22 7:58:07 PM :Debug: Time:551.362s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:07 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:07 PM :Info: Looks like Speeduino + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.435s. + +2/27/22 7:58:07 PM :Debug: Time:551.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.499s. + +2/27/22 7:58:07 PM :Debug: Time:551.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.563s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.563s. + +2/27/22 7:58:07 PM :Debug: Time:551.563s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.629s. + +2/27/22 7:58:07 PM :Debug: Time:551.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.701s. + +2/27/22 7:58:07 PM :Debug: Time:551.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.766s. + +2/27/22 7:58:07 PM :Debug: Time:551.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.837s. + +2/27/22 7:58:07 PM :Debug: Time:551.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.902s. + +2/27/22 7:58:07 PM :Debug: Time:551.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:551.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:551.964s. + +2/27/22 7:58:07 PM :Debug: Time:551.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:07 PM :Debug: Time:552.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:07 PM :Debug: Time:552.03s. + +2/27/22 7:58:07 PM :Debug: Time:552.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.095s. + +2/27/22 7:58:08 PM :Debug: Time:552.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.167s. + +2/27/22 7:58:08 PM :Debug: Time:552.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.236s. + +2/27/22 7:58:08 PM :Debug: Time:552.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.306s. + +2/27/22 7:58:08 PM :Debug: Time:552.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.37s. + +2/27/22 7:58:08 PM :Debug: Time:552.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.435s. + +2/27/22 7:58:08 PM :Debug: Time:552.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.505s. + +2/27/22 7:58:08 PM :Debug: Time:552.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.573s. + +2/27/22 7:58:08 PM :Debug: Time:552.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.638s. + +2/27/22 7:58:08 PM :Debug: Time:552.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.702s. + +2/27/22 7:58:08 PM :Debug: Time:552.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.766s. + +2/27/22 7:58:08 PM :Debug: Time:552.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.837s. + +2/27/22 7:58:08 PM :Debug: Time:552.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.901s. + +2/27/22 7:58:08 PM :Debug: Time:552.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:552.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:552.966s. + +2/27/22 7:58:08 PM :Debug: Time:552.966s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:08 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:08 PM :Info: Looks like Speeduino + +2/27/22 7:58:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:08 PM :Debug: Time:553.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:08 PM :Debug: Time:553.035s. + +2/27/22 7:58:08 PM :Debug: Time:553.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.098s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.098s. + +2/27/22 7:58:09 PM :Debug: Time:553.098s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.168s. + +2/27/22 7:58:09 PM :Debug: Time:553.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.231s. + +2/27/22 7:58:09 PM :Debug: Time:553.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.296s. + +2/27/22 7:58:09 PM :Debug: Time:553.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.368s. + +2/27/22 7:58:09 PM :Debug: Time:553.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.432s. + +2/27/22 7:58:09 PM :Debug: Time:553.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.496s. + +2/27/22 7:58:09 PM :Debug: Time:553.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.561s. + +2/27/22 7:58:09 PM :Debug: Time:553.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.627s. + +2/27/22 7:58:09 PM :Debug: Time:553.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.7s. + +2/27/22 7:58:09 PM :Debug: Time:553.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.769s. + +2/27/22 7:58:09 PM :Debug: Time:553.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.837s. + +2/27/22 7:58:09 PM :Debug: Time:553.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.902s. + +2/27/22 7:58:09 PM :Debug: Time:553.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:553.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:553.966s. + +2/27/22 7:58:09 PM :Debug: Time:553.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:09 PM :Debug: Time:554.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:09 PM :Debug: Time:554.029s. + +2/27/22 7:58:09 PM :Debug: Time:554.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.094s. + +2/27/22 7:58:10 PM :Debug: Time:554.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.16s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.16s. + +2/27/22 7:58:10 PM :Debug: Time:554.16s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.232s. + +2/27/22 7:58:10 PM :Debug: Time:554.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.297s. + +2/27/22 7:58:10 PM :Debug: Time:554.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.362s. + +2/27/22 7:58:10 PM :Debug: Time:554.362s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.428s. + +2/27/22 7:58:10 PM :Debug: Time:554.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.5s. + +2/27/22 7:58:10 PM :Debug: Time:554.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.57s. + +2/27/22 7:58:10 PM :Debug: Time:554.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.638s. + +2/27/22 7:58:10 PM :Debug: Time:554.638s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:10 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:10 PM :Info: Looks like Speeduino + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.702s. + +2/27/22 7:58:10 PM :Debug: Time:554.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.768s. + +2/27/22 7:58:10 PM :Debug: Time:554.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.835s. + +2/27/22 7:58:10 PM :Debug: Time:554.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.903s. + +2/27/22 7:58:10 PM :Debug: Time:554.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:554.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:554.968s. + +2/27/22 7:58:10 PM :Debug: Time:554.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:10 PM :Debug: Time:555.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:10 PM :Debug: Time:555.038s. + +2/27/22 7:58:10 PM :Debug: Time:555.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.106s. + +2/27/22 7:58:11 PM :Debug: Time:555.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.17s. + +2/27/22 7:58:11 PM :Debug: Time:555.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.234s. + +2/27/22 7:58:11 PM :Debug: Time:555.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.304s. + +2/27/22 7:58:11 PM :Debug: Time:555.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.373s. + +2/27/22 7:58:11 PM :Debug: Time:555.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.436s. + +2/27/22 7:58:11 PM :Debug: Time:555.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.501s. + +2/27/22 7:58:11 PM :Debug: Time:555.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.571s. + +2/27/22 7:58:11 PM :Debug: Time:555.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.636s. + +2/27/22 7:58:11 PM :Debug: Time:555.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.704s. + +2/27/22 7:58:11 PM :Debug: Time:555.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.768s. + +2/27/22 7:58:11 PM :Debug: Time:555.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.833s. + +2/27/22 7:58:11 PM :Debug: Time:555.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.897s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.897s. + +2/27/22 7:58:11 PM :Debug: Time:555.897s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:555.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:555.968s. + +2/27/22 7:58:11 PM :Debug: Time:555.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:11 PM :Debug: Time:556.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:11 PM :Debug: Time:556.034s. + +2/27/22 7:58:11 PM :Debug: Time:556.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.099s. + +2/27/22 7:58:12 PM :Debug: Time:556.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.163s. + +2/27/22 7:58:12 PM :Debug: Time:556.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.236s. + +2/27/22 7:58:12 PM :Debug: Time:556.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.301s. + +2/27/22 7:58:12 PM :Debug: Time:556.301s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:12 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:12 PM :Info: Looks like Speeduino + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.363s. + +2/27/22 7:58:12 PM :Debug: Time:556.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.43s. + +2/27/22 7:58:12 PM :Debug: Time:556.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.495s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.495s. + +2/27/22 7:58:12 PM :Debug: Time:556.495s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.569s. + +2/27/22 7:58:12 PM :Debug: Time:556.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.632s. + +2/27/22 7:58:12 PM :Debug: Time:556.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.697s. + +2/27/22 7:58:12 PM :Debug: Time:556.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.769s. + +2/27/22 7:58:12 PM :Debug: Time:556.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.834s. + +2/27/22 7:58:12 PM :Debug: Time:556.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.902s. + +2/27/22 7:58:12 PM :Debug: Time:556.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:556.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:556.97s. + +2/27/22 7:58:12 PM :Debug: Time:556.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:12 PM :Debug: Time:557.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:12 PM :Debug: Time:557.034s. + +2/27/22 7:58:12 PM :Debug: Time:557.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.104s. + +2/27/22 7:58:13 PM :Debug: Time:557.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.172s. + +2/27/22 7:58:13 PM :Debug: Time:557.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.236s. + +2/27/22 7:58:13 PM :Debug: Time:557.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.3s. + +2/27/22 7:58:13 PM :Debug: Time:557.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.365s. + +2/27/22 7:58:13 PM :Debug: Time:557.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.431s. + +2/27/22 7:58:13 PM :Debug: Time:557.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.496s. + +2/27/22 7:58:13 PM :Debug: Time:557.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.569s. + +2/27/22 7:58:13 PM :Debug: Time:557.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.632s. + +2/27/22 7:58:13 PM :Debug: Time:557.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.698s. + +2/27/22 7:58:13 PM :Debug: Time:557.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.762s. + +2/27/22 7:58:13 PM :Debug: Time:557.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.828s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.828s. + +2/27/22 7:58:13 PM :Debug: Time:557.828s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.9s. + +2/27/22 7:58:13 PM :Debug: Time:557.9s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:13 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:13 PM :Info: Looks like Speeduino + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:557.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:557.97s. + +2/27/22 7:58:13 PM :Debug: Time:557.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:13 PM :Debug: Time:558.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:13 PM :Debug: Time:558.038s. + +2/27/22 7:58:13 PM :Debug: Time:558.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.103s. + +2/27/22 7:58:14 PM :Debug: Time:558.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.168s. + +2/27/22 7:58:14 PM :Debug: Time:558.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.231s. + +2/27/22 7:58:14 PM :Debug: Time:558.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.295s. + +2/27/22 7:58:14 PM :Debug: Time:558.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.368s. + +2/27/22 7:58:14 PM :Debug: Time:558.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.432s. + +2/27/22 7:58:14 PM :Debug: Time:558.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.502s. + +2/27/22 7:58:14 PM :Debug: Time:558.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.57s. + +2/27/22 7:58:14 PM :Debug: Time:558.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.633s. + +2/27/22 7:58:14 PM :Debug: Time:558.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.698s. + +2/27/22 7:58:14 PM :Debug: Time:558.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.763s. + +2/27/22 7:58:14 PM :Debug: Time:558.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.828s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.828s. + +2/27/22 7:58:14 PM :Debug: Time:558.828s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.899s. + +2/27/22 7:58:14 PM :Debug: Time:558.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:558.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:558.963s. + +2/27/22 7:58:14 PM :Debug: Time:558.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:14 PM :Debug: Time:559.028s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:14 PM :Debug: Time:559.028s. + +2/27/22 7:58:14 PM :Debug: Time:559.028s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.094s. + +2/27/22 7:58:15 PM :Debug: Time:559.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.165s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.165s. + +2/27/22 7:58:15 PM :Debug: Time:559.165s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.23s. + +2/27/22 7:58:15 PM :Debug: Time:559.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.294s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.294s. + +2/27/22 7:58:15 PM :Debug: Time:559.294s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.359s. + +2/27/22 7:58:15 PM :Debug: Time:559.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.436s. + +2/27/22 7:58:15 PM :Debug: Time:559.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.505s. + +2/27/22 7:58:15 PM :Debug: Time:559.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.568s. + +2/27/22 7:58:15 PM :Debug: Time:559.568s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:15 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:15 PM :Info: Looks like Speeduino + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.633s. + +2/27/22 7:58:15 PM :Debug: Time:559.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.703s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.703s. + +2/27/22 7:58:15 PM :Debug: Time:559.703s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.771s. + +2/27/22 7:58:15 PM :Debug: Time:559.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.835s. + +2/27/22 7:58:15 PM :Debug: Time:559.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.9s. + +2/27/22 7:58:15 PM :Debug: Time:559.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:559.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:559.969s. + +2/27/22 7:58:15 PM :Debug: Time:559.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:15 PM :Debug: Time:560.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:15 PM :Debug: Time:560.032s. + +2/27/22 7:58:15 PM :Debug: Time:560.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.103s. + +2/27/22 7:58:16 PM :Debug: Time:560.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.166s. + +2/27/22 7:58:16 PM :Debug: Time:560.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.231s. + +2/27/22 7:58:16 PM :Debug: Time:560.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.296s. + +2/27/22 7:58:16 PM :Debug: Time:560.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.368s. + +2/27/22 7:58:16 PM :Debug: Time:560.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.432s. + +2/27/22 7:58:16 PM :Debug: Time:560.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.496s. + +2/27/22 7:58:16 PM :Debug: Time:560.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.561s. + +2/27/22 7:58:16 PM :Debug: Time:560.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.633s. + +2/27/22 7:58:16 PM :Debug: Time:560.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.704s. + +2/27/22 7:58:16 PM :Debug: Time:560.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.771s. + +2/27/22 7:58:16 PM :Debug: Time:560.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.835s. + +2/27/22 7:58:16 PM :Debug: Time:560.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.9s. + +2/27/22 7:58:16 PM :Debug: Time:560.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:560.979s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:560.979s. + +2/27/22 7:58:16 PM :Debug: Time:560.979s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:16 PM :Debug: Time:561.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:16 PM :Debug: Time:561.038s. + +2/27/22 7:58:16 PM :Debug: Time:561.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.104s. + +2/27/22 7:58:17 PM :Debug: Time:561.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.169s. + +2/27/22 7:58:17 PM :Debug: Time:561.169s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:17 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:17 PM :Info: Looks like Speeduino + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.235s. + +2/27/22 7:58:17 PM :Debug: Time:561.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.305s. + +2/27/22 7:58:17 PM :Debug: Time:561.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.367s. + +2/27/22 7:58:17 PM :Debug: Time:561.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.438s. + +2/27/22 7:58:17 PM :Debug: Time:561.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.502s. + +2/27/22 7:58:17 PM :Debug: Time:561.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.568s. + +2/27/22 7:58:17 PM :Debug: Time:561.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.633s. + +2/27/22 7:58:17 PM :Debug: Time:561.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.706s. + +2/27/22 7:58:17 PM :Debug: Time:561.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.771s. + +2/27/22 7:58:17 PM :Debug: Time:561.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.835s. + +2/27/22 7:58:17 PM :Debug: Time:561.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.901s. + +2/27/22 7:58:17 PM :Debug: Time:561.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:561.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:561.966s. + +2/27/22 7:58:17 PM :Debug: Time:561.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:17 PM :Debug: Time:562.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:17 PM :Debug: Time:562.031s. + +2/27/22 7:58:17 PM :Debug: Time:562.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.102s. + +2/27/22 7:58:18 PM :Debug: Time:562.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.166s. + +2/27/22 7:58:18 PM :Debug: Time:562.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.232s. + +2/27/22 7:58:18 PM :Debug: Time:562.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.298s. + +2/27/22 7:58:18 PM :Debug: Time:562.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.369s. + +2/27/22 7:58:18 PM :Debug: Time:562.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.435s. + +2/27/22 7:58:18 PM :Debug: Time:562.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.499s. + +2/27/22 7:58:18 PM :Debug: Time:562.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.564s. + +2/27/22 7:58:18 PM :Debug: Time:562.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.632s. + +2/27/22 7:58:18 PM :Debug: Time:562.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.704s. + +2/27/22 7:58:18 PM :Debug: Time:562.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.769s. + +2/27/22 7:58:18 PM :Debug: Time:562.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.839s. + +2/27/22 7:58:18 PM :Debug: Time:562.839s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:18 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:18 PM :Info: Looks like Speeduino + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.909s. + +2/27/22 7:58:18 PM :Debug: Time:562.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:562.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:562.973s. + +2/27/22 7:58:18 PM :Debug: Time:562.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:18 PM :Debug: Time:563.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:18 PM :Debug: Time:563.038s. + +2/27/22 7:58:18 PM :Debug: Time:563.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.103s. + +2/27/22 7:58:19 PM :Debug: Time:563.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.167s. + +2/27/22 7:58:19 PM :Debug: Time:563.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.232s. + +2/27/22 7:58:19 PM :Debug: Time:563.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.311s. + +2/27/22 7:58:19 PM :Debug: Time:563.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.37s. + +2/27/22 7:58:19 PM :Debug: Time:563.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.432s. + +2/27/22 7:58:19 PM :Debug: Time:563.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.506s. + +2/27/22 7:58:19 PM :Debug: Time:563.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.575s. + +2/27/22 7:58:19 PM :Debug: Time:563.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.641s. + +2/27/22 7:58:19 PM :Debug: Time:563.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.706s. + +2/27/22 7:58:19 PM :Debug: Time:563.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.77s. + +2/27/22 7:58:19 PM :Debug: Time:563.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.835s. + +2/27/22 7:58:19 PM :Debug: Time:563.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.907s. + +2/27/22 7:58:19 PM :Debug: Time:563.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:563.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:563.975s. + +2/27/22 7:58:19 PM :Debug: Time:563.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:19 PM :Debug: Time:564.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:19 PM :Debug: Time:564.04s. + +2/27/22 7:58:19 PM :Debug: Time:564.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.105s. + +2/27/22 7:58:20 PM :Debug: Time:564.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.17s. + +2/27/22 7:58:20 PM :Debug: Time:564.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.235s. + +2/27/22 7:58:20 PM :Debug: Time:564.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.299s. + +2/27/22 7:58:20 PM :Debug: Time:564.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.365s. + +2/27/22 7:58:20 PM :Debug: Time:564.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.436s. + +2/27/22 7:58:20 PM :Debug: Time:564.436s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:20 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:20 PM :Info: Looks like Speeduino + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.506s. + +2/27/22 7:58:20 PM :Debug: Time:564.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.574s. + +2/27/22 7:58:20 PM :Debug: Time:564.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.638s. + +2/27/22 7:58:20 PM :Debug: Time:564.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.704s. + +2/27/22 7:58:20 PM :Debug: Time:564.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.775s. + +2/27/22 7:58:20 PM :Debug: Time:564.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.837s. + +2/27/22 7:58:20 PM :Debug: Time:564.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.906s. + +2/27/22 7:58:20 PM :Debug: Time:564.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:564.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:564.971s. + +2/27/22 7:58:20 PM :Debug: Time:564.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:20 PM :Debug: Time:565.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:20 PM :Debug: Time:565.042s. + +2/27/22 7:58:20 PM :Debug: Time:565.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.102s. + +2/27/22 7:58:21 PM :Debug: Time:565.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.174s. + +2/27/22 7:58:21 PM :Debug: Time:565.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.238s. + +2/27/22 7:58:21 PM :Debug: Time:565.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.304s. + +2/27/22 7:58:21 PM :Debug: Time:565.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.367s. + +2/27/22 7:58:21 PM :Debug: Time:565.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.433s. + +2/27/22 7:58:21 PM :Debug: Time:565.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.498s. + +2/27/22 7:58:21 PM :Debug: Time:565.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.57s. + +2/27/22 7:58:21 PM :Debug: Time:565.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.632s. + +2/27/22 7:58:21 PM :Debug: Time:565.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.707s. + +2/27/22 7:58:21 PM :Debug: Time:565.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.775s. + +2/27/22 7:58:21 PM :Debug: Time:565.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.84s. + +2/27/22 7:58:21 PM :Debug: Time:565.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.905s. + +2/27/22 7:58:21 PM :Debug: Time:565.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:565.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:565.971s. + +2/27/22 7:58:21 PM :Debug: Time:565.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:21 PM :Debug: Time:566.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:21 PM :Debug: Time:566.041s. + +2/27/22 7:58:21 PM :Debug: Time:566.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.103s. + +2/27/22 7:58:22 PM :Debug: Time:566.103s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:22 PM :Info: Looks like Speeduino + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.174s. + +2/27/22 7:58:22 PM :Debug: Time:566.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.238s. + +2/27/22 7:58:22 PM :Debug: Time:566.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.303s. + +2/27/22 7:58:22 PM :Debug: Time:566.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.373s. + +2/27/22 7:58:22 PM :Debug: Time:566.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.443s. + +2/27/22 7:58:22 PM :Debug: Time:566.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.507s. + +2/27/22 7:58:22 PM :Debug: Time:566.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.572s. + +2/27/22 7:58:22 PM :Debug: Time:566.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.637s. + +2/27/22 7:58:22 PM :Debug: Time:566.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.708s. + +2/27/22 7:58:22 PM :Debug: Time:566.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.776s. + +2/27/22 7:58:22 PM :Debug: Time:566.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.841s. + +2/27/22 7:58:22 PM :Debug: Time:566.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.905s. + +2/27/22 7:58:22 PM :Debug: Time:566.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:566.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:566.97s. + +2/27/22 7:58:22 PM :Debug: Time:566.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:22 PM :Debug: Time:567.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:22 PM :Debug: Time:567.034s. + +2/27/22 7:58:22 PM :Debug: Time:567.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.1s. + +2/27/22 7:58:23 PM :Debug: Time:567.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.172s. + +2/27/22 7:58:23 PM :Debug: Time:567.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.239s. + +2/27/22 7:58:23 PM :Debug: Time:567.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.303s. + +2/27/22 7:58:23 PM :Debug: Time:567.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.366s. + +2/27/22 7:58:23 PM :Debug: Time:567.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.431s. + +2/27/22 7:58:23 PM :Debug: Time:567.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.502s. + +2/27/22 7:58:23 PM :Debug: Time:567.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.572s. + +2/27/22 7:58:23 PM :Debug: Time:567.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.64s. + +2/27/22 7:58:23 PM :Debug: Time:567.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.705s. + +2/27/22 7:58:23 PM :Debug: Time:567.705s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:23 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:23 PM :Info: Looks like Speeduino + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.77s. + +2/27/22 7:58:23 PM :Debug: Time:567.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.84s. + +2/27/22 7:58:23 PM :Debug: Time:567.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.907s. + +2/27/22 7:58:23 PM :Debug: Time:567.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:567.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:567.968s. + +2/27/22 7:58:23 PM :Debug: Time:567.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:23 PM :Debug: Time:568.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:23 PM :Debug: Time:568.038s. + +2/27/22 7:58:23 PM :Debug: Time:568.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.107s. + +2/27/22 7:58:24 PM :Debug: Time:568.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.174s. + +2/27/22 7:58:24 PM :Debug: Time:568.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.239s. + +2/27/22 7:58:24 PM :Debug: Time:568.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.304s. + +2/27/22 7:58:24 PM :Debug: Time:568.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.374s. + +2/27/22 7:58:24 PM :Debug: Time:568.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.441s. + +2/27/22 7:58:24 PM :Debug: Time:568.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.506s. + +2/27/22 7:58:24 PM :Debug: Time:568.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.57s. + +2/27/22 7:58:24 PM :Debug: Time:568.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.64s. + +2/27/22 7:58:24 PM :Debug: Time:568.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.704s. + +2/27/22 7:58:24 PM :Debug: Time:568.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.774s. + +2/27/22 7:58:24 PM :Debug: Time:568.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.839s. + +2/27/22 7:58:24 PM :Debug: Time:568.839s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.904s. + +2/27/22 7:58:24 PM :Debug: Time:568.904s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:568.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:568.974s. + +2/27/22 7:58:24 PM :Debug: Time:568.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:24 PM :Debug: Time:569.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:24 PM :Debug: Time:569.042s. + +2/27/22 7:58:24 PM :Debug: Time:569.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.108s. + +2/27/22 7:58:25 PM :Debug: Time:569.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.172s. + +2/27/22 7:58:25 PM :Debug: Time:569.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.237s. + +2/27/22 7:58:25 PM :Debug: Time:569.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.302s. + +2/27/22 7:58:25 PM :Debug: Time:569.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.367s. + +2/27/22 7:58:25 PM :Debug: Time:569.367s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:25 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:25 PM :Info: Looks like Speeduino + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.434s. + +2/27/22 7:58:25 PM :Debug: Time:569.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.505s. + +2/27/22 7:58:25 PM :Debug: Time:569.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.571s. + +2/27/22 7:58:25 PM :Debug: Time:569.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.633s. + +2/27/22 7:58:25 PM :Debug: Time:569.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.699s. + +2/27/22 7:58:25 PM :Debug: Time:569.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.765s. + +2/27/22 7:58:25 PM :Debug: Time:569.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.837s. + +2/27/22 7:58:25 PM :Debug: Time:569.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.907s. + +2/27/22 7:58:25 PM :Debug: Time:569.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:569.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:569.975s. + +2/27/22 7:58:25 PM :Debug: Time:569.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:25 PM :Debug: Time:570.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:25 PM :Debug: Time:570.039s. + +2/27/22 7:58:25 PM :Debug: Time:570.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.104s. + +2/27/22 7:58:26 PM :Debug: Time:570.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.173s. + +2/27/22 7:58:26 PM :Debug: Time:570.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.24s. + +2/27/22 7:58:26 PM :Debug: Time:570.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.305s. + +2/27/22 7:58:26 PM :Debug: Time:570.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.37s. + +2/27/22 7:58:26 PM :Debug: Time:570.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.441s. + +2/27/22 7:58:26 PM :Debug: Time:570.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.512s. + +2/27/22 7:58:26 PM :Debug: Time:570.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.574s. + +2/27/22 7:58:26 PM :Debug: Time:570.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.637s. + +2/27/22 7:58:26 PM :Debug: Time:570.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.707s. + +2/27/22 7:58:26 PM :Debug: Time:570.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.769s. + +2/27/22 7:58:26 PM :Debug: Time:570.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.838s. + +2/27/22 7:58:26 PM :Debug: Time:570.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.903s. + +2/27/22 7:58:26 PM :Debug: Time:570.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:570.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:570.974s. + +2/27/22 7:58:26 PM :Debug: Time:570.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:26 PM :Debug: Time:571.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:26 PM :Debug: Time:571.036s. + +2/27/22 7:58:26 PM :Debug: Time:571.036s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:27 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:27 PM :Info: Looks like Speeduino + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.106s. + +2/27/22 7:58:27 PM :Debug: Time:571.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.171s. + +2/27/22 7:58:27 PM :Debug: Time:571.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.24s. + +2/27/22 7:58:27 PM :Debug: Time:571.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.303s. + +2/27/22 7:58:27 PM :Debug: Time:571.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.372s. + +2/27/22 7:58:27 PM :Debug: Time:571.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.437s. + +2/27/22 7:58:27 PM :Debug: Time:571.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.501s. + +2/27/22 7:58:27 PM :Debug: Time:571.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.564s. + +2/27/22 7:58:27 PM :Debug: Time:571.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.637s. + +2/27/22 7:58:27 PM :Debug: Time:571.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.702s. + +2/27/22 7:58:27 PM :Debug: Time:571.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.766s. + +2/27/22 7:58:27 PM :Debug: Time:571.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.832s. + +2/27/22 7:58:27 PM :Debug: Time:571.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.904s. + +2/27/22 7:58:27 PM :Debug: Time:571.904s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:571.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:571.967s. + +2/27/22 7:58:27 PM :Debug: Time:571.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:27 PM :Debug: Time:572.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:27 PM :Debug: Time:572.032s. + +2/27/22 7:58:27 PM :Debug: Time:572.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.097s. + +2/27/22 7:58:28 PM :Debug: Time:572.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.169s. + +2/27/22 7:58:28 PM :Debug: Time:572.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.235s. + +2/27/22 7:58:28 PM :Debug: Time:572.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.299s. + +2/27/22 7:58:28 PM :Debug: Time:572.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.364s. + +2/27/22 7:58:28 PM :Debug: Time:572.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.437s. + +2/27/22 7:58:28 PM :Debug: Time:572.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.502s. + +2/27/22 7:58:28 PM :Debug: Time:572.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.567s. + +2/27/22 7:58:28 PM :Debug: Time:572.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.632s. + +2/27/22 7:58:28 PM :Debug: Time:572.632s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:28 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:28 PM :Info: Looks like Speeduino + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.698s. + +2/27/22 7:58:28 PM :Debug: Time:572.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.769s. + +2/27/22 7:58:28 PM :Debug: Time:572.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.835s. + +2/27/22 7:58:28 PM :Debug: Time:572.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.905s. + +2/27/22 7:58:28 PM :Debug: Time:572.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:572.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:572.973s. + +2/27/22 7:58:28 PM :Debug: Time:572.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:28 PM :Debug: Time:573.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:28 PM :Debug: Time:573.038s. + +2/27/22 7:58:28 PM :Debug: Time:573.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.103s. + +2/27/22 7:58:29 PM :Debug: Time:573.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.172s. + +2/27/22 7:58:29 PM :Debug: Time:573.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.243s. + +2/27/22 7:58:29 PM :Debug: Time:573.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.304s. + +2/27/22 7:58:29 PM :Debug: Time:573.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.369s. + +2/27/22 7:58:29 PM :Debug: Time:573.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.434s. + +2/27/22 7:58:29 PM :Debug: Time:573.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.498s. + +2/27/22 7:58:29 PM :Debug: Time:573.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.57s. + +2/27/22 7:58:29 PM :Debug: Time:573.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.636s. + +2/27/22 7:58:29 PM :Debug: Time:573.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.699s. + +2/27/22 7:58:29 PM :Debug: Time:573.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.765s. + +2/27/22 7:58:29 PM :Debug: Time:573.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.831s. + +2/27/22 7:58:29 PM :Debug: Time:573.831s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.902s. + +2/27/22 7:58:29 PM :Debug: Time:573.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:573.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:573.966s. + +2/27/22 7:58:29 PM :Debug: Time:573.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:29 PM :Debug: Time:574.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:29 PM :Debug: Time:574.038s. + +2/27/22 7:58:29 PM :Debug: Time:574.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.103s. + +2/27/22 7:58:30 PM :Debug: Time:574.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.167s. + +2/27/22 7:58:30 PM :Debug: Time:574.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.233s. + +2/27/22 7:58:30 PM :Debug: Time:574.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.297s. + +2/27/22 7:58:30 PM :Debug: Time:574.297s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:30 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:30 PM :Info: Looks like Speeduino + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.37s. + +2/27/22 7:58:30 PM :Debug: Time:574.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.435s. + +2/27/22 7:58:30 PM :Debug: Time:574.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.499s. + +2/27/22 7:58:30 PM :Debug: Time:574.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.571s. + +2/27/22 7:58:30 PM :Debug: Time:574.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.635s. + +2/27/22 7:58:30 PM :Debug: Time:574.635s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.7s. + +2/27/22 7:58:30 PM :Debug: Time:574.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.765s. + +2/27/22 7:58:30 PM :Debug: Time:574.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.837s. + +2/27/22 7:58:30 PM :Debug: Time:574.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.901s. + +2/27/22 7:58:30 PM :Debug: Time:574.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:574.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:574.967s. + +2/27/22 7:58:30 PM :Debug: Time:574.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:30 PM :Debug: Time:575.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:30 PM :Debug: Time:575.031s. + +2/27/22 7:58:30 PM :Debug: Time:575.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.097s. + +2/27/22 7:58:31 PM :Debug: Time:575.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.164s. + +2/27/22 7:58:31 PM :Debug: Time:575.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.233s. + +2/27/22 7:58:31 PM :Debug: Time:575.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.304s. + +2/27/22 7:58:31 PM :Debug: Time:575.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.369s. + +2/27/22 7:58:31 PM :Debug: Time:575.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.44s. + +2/27/22 7:58:31 PM :Debug: Time:575.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.507s. + +2/27/22 7:58:31 PM :Debug: Time:575.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.573s. + +2/27/22 7:58:31 PM :Debug: Time:575.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.637s. + +2/27/22 7:58:31 PM :Debug: Time:575.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.706s. + +2/27/22 7:58:31 PM :Debug: Time:575.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.776s. + +2/27/22 7:58:31 PM :Debug: Time:575.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.84s. + +2/27/22 7:58:31 PM :Debug: Time:575.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.904s. + +2/27/22 7:58:31 PM :Debug: Time:575.904s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:31 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:31 PM :Info: Looks like Speeduino + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:575.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:575.969s. + +2/27/22 7:58:31 PM :Debug: Time:575.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:31 PM :Debug: Time:576.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:31 PM :Debug: Time:576.034s. + +2/27/22 7:58:31 PM :Debug: Time:576.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.103s. + +2/27/22 7:58:32 PM :Debug: Time:576.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.17s. + +2/27/22 7:58:32 PM :Debug: Time:576.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.235s. + +2/27/22 7:58:32 PM :Debug: Time:576.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.298s. + +2/27/22 7:58:32 PM :Debug: Time:576.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.364s. + +2/27/22 7:58:32 PM :Debug: Time:576.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.429s. + +2/27/22 7:58:32 PM :Debug: Time:576.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.501s. + +2/27/22 7:58:32 PM :Debug: Time:576.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.571s. + +2/27/22 7:58:32 PM :Debug: Time:576.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.64s. + +2/27/22 7:58:32 PM :Debug: Time:576.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.704s. + +2/27/22 7:58:32 PM :Debug: Time:576.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.769s. + +2/27/22 7:58:32 PM :Debug: Time:576.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.833s. + +2/27/22 7:58:32 PM :Debug: Time:576.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.898s. + +2/27/22 7:58:32 PM :Debug: Time:576.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:576.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:576.97s. + +2/27/22 7:58:32 PM :Debug: Time:576.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:32 PM :Debug: Time:577.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:32 PM :Debug: Time:577.035s. + +2/27/22 7:58:32 PM :Debug: Time:577.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.104s. + +2/27/22 7:58:33 PM :Debug: Time:577.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.171s. + +2/27/22 7:58:33 PM :Debug: Time:577.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.236s. + +2/27/22 7:58:33 PM :Debug: Time:577.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.301s. + +2/27/22 7:58:33 PM :Debug: Time:577.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.372s. + +2/27/22 7:58:33 PM :Debug: Time:577.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.433s. + +2/27/22 7:58:33 PM :Debug: Time:577.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.503s. + +2/27/22 7:58:33 PM :Debug: Time:577.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.568s. + +2/27/22 7:58:33 PM :Debug: Time:577.568s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:33 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:33 PM :Info: Looks like Speeduino + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.637s. + +2/27/22 7:58:33 PM :Debug: Time:577.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.705s. + +2/27/22 7:58:33 PM :Debug: Time:577.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.769s. + +2/27/22 7:58:33 PM :Debug: Time:577.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.834s. + +2/27/22 7:58:33 PM :Debug: Time:577.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.903s. + +2/27/22 7:58:33 PM :Debug: Time:577.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:577.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:577.966s. + +2/27/22 7:58:33 PM :Debug: Time:577.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:33 PM :Debug: Time:578.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:33 PM :Debug: Time:578.037s. + +2/27/22 7:58:33 PM :Debug: Time:578.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.101s. + +2/27/22 7:58:34 PM :Debug: Time:578.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.168s. + +2/27/22 7:58:34 PM :Debug: Time:578.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.238s. + +2/27/22 7:58:34 PM :Debug: Time:578.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.306s. + +2/27/22 7:58:34 PM :Debug: Time:578.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.369s. + +2/27/22 7:58:34 PM :Debug: Time:578.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.434s. + +2/27/22 7:58:34 PM :Debug: Time:578.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.505s. + +2/27/22 7:58:34 PM :Debug: Time:578.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.573s. + +2/27/22 7:58:34 PM :Debug: Time:578.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.638s. + +2/27/22 7:58:34 PM :Debug: Time:578.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.705s. + +2/27/22 7:58:34 PM :Debug: Time:578.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.768s. + +2/27/22 7:58:34 PM :Debug: Time:578.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.832s. + +2/27/22 7:58:34 PM :Debug: Time:578.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.903s. + +2/27/22 7:58:34 PM :Debug: Time:578.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:578.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:578.972s. + +2/27/22 7:58:34 PM :Debug: Time:578.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:34 PM :Debug: Time:579.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:34 PM :Debug: Time:579.037s. + +2/27/22 7:58:34 PM :Debug: Time:579.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.102s. + +2/27/22 7:58:35 PM :Debug: Time:579.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.166s. + +2/27/22 7:58:35 PM :Debug: Time:579.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.236s. + +2/27/22 7:58:35 PM :Debug: Time:579.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.306s. + +2/27/22 7:58:35 PM :Debug: Time:579.306s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:35 PM :Info: Looks like Speeduino + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.371s. + +2/27/22 7:58:35 PM :Debug: Time:579.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.436s. + +2/27/22 7:58:35 PM :Debug: Time:579.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.5s. + +2/27/22 7:58:35 PM :Debug: Time:579.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.566s. + +2/27/22 7:58:35 PM :Debug: Time:579.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.631s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.631s. + +2/27/22 7:58:35 PM :Debug: Time:579.631s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.697s. + +2/27/22 7:58:35 PM :Debug: Time:579.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.769s. + +2/27/22 7:58:35 PM :Debug: Time:579.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.834s. + +2/27/22 7:58:35 PM :Debug: Time:579.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.902s. + +2/27/22 7:58:35 PM :Debug: Time:579.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:579.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:579.967s. + +2/27/22 7:58:35 PM :Debug: Time:579.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:35 PM :Debug: Time:580.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:35 PM :Debug: Time:580.032s. + +2/27/22 7:58:35 PM :Debug: Time:580.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.097s. + +2/27/22 7:58:36 PM :Debug: Time:580.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.162s. + +2/27/22 7:58:36 PM :Debug: Time:580.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.234s. + +2/27/22 7:58:36 PM :Debug: Time:580.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.299s. + +2/27/22 7:58:36 PM :Debug: Time:580.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.364s. + +2/27/22 7:58:36 PM :Debug: Time:580.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.429s. + +2/27/22 7:58:36 PM :Debug: Time:580.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.493s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.493s. + +2/27/22 7:58:36 PM :Debug: Time:580.493s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.569s. + +2/27/22 7:58:36 PM :Debug: Time:580.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.631s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.632s. + +2/27/22 7:58:36 PM :Debug: Time:580.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.696s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.696s. + +2/27/22 7:58:36 PM :Debug: Time:580.696s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.762s. + +2/27/22 7:58:36 PM :Debug: Time:580.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.833s. + +2/27/22 7:58:36 PM :Debug: Time:580.833s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:36 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:36 PM :Info: Looks like Speeduino + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.899s. + +2/27/22 7:58:36 PM :Debug: Time:580.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:580.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:580.963s. + +2/27/22 7:58:36 PM :Debug: Time:580.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:36 PM :Debug: Time:581.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:36 PM :Debug: Time:581.036s. + +2/27/22 7:58:36 PM :Debug: Time:581.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.099s. + +2/27/22 7:58:37 PM :Debug: Time:581.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.164s. + +2/27/22 7:58:37 PM :Debug: Time:581.165s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.228s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.228s. + +2/27/22 7:58:37 PM :Debug: Time:581.228s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.3s. + +2/27/22 7:58:37 PM :Debug: Time:581.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.365s. + +2/27/22 7:58:37 PM :Debug: Time:581.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.436s. + +2/27/22 7:58:37 PM :Debug: Time:581.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.504s. + +2/27/22 7:58:37 PM :Debug: Time:581.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.57s. + +2/27/22 7:58:37 PM :Debug: Time:581.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.634s. + +2/27/22 7:58:37 PM :Debug: Time:581.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.7s. + +2/27/22 7:58:37 PM :Debug: Time:581.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.765s. + +2/27/22 7:58:37 PM :Debug: Time:581.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.83s. + +2/27/22 7:58:37 PM :Debug: Time:581.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.896s. + +2/27/22 7:58:37 PM :Debug: Time:581.896s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:581.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:581.969s. + +2/27/22 7:58:37 PM :Debug: Time:581.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:37 PM :Debug: Time:582.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:37 PM :Debug: Time:582.031s. + +2/27/22 7:58:37 PM :Debug: Time:582.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.104s. + +2/27/22 7:58:38 PM :Debug: Time:582.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.173s. + +2/27/22 7:58:38 PM :Debug: Time:582.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.237s. + +2/27/22 7:58:38 PM :Debug: Time:582.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.301s. + +2/27/22 7:58:38 PM :Debug: Time:582.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.368s. + +2/27/22 7:58:38 PM :Debug: Time:582.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.431s. + +2/27/22 7:58:38 PM :Debug: Time:582.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.498s. + +2/27/22 7:58:38 PM :Debug: Time:582.498s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:38 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:38 PM :Info: Looks like Speeduino + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.57s. + +2/27/22 7:58:38 PM :Debug: Time:582.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.633s. + +2/27/22 7:58:38 PM :Debug: Time:582.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.699s. + +2/27/22 7:58:38 PM :Debug: Time:582.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.763s. + +2/27/22 7:58:38 PM :Debug: Time:582.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.835s. + +2/27/22 7:58:38 PM :Debug: Time:582.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.899s. + +2/27/22 7:58:38 PM :Debug: Time:582.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:582.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:582.964s. + +2/27/22 7:58:38 PM :Debug: Time:582.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:38 PM :Debug: Time:583.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:38 PM :Debug: Time:583.036s. + +2/27/22 7:58:38 PM :Debug: Time:583.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.1s. + +2/27/22 7:58:39 PM :Debug: Time:583.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.171s. + +2/27/22 7:58:39 PM :Debug: Time:583.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.238s. + +2/27/22 7:58:39 PM :Debug: Time:583.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.303s. + +2/27/22 7:58:39 PM :Debug: Time:583.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.381s. + +2/27/22 7:58:39 PM :Debug: Time:583.381s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.445s. + +2/27/22 7:58:39 PM :Debug: Time:583.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.509s. + +2/27/22 7:58:39 PM :Debug: Time:583.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.573s. + +2/27/22 7:58:39 PM :Debug: Time:583.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.637s. + +2/27/22 7:58:39 PM :Debug: Time:583.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.701s. + +2/27/22 7:58:39 PM :Debug: Time:583.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.765s. + +2/27/22 7:58:39 PM :Debug: Time:583.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.83s. + +2/27/22 7:58:39 PM :Debug: Time:583.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.895s. + +2/27/22 7:58:39 PM :Debug: Time:583.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:583.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:583.967s. + +2/27/22 7:58:39 PM :Debug: Time:583.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:39 PM :Debug: Time:584.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:39 PM :Debug: Time:584.031s. + +2/27/22 7:58:39 PM :Debug: Time:584.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.097s. + +2/27/22 7:58:40 PM :Debug: Time:584.097s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:40 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:40 PM :Info: Looks like Speeduino + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.162s. + +2/27/22 7:58:40 PM :Debug: Time:584.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.235s. + +2/27/22 7:58:40 PM :Debug: Time:584.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.3s. + +2/27/22 7:58:40 PM :Debug: Time:584.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.365s. + +2/27/22 7:58:40 PM :Debug: Time:584.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.437s. + +2/27/22 7:58:40 PM :Debug: Time:584.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.502s. + +2/27/22 7:58:40 PM :Debug: Time:584.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.565s. + +2/27/22 7:58:40 PM :Debug: Time:584.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.63s. + +2/27/22 7:58:40 PM :Debug: Time:584.63s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.695s. + +2/27/22 7:58:40 PM :Debug: Time:584.695s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.76s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.76s. + +2/27/22 7:58:40 PM :Debug: Time:584.76s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.833s. + +2/27/22 7:58:40 PM :Debug: Time:584.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.898s. + +2/27/22 7:58:40 PM :Debug: Time:584.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:584.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:584.964s. + +2/27/22 7:58:40 PM :Debug: Time:584.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:40 PM :Debug: Time:585.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:40 PM :Debug: Time:585.036s. + +2/27/22 7:58:40 PM :Debug: Time:585.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.1s. + +2/27/22 7:58:41 PM :Debug: Time:585.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.163s. + +2/27/22 7:58:41 PM :Debug: Time:585.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.23s. + +2/27/22 7:58:41 PM :Debug: Time:585.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.295s. + +2/27/22 7:58:41 PM :Debug: Time:585.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.367s. + +2/27/22 7:58:41 PM :Debug: Time:585.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.432s. + +2/27/22 7:58:41 PM :Debug: Time:585.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.498s. + +2/27/22 7:58:41 PM :Debug: Time:585.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.569s. + +2/27/22 7:58:41 PM :Debug: Time:585.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.633s. + +2/27/22 7:58:41 PM :Debug: Time:585.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.704s. + +2/27/22 7:58:41 PM :Debug: Time:585.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.772s. + +2/27/22 7:58:41 PM :Debug: Time:585.772s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:41 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:41 PM :Info: Looks like Speeduino + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.833s. + +2/27/22 7:58:41 PM :Debug: Time:585.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.902s. + +2/27/22 7:58:41 PM :Debug: Time:585.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:585.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:585.966s. + +2/27/22 7:58:41 PM :Debug: Time:585.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:41 PM :Debug: Time:586.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:41 PM :Debug: Time:586.032s. + +2/27/22 7:58:41 PM :Debug: Time:586.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.097s. + +2/27/22 7:58:42 PM :Debug: Time:586.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.163s. + +2/27/22 7:58:42 PM :Debug: Time:586.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.234s. + +2/27/22 7:58:42 PM :Debug: Time:586.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.298s. + +2/27/22 7:58:42 PM :Debug: Time:586.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.362s. + +2/27/22 7:58:42 PM :Debug: Time:586.362s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.429s. + +2/27/22 7:58:42 PM :Debug: Time:586.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.5s. + +2/27/22 7:58:42 PM :Debug: Time:586.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.565s. + +2/27/22 7:58:42 PM :Debug: Time:586.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.63s. + +2/27/22 7:58:42 PM :Debug: Time:586.63s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.702s. + +2/27/22 7:58:42 PM :Debug: Time:586.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.766s. + +2/27/22 7:58:42 PM :Debug: Time:586.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.831s. + +2/27/22 7:58:42 PM :Debug: Time:586.831s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.896s. + +2/27/22 7:58:42 PM :Debug: Time:586.896s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:586.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:586.96s. + +2/27/22 7:58:42 PM :Debug: Time:586.96s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:42 PM :Debug: Time:587.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:42 PM :Debug: Time:587.032s. + +2/27/22 7:58:42 PM :Debug: Time:587.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.097s. + +2/27/22 7:58:43 PM :Debug: Time:587.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.162s. + +2/27/22 7:58:43 PM :Debug: Time:587.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.233s. + +2/27/22 7:58:43 PM :Debug: Time:587.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.297s. + +2/27/22 7:58:43 PM :Debug: Time:587.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.362s. + +2/27/22 7:58:43 PM :Debug: Time:587.362s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:43 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:43 PM :Info: Looks like Speeduino + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.427s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.427s. + +2/27/22 7:58:43 PM :Debug: Time:587.427s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.492s. + +2/27/22 7:58:43 PM :Debug: Time:587.492s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.564s. + +2/27/22 7:58:43 PM :Debug: Time:587.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.634s. + +2/27/22 7:58:43 PM :Debug: Time:587.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.701s. + +2/27/22 7:58:43 PM :Debug: Time:587.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.766s. + +2/27/22 7:58:43 PM :Debug: Time:587.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.83s. + +2/27/22 7:58:43 PM :Debug: Time:587.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.895s. + +2/27/22 7:58:43 PM :Debug: Time:587.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:587.959s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:587.959s. + +2/27/22 7:58:43 PM :Debug: Time:587.959s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:43 PM :Debug: Time:588.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:43 PM :Debug: Time:588.031s. + +2/27/22 7:58:43 PM :Debug: Time:588.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.095s. + +2/27/22 7:58:44 PM :Debug: Time:588.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.161s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.161s. + +2/27/22 7:58:44 PM :Debug: Time:588.161s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.226s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.226s. + +2/27/22 7:58:44 PM :Debug: Time:588.226s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.299s. + +2/27/22 7:58:44 PM :Debug: Time:588.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.365s. + +2/27/22 7:58:44 PM :Debug: Time:588.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.434s. + +2/27/22 7:58:44 PM :Debug: Time:588.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.503s. + +2/27/22 7:58:44 PM :Debug: Time:588.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.568s. + +2/27/22 7:58:44 PM :Debug: Time:588.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.632s. + +2/27/22 7:58:44 PM :Debug: Time:588.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.698s. + +2/27/22 7:58:44 PM :Debug: Time:588.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.768s. + +2/27/22 7:58:44 PM :Debug: Time:588.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.83s. + +2/27/22 7:58:44 PM :Debug: Time:588.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.901s. + +2/27/22 7:58:44 PM :Debug: Time:588.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:588.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:588.966s. + +2/27/22 7:58:44 PM :Debug: Time:588.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:44 PM :Debug: Time:589.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:44 PM :Debug: Time:589.031s. + +2/27/22 7:58:44 PM :Debug: Time:589.031s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:45 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:45 PM :Info: Looks like Speeduino + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.094s. + +2/27/22 7:58:45 PM :Debug: Time:589.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.16s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.16s. + +2/27/22 7:58:45 PM :Debug: Time:589.16s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.226s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.226s. + +2/27/22 7:58:45 PM :Debug: Time:589.226s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.298s. + +2/27/22 7:58:45 PM :Debug: Time:589.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.364s. + +2/27/22 7:58:45 PM :Debug: Time:589.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.435s. + +2/27/22 7:58:45 PM :Debug: Time:589.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.503s. + +2/27/22 7:58:45 PM :Debug: Time:589.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.566s. + +2/27/22 7:58:45 PM :Debug: Time:589.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.632s. + +2/27/22 7:58:45 PM :Debug: Time:589.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.697s. + +2/27/22 7:58:45 PM :Debug: Time:589.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.762s. + +2/27/22 7:58:45 PM :Debug: Time:589.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.827s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.827s. + +2/27/22 7:58:45 PM :Debug: Time:589.827s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.892s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.892s. + +2/27/22 7:58:45 PM :Debug: Time:589.892s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:589.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:589.964s. + +2/27/22 7:58:45 PM :Debug: Time:589.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:45 PM :Debug: Time:590.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:45 PM :Debug: Time:590.03s. + +2/27/22 7:58:45 PM :Debug: Time:590.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.101s. + +2/27/22 7:58:46 PM :Debug: Time:590.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.169s. + +2/27/22 7:58:46 PM :Debug: Time:590.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.234s. + +2/27/22 7:58:46 PM :Debug: Time:590.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.298s. + +2/27/22 7:58:46 PM :Debug: Time:590.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.364s. + +2/27/22 7:58:46 PM :Debug: Time:590.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.428s. + +2/27/22 7:58:46 PM :Debug: Time:590.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.493s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.494s. + +2/27/22 7:58:46 PM :Debug: Time:590.494s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.565s. + +2/27/22 7:58:46 PM :Debug: Time:590.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.63s. + +2/27/22 7:58:46 PM :Debug: Time:590.63s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.697s. + +2/27/22 7:58:46 PM :Debug: Time:590.697s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:46 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:46 PM :Info: Looks like Speeduino + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.762s. + +2/27/22 7:58:46 PM :Debug: Time:590.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.832s. + +2/27/22 7:58:46 PM :Debug: Time:590.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.898s. + +2/27/22 7:58:46 PM :Debug: Time:590.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:590.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:590.964s. + +2/27/22 7:58:46 PM :Debug: Time:590.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:46 PM :Debug: Time:591.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:46 PM :Debug: Time:591.029s. + +2/27/22 7:58:46 PM :Debug: Time:591.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.092s. + +2/27/22 7:58:47 PM :Debug: Time:591.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.157s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.157s. + +2/27/22 7:58:47 PM :Debug: Time:591.157s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.222s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.222s. + +2/27/22 7:58:47 PM :Debug: Time:591.222s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.295s. + +2/27/22 7:58:47 PM :Debug: Time:591.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.362s. + +2/27/22 7:58:47 PM :Debug: Time:591.362s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.428s. + +2/27/22 7:58:47 PM :Debug: Time:591.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.499s. + +2/27/22 7:58:47 PM :Debug: Time:591.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.562s. + +2/27/22 7:58:47 PM :Debug: Time:591.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.628s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.628s. + +2/27/22 7:58:47 PM :Debug: Time:591.628s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.698s. + +2/27/22 7:58:47 PM :Debug: Time:591.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.767s. + +2/27/22 7:58:47 PM :Debug: Time:591.767s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.834s. + +2/27/22 7:58:47 PM :Debug: Time:591.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.898s. + +2/27/22 7:58:47 PM :Debug: Time:591.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:591.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:591.963s. + +2/27/22 7:58:47 PM :Debug: Time:591.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:47 PM :Debug: Time:592.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:47 PM :Debug: Time:592.033s. + +2/27/22 7:58:47 PM :Debug: Time:592.033s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.101s. + +2/27/22 7:58:48 PM :Debug: Time:592.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.167s. + +2/27/22 7:58:48 PM :Debug: Time:592.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.231s. + +2/27/22 7:58:48 PM :Debug: Time:592.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.294s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.294s. + +2/27/22 7:58:48 PM :Debug: Time:592.294s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:48 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:48 PM :Info: Looks like Speeduino + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.359s. + +2/27/22 7:58:48 PM :Debug: Time:592.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.423s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.423s. + +2/27/22 7:58:48 PM :Debug: Time:592.423s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.497s. + +2/27/22 7:58:48 PM :Debug: Time:592.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.561s. + +2/27/22 7:58:48 PM :Debug: Time:592.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.632s. + +2/27/22 7:58:48 PM :Debug: Time:592.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.701s. + +2/27/22 7:58:48 PM :Debug: Time:592.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.766s. + +2/27/22 7:58:48 PM :Debug: Time:592.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.829s. + +2/27/22 7:58:48 PM :Debug: Time:592.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.895s. + +2/27/22 7:58:48 PM :Debug: Time:592.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:592.961s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:592.961s. + +2/27/22 7:58:48 PM :Debug: Time:592.961s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:48 PM :Debug: Time:593.024s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:48 PM :Debug: Time:593.024s. + +2/27/22 7:58:48 PM :Debug: Time:593.024s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.09s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.09s. + +2/27/22 7:58:49 PM :Debug: Time:593.091s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.163s. + +2/27/22 7:58:49 PM :Debug: Time:593.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.228s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.228s. + +2/27/22 7:58:49 PM :Debug: Time:593.228s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.293s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.293s. + +2/27/22 7:58:49 PM :Debug: Time:593.293s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.364s. + +2/27/22 7:58:49 PM :Debug: Time:593.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.428s. + +2/27/22 7:58:49 PM :Debug: Time:593.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.493s. + +2/27/22 7:58:49 PM :Debug: Time:593.493s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.557s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.557s. + +2/27/22 7:58:49 PM :Debug: Time:593.557s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.629s. + +2/27/22 7:58:49 PM :Debug: Time:593.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.702s. + +2/27/22 7:58:49 PM :Debug: Time:593.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.768s. + +2/27/22 7:58:49 PM :Debug: Time:593.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.832s. + +2/27/22 7:58:49 PM :Debug: Time:593.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.898s. + +2/27/22 7:58:49 PM :Debug: Time:593.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:593.962s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:593.962s. + +2/27/22 7:58:49 PM :Debug: Time:593.962s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:49 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:49 PM :Info: Looks like Speeduino + +2/27/22 7:58:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:49 PM :Debug: Time:594.027s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:49 PM :Debug: Time:594.027s. + +2/27/22 7:58:49 PM :Debug: Time:594.027s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.092s. + +2/27/22 7:58:50 PM :Debug: Time:594.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.157s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.157s. + +2/27/22 7:58:50 PM :Debug: Time:594.157s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.23s. + +2/27/22 7:58:50 PM :Debug: Time:594.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.299s. + +2/27/22 7:58:50 PM :Debug: Time:594.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.363s. + +2/27/22 7:58:50 PM :Debug: Time:594.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.426s. + +2/27/22 7:58:50 PM :Debug: Time:594.426s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.491s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.491s. + +2/27/22 7:58:50 PM :Debug: Time:594.491s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.556s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.556s. + +2/27/22 7:58:50 PM :Debug: Time:594.556s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.622s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.622s. + +2/27/22 7:58:50 PM :Debug: Time:594.622s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.688s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.688s. + +2/27/22 7:58:50 PM :Debug: Time:594.688s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.766s. + +2/27/22 7:58:50 PM :Debug: Time:594.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.833s. + +2/27/22 7:58:50 PM :Debug: Time:594.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.898s. + +2/27/22 7:58:50 PM :Debug: Time:594.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:594.961s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:594.961s. + +2/27/22 7:58:50 PM :Debug: Time:594.961s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:50 PM :Debug: Time:595.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:50 PM :Debug: Time:595.034s. + +2/27/22 7:58:50 PM :Debug: Time:595.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.101s. + +2/27/22 7:58:51 PM :Debug: Time:595.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.166s. + +2/27/22 7:58:51 PM :Debug: Time:595.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.231s. + +2/27/22 7:58:51 PM :Debug: Time:595.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.295s. + +2/27/22 7:58:51 PM :Debug: Time:595.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.359s. + +2/27/22 7:58:51 PM :Debug: Time:595.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.426s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.426s. + +2/27/22 7:58:51 PM :Debug: Time:595.426s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.497s. + +2/27/22 7:58:51 PM :Debug: Time:595.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.562s. + +2/27/22 7:58:51 PM :Debug: Time:595.562s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:51 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:51 PM :Info: Looks like Speeduino + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.627s. + +2/27/22 7:58:51 PM :Debug: Time:595.628s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.691s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.691s. + +2/27/22 7:58:51 PM :Debug: Time:595.691s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.756s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.756s. + +2/27/22 7:58:51 PM :Debug: Time:595.756s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.83s. + +2/27/22 7:58:51 PM :Debug: Time:595.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.895s. + +2/27/22 7:58:51 PM :Debug: Time:595.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:595.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:595.965s. + +2/27/22 7:58:51 PM :Debug: Time:595.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:51 PM :Debug: Time:596.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:51 PM :Debug: Time:596.033s. + +2/27/22 7:58:51 PM :Debug: Time:596.033s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.099s. + +2/27/22 7:58:52 PM :Debug: Time:596.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.164s. + +2/27/22 7:58:52 PM :Debug: Time:596.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.229s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.229s. + +2/27/22 7:58:52 PM :Debug: Time:596.229s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.291s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.291s. + +2/27/22 7:58:52 PM :Debug: Time:596.291s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.363s. + +2/27/22 7:58:52 PM :Debug: Time:596.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.432s. + +2/27/22 7:58:52 PM :Debug: Time:596.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.5s. + +2/27/22 7:58:52 PM :Debug: Time:596.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.566s. + +2/27/22 7:58:52 PM :Debug: Time:596.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.63s. + +2/27/22 7:58:52 PM :Debug: Time:596.63s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.695s. + +2/27/22 7:58:52 PM :Debug: Time:596.695s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.761s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.761s. + +2/27/22 7:58:52 PM :Debug: Time:596.761s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.824s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.825s. + +2/27/22 7:58:52 PM :Debug: Time:596.825s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.896s. + +2/27/22 7:58:52 PM :Debug: Time:596.896s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:596.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:596.96s. + +2/27/22 7:58:52 PM :Debug: Time:596.961s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:52 PM :Debug: Time:597.025s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:52 PM :Debug: Time:597.025s. + +2/27/22 7:58:52 PM :Debug: Time:597.025s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.092s. + +2/27/22 7:58:53 PM :Debug: Time:597.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.163s. + +2/27/22 7:58:53 PM :Debug: Time:597.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.228s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.228s. + +2/27/22 7:58:53 PM :Debug: Time:597.228s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:53 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:53 PM :Info: Looks like Speeduino + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.291s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.291s. + +2/27/22 7:58:53 PM :Debug: Time:597.291s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.358s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.358s. + +2/27/22 7:58:53 PM :Debug: Time:597.358s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.423s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.423s. + +2/27/22 7:58:53 PM :Debug: Time:597.423s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.495s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.495s. + +2/27/22 7:58:53 PM :Debug: Time:597.495s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.559s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.559s. + +2/27/22 7:58:53 PM :Debug: Time:597.559s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.625s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.625s. + +2/27/22 7:58:53 PM :Debug: Time:597.625s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.696s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.696s. + +2/27/22 7:58:53 PM :Debug: Time:597.696s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.759s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.759s. + +2/27/22 7:58:53 PM :Debug: Time:597.759s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.832s. + +2/27/22 7:58:53 PM :Debug: Time:597.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.9s. + +2/27/22 7:58:53 PM :Debug: Time:597.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:597.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:597.964s. + +2/27/22 7:58:53 PM :Debug: Time:597.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:53 PM :Debug: Time:598.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:53 PM :Debug: Time:598.03s. + +2/27/22 7:58:53 PM :Debug: Time:598.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.1s. + +2/27/22 7:58:54 PM :Debug: Time:598.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.168s. + +2/27/22 7:58:54 PM :Debug: Time:598.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.232s. + +2/27/22 7:58:54 PM :Debug: Time:598.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.296s. + +2/27/22 7:58:54 PM :Debug: Time:598.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.361s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.361s. + +2/27/22 7:58:54 PM :Debug: Time:598.361s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.425s. + +2/27/22 7:58:54 PM :Debug: Time:598.425s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.497s. + +2/27/22 7:58:54 PM :Debug: Time:598.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.561s. + +2/27/22 7:58:54 PM :Debug: Time:598.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.625s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.625s. + +2/27/22 7:58:54 PM :Debug: Time:598.625s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.691s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.691s. + +2/27/22 7:58:54 PM :Debug: Time:598.691s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.763s. + +2/27/22 7:58:54 PM :Debug: Time:598.764s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.83s. + +2/27/22 7:58:54 PM :Debug: Time:598.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.893s. + +2/27/22 7:58:54 PM :Debug: Time:598.893s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:54 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:54 PM :Info: Looks like Speeduino + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:598.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:598.964s. + +2/27/22 7:58:54 PM :Debug: Time:598.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:54 PM :Debug: Time:599.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:54 PM :Debug: Time:599.035s. + +2/27/22 7:58:54 PM :Debug: Time:599.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.097s. + +2/27/22 7:58:55 PM :Debug: Time:599.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.163s. + +2/27/22 7:58:55 PM :Debug: Time:599.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.228s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.228s. + +2/27/22 7:58:55 PM :Debug: Time:599.228s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.295s. + +2/27/22 7:58:55 PM :Debug: Time:599.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.364s. + +2/27/22 7:58:55 PM :Debug: Time:599.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.43s. + +2/27/22 7:58:55 PM :Debug: Time:599.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.495s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.495s. + +2/27/22 7:58:55 PM :Debug: Time:599.495s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.56s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.56s. + +2/27/22 7:58:55 PM :Debug: Time:599.56s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.625s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.625s. + +2/27/22 7:58:55 PM :Debug: Time:599.625s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.689s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.689s. + +2/27/22 7:58:55 PM :Debug: Time:599.69s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.762s. + +2/27/22 7:58:55 PM :Debug: Time:599.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.829s. + +2/27/22 7:58:55 PM :Debug: Time:599.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.899s. + +2/27/22 7:58:55 PM :Debug: Time:599.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:599.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:599.968s. + +2/27/22 7:58:55 PM :Debug: Time:599.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:55 PM :Debug: Time:600.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:55 PM :Debug: Time:600.03s. + +2/27/22 7:58:55 PM :Debug: Time:600.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.095s. + +2/27/22 7:58:56 PM :Debug: Time:600.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.164s. + +2/27/22 7:58:56 PM :Debug: Time:600.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.232s. + +2/27/22 7:58:56 PM :Debug: Time:600.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.296s. + +2/27/22 7:58:56 PM :Debug: Time:600.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.36s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.36s. + +2/27/22 7:58:56 PM :Debug: Time:600.36s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.43s. + +2/27/22 7:58:56 PM :Debug: Time:600.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.492s. + +2/27/22 7:58:56 PM :Debug: Time:600.492s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:56 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:56 PM :Info: Looks like Speeduino + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.563s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.563s. + +2/27/22 7:58:56 PM :Debug: Time:600.563s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.628s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.628s. + +2/27/22 7:58:56 PM :Debug: Time:600.628s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.693s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.693s. + +2/27/22 7:58:56 PM :Debug: Time:600.693s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.759s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.759s. + +2/27/22 7:58:56 PM :Debug: Time:600.759s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.829s. + +2/27/22 7:58:56 PM :Debug: Time:600.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.894s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.894s. + +2/27/22 7:58:56 PM :Debug: Time:600.894s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:600.958s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:600.958s. + +2/27/22 7:58:56 PM :Debug: Time:600.958s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:56 PM :Debug: Time:601.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:56 PM :Debug: Time:601.03s. + +2/27/22 7:58:56 PM :Debug: Time:601.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.094s. + +2/27/22 7:58:57 PM :Debug: Time:601.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.158s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.158s. + +2/27/22 7:58:57 PM :Debug: Time:601.158s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.229s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.229s. + +2/27/22 7:58:57 PM :Debug: Time:601.229s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.296s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.296s. + +2/27/22 7:58:57 PM :Debug: Time:601.296s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.361s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.361s. + +2/27/22 7:58:57 PM :Debug: Time:601.361s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.424s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.424s. + +2/27/22 7:58:57 PM :Debug: Time:601.424s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.49s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.49s. + +2/27/22 7:58:57 PM :Debug: Time:601.49s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.554s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.554s. + +2/27/22 7:58:57 PM :Debug: Time:601.554s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.627s. + +2/27/22 7:58:57 PM :Debug: Time:601.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.692s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.692s. + +2/27/22 7:58:57 PM :Debug: Time:601.692s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.762s. + +2/27/22 7:58:57 PM :Debug: Time:601.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.83s. + +2/27/22 7:58:57 PM :Debug: Time:601.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.895s. + +2/27/22 7:58:57 PM :Debug: Time:601.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:601.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:601.96s. + +2/27/22 7:58:57 PM :Debug: Time:601.96s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:57 PM :Debug: Time:602.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:57 PM :Debug: Time:602.03s. + +2/27/22 7:58:57 PM :Debug: Time:602.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.094s. + +2/27/22 7:58:58 PM :Debug: Time:602.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.163s. + +2/27/22 7:58:58 PM :Debug: Time:602.163s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:58 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:58 PM :Info: Looks like Speeduino + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.229s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.229s. + +2/27/22 7:58:58 PM :Debug: Time:602.229s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.293s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.294s. + +2/27/22 7:58:58 PM :Debug: Time:602.294s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.357s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.357s. + +2/27/22 7:58:58 PM :Debug: Time:602.357s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.425s. + +2/27/22 7:58:58 PM :Debug: Time:602.425s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.489s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.489s. + +2/27/22 7:58:58 PM :Debug: Time:602.489s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.553s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.553s. + +2/27/22 7:58:58 PM :Debug: Time:602.553s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.628s. + +2/27/22 7:58:58 PM :Debug: Time:602.628s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.696s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.696s. + +2/27/22 7:58:58 PM :Debug: Time:602.696s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.761s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.761s. + +2/27/22 7:58:58 PM :Debug: Time:602.761s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.827s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.827s. + +2/27/22 7:58:58 PM :Debug: Time:602.827s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.89s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.89s. + +2/27/22 7:58:58 PM :Debug: Time:602.89s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:602.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:602.963s. + +2/27/22 7:58:58 PM :Debug: Time:602.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:58 PM :Debug: Time:603.033s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:58 PM :Debug: Time:603.033s. + +2/27/22 7:58:58 PM :Debug: Time:603.033s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.095s. + +2/27/22 7:58:59 PM :Debug: Time:603.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.156s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.156s. + +2/27/22 7:58:59 PM :Debug: Time:603.156s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.226s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.226s. + +2/27/22 7:58:59 PM :Debug: Time:603.226s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.29s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.29s. + +2/27/22 7:58:59 PM :Debug: Time:603.29s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.356s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.356s. + +2/27/22 7:58:59 PM :Debug: Time:603.356s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.421s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.421s. + +2/27/22 7:58:59 PM :Debug: Time:603.421s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.49s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.49s. + +2/27/22 7:58:59 PM :Debug: Time:603.49s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.553s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.553s. + +2/27/22 7:58:59 PM :Debug: Time:603.553s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.619s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.619s. + +2/27/22 7:58:59 PM :Debug: Time:603.619s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.684s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.684s. + +2/27/22 7:58:59 PM :Debug: Time:603.684s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.75s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.75s. + +2/27/22 7:58:59 PM :Debug: Time:603.75s. . & . . . . . . . . ~ . . . . . +2/27/22 7:58:59 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:58:59 PM :Info: Looks like Speeduino + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.827s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.827s. + +2/27/22 7:58:59 PM :Debug: Time:603.827s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.897s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.897s. + +2/27/22 7:58:59 PM :Debug: Time:603.897s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:603.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:603.96s. + +2/27/22 7:58:59 PM :Debug: Time:603.96s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:58:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:58:59 PM :Debug: Time:604.025s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:58:59 PM :Debug: Time:604.025s. + +2/27/22 7:58:59 PM :Debug: Time:604.025s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.09s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.09s. + +2/27/22 7:59:00 PM :Debug: Time:604.09s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.156s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.156s. + +2/27/22 7:59:00 PM :Debug: Time:604.156s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.222s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.222s. + +2/27/22 7:59:00 PM :Debug: Time:604.222s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.285s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.285s. + +2/27/22 7:59:00 PM :Debug: Time:604.285s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.351s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.351s. + +2/27/22 7:59:00 PM :Debug: Time:604.351s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.417s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.417s. + +2/27/22 7:59:00 PM :Debug: Time:604.417s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.488s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.488s. + +2/27/22 7:59:00 PM :Debug: Time:604.488s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.555s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.555s. + +2/27/22 7:59:00 PM :Debug: Time:604.555s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.619s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.619s. + +2/27/22 7:59:00 PM :Debug: Time:604.62s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.692s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.692s. + +2/27/22 7:59:00 PM :Debug: Time:604.692s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.758s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.758s. + +2/27/22 7:59:00 PM :Debug: Time:604.758s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.822s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.822s. + +2/27/22 7:59:00 PM :Debug: Time:604.822s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.893s. + +2/27/22 7:59:00 PM :Debug: Time:604.893s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:604.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:604.963s. + +2/27/22 7:59:00 PM :Debug: Time:604.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:00 PM :Debug: Time:605.027s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:00 PM :Debug: Time:605.027s. + +2/27/22 7:59:00 PM :Debug: Time:605.027s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.091s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.091s. + +2/27/22 7:59:01 PM :Debug: Time:605.091s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.161s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.161s. + +2/27/22 7:59:01 PM :Debug: Time:605.161s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.23s. + +2/27/22 7:59:01 PM :Debug: Time:605.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.295s. + +2/27/22 7:59:01 PM :Debug: Time:605.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.359s. + +2/27/22 7:59:01 PM :Debug: Time:605.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.428s. + +2/27/22 7:59:01 PM :Debug: Time:605.428s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:01 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:01 PM :Info: Looks like Speeduino + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.491s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.491s. + +2/27/22 7:59:01 PM :Debug: Time:605.491s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.561s. + +2/27/22 7:59:01 PM :Debug: Time:605.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.626s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.627s. + +2/27/22 7:59:01 PM :Debug: Time:605.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.691s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.691s. + +2/27/22 7:59:01 PM :Debug: Time:605.691s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.762s. + +2/27/22 7:59:01 PM :Debug: Time:605.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.831s. + +2/27/22 7:59:01 PM :Debug: Time:605.831s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.893s. + +2/27/22 7:59:01 PM :Debug: Time:605.893s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:605.958s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:605.958s. + +2/27/22 7:59:01 PM :Debug: Time:605.958s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:01 PM :Debug: Time:606.027s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:01 PM :Debug: Time:606.027s. + +2/27/22 7:59:01 PM :Debug: Time:606.027s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.097s. + +2/27/22 7:59:02 PM :Debug: Time:606.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.161s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.162s. + +2/27/22 7:59:02 PM :Debug: Time:606.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.225s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.226s. + +2/27/22 7:59:02 PM :Debug: Time:606.226s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.291s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.291s. + +2/27/22 7:59:02 PM :Debug: Time:606.291s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.355s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.355s. + +2/27/22 7:59:02 PM :Debug: Time:606.355s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.425s. + +2/27/22 7:59:02 PM :Debug: Time:606.425s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.49s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.49s. + +2/27/22 7:59:02 PM :Debug: Time:606.49s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.555s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.555s. + +2/27/22 7:59:02 PM :Debug: Time:606.555s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.621s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.621s. + +2/27/22 7:59:02 PM :Debug: Time:606.621s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.694s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.694s. + +2/27/22 7:59:02 PM :Debug: Time:606.694s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.759s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.759s. + +2/27/22 7:59:02 PM :Debug: Time:606.759s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.824s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.824s. + +2/27/22 7:59:02 PM :Debug: Time:606.825s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.894s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.894s. + +2/27/22 7:59:02 PM :Debug: Time:606.894s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:606.962s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:606.962s. + +2/27/22 7:59:02 PM :Debug: Time:606.962s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:02 PM :Debug: Time:607.027s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:02 PM :Debug: Time:607.027s. + +2/27/22 7:59:02 PM :Debug: Time:607.028s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:03 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:03 PM :Info: Looks like Speeduino + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.093s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.093s. + +2/27/22 7:59:03 PM :Debug: Time:607.093s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.158s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.158s. + +2/27/22 7:59:03 PM :Debug: Time:607.158s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.222s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.222s. + +2/27/22 7:59:03 PM :Debug: Time:607.222s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.287s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.287s. + +2/27/22 7:59:03 PM :Debug: Time:607.287s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.358s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.358s. + +2/27/22 7:59:03 PM :Debug: Time:607.358s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.423s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.423s. + +2/27/22 7:59:03 PM :Debug: Time:607.424s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.489s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.489s. + +2/27/22 7:59:03 PM :Debug: Time:607.49s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.559s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.559s. + +2/27/22 7:59:03 PM :Debug: Time:607.559s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.627s. + +2/27/22 7:59:03 PM :Debug: Time:607.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.702s. + +2/27/22 7:59:03 PM :Debug: Time:607.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.767s. + +2/27/22 7:59:03 PM :Debug: Time:607.767s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.832s. + +2/27/22 7:59:03 PM :Debug: Time:607.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.895s. + +2/27/22 7:59:03 PM :Debug: Time:607.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:607.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:607.96s. + +2/27/22 7:59:03 PM :Debug: Time:607.96s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:03 PM :Debug: Time:608.024s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:03 PM :Debug: Time:608.024s. + +2/27/22 7:59:03 PM :Debug: Time:608.024s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.09s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.09s. + +2/27/22 7:59:04 PM :Debug: Time:608.09s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.162s. + +2/27/22 7:59:04 PM :Debug: Time:608.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.229s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.229s. + +2/27/22 7:59:04 PM :Debug: Time:608.229s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.295s. + +2/27/22 7:59:04 PM :Debug: Time:608.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.358s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.359s. + +2/27/22 7:59:04 PM :Debug: Time:608.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.422s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.422s. + +2/27/22 7:59:04 PM :Debug: Time:608.422s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.494s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.494s. + +2/27/22 7:59:04 PM :Debug: Time:608.494s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.563s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.563s. + +2/27/22 7:59:04 PM :Debug: Time:608.563s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.627s. + +2/27/22 7:59:04 PM :Debug: Time:608.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.693s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.693s. + +2/27/22 7:59:04 PM :Debug: Time:608.693s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:04 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:04 PM :Info: Looks like Speeduino + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.757s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.757s. + +2/27/22 7:59:04 PM :Debug: Time:608.757s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.826s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.826s. + +2/27/22 7:59:04 PM :Debug: Time:608.826s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.888s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.888s. + +2/27/22 7:59:04 PM :Debug: Time:608.888s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:608.962s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:608.962s. + +2/27/22 7:59:04 PM :Debug: Time:608.962s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:04 PM :Debug: Time:609.024s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:04 PM :Debug: Time:609.024s. + +2/27/22 7:59:04 PM :Debug: Time:609.024s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.088s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.088s. + +2/27/22 7:59:05 PM :Debug: Time:609.088s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.153s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.153s. + +2/27/22 7:59:05 PM :Debug: Time:609.153s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.226s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.226s. + +2/27/22 7:59:05 PM :Debug: Time:609.226s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.29s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.29s. + +2/27/22 7:59:05 PM :Debug: Time:609.29s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.36s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.361s. + +2/27/22 7:59:05 PM :Debug: Time:609.361s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.428s. + +2/27/22 7:59:05 PM :Debug: Time:609.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.491s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.491s. + +2/27/22 7:59:05 PM :Debug: Time:609.491s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.556s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.556s. + +2/27/22 7:59:05 PM :Debug: Time:609.556s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.62s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.62s. + +2/27/22 7:59:05 PM :Debug: Time:609.62s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.692s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.692s. + +2/27/22 7:59:05 PM :Debug: Time:609.692s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.757s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.757s. + +2/27/22 7:59:05 PM :Debug: Time:609.757s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.822s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.822s. + +2/27/22 7:59:05 PM :Debug: Time:609.822s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.886s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.886s. + +2/27/22 7:59:05 PM :Debug: Time:609.886s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:609.951s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:609.951s. + +2/27/22 7:59:05 PM :Debug: Time:609.951s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:05 PM :Debug: Time:610.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:05 PM :Debug: Time:610.029s. + +2/27/22 7:59:05 PM :Debug: Time:610.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.092s. + +2/27/22 7:59:06 PM :Debug: Time:610.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.16s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.16s. + +2/27/22 7:59:06 PM :Debug: Time:610.16s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.23s. + +2/27/22 7:59:06 PM :Debug: Time:610.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.297s. + +2/27/22 7:59:06 PM :Debug: Time:610.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.363s. + +2/27/22 7:59:06 PM :Debug: Time:610.363s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:06 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:06 PM :Info: Looks like Speeduino + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.428s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.428s. + +2/27/22 7:59:06 PM :Debug: Time:610.428s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.497s. + +2/27/22 7:59:06 PM :Debug: Time:610.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.561s. + +2/27/22 7:59:06 PM :Debug: Time:610.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.629s. + +2/27/22 7:59:06 PM :Debug: Time:610.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.697s. + +2/27/22 7:59:06 PM :Debug: Time:610.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.763s. + +2/27/22 7:59:06 PM :Debug: Time:610.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.83s. + +2/27/22 7:59:06 PM :Debug: Time:610.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.898s. + +2/27/22 7:59:06 PM :Debug: Time:610.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:610.958s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:610.958s. + +2/27/22 7:59:06 PM :Debug: Time:610.958s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:06 PM :Debug: Time:611.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:06 PM :Debug: Time:611.031s. + +2/27/22 7:59:06 PM :Debug: Time:611.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.098s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.098s. + +2/27/22 7:59:07 PM :Debug: Time:611.098s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.163s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.163s. + +2/27/22 7:59:07 PM :Debug: Time:611.163s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.231s. + +2/27/22 7:59:07 PM :Debug: Time:611.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.299s. + +2/27/22 7:59:07 PM :Debug: Time:611.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.363s. + +2/27/22 7:59:07 PM :Debug: Time:611.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.44s. + +2/27/22 7:59:07 PM :Debug: Time:611.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.501s. + +2/27/22 7:59:07 PM :Debug: Time:611.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.568s. + +2/27/22 7:59:07 PM :Debug: Time:611.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.635s. + +2/27/22 7:59:07 PM :Debug: Time:611.635s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.702s. + +2/27/22 7:59:07 PM :Debug: Time:611.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.769s. + +2/27/22 7:59:07 PM :Debug: Time:611.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.836s. + +2/27/22 7:59:07 PM :Debug: Time:611.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.904s. + +2/27/22 7:59:07 PM :Debug: Time:611.904s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:611.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:611.967s. + +2/27/22 7:59:07 PM :Debug: Time:611.967s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:07 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:07 PM :Info: Looks like Speeduino + +2/27/22 7:59:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:07 PM :Debug: Time:612.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:07 PM :Debug: Time:612.029s. + +2/27/22 7:59:07 PM :Debug: Time:612.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.099s. + +2/27/22 7:59:08 PM :Debug: Time:612.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.168s. + +2/27/22 7:59:08 PM :Debug: Time:612.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.235s. + +2/27/22 7:59:08 PM :Debug: Time:612.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.297s. + +2/27/22 7:59:08 PM :Debug: Time:612.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.365s. + +2/27/22 7:59:08 PM :Debug: Time:612.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.429s. + +2/27/22 7:59:08 PM :Debug: Time:612.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.501s. + +2/27/22 7:59:08 PM :Debug: Time:612.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.566s. + +2/27/22 7:59:08 PM :Debug: Time:612.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.636s. + +2/27/22 7:59:08 PM :Debug: Time:612.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.704s. + +2/27/22 7:59:08 PM :Debug: Time:612.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.767s. + +2/27/22 7:59:08 PM :Debug: Time:612.767s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.834s. + +2/27/22 7:59:08 PM :Debug: Time:612.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.9s. + +2/27/22 7:59:08 PM :Debug: Time:612.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:612.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:612.968s. + +2/27/22 7:59:08 PM :Debug: Time:612.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:08 PM :Debug: Time:613.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:08 PM :Debug: Time:613.036s. + +2/27/22 7:59:08 PM :Debug: Time:613.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.103s. + +2/27/22 7:59:09 PM :Debug: Time:613.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.169s. + +2/27/22 7:59:09 PM :Debug: Time:613.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.23s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.23s. + +2/27/22 7:59:09 PM :Debug: Time:613.23s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.303s. + +2/27/22 7:59:09 PM :Debug: Time:613.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.372s. + +2/27/22 7:59:09 PM :Debug: Time:613.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.435s. + +2/27/22 7:59:09 PM :Debug: Time:613.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.499s. + +2/27/22 7:59:09 PM :Debug: Time:613.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.564s. + +2/27/22 7:59:09 PM :Debug: Time:613.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.634s. + +2/27/22 7:59:09 PM :Debug: Time:613.634s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:09 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:09 PM :Info: Looks like Speeduino + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.7s. + +2/27/22 7:59:09 PM :Debug: Time:613.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.765s. + +2/27/22 7:59:09 PM :Debug: Time:613.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.835s. + +2/27/22 7:59:09 PM :Debug: Time:613.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.902s. + +2/27/22 7:59:09 PM :Debug: Time:613.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:613.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:613.968s. + +2/27/22 7:59:09 PM :Debug: Time:613.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:09 PM :Debug: Time:614.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:09 PM :Debug: Time:614.032s. + +2/27/22 7:59:09 PM :Debug: Time:614.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.097s. + +2/27/22 7:59:10 PM :Debug: Time:614.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.162s. + +2/27/22 7:59:10 PM :Debug: Time:614.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.233s. + +2/27/22 7:59:10 PM :Debug: Time:614.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.297s. + +2/27/22 7:59:10 PM :Debug: Time:614.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.368s. + +2/27/22 7:59:10 PM :Debug: Time:614.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.436s. + +2/27/22 7:59:10 PM :Debug: Time:614.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.501s. + +2/27/22 7:59:10 PM :Debug: Time:614.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.565s. + +2/27/22 7:59:10 PM :Debug: Time:614.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.629s. + +2/27/22 7:59:10 PM :Debug: Time:614.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.694s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.694s. + +2/27/22 7:59:10 PM :Debug: Time:614.694s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.766s. + +2/27/22 7:59:10 PM :Debug: Time:614.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.831s. + +2/27/22 7:59:10 PM :Debug: Time:614.831s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.899s. + +2/27/22 7:59:10 PM :Debug: Time:614.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:614.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:614.976s. + +2/27/22 7:59:10 PM :Debug: Time:614.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:10 PM :Debug: Time:615.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:10 PM :Debug: Time:615.04s. + +2/27/22 7:59:10 PM :Debug: Time:615.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.103s. + +2/27/22 7:59:11 PM :Debug: Time:615.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.17s. + +2/27/22 7:59:11 PM :Debug: Time:615.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.236s. + +2/27/22 7:59:11 PM :Debug: Time:615.236s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:11 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:11 PM :Info: Looks like Speeduino + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.299s. + +2/27/22 7:59:11 PM :Debug: Time:615.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.362s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.362s. + +2/27/22 7:59:11 PM :Debug: Time:615.362s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.429s. + +2/27/22 7:59:11 PM :Debug: Time:615.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.493s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.493s. + +2/27/22 7:59:11 PM :Debug: Time:615.493s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.559s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.559s. + +2/27/22 7:59:11 PM :Debug: Time:615.559s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.631s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.631s. + +2/27/22 7:59:11 PM :Debug: Time:615.631s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.696s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.696s. + +2/27/22 7:59:11 PM :Debug: Time:615.696s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.765s. + +2/27/22 7:59:11 PM :Debug: Time:615.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.833s. + +2/27/22 7:59:11 PM :Debug: Time:615.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.898s. + +2/27/22 7:59:11 PM :Debug: Time:615.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:615.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:615.963s. + +2/27/22 7:59:11 PM :Debug: Time:615.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:11 PM :Debug: Time:616.028s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:11 PM :Debug: Time:616.028s. + +2/27/22 7:59:11 PM :Debug: Time:616.028s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.099s. + +2/27/22 7:59:12 PM :Debug: Time:616.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.164s. + +2/27/22 7:59:12 PM :Debug: Time:616.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.234s. + +2/27/22 7:59:12 PM :Debug: Time:616.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.301s. + +2/27/22 7:59:12 PM :Debug: Time:616.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.365s. + +2/27/22 7:59:12 PM :Debug: Time:616.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.43s. + +2/27/22 7:59:12 PM :Debug: Time:616.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.495s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.495s. + +2/27/22 7:59:12 PM :Debug: Time:616.495s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.56s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.56s. + +2/27/22 7:59:12 PM :Debug: Time:616.56s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.625s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.625s. + +2/27/22 7:59:12 PM :Debug: Time:616.625s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.697s. + +2/27/22 7:59:12 PM :Debug: Time:616.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.761s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.761s. + +2/27/22 7:59:12 PM :Debug: Time:616.761s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.825s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.825s. + +2/27/22 7:59:12 PM :Debug: Time:616.825s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.896s. + +2/27/22 7:59:12 PM :Debug: Time:616.896s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:12 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:12 PM :Info: Looks like Speeduino + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:616.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:616.964s. + +2/27/22 7:59:12 PM :Debug: Time:616.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:12 PM :Debug: Time:617.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:12 PM :Debug: Time:617.041s. + +2/27/22 7:59:12 PM :Debug: Time:617.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.106s. + +2/27/22 7:59:13 PM :Debug: Time:617.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.167s. + +2/27/22 7:59:13 PM :Debug: Time:617.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.246s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.246s. + +2/27/22 7:59:13 PM :Debug: Time:617.246s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.305s. + +2/27/22 7:59:13 PM :Debug: Time:617.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.374s. + +2/27/22 7:59:13 PM :Debug: Time:617.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.438s. + +2/27/22 7:59:13 PM :Debug: Time:617.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.504s. + +2/27/22 7:59:13 PM :Debug: Time:617.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.567s. + +2/27/22 7:59:13 PM :Debug: Time:617.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.634s. + +2/27/22 7:59:13 PM :Debug: Time:617.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.706s. + +2/27/22 7:59:13 PM :Debug: Time:617.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.772s. + +2/27/22 7:59:13 PM :Debug: Time:617.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.841s. + +2/27/22 7:59:13 PM :Debug: Time:617.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.91s. + +2/27/22 7:59:13 PM :Debug: Time:617.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:617.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:617.974s. + +2/27/22 7:59:13 PM :Debug: Time:617.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:13 PM :Debug: Time:618.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:13 PM :Debug: Time:618.037s. + +2/27/22 7:59:13 PM :Debug: Time:618.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.102s. + +2/27/22 7:59:14 PM :Debug: Time:618.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.167s. + +2/27/22 7:59:14 PM :Debug: Time:618.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.239s. + +2/27/22 7:59:14 PM :Debug: Time:618.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.304s. + +2/27/22 7:59:14 PM :Debug: Time:618.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.374s. + +2/27/22 7:59:14 PM :Debug: Time:618.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.442s. + +2/27/22 7:59:14 PM :Debug: Time:618.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.506s. + +2/27/22 7:59:14 PM :Debug: Time:618.506s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:14 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:14 PM :Info: Looks like Speeduino + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.57s. + +2/27/22 7:59:14 PM :Debug: Time:618.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.636s. + +2/27/22 7:59:14 PM :Debug: Time:618.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.701s. + +2/27/22 7:59:14 PM :Debug: Time:618.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.772s. + +2/27/22 7:59:14 PM :Debug: Time:618.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.837s. + +2/27/22 7:59:14 PM :Debug: Time:618.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.906s. + +2/27/22 7:59:14 PM :Debug: Time:618.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:618.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:618.977s. + +2/27/22 7:59:14 PM :Debug: Time:618.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:14 PM :Debug: Time:619.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:14 PM :Debug: Time:619.047s. + +2/27/22 7:59:14 PM :Debug: Time:619.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.114s. + +2/27/22 7:59:15 PM :Debug: Time:619.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.18s. + +2/27/22 7:59:15 PM :Debug: Time:619.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.247s. + +2/27/22 7:59:15 PM :Debug: Time:619.247s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.311s. + +2/27/22 7:59:15 PM :Debug: Time:619.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.38s. + +2/27/22 7:59:15 PM :Debug: Time:619.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.448s. + +2/27/22 7:59:15 PM :Debug: Time:619.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.515s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.515s. + +2/27/22 7:59:15 PM :Debug: Time:619.515s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.585s. + +2/27/22 7:59:15 PM :Debug: Time:619.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.65s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.65s. + +2/27/22 7:59:15 PM :Debug: Time:619.65s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.718s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.718s. + +2/27/22 7:59:15 PM :Debug: Time:619.718s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.784s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.784s. + +2/27/22 7:59:15 PM :Debug: Time:619.784s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.852s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.852s. + +2/27/22 7:59:15 PM :Debug: Time:619.852s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.921s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.921s. + +2/27/22 7:59:15 PM :Debug: Time:619.921s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:619.986s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:619.986s. + +2/27/22 7:59:15 PM :Debug: Time:619.986s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:15 PM :Debug: Time:620.053s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:15 PM :Debug: Time:620.053s. + +2/27/22 7:59:15 PM :Debug: Time:620.053s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.12s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.12s. + +2/27/22 7:59:16 PM :Debug: Time:620.12s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.188s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.188s. + +2/27/22 7:59:16 PM :Debug: Time:620.188s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:16 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:16 PM :Info: Looks like Speeduino + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.255s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.255s. + +2/27/22 7:59:16 PM :Debug: Time:620.255s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.319s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.319s. + +2/27/22 7:59:16 PM :Debug: Time:620.319s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.383s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.383s. + +2/27/22 7:59:16 PM :Debug: Time:620.383s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.448s. + +2/27/22 7:59:16 PM :Debug: Time:620.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.514s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.514s. + +2/27/22 7:59:16 PM :Debug: Time:620.514s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.585s. + +2/27/22 7:59:16 PM :Debug: Time:620.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.648s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.648s. + +2/27/22 7:59:16 PM :Debug: Time:620.648s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.713s. + +2/27/22 7:59:16 PM :Debug: Time:620.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.778s. + +2/27/22 7:59:16 PM :Debug: Time:620.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.842s. + +2/27/22 7:59:16 PM :Debug: Time:620.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.93s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.93s. + +2/27/22 7:59:16 PM :Debug: Time:620.93s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:620.993s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:620.993s. + +2/27/22 7:59:16 PM :Debug: Time:620.993s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:16 PM :Debug: Time:621.055s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:16 PM :Debug: Time:621.055s. + +2/27/22 7:59:16 PM :Debug: Time:621.055s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.115s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.115s. + +2/27/22 7:59:17 PM :Debug: Time:621.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.183s. + +2/27/22 7:59:17 PM :Debug: Time:621.183s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.251s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.251s. + +2/27/22 7:59:17 PM :Debug: Time:621.251s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.316s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.316s. + +2/27/22 7:59:17 PM :Debug: Time:621.316s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.376s. + +2/27/22 7:59:17 PM :Debug: Time:621.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.449s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.449s. + +2/27/22 7:59:17 PM :Debug: Time:621.449s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.517s. + +2/27/22 7:59:17 PM :Debug: Time:621.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.581s. + +2/27/22 7:59:17 PM :Debug: Time:621.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.647s. + +2/27/22 7:59:17 PM :Debug: Time:621.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.711s. + +2/27/22 7:59:17 PM :Debug: Time:621.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.775s. + +2/27/22 7:59:17 PM :Debug: Time:621.775s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:17 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:17 PM :Info: Looks like Speeduino + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.84s. + +2/27/22 7:59:17 PM :Debug: Time:621.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.912s. + +2/27/22 7:59:17 PM :Debug: Time:621.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:621.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:621.977s. + +2/27/22 7:59:17 PM :Debug: Time:621.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:17 PM :Debug: Time:622.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:17 PM :Debug: Time:622.043s. + +2/27/22 7:59:17 PM :Debug: Time:622.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.107s. + +2/27/22 7:59:18 PM :Debug: Time:622.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.179s. + +2/27/22 7:59:18 PM :Debug: Time:622.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.243s. + +2/27/22 7:59:18 PM :Debug: Time:622.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.322s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.322s. + +2/27/22 7:59:18 PM :Debug: Time:622.322s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.383s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.383s. + +2/27/22 7:59:18 PM :Debug: Time:622.383s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.448s. + +2/27/22 7:59:18 PM :Debug: Time:622.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.513s. + +2/27/22 7:59:18 PM :Debug: Time:622.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.577s. + +2/27/22 7:59:18 PM :Debug: Time:622.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.642s. + +2/27/22 7:59:18 PM :Debug: Time:622.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.714s. + +2/27/22 7:59:18 PM :Debug: Time:622.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.778s. + +2/27/22 7:59:18 PM :Debug: Time:622.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.843s. + +2/27/22 7:59:18 PM :Debug: Time:622.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.914s. + +2/27/22 7:59:18 PM :Debug: Time:622.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:622.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:622.977s. + +2/27/22 7:59:18 PM :Debug: Time:622.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:18 PM :Debug: Time:623.048s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:18 PM :Debug: Time:623.048s. + +2/27/22 7:59:18 PM :Debug: Time:623.048s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.112s. + +2/27/22 7:59:19 PM :Debug: Time:623.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.177s. + +2/27/22 7:59:19 PM :Debug: Time:623.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.242s. + +2/27/22 7:59:19 PM :Debug: Time:623.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.313s. + +2/27/22 7:59:19 PM :Debug: Time:623.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.38s. + +2/27/22 7:59:19 PM :Debug: Time:623.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.464s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.464s. + +2/27/22 7:59:19 PM :Debug: Time:623.464s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:19 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:19 PM :Info: Looks like Speeduino + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.533s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.533s. + +2/27/22 7:59:19 PM :Debug: Time:623.533s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.603s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.603s. + +2/27/22 7:59:19 PM :Debug: Time:623.603s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.666s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.666s. + +2/27/22 7:59:19 PM :Debug: Time:623.666s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.732s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.732s. + +2/27/22 7:59:19 PM :Debug: Time:623.732s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.799s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.799s. + +2/27/22 7:59:19 PM :Debug: Time:623.799s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.865s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.865s. + +2/27/22 7:59:19 PM :Debug: Time:623.865s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:623.935s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:623.935s. + +2/27/22 7:59:19 PM :Debug: Time:623.935s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:624.0s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:624.0s. + +2/27/22 7:59:19 PM :Debug: Time:624.0s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:19 PM :Debug: Time:624.067s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:19 PM :Debug: Time:624.067s. + +2/27/22 7:59:19 PM :Debug: Time:624.067s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.13s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.13s. + +2/27/22 7:59:20 PM :Debug: Time:624.13s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.201s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.201s. + +2/27/22 7:59:20 PM :Debug: Time:624.201s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.269s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.27s. + +2/27/22 7:59:20 PM :Debug: Time:624.27s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.334s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.334s. + +2/27/22 7:59:20 PM :Debug: Time:624.334s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.399s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.399s. + +2/27/22 7:59:20 PM :Debug: Time:624.4s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.469s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.469s. + +2/27/22 7:59:20 PM :Debug: Time:624.469s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.538s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.538s. + +2/27/22 7:59:20 PM :Debug: Time:624.538s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.602s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.602s. + +2/27/22 7:59:20 PM :Debug: Time:624.602s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.667s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.667s. + +2/27/22 7:59:20 PM :Debug: Time:624.667s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.738s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.738s. + +2/27/22 7:59:20 PM :Debug: Time:624.738s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.798s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.798s. + +2/27/22 7:59:20 PM :Debug: Time:624.798s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.869s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.869s. + +2/27/22 7:59:20 PM :Debug: Time:624.869s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.934s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.934s. + +2/27/22 7:59:20 PM :Debug: Time:624.934s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:624.999s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:624.999s. + +2/27/22 7:59:20 PM :Debug: Time:624.999s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:20 PM :Debug: Time:625.07s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:20 PM :Debug: Time:625.07s. + +2/27/22 7:59:20 PM :Debug: Time:625.07s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:21 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:21 PM :Info: Looks like Speeduino + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.139s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.139s. + +2/27/22 7:59:21 PM :Debug: Time:625.139s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.204s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.204s. + +2/27/22 7:59:21 PM :Debug: Time:625.204s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.27s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.27s. + +2/27/22 7:59:21 PM :Debug: Time:625.27s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.338s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.338s. + +2/27/22 7:59:21 PM :Debug: Time:625.338s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.403s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.403s. + +2/27/22 7:59:21 PM :Debug: Time:625.403s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.471s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.471s. + +2/27/22 7:59:21 PM :Debug: Time:625.471s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.536s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.536s. + +2/27/22 7:59:21 PM :Debug: Time:625.536s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.603s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.603s. + +2/27/22 7:59:21 PM :Debug: Time:625.603s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.671s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.671s. + +2/27/22 7:59:21 PM :Debug: Time:625.671s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.754s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.754s. + +2/27/22 7:59:21 PM :Debug: Time:625.754s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.822s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.822s. + +2/27/22 7:59:21 PM :Debug: Time:625.822s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.888s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.888s. + +2/27/22 7:59:21 PM :Debug: Time:625.888s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:625.956s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:625.956s. + +2/27/22 7:59:21 PM :Debug: Time:625.956s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:21 PM :Debug: Time:626.024s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:21 PM :Debug: Time:626.024s. + +2/27/22 7:59:21 PM :Debug: Time:626.024s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.09s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.09s. + +2/27/22 7:59:22 PM :Debug: Time:626.09s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.153s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.153s. + +2/27/22 7:59:22 PM :Debug: Time:626.153s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.223s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.223s. + +2/27/22 7:59:22 PM :Debug: Time:626.223s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.29s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.29s. + +2/27/22 7:59:22 PM :Debug: Time:626.29s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.357s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.357s. + +2/27/22 7:59:22 PM :Debug: Time:626.357s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.426s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.426s. + +2/27/22 7:59:22 PM :Debug: Time:626.426s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.492s. + +2/27/22 7:59:22 PM :Debug: Time:626.492s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.559s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.559s. + +2/27/22 7:59:22 PM :Debug: Time:626.559s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.621s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.621s. + +2/27/22 7:59:22 PM :Debug: Time:626.621s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.683s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.683s. + +2/27/22 7:59:22 PM :Debug: Time:626.683s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:22 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:22 PM :Info: Looks like Speeduino + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.755s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.755s. + +2/27/22 7:59:22 PM :Debug: Time:626.756s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.824s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.824s. + +2/27/22 7:59:22 PM :Debug: Time:626.824s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.893s. + +2/27/22 7:59:22 PM :Debug: Time:626.893s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:626.96s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:626.96s. + +2/27/22 7:59:22 PM :Debug: Time:626.96s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:22 PM :Debug: Time:627.026s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:22 PM :Debug: Time:627.026s. + +2/27/22 7:59:22 PM :Debug: Time:627.026s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.092s. + +2/27/22 7:59:23 PM :Debug: Time:627.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.159s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.159s. + +2/27/22 7:59:23 PM :Debug: Time:627.159s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.227s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.227s. + +2/27/22 7:59:23 PM :Debug: Time:627.227s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.293s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.293s. + +2/27/22 7:59:23 PM :Debug: Time:627.293s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.353s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.353s. + +2/27/22 7:59:23 PM :Debug: Time:627.353s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.424s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.424s. + +2/27/22 7:59:23 PM :Debug: Time:627.424s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.492s. + +2/27/22 7:59:23 PM :Debug: Time:627.492s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.561s. + +2/27/22 7:59:23 PM :Debug: Time:627.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.622s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.622s. + +2/27/22 7:59:23 PM :Debug: Time:627.622s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.686s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.686s. + +2/27/22 7:59:23 PM :Debug: Time:627.686s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.758s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.758s. + +2/27/22 7:59:23 PM :Debug: Time:627.758s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.825s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.825s. + +2/27/22 7:59:23 PM :Debug: Time:627.825s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.895s. + +2/27/22 7:59:23 PM :Debug: Time:627.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:627.963s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:627.963s. + +2/27/22 7:59:23 PM :Debug: Time:627.963s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:23 PM :Debug: Time:628.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:23 PM :Debug: Time:628.031s. + +2/27/22 7:59:23 PM :Debug: Time:628.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.097s. + +2/27/22 7:59:24 PM :Debug: Time:628.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.18s. + +2/27/22 7:59:24 PM :Debug: Time:628.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.248s. + +2/27/22 7:59:24 PM :Debug: Time:628.248s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.312s. + +2/27/22 7:59:24 PM :Debug: Time:628.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.377s. + +2/27/22 7:59:24 PM :Debug: Time:628.377s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:24 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:24 PM :Info: Looks like Speeduino + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.447s. + +2/27/22 7:59:24 PM :Debug: Time:628.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.509s. + +2/27/22 7:59:24 PM :Debug: Time:628.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.579s. + +2/27/22 7:59:24 PM :Debug: Time:628.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.643s. + +2/27/22 7:59:24 PM :Debug: Time:628.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.709s. + +2/27/22 7:59:24 PM :Debug: Time:628.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.773s. + +2/27/22 7:59:24 PM :Debug: Time:628.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.845s. + +2/27/22 7:59:24 PM :Debug: Time:628.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.909s. + +2/27/22 7:59:24 PM :Debug: Time:628.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:628.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:628.974s. + +2/27/22 7:59:24 PM :Debug: Time:628.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:24 PM :Debug: Time:629.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:24 PM :Debug: Time:629.039s. + +2/27/22 7:59:24 PM :Debug: Time:629.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.111s. + +2/27/22 7:59:25 PM :Debug: Time:629.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.176s. + +2/27/22 7:59:25 PM :Debug: Time:629.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.24s. + +2/27/22 7:59:25 PM :Debug: Time:629.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.307s. + +2/27/22 7:59:25 PM :Debug: Time:629.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.383s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.383s. + +2/27/22 7:59:25 PM :Debug: Time:629.383s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.452s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.452s. + +2/27/22 7:59:25 PM :Debug: Time:629.452s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.517s. + +2/27/22 7:59:25 PM :Debug: Time:629.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.585s. + +2/27/22 7:59:25 PM :Debug: Time:629.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.652s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.652s. + +2/27/22 7:59:25 PM :Debug: Time:629.652s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.718s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.718s. + +2/27/22 7:59:25 PM :Debug: Time:629.718s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.786s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.786s. + +2/27/22 7:59:25 PM :Debug: Time:629.786s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.853s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.853s. + +2/27/22 7:59:25 PM :Debug: Time:629.853s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.914s. + +2/27/22 7:59:25 PM :Debug: Time:629.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:629.985s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:629.985s. + +2/27/22 7:59:25 PM :Debug: Time:629.985s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:25 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:25 PM :Info: Looks like Speeduino + +2/27/22 7:59:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:25 PM :Debug: Time:630.054s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:25 PM :Debug: Time:630.054s. + +2/27/22 7:59:25 PM :Debug: Time:630.054s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.115s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.115s. + +2/27/22 7:59:26 PM :Debug: Time:630.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.178s. + +2/27/22 7:59:26 PM :Debug: Time:630.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.249s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.249s. + +2/27/22 7:59:26 PM :Debug: Time:630.249s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.319s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.32s. + +2/27/22 7:59:26 PM :Debug: Time:630.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.387s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.387s. + +2/27/22 7:59:26 PM :Debug: Time:630.387s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.452s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.452s. + +2/27/22 7:59:26 PM :Debug: Time:630.452s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.517s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.517s. + +2/27/22 7:59:26 PM :Debug: Time:630.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.587s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.587s. + +2/27/22 7:59:26 PM :Debug: Time:630.587s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.648s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.648s. + +2/27/22 7:59:26 PM :Debug: Time:630.648s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.719s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.719s. + +2/27/22 7:59:26 PM :Debug: Time:630.719s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.783s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.783s. + +2/27/22 7:59:26 PM :Debug: Time:630.783s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.853s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.853s. + +2/27/22 7:59:26 PM :Debug: Time:630.853s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.915s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.915s. + +2/27/22 7:59:26 PM :Debug: Time:630.915s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:630.985s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:630.985s. + +2/27/22 7:59:26 PM :Debug: Time:630.985s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:26 PM :Debug: Time:631.048s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:26 PM :Debug: Time:631.048s. + +2/27/22 7:59:26 PM :Debug: Time:631.048s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.114s. + +2/27/22 7:59:27 PM :Debug: Time:631.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.179s. + +2/27/22 7:59:27 PM :Debug: Time:631.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.253s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.253s. + +2/27/22 7:59:27 PM :Debug: Time:631.253s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.32s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.32s. + +2/27/22 7:59:27 PM :Debug: Time:631.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.388s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.388s. + +2/27/22 7:59:27 PM :Debug: Time:631.388s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.456s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.456s. + +2/27/22 7:59:27 PM :Debug: Time:631.456s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.52s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.52s. + +2/27/22 7:59:27 PM :Debug: Time:631.52s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.589s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.589s. + +2/27/22 7:59:27 PM :Debug: Time:631.589s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.663s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.663s. + +2/27/22 7:59:27 PM :Debug: Time:631.663s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:27 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:27 PM :Info: Looks like Speeduino + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.724s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.724s. + +2/27/22 7:59:27 PM :Debug: Time:631.724s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.792s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.792s. + +2/27/22 7:59:27 PM :Debug: Time:631.792s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.862s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.862s. + +2/27/22 7:59:27 PM :Debug: Time:631.862s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.923s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.923s. + +2/27/22 7:59:27 PM :Debug: Time:631.923s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:631.992s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:631.992s. + +2/27/22 7:59:27 PM :Debug: Time:631.992s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:27 PM :Debug: Time:632.059s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:27 PM :Debug: Time:632.059s. + +2/27/22 7:59:27 PM :Debug: Time:632.059s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.119s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.119s. + +2/27/22 7:59:28 PM :Debug: Time:632.119s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.192s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.192s. + +2/27/22 7:59:28 PM :Debug: Time:632.192s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.259s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.259s. + +2/27/22 7:59:28 PM :Debug: Time:632.259s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.326s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.326s. + +2/27/22 7:59:28 PM :Debug: Time:632.326s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.391s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.391s. + +2/27/22 7:59:28 PM :Debug: Time:632.391s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.456s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.456s. + +2/27/22 7:59:28 PM :Debug: Time:632.456s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.524s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.524s. + +2/27/22 7:59:28 PM :Debug: Time:632.524s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.586s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.586s. + +2/27/22 7:59:28 PM :Debug: Time:632.586s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.658s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.658s. + +2/27/22 7:59:28 PM :Debug: Time:632.658s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.722s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.722s. + +2/27/22 7:59:28 PM :Debug: Time:632.723s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.787s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.787s. + +2/27/22 7:59:28 PM :Debug: Time:632.787s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.851s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.851s. + +2/27/22 7:59:28 PM :Debug: Time:632.851s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.923s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.923s. + +2/27/22 7:59:28 PM :Debug: Time:632.923s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:632.987s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:632.987s. + +2/27/22 7:59:28 PM :Debug: Time:632.987s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:28 PM :Debug: Time:633.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:28 PM :Debug: Time:633.049s. + +2/27/22 7:59:28 PM :Debug: Time:633.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.118s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.118s. + +2/27/22 7:59:29 PM :Debug: Time:633.118s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.183s. + +2/27/22 7:59:29 PM :Debug: Time:633.183s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.247s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.247s. + +2/27/22 7:59:29 PM :Debug: Time:633.247s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:29 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:29 PM :Info: Looks like Speeduino + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.315s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.315s. + +2/27/22 7:59:29 PM :Debug: Time:633.315s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.386s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.386s. + +2/27/22 7:59:29 PM :Debug: Time:633.386s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.451s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.451s. + +2/27/22 7:59:29 PM :Debug: Time:633.451s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.516s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.516s. + +2/27/22 7:59:29 PM :Debug: Time:633.516s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.582s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.582s. + +2/27/22 7:59:29 PM :Debug: Time:633.582s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.652s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.652s. + +2/27/22 7:59:29 PM :Debug: Time:633.652s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.717s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.717s. + +2/27/22 7:59:29 PM :Debug: Time:633.717s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.787s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.787s. + +2/27/22 7:59:29 PM :Debug: Time:633.787s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.853s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.853s. + +2/27/22 7:59:29 PM :Debug: Time:633.853s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.919s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.919s. + +2/27/22 7:59:29 PM :Debug: Time:633.919s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:633.985s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:633.985s. + +2/27/22 7:59:29 PM :Debug: Time:633.985s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:29 PM :Debug: Time:634.054s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:29 PM :Debug: Time:634.054s. + +2/27/22 7:59:29 PM :Debug: Time:634.055s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.123s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.123s. + +2/27/22 7:59:30 PM :Debug: Time:634.123s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.187s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.187s. + +2/27/22 7:59:30 PM :Debug: Time:634.187s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.252s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.252s. + +2/27/22 7:59:30 PM :Debug: Time:634.252s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.317s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.317s. + +2/27/22 7:59:30 PM :Debug: Time:634.317s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.383s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.383s. + +2/27/22 7:59:30 PM :Debug: Time:634.383s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.446s. + +2/27/22 7:59:30 PM :Debug: Time:634.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.512s. + +2/27/22 7:59:30 PM :Debug: Time:634.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.585s. + +2/27/22 7:59:30 PM :Debug: Time:634.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.648s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.648s. + +2/27/22 7:59:30 PM :Debug: Time:634.648s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.714s. + +2/27/22 7:59:30 PM :Debug: Time:634.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.779s. + +2/27/22 7:59:30 PM :Debug: Time:634.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.851s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.851s. + +2/27/22 7:59:30 PM :Debug: Time:634.851s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.917s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.918s. + +2/27/22 7:59:30 PM :Debug: Time:634.918s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:30 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:30 PM :Info: Looks like Speeduino + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:634.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:634.983s. + +2/27/22 7:59:30 PM :Debug: Time:634.983s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:30 PM :Debug: Time:635.055s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:30 PM :Debug: Time:635.056s. + +2/27/22 7:59:30 PM :Debug: Time:635.056s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.124s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.124s. + +2/27/22 7:59:31 PM :Debug: Time:635.124s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.188s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.188s. + +2/27/22 7:59:31 PM :Debug: Time:635.188s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.251s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.251s. + +2/27/22 7:59:31 PM :Debug: Time:635.251s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.316s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.316s. + +2/27/22 7:59:31 PM :Debug: Time:635.317s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.382s. + +2/27/22 7:59:31 PM :Debug: Time:635.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.448s. + +2/27/22 7:59:31 PM :Debug: Time:635.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.512s. + +2/27/22 7:59:31 PM :Debug: Time:635.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.585s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.585s. + +2/27/22 7:59:31 PM :Debug: Time:635.585s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.646s. + +2/27/22 7:59:31 PM :Debug: Time:635.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.713s. + +2/27/22 7:59:31 PM :Debug: Time:635.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.777s. + +2/27/22 7:59:31 PM :Debug: Time:635.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.842s. + +2/27/22 7:59:31 PM :Debug: Time:635.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.915s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.915s. + +2/27/22 7:59:31 PM :Debug: Time:635.915s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:635.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:635.981s. + +2/27/22 7:59:31 PM :Debug: Time:635.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:31 PM :Debug: Time:636.049s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:31 PM :Debug: Time:636.049s. + +2/27/22 7:59:31 PM :Debug: Time:636.049s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.118s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.119s. + +2/27/22 7:59:32 PM :Debug: Time:636.119s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.183s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.183s. + +2/27/22 7:59:32 PM :Debug: Time:636.183s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.252s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.252s. + +2/27/22 7:59:32 PM :Debug: Time:636.252s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.32s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.32s. + +2/27/22 7:59:32 PM :Debug: Time:636.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.385s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.385s. + +2/27/22 7:59:32 PM :Debug: Time:636.385s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.45s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.45s. + +2/27/22 7:59:32 PM :Debug: Time:636.45s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.513s. + +2/27/22 7:59:32 PM :Debug: Time:636.513s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:32 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:32 PM :Info: Looks like Speeduino + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.578s. + +2/27/22 7:59:32 PM :Debug: Time:636.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.642s. + +2/27/22 7:59:32 PM :Debug: Time:636.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.714s. + +2/27/22 7:59:32 PM :Debug: Time:636.715s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.779s. + +2/27/22 7:59:32 PM :Debug: Time:636.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.843s. + +2/27/22 7:59:32 PM :Debug: Time:636.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.908s. + +2/27/22 7:59:32 PM :Debug: Time:636.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:636.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:636.975s. + +2/27/22 7:59:32 PM :Debug: Time:636.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:32 PM :Debug: Time:637.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:32 PM :Debug: Time:637.046s. + +2/27/22 7:59:32 PM :Debug: Time:637.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.117s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.117s. + +2/27/22 7:59:33 PM :Debug: Time:637.117s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.186s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.187s. + +2/27/22 7:59:33 PM :Debug: Time:637.187s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.25s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.25s. + +2/27/22 7:59:33 PM :Debug: Time:637.25s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.313s. + +2/27/22 7:59:33 PM :Debug: Time:637.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.379s. + +2/27/22 7:59:33 PM :Debug: Time:637.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.443s. + +2/27/22 7:59:33 PM :Debug: Time:637.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.515s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.515s. + +2/27/22 7:59:33 PM :Debug: Time:637.515s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.582s. + +2/27/22 7:59:33 PM :Debug: Time:637.582s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.645s. + +2/27/22 7:59:33 PM :Debug: Time:637.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.71s. + +2/27/22 7:59:33 PM :Debug: Time:637.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.775s. + +2/27/22 7:59:33 PM :Debug: Time:637.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.841s. + +2/27/22 7:59:33 PM :Debug: Time:637.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.914s. + +2/27/22 7:59:33 PM :Debug: Time:637.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:637.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:637.978s. + +2/27/22 7:59:33 PM :Debug: Time:637.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:33 PM :Debug: Time:638.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:33 PM :Debug: Time:638.042s. + +2/27/22 7:59:33 PM :Debug: Time:638.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.107s. + +2/27/22 7:59:34 PM :Debug: Time:638.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.182s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.182s. + +2/27/22 7:59:34 PM :Debug: Time:638.182s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:34 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:34 PM :Info: Looks like Speeduino + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.245s. + +2/27/22 7:59:34 PM :Debug: Time:638.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.309s. + +2/27/22 7:59:34 PM :Debug: Time:638.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.381s. + +2/27/22 7:59:34 PM :Debug: Time:638.381s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.446s. + +2/27/22 7:59:34 PM :Debug: Time:638.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.512s. + +2/27/22 7:59:34 PM :Debug: Time:638.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.577s. + +2/27/22 7:59:34 PM :Debug: Time:638.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.642s. + +2/27/22 7:59:34 PM :Debug: Time:638.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.714s. + +2/27/22 7:59:34 PM :Debug: Time:638.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.78s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.78s. + +2/27/22 7:59:34 PM :Debug: Time:638.78s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.848s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.848s. + +2/27/22 7:59:34 PM :Debug: Time:638.848s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.916s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.916s. + +2/27/22 7:59:34 PM :Debug: Time:638.916s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:638.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:638.981s. + +2/27/22 7:59:34 PM :Debug: Time:638.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:34 PM :Debug: Time:639.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:34 PM :Debug: Time:639.046s. + +2/27/22 7:59:34 PM :Debug: Time:639.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.108s. + +2/27/22 7:59:35 PM :Debug: Time:639.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.181s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.181s. + +2/27/22 7:59:35 PM :Debug: Time:639.181s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.248s. + +2/27/22 7:59:35 PM :Debug: Time:639.248s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.312s. + +2/27/22 7:59:35 PM :Debug: Time:639.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.378s. + +2/27/22 7:59:35 PM :Debug: Time:639.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.448s. + +2/27/22 7:59:35 PM :Debug: Time:639.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.516s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.516s. + +2/27/22 7:59:35 PM :Debug: Time:639.517s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.58s. + +2/27/22 7:59:35 PM :Debug: Time:639.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.645s. + +2/27/22 7:59:35 PM :Debug: Time:639.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.717s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.717s. + +2/27/22 7:59:35 PM :Debug: Time:639.717s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.779s. + +2/27/22 7:59:35 PM :Debug: Time:639.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.848s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.848s. + +2/27/22 7:59:35 PM :Debug: Time:639.848s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:35 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:35 PM :Info: Looks like Speeduino + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.912s. + +2/27/22 7:59:35 PM :Debug: Time:639.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:639.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:639.977s. + +2/27/22 7:59:35 PM :Debug: Time:639.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:35 PM :Debug: Time:640.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:35 PM :Debug: Time:640.042s. + +2/27/22 7:59:35 PM :Debug: Time:640.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.107s. + +2/27/22 7:59:36 PM :Debug: Time:640.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.18s. + +2/27/22 7:59:36 PM :Debug: Time:640.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.245s. + +2/27/22 7:59:36 PM :Debug: Time:640.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.314s. + +2/27/22 7:59:36 PM :Debug: Time:640.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.384s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.384s. + +2/27/22 7:59:36 PM :Debug: Time:640.384s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.447s. + +2/27/22 7:59:36 PM :Debug: Time:640.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.511s. + +2/27/22 7:59:36 PM :Debug: Time:640.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.581s. + +2/27/22 7:59:36 PM :Debug: Time:640.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.65s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.65s. + +2/27/22 7:59:36 PM :Debug: Time:640.65s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.714s. + +2/27/22 7:59:36 PM :Debug: Time:640.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.778s. + +2/27/22 7:59:36 PM :Debug: Time:640.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.844s. + +2/27/22 7:59:36 PM :Debug: Time:640.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.907s. + +2/27/22 7:59:36 PM :Debug: Time:640.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:640.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:640.973s. + +2/27/22 7:59:36 PM :Debug: Time:640.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:36 PM :Debug: Time:641.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:36 PM :Debug: Time:641.046s. + +2/27/22 7:59:36 PM :Debug: Time:641.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.11s. + +2/27/22 7:59:37 PM :Debug: Time:641.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.174s. + +2/27/22 7:59:37 PM :Debug: Time:641.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.245s. + +2/27/22 7:59:37 PM :Debug: Time:641.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.31s. + +2/27/22 7:59:37 PM :Debug: Time:641.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.374s. + +2/27/22 7:59:37 PM :Debug: Time:641.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.441s. + +2/27/22 7:59:37 PM :Debug: Time:641.441s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:37 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:37 PM :Info: Looks like Speeduino + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.513s. + +2/27/22 7:59:37 PM :Debug: Time:641.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.578s. + +2/27/22 7:59:37 PM :Debug: Time:641.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.642s. + +2/27/22 7:59:37 PM :Debug: Time:641.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.707s. + +2/27/22 7:59:37 PM :Debug: Time:641.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.78s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.78s. + +2/27/22 7:59:37 PM :Debug: Time:641.78s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.844s. + +2/27/22 7:59:37 PM :Debug: Time:641.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.915s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.915s. + +2/27/22 7:59:37 PM :Debug: Time:641.915s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:641.983s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:641.983s. + +2/27/22 7:59:37 PM :Debug: Time:641.983s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:37 PM :Debug: Time:642.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:37 PM :Debug: Time:642.047s. + +2/27/22 7:59:37 PM :Debug: Time:642.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.112s. + +2/27/22 7:59:38 PM :Debug: Time:642.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.181s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.181s. + +2/27/22 7:59:38 PM :Debug: Time:642.181s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.244s. + +2/27/22 7:59:38 PM :Debug: Time:642.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.314s. + +2/27/22 7:59:38 PM :Debug: Time:642.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.378s. + +2/27/22 7:59:38 PM :Debug: Time:642.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.448s. + +2/27/22 7:59:38 PM :Debug: Time:642.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.511s. + +2/27/22 7:59:38 PM :Debug: Time:642.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.581s. + +2/27/22 7:59:38 PM :Debug: Time:642.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.646s. + +2/27/22 7:59:38 PM :Debug: Time:642.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.71s. + +2/27/22 7:59:38 PM :Debug: Time:642.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.774s. + +2/27/22 7:59:38 PM :Debug: Time:642.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.839s. + +2/27/22 7:59:38 PM :Debug: Time:642.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.912s. + +2/27/22 7:59:38 PM :Debug: Time:642.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:642.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:642.978s. + +2/27/22 7:59:38 PM :Debug: Time:642.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:38 PM :Debug: Time:643.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:38 PM :Debug: Time:643.047s. + +2/27/22 7:59:38 PM :Debug: Time:643.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.116s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.116s. + +2/27/22 7:59:39 PM :Debug: Time:643.116s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:39 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:39 PM :Info: Looks like Speeduino + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.18s. + +2/27/22 7:59:39 PM :Debug: Time:643.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.242s. + +2/27/22 7:59:39 PM :Debug: Time:643.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.315s. + +2/27/22 7:59:39 PM :Debug: Time:643.315s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.382s. + +2/27/22 7:59:39 PM :Debug: Time:643.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.446s. + +2/27/22 7:59:39 PM :Debug: Time:643.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.511s. + +2/27/22 7:59:39 PM :Debug: Time:643.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.582s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.582s. + +2/27/22 7:59:39 PM :Debug: Time:643.582s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.649s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.649s. + +2/27/22 7:59:39 PM :Debug: Time:643.649s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.715s. + +2/27/22 7:59:39 PM :Debug: Time:643.715s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.778s. + +2/27/22 7:59:39 PM :Debug: Time:643.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.848s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.848s. + +2/27/22 7:59:39 PM :Debug: Time:643.848s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.912s. + +2/27/22 7:59:39 PM :Debug: Time:643.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:643.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:643.976s. + +2/27/22 7:59:39 PM :Debug: Time:643.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:39 PM :Debug: Time:644.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:39 PM :Debug: Time:644.047s. + +2/27/22 7:59:39 PM :Debug: Time:644.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.114s. + +2/27/22 7:59:40 PM :Debug: Time:644.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.179s. + +2/27/22 7:59:40 PM :Debug: Time:644.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.244s. + +2/27/22 7:59:40 PM :Debug: Time:644.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.314s. + +2/27/22 7:59:40 PM :Debug: Time:644.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.376s. + +2/27/22 7:59:40 PM :Debug: Time:644.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.445s. + +2/27/22 7:59:40 PM :Debug: Time:644.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.509s. + +2/27/22 7:59:40 PM :Debug: Time:644.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.574s. + +2/27/22 7:59:40 PM :Debug: Time:644.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.638s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.638s. + +2/27/22 7:59:40 PM :Debug: Time:644.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.71s. + +2/27/22 7:59:40 PM :Debug: Time:644.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.776s. + +2/27/22 7:59:40 PM :Debug: Time:644.776s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:40 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:40 PM :Info: Looks like Speeduino + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.84s. + +2/27/22 7:59:40 PM :Debug: Time:644.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.905s. + +2/27/22 7:59:40 PM :Debug: Time:644.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:644.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:644.977s. + +2/27/22 7:59:40 PM :Debug: Time:644.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:40 PM :Debug: Time:645.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:40 PM :Debug: Time:645.041s. + +2/27/22 7:59:40 PM :Debug: Time:645.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.106s. + +2/27/22 7:59:41 PM :Debug: Time:645.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.172s. + +2/27/22 7:59:41 PM :Debug: Time:645.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.244s. + +2/27/22 7:59:41 PM :Debug: Time:645.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.309s. + +2/27/22 7:59:41 PM :Debug: Time:645.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.373s. + +2/27/22 7:59:41 PM :Debug: Time:645.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.438s. + +2/27/22 7:59:41 PM :Debug: Time:645.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.511s. + +2/27/22 7:59:41 PM :Debug: Time:645.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.575s. + +2/27/22 7:59:41 PM :Debug: Time:645.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.646s. + +2/27/22 7:59:41 PM :Debug: Time:645.646s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.714s. + +2/27/22 7:59:41 PM :Debug: Time:645.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.778s. + +2/27/22 7:59:41 PM :Debug: Time:645.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.842s. + +2/27/22 7:59:41 PM :Debug: Time:645.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.906s. + +2/27/22 7:59:41 PM :Debug: Time:645.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:645.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:645.972s. + +2/27/22 7:59:41 PM :Debug: Time:645.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:41 PM :Debug: Time:646.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:41 PM :Debug: Time:646.043s. + +2/27/22 7:59:41 PM :Debug: Time:646.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.114s. + +2/27/22 7:59:42 PM :Debug: Time:646.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.182s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.182s. + +2/27/22 7:59:42 PM :Debug: Time:646.182s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.246s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.246s. + +2/27/22 7:59:42 PM :Debug: Time:646.246s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.311s. + +2/27/22 7:59:42 PM :Debug: Time:646.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.376s. + +2/27/22 7:59:42 PM :Debug: Time:646.376s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:42 PM :Info: Looks like Speeduino + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.441s. + +2/27/22 7:59:42 PM :Debug: Time:646.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.504s. + +2/27/22 7:59:42 PM :Debug: Time:646.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.577s. + +2/27/22 7:59:42 PM :Debug: Time:646.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.642s. + +2/27/22 7:59:42 PM :Debug: Time:646.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.706s. + +2/27/22 7:59:42 PM :Debug: Time:646.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.771s. + +2/27/22 7:59:42 PM :Debug: Time:646.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.843s. + +2/27/22 7:59:42 PM :Debug: Time:646.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.907s. + +2/27/22 7:59:42 PM :Debug: Time:646.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:646.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:646.973s. + +2/27/22 7:59:42 PM :Debug: Time:646.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:42 PM :Debug: Time:647.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:42 PM :Debug: Time:647.037s. + +2/27/22 7:59:42 PM :Debug: Time:647.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.111s. + +2/27/22 7:59:43 PM :Debug: Time:647.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.176s. + +2/27/22 7:59:43 PM :Debug: Time:647.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.241s. + +2/27/22 7:59:43 PM :Debug: Time:647.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.305s. + +2/27/22 7:59:43 PM :Debug: Time:647.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.371s. + +2/27/22 7:59:43 PM :Debug: Time:647.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.446s. + +2/27/22 7:59:43 PM :Debug: Time:647.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.515s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.515s. + +2/27/22 7:59:43 PM :Debug: Time:647.515s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.578s. + +2/27/22 7:59:43 PM :Debug: Time:647.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.64s. + +2/27/22 7:59:43 PM :Debug: Time:647.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.706s. + +2/27/22 7:59:43 PM :Debug: Time:647.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.772s. + +2/27/22 7:59:43 PM :Debug: Time:647.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.845s. + +2/27/22 7:59:43 PM :Debug: Time:647.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.913s. + +2/27/22 7:59:43 PM :Debug: Time:647.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:647.98s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:647.98s. + +2/27/22 7:59:43 PM :Debug: Time:647.98s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:43 PM :Debug: Time:648.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:43 PM :Debug: Time:648.045s. + +2/27/22 7:59:43 PM :Debug: Time:648.045s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:44 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:44 PM :Info: Looks like Speeduino + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.11s. + +2/27/22 7:59:44 PM :Debug: Time:648.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.18s. + +2/27/22 7:59:44 PM :Debug: Time:648.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.248s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.248s. + +2/27/22 7:59:44 PM :Debug: Time:648.248s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.312s. + +2/27/22 7:59:44 PM :Debug: Time:648.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.376s. + +2/27/22 7:59:44 PM :Debug: Time:648.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.44s. + +2/27/22 7:59:44 PM :Debug: Time:648.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.506s. + +2/27/22 7:59:44 PM :Debug: Time:648.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.577s. + +2/27/22 7:59:44 PM :Debug: Time:648.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.643s. + +2/27/22 7:59:44 PM :Debug: Time:648.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.707s. + +2/27/22 7:59:44 PM :Debug: Time:648.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.772s. + +2/27/22 7:59:44 PM :Debug: Time:648.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.838s. + +2/27/22 7:59:44 PM :Debug: Time:648.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.903s. + +2/27/22 7:59:44 PM :Debug: Time:648.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:648.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:648.97s. + +2/27/22 7:59:44 PM :Debug: Time:648.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:44 PM :Debug: Time:649.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:44 PM :Debug: Time:649.04s. + +2/27/22 7:59:44 PM :Debug: Time:649.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.105s. + +2/27/22 7:59:45 PM :Debug: Time:649.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.17s. + +2/27/22 7:59:45 PM :Debug: Time:649.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.237s. + +2/27/22 7:59:45 PM :Debug: Time:649.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.307s. + +2/27/22 7:59:45 PM :Debug: Time:649.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.371s. + +2/27/22 7:59:45 PM :Debug: Time:649.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.444s. + +2/27/22 7:59:45 PM :Debug: Time:649.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.508s. + +2/27/22 7:59:45 PM :Debug: Time:649.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.574s. + +2/27/22 7:59:45 PM :Debug: Time:649.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.646s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.646s. + +2/27/22 7:59:45 PM :Debug: Time:649.646s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:45 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:45 PM :Info: Looks like Speeduino + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.711s. + +2/27/22 7:59:45 PM :Debug: Time:649.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.775s. + +2/27/22 7:59:45 PM :Debug: Time:649.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.84s. + +2/27/22 7:59:45 PM :Debug: Time:649.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.912s. + +2/27/22 7:59:45 PM :Debug: Time:649.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:649.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:649.977s. + +2/27/22 7:59:45 PM :Debug: Time:649.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:45 PM :Debug: Time:650.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:45 PM :Debug: Time:650.041s. + +2/27/22 7:59:45 PM :Debug: Time:650.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.105s. + +2/27/22 7:59:46 PM :Debug: Time:650.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.178s. + +2/27/22 7:59:46 PM :Debug: Time:650.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.242s. + +2/27/22 7:59:46 PM :Debug: Time:650.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.306s. + +2/27/22 7:59:46 PM :Debug: Time:650.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.371s. + +2/27/22 7:59:46 PM :Debug: Time:650.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.444s. + +2/27/22 7:59:46 PM :Debug: Time:650.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.509s. + +2/27/22 7:59:46 PM :Debug: Time:650.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.574s. + +2/27/22 7:59:46 PM :Debug: Time:650.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.639s. + +2/27/22 7:59:46 PM :Debug: Time:650.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.705s. + +2/27/22 7:59:46 PM :Debug: Time:650.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.776s. + +2/27/22 7:59:46 PM :Debug: Time:650.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.846s. + +2/27/22 7:59:46 PM :Debug: Time:650.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.914s. + +2/27/22 7:59:46 PM :Debug: Time:650.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:650.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:650.978s. + +2/27/22 7:59:46 PM :Debug: Time:650.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:46 PM :Debug: Time:651.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:46 PM :Debug: Time:651.043s. + +2/27/22 7:59:46 PM :Debug: Time:651.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.108s. + +2/27/22 7:59:47 PM :Debug: Time:651.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.173s. + +2/27/22 7:59:47 PM :Debug: Time:651.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.237s. + +2/27/22 7:59:47 PM :Debug: Time:651.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.311s. + +2/27/22 7:59:47 PM :Debug: Time:651.311s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:47 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:47 PM :Info: Looks like Speeduino + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.375s. + +2/27/22 7:59:47 PM :Debug: Time:651.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.441s. + +2/27/22 7:59:47 PM :Debug: Time:651.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.506s. + +2/27/22 7:59:47 PM :Debug: Time:651.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.578s. + +2/27/22 7:59:47 PM :Debug: Time:651.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.644s. + +2/27/22 7:59:47 PM :Debug: Time:651.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.709s. + +2/27/22 7:59:47 PM :Debug: Time:651.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.773s. + +2/27/22 7:59:47 PM :Debug: Time:651.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.838s. + +2/27/22 7:59:47 PM :Debug: Time:651.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.91s. + +2/27/22 7:59:47 PM :Debug: Time:651.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:651.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:651.974s. + +2/27/22 7:59:47 PM :Debug: Time:651.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:47 PM :Debug: Time:652.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:47 PM :Debug: Time:652.046s. + +2/27/22 7:59:47 PM :Debug: Time:652.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.11s. + +2/27/22 7:59:48 PM :Debug: Time:652.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.18s. + +2/27/22 7:59:48 PM :Debug: Time:652.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.249s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.249s. + +2/27/22 7:59:48 PM :Debug: Time:652.249s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.313s. + +2/27/22 7:59:48 PM :Debug: Time:652.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.378s. + +2/27/22 7:59:48 PM :Debug: Time:652.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.448s. + +2/27/22 7:59:48 PM :Debug: Time:652.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.51s. + +2/27/22 7:59:48 PM :Debug: Time:652.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.58s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.58s. + +2/27/22 7:59:48 PM :Debug: Time:652.58s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.644s. + +2/27/22 7:59:48 PM :Debug: Time:652.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.714s. + +2/27/22 7:59:48 PM :Debug: Time:652.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.777s. + +2/27/22 7:59:48 PM :Debug: Time:652.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.846s. + +2/27/22 7:59:48 PM :Debug: Time:652.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.911s. + +2/27/22 7:59:48 PM :Debug: Time:652.911s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:48 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:48 PM :Info: Looks like Speeduino + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:652.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:652.975s. + +2/27/22 7:59:48 PM :Debug: Time:652.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:48 PM :Debug: Time:653.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:48 PM :Debug: Time:653.038s. + +2/27/22 7:59:48 PM :Debug: Time:653.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.104s. + +2/27/22 7:59:49 PM :Debug: Time:653.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.176s. + +2/27/22 7:59:49 PM :Debug: Time:653.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.241s. + +2/27/22 7:59:49 PM :Debug: Time:653.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.313s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.313s. + +2/27/22 7:59:49 PM :Debug: Time:653.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.378s. + +2/27/22 7:59:49 PM :Debug: Time:653.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.442s. + +2/27/22 7:59:49 PM :Debug: Time:653.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.506s. + +2/27/22 7:59:49 PM :Debug: Time:653.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.571s. + +2/27/22 7:59:49 PM :Debug: Time:653.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.637s. + +2/27/22 7:59:49 PM :Debug: Time:653.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.703s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.703s. + +2/27/22 7:59:49 PM :Debug: Time:653.703s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.779s. + +2/27/22 7:59:49 PM :Debug: Time:653.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.847s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.847s. + +2/27/22 7:59:49 PM :Debug: Time:653.847s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.911s. + +2/27/22 7:59:49 PM :Debug: Time:653.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:653.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:653.976s. + +2/27/22 7:59:49 PM :Debug: Time:653.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:49 PM :Debug: Time:654.047s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:49 PM :Debug: Time:654.047s. + +2/27/22 7:59:49 PM :Debug: Time:654.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.115s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.115s. + +2/27/22 7:59:50 PM :Debug: Time:654.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.179s. + +2/27/22 7:59:50 PM :Debug: Time:654.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.244s. + +2/27/22 7:59:50 PM :Debug: Time:654.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.31s. + +2/27/22 7:59:50 PM :Debug: Time:654.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.372s. + +2/27/22 7:59:50 PM :Debug: Time:654.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.438s. + +2/27/22 7:59:50 PM :Debug: Time:654.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.512s. + +2/27/22 7:59:50 PM :Debug: Time:654.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.577s. + +2/27/22 7:59:50 PM :Debug: Time:654.577s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:50 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:50 PM :Info: Looks like Speeduino + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.641s. + +2/27/22 7:59:50 PM :Debug: Time:654.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.705s. + +2/27/22 7:59:50 PM :Debug: Time:654.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.772s. + +2/27/22 7:59:50 PM :Debug: Time:654.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.838s. + +2/27/22 7:59:50 PM :Debug: Time:654.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.913s. + +2/27/22 7:59:50 PM :Debug: Time:654.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:654.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:654.981s. + +2/27/22 7:59:50 PM :Debug: Time:654.981s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:50 PM :Debug: Time:655.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:50 PM :Debug: Time:655.046s. + +2/27/22 7:59:50 PM :Debug: Time:655.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.11s. + +2/27/22 7:59:51 PM :Debug: Time:655.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.18s. + +2/27/22 7:59:51 PM :Debug: Time:655.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.249s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.249s. + +2/27/22 7:59:51 PM :Debug: Time:655.249s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.312s. + +2/27/22 7:59:51 PM :Debug: Time:655.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.376s. + +2/27/22 7:59:51 PM :Debug: Time:655.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.441s. + +2/27/22 7:59:51 PM :Debug: Time:655.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.505s. + +2/27/22 7:59:51 PM :Debug: Time:655.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.577s. + +2/27/22 7:59:51 PM :Debug: Time:655.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.641s. + +2/27/22 7:59:51 PM :Debug: Time:655.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.706s. + +2/27/22 7:59:51 PM :Debug: Time:655.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.77s. + +2/27/22 7:59:51 PM :Debug: Time:655.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.843s. + +2/27/22 7:59:51 PM :Debug: Time:655.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.913s. + +2/27/22 7:59:51 PM :Debug: Time:655.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:655.981s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:655.981s. + +2/27/22 7:59:51 PM :Debug: Time:655.982s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:51 PM :Debug: Time:656.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:51 PM :Debug: Time:656.045s. + +2/27/22 7:59:51 PM :Debug: Time:656.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.11s. + +2/27/22 7:59:52 PM :Debug: Time:656.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.175s. + +2/27/22 7:59:52 PM :Debug: Time:656.175s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:52 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:52 PM :Info: Looks like Speeduino + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.246s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.246s. + +2/27/22 7:59:52 PM :Debug: Time:656.246s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.311s. + +2/27/22 7:59:52 PM :Debug: Time:656.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.375s. + +2/27/22 7:59:52 PM :Debug: Time:656.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.439s. + +2/27/22 7:59:52 PM :Debug: Time:656.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.504s. + +2/27/22 7:59:52 PM :Debug: Time:656.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.577s. + +2/27/22 7:59:52 PM :Debug: Time:656.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.642s. + +2/27/22 7:59:52 PM :Debug: Time:656.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.707s. + +2/27/22 7:59:52 PM :Debug: Time:656.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.77s. + +2/27/22 7:59:52 PM :Debug: Time:656.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.836s. + +2/27/22 7:59:52 PM :Debug: Time:656.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.908s. + +2/27/22 7:59:52 PM :Debug: Time:656.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:656.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:656.973s. + +2/27/22 7:59:52 PM :Debug: Time:656.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:52 PM :Debug: Time:657.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:52 PM :Debug: Time:657.037s. + +2/27/22 7:59:52 PM :Debug: Time:657.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.11s. + +2/27/22 7:59:53 PM :Debug: Time:657.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.175s. + +2/27/22 7:59:53 PM :Debug: Time:657.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.24s. + +2/27/22 7:59:53 PM :Debug: Time:657.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.304s. + +2/27/22 7:59:53 PM :Debug: Time:657.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.376s. + +2/27/22 7:59:53 PM :Debug: Time:657.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.447s. + +2/27/22 7:59:53 PM :Debug: Time:657.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.514s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.514s. + +2/27/22 7:59:53 PM :Debug: Time:657.514s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.579s. + +2/27/22 7:59:53 PM :Debug: Time:657.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.643s. + +2/27/22 7:59:53 PM :Debug: Time:657.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.713s. + +2/27/22 7:59:53 PM :Debug: Time:657.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.781s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.781s. + +2/27/22 7:59:53 PM :Debug: Time:657.781s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.846s. + +2/27/22 7:59:53 PM :Debug: Time:657.846s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:53 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:53 PM :Info: Looks like Speeduino + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.909s. + +2/27/22 7:59:53 PM :Debug: Time:657.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:657.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:657.974s. + +2/27/22 7:59:53 PM :Debug: Time:657.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:53 PM :Debug: Time:658.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:53 PM :Debug: Time:658.039s. + +2/27/22 7:59:53 PM :Debug: Time:658.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.11s. + +2/27/22 7:59:54 PM :Debug: Time:658.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.176s. + +2/27/22 7:59:54 PM :Debug: Time:658.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.24s. + +2/27/22 7:59:54 PM :Debug: Time:658.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.304s. + +2/27/22 7:59:54 PM :Debug: Time:658.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.376s. + +2/27/22 7:59:54 PM :Debug: Time:658.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.44s. + +2/27/22 7:59:54 PM :Debug: Time:658.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.505s. + +2/27/22 7:59:54 PM :Debug: Time:658.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.578s. + +2/27/22 7:59:54 PM :Debug: Time:658.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.642s. + +2/27/22 7:59:54 PM :Debug: Time:658.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.705s. + +2/27/22 7:59:54 PM :Debug: Time:658.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.771s. + +2/27/22 7:59:54 PM :Debug: Time:658.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.844s. + +2/27/22 7:59:54 PM :Debug: Time:658.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.911s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.911s. + +2/27/22 7:59:54 PM :Debug: Time:658.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:658.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:658.976s. + +2/27/22 7:59:54 PM :Debug: Time:658.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:54 PM :Debug: Time:659.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:54 PM :Debug: Time:659.04s. + +2/27/22 7:59:54 PM :Debug: Time:659.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.104s. + +2/27/22 7:59:55 PM :Debug: Time:659.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.176s. + +2/27/22 7:59:55 PM :Debug: Time:659.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.242s. + +2/27/22 7:59:55 PM :Debug: Time:659.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.306s. + +2/27/22 7:59:55 PM :Debug: Time:659.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.371s. + +2/27/22 7:59:55 PM :Debug: Time:659.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.437s. + +2/27/22 7:59:55 PM :Debug: Time:659.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.513s. + +2/27/22 7:59:55 PM :Debug: Time:659.513s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:55 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:55 PM :Info: Looks like Speeduino + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.581s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.581s. + +2/27/22 7:59:55 PM :Debug: Time:659.581s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.645s. + +2/27/22 7:59:55 PM :Debug: Time:659.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.709s. + +2/27/22 7:59:55 PM :Debug: Time:659.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.774s. + +2/27/22 7:59:55 PM :Debug: Time:659.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.846s. + +2/27/22 7:59:55 PM :Debug: Time:659.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.912s. + +2/27/22 7:59:55 PM :Debug: Time:659.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:659.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:659.975s. + +2/27/22 7:59:55 PM :Debug: Time:659.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:55 PM :Debug: Time:660.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:55 PM :Debug: Time:660.041s. + +2/27/22 7:59:55 PM :Debug: Time:660.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.106s. + +2/27/22 7:59:56 PM :Debug: Time:660.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.178s. + +2/27/22 7:59:56 PM :Debug: Time:660.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.243s. + +2/27/22 7:59:56 PM :Debug: Time:660.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.306s. + +2/27/22 7:59:56 PM :Debug: Time:660.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.371s. + +2/27/22 7:59:56 PM :Debug: Time:660.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.442s. + +2/27/22 7:59:56 PM :Debug: Time:660.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.507s. + +2/27/22 7:59:56 PM :Debug: Time:660.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.571s. + +2/27/22 7:59:56 PM :Debug: Time:660.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.644s. + +2/27/22 7:59:56 PM :Debug: Time:660.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.709s. + +2/27/22 7:59:56 PM :Debug: Time:660.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.772s. + +2/27/22 7:59:56 PM :Debug: Time:660.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.838s. + +2/27/22 7:59:56 PM :Debug: Time:660.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.91s. + +2/27/22 7:59:56 PM :Debug: Time:660.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:660.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:660.975s. + +2/27/22 7:59:56 PM :Debug: Time:660.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:56 PM :Debug: Time:661.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:56 PM :Debug: Time:661.04s. + +2/27/22 7:59:56 PM :Debug: Time:661.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.104s. + +2/27/22 7:59:57 PM :Debug: Time:661.104s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:57 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:57 PM :Info: Looks like Speeduino + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.17s. + +2/27/22 7:59:57 PM :Debug: Time:661.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.242s. + +2/27/22 7:59:57 PM :Debug: Time:661.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.312s. + +2/27/22 7:59:57 PM :Debug: Time:661.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.38s. + +2/27/22 7:59:57 PM :Debug: Time:661.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.445s. + +2/27/22 7:59:57 PM :Debug: Time:661.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.51s. + +2/27/22 7:59:57 PM :Debug: Time:661.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.579s. + +2/27/22 7:59:57 PM :Debug: Time:661.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.647s. + +2/27/22 7:59:57 PM :Debug: Time:661.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.711s. + +2/27/22 7:59:57 PM :Debug: Time:661.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.776s. + +2/27/22 7:59:57 PM :Debug: Time:661.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.854s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.854s. + +2/27/22 7:59:57 PM :Debug: Time:661.854s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.913s. + +2/27/22 7:59:57 PM :Debug: Time:661.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:661.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:661.978s. + +2/27/22 7:59:57 PM :Debug: Time:661.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:57 PM :Debug: Time:662.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:57 PM :Debug: Time:662.042s. + +2/27/22 7:59:57 PM :Debug: Time:662.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.108s. + +2/27/22 7:59:58 PM :Debug: Time:662.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.172s. + +2/27/22 7:59:58 PM :Debug: Time:662.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.244s. + +2/27/22 7:59:58 PM :Debug: Time:662.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.309s. + +2/27/22 7:59:58 PM :Debug: Time:662.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.374s. + +2/27/22 7:59:58 PM :Debug: Time:662.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.439s. + +2/27/22 7:59:58 PM :Debug: Time:662.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.511s. + +2/27/22 7:59:58 PM :Debug: Time:662.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.577s. + +2/27/22 7:59:58 PM :Debug: Time:662.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.641s. + +2/27/22 7:59:58 PM :Debug: Time:662.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.706s. + +2/27/22 7:59:58 PM :Debug: Time:662.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.771s. + +2/27/22 7:59:58 PM :Debug: Time:662.771s. . & . . . . . . . . ~ . . . . . +2/27/22 7:59:58 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 7:59:58 PM :Info: Looks like Speeduino + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.843s. + +2/27/22 7:59:58 PM :Debug: Time:662.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.909s. + +2/27/22 7:59:58 PM :Debug: Time:662.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:662.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:662.973s. + +2/27/22 7:59:58 PM :Debug: Time:662.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:58 PM :Debug: Time:663.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:58 PM :Debug: Time:663.044s. + +2/27/22 7:59:58 PM :Debug: Time:663.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.107s. + +2/27/22 7:59:59 PM :Debug: Time:663.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.172s. + +2/27/22 7:59:59 PM :Debug: Time:663.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.245s. + +2/27/22 7:59:59 PM :Debug: Time:663.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.308s. + +2/27/22 7:59:59 PM :Debug: Time:663.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.373s. + +2/27/22 7:59:59 PM :Debug: Time:663.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.438s. + +2/27/22 7:59:59 PM :Debug: Time:663.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.511s. + +2/27/22 7:59:59 PM :Debug: Time:663.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.575s. + +2/27/22 7:59:59 PM :Debug: Time:663.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.64s. + +2/27/22 7:59:59 PM :Debug: Time:663.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.704s. + +2/27/22 7:59:59 PM :Debug: Time:663.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.777s. + +2/27/22 7:59:59 PM :Debug: Time:663.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.841s. + +2/27/22 7:59:59 PM :Debug: Time:663.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.906s. + +2/27/22 7:59:59 PM :Debug: Time:663.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:663.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:663.972s. + +2/27/22 7:59:59 PM :Debug: Time:663.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 7:59:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 7:59:59 PM :Debug: Time:664.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 7:59:59 PM :Debug: Time:664.036s. + +2/27/22 7:59:59 PM :Debug: Time:664.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.112s. + +2/27/22 8:00:00 PM :Debug: Time:664.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.179s. + +2/27/22 8:00:00 PM :Debug: Time:664.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.244s. + +2/27/22 8:00:00 PM :Debug: Time:664.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.314s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.314s. + +2/27/22 8:00:00 PM :Debug: Time:664.314s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.381s. + +2/27/22 8:00:00 PM :Debug: Time:664.381s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:00 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:00 PM :Info: Looks like Speeduino + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.446s. + +2/27/22 8:00:00 PM :Debug: Time:664.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.509s. + +2/27/22 8:00:00 PM :Debug: Time:664.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.576s. + +2/27/22 8:00:00 PM :Debug: Time:664.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.641s. + +2/27/22 8:00:00 PM :Debug: Time:664.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.712s. + +2/27/22 8:00:00 PM :Debug: Time:664.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.776s. + +2/27/22 8:00:00 PM :Debug: Time:664.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.84s. + +2/27/22 8:00:00 PM :Debug: Time:664.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.91s. + +2/27/22 8:00:00 PM :Debug: Time:664.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:664.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:664.973s. + +2/27/22 8:00:00 PM :Debug: Time:664.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:00 PM :Debug: Time:665.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:00 PM :Debug: Time:665.043s. + +2/27/22 8:00:00 PM :Debug: Time:665.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.108s. + +2/27/22 8:00:01 PM :Debug: Time:665.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.172s. + +2/27/22 8:00:01 PM :Debug: Time:665.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.236s. + +2/27/22 8:00:01 PM :Debug: Time:665.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.308s. + +2/27/22 8:00:01 PM :Debug: Time:665.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.373s. + +2/27/22 8:00:01 PM :Debug: Time:665.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.437s. + +2/27/22 8:00:01 PM :Debug: Time:665.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.502s. + +2/27/22 8:00:01 PM :Debug: Time:665.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.575s. + +2/27/22 8:00:01 PM :Debug: Time:665.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.645s. + +2/27/22 8:00:01 PM :Debug: Time:665.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.712s. + +2/27/22 8:00:01 PM :Debug: Time:665.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.776s. + +2/27/22 8:00:01 PM :Debug: Time:665.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.841s. + +2/27/22 8:00:01 PM :Debug: Time:665.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.906s. + +2/27/22 8:00:01 PM :Debug: Time:665.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:665.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:665.97s. + +2/27/22 8:00:01 PM :Debug: Time:665.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:01 PM :Debug: Time:666.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:01 PM :Debug: Time:666.036s. + +2/27/22 8:00:01 PM :Debug: Time:666.036s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:02 PM :Info: Looks like Speeduino + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.107s. + +2/27/22 8:00:02 PM :Debug: Time:666.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.172s. + +2/27/22 8:00:02 PM :Debug: Time:666.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.238s. + +2/27/22 8:00:02 PM :Debug: Time:666.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.303s. + +2/27/22 8:00:02 PM :Debug: Time:666.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.375s. + +2/27/22 8:00:02 PM :Debug: Time:666.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.445s. + +2/27/22 8:00:02 PM :Debug: Time:666.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.513s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.513s. + +2/27/22 8:00:02 PM :Debug: Time:666.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.577s. + +2/27/22 8:00:02 PM :Debug: Time:666.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.642s. + +2/27/22 8:00:02 PM :Debug: Time:666.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.707s. + +2/27/22 8:00:02 PM :Debug: Time:666.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.773s. + +2/27/22 8:00:02 PM :Debug: Time:666.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.837s. + +2/27/22 8:00:02 PM :Debug: Time:666.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.909s. + +2/27/22 8:00:02 PM :Debug: Time:666.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:666.979s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:666.979s. + +2/27/22 8:00:02 PM :Debug: Time:666.979s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:02 PM :Debug: Time:667.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:02 PM :Debug: Time:667.046s. + +2/27/22 8:00:02 PM :Debug: Time:667.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.11s. + +2/27/22 8:00:03 PM :Debug: Time:667.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.175s. + +2/27/22 8:00:03 PM :Debug: Time:667.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.246s. + +2/27/22 8:00:03 PM :Debug: Time:667.246s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.307s. + +2/27/22 8:00:03 PM :Debug: Time:667.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.377s. + +2/27/22 8:00:03 PM :Debug: Time:667.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.441s. + +2/27/22 8:00:03 PM :Debug: Time:667.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.506s. + +2/27/22 8:00:03 PM :Debug: Time:667.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.571s. + +2/27/22 8:00:03 PM :Debug: Time:667.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.643s. + +2/27/22 8:00:03 PM :Debug: Time:667.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.708s. + +2/27/22 8:00:03 PM :Debug: Time:667.708s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:03 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:03 PM :Info: Looks like Speeduino + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.772s. + +2/27/22 8:00:03 PM :Debug: Time:667.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.838s. + +2/27/22 8:00:03 PM :Debug: Time:667.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.91s. + +2/27/22 8:00:03 PM :Debug: Time:667.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:667.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:667.975s. + +2/27/22 8:00:03 PM :Debug: Time:667.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:03 PM :Debug: Time:668.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:03 PM :Debug: Time:668.045s. + +2/27/22 8:00:03 PM :Debug: Time:668.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.114s. + +2/27/22 8:00:04 PM :Debug: Time:668.114s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.177s. + +2/27/22 8:00:04 PM :Debug: Time:668.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.242s. + +2/27/22 8:00:04 PM :Debug: Time:668.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.311s. + +2/27/22 8:00:04 PM :Debug: Time:668.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.378s. + +2/27/22 8:00:04 PM :Debug: Time:668.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.444s. + +2/27/22 8:00:04 PM :Debug: Time:668.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.508s. + +2/27/22 8:00:04 PM :Debug: Time:668.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.573s. + +2/27/22 8:00:04 PM :Debug: Time:668.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.645s. + +2/27/22 8:00:04 PM :Debug: Time:668.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.708s. + +2/27/22 8:00:04 PM :Debug: Time:668.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.778s. + +2/27/22 8:00:04 PM :Debug: Time:668.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.842s. + +2/27/22 8:00:04 PM :Debug: Time:668.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.905s. + +2/27/22 8:00:04 PM :Debug: Time:668.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:668.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:668.972s. + +2/27/22 8:00:04 PM :Debug: Time:668.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:04 PM :Debug: Time:669.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:04 PM :Debug: Time:669.037s. + +2/27/22 8:00:04 PM :Debug: Time:669.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.109s. + +2/27/22 8:00:05 PM :Debug: Time:669.109s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.174s. + +2/27/22 8:00:05 PM :Debug: Time:669.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.244s. + +2/27/22 8:00:05 PM :Debug: Time:669.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.312s. + +2/27/22 8:00:05 PM :Debug: Time:669.312s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:05 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:05 PM :Info: Looks like Speeduino + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.376s. + +2/27/22 8:00:05 PM :Debug: Time:669.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.441s. + +2/27/22 8:00:05 PM :Debug: Time:669.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.511s. + +2/27/22 8:00:05 PM :Debug: Time:669.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.573s. + +2/27/22 8:00:05 PM :Debug: Time:669.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.645s. + +2/27/22 8:00:05 PM :Debug: Time:669.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.71s. + +2/27/22 8:00:05 PM :Debug: Time:669.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.777s. + +2/27/22 8:00:05 PM :Debug: Time:669.777s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.846s. + +2/27/22 8:00:05 PM :Debug: Time:669.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.914s. + +2/27/22 8:00:05 PM :Debug: Time:669.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:669.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:669.977s. + +2/27/22 8:00:05 PM :Debug: Time:669.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:05 PM :Debug: Time:670.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:05 PM :Debug: Time:670.041s. + +2/27/22 8:00:05 PM :Debug: Time:670.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.112s. + +2/27/22 8:00:06 PM :Debug: Time:670.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.179s. + +2/27/22 8:00:06 PM :Debug: Time:670.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.243s. + +2/27/22 8:00:06 PM :Debug: Time:670.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.309s. + +2/27/22 8:00:06 PM :Debug: Time:670.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.374s. + +2/27/22 8:00:06 PM :Debug: Time:670.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.438s. + +2/27/22 8:00:06 PM :Debug: Time:670.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.506s. + +2/27/22 8:00:06 PM :Debug: Time:670.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.575s. + +2/27/22 8:00:06 PM :Debug: Time:670.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.639s. + +2/27/22 8:00:06 PM :Debug: Time:670.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.704s. + +2/27/22 8:00:06 PM :Debug: Time:670.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.769s. + +2/27/22 8:00:06 PM :Debug: Time:670.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.841s. + +2/27/22 8:00:06 PM :Debug: Time:670.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.907s. + +2/27/22 8:00:06 PM :Debug: Time:670.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:670.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:670.971s. + +2/27/22 8:00:06 PM :Debug: Time:670.971s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:06 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:06 PM :Info: Looks like Speeduino + +2/27/22 8:00:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:06 PM :Debug: Time:671.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:06 PM :Debug: Time:671.035s. + +2/27/22 8:00:06 PM :Debug: Time:671.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.11s. + +2/27/22 8:00:07 PM :Debug: Time:671.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.175s. + +2/27/22 8:00:07 PM :Debug: Time:671.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.255s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.255s. + +2/27/22 8:00:07 PM :Debug: Time:671.255s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.32s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.32s. + +2/27/22 8:00:07 PM :Debug: Time:671.32s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.382s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.382s. + +2/27/22 8:00:07 PM :Debug: Time:671.382s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.446s. + +2/27/22 8:00:07 PM :Debug: Time:671.446s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.51s. + +2/27/22 8:00:07 PM :Debug: Time:671.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.575s. + +2/27/22 8:00:07 PM :Debug: Time:671.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.639s. + +2/27/22 8:00:07 PM :Debug: Time:671.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.709s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.709s. + +2/27/22 8:00:07 PM :Debug: Time:671.709s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.778s. + +2/27/22 8:00:07 PM :Debug: Time:671.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.842s. + +2/27/22 8:00:07 PM :Debug: Time:671.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.907s. + +2/27/22 8:00:07 PM :Debug: Time:671.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:671.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:671.971s. + +2/27/22 8:00:07 PM :Debug: Time:671.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:07 PM :Debug: Time:672.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:07 PM :Debug: Time:672.035s. + +2/27/22 8:00:07 PM :Debug: Time:672.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.1s. + +2/27/22 8:00:08 PM :Debug: Time:672.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.172s. + +2/27/22 8:00:08 PM :Debug: Time:672.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.236s. + +2/27/22 8:00:08 PM :Debug: Time:672.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.3s. + +2/27/22 8:00:08 PM :Debug: Time:672.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.366s. + +2/27/22 8:00:08 PM :Debug: Time:672.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.438s. + +2/27/22 8:00:08 PM :Debug: Time:672.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.503s. + +2/27/22 8:00:08 PM :Debug: Time:672.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.568s. + +2/27/22 8:00:08 PM :Debug: Time:672.568s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:08 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:08 PM :Info: Looks like Speeduino + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.64s. + +2/27/22 8:00:08 PM :Debug: Time:672.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.705s. + +2/27/22 8:00:08 PM :Debug: Time:672.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.775s. + +2/27/22 8:00:08 PM :Debug: Time:672.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.844s. + +2/27/22 8:00:08 PM :Debug: Time:672.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.907s. + +2/27/22 8:00:08 PM :Debug: Time:672.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:672.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:672.973s. + +2/27/22 8:00:08 PM :Debug: Time:672.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:08 PM :Debug: Time:673.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:08 PM :Debug: Time:673.039s. + +2/27/22 8:00:08 PM :Debug: Time:673.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.104s. + +2/27/22 8:00:09 PM :Debug: Time:673.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.168s. + +2/27/22 8:00:09 PM :Debug: Time:673.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.24s. + +2/27/22 8:00:09 PM :Debug: Time:673.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.305s. + +2/27/22 8:00:09 PM :Debug: Time:673.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.37s. + +2/27/22 8:00:09 PM :Debug: Time:673.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.435s. + +2/27/22 8:00:09 PM :Debug: Time:673.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.5s. + +2/27/22 8:00:09 PM :Debug: Time:673.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.565s. + +2/27/22 8:00:09 PM :Debug: Time:673.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.643s. + +2/27/22 8:00:09 PM :Debug: Time:673.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.712s. + +2/27/22 8:00:09 PM :Debug: Time:673.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.776s. + +2/27/22 8:00:09 PM :Debug: Time:673.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.846s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.846s. + +2/27/22 8:00:09 PM :Debug: Time:673.846s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.912s. + +2/27/22 8:00:09 PM :Debug: Time:673.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:673.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:673.976s. + +2/27/22 8:00:09 PM :Debug: Time:673.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:09 PM :Debug: Time:674.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:09 PM :Debug: Time:674.037s. + +2/27/22 8:00:09 PM :Debug: Time:674.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.119s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.119s. + +2/27/22 8:00:10 PM :Debug: Time:674.119s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.181s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.181s. + +2/27/22 8:00:10 PM :Debug: Time:674.181s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.244s. + +2/27/22 8:00:10 PM :Debug: Time:674.244s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:10 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:10 PM :Info: Looks like Speeduino + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.318s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.318s. + +2/27/22 8:00:10 PM :Debug: Time:674.318s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.384s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.384s. + +2/27/22 8:00:10 PM :Debug: Time:674.384s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.448s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.448s. + +2/27/22 8:00:10 PM :Debug: Time:674.448s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.512s. + +2/27/22 8:00:10 PM :Debug: Time:674.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.576s. + +2/27/22 8:00:10 PM :Debug: Time:674.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.641s. + +2/27/22 8:00:10 PM :Debug: Time:674.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.711s. + +2/27/22 8:00:10 PM :Debug: Time:674.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.774s. + +2/27/22 8:00:10 PM :Debug: Time:674.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.844s. + +2/27/22 8:00:10 PM :Debug: Time:674.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.91s. + +2/27/22 8:00:10 PM :Debug: Time:674.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:674.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:674.975s. + +2/27/22 8:00:10 PM :Debug: Time:674.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:10 PM :Debug: Time:675.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:10 PM :Debug: Time:675.046s. + +2/27/22 8:00:10 PM :Debug: Time:675.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.113s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.113s. + +2/27/22 8:00:11 PM :Debug: Time:675.113s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.177s. + +2/27/22 8:00:11 PM :Debug: Time:675.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.241s. + +2/27/22 8:00:11 PM :Debug: Time:675.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.306s. + +2/27/22 8:00:11 PM :Debug: Time:675.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.37s. + +2/27/22 8:00:11 PM :Debug: Time:675.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.443s. + +2/27/22 8:00:11 PM :Debug: Time:675.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.508s. + +2/27/22 8:00:11 PM :Debug: Time:675.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.579s. + +2/27/22 8:00:11 PM :Debug: Time:675.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.647s. + +2/27/22 8:00:11 PM :Debug: Time:675.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.71s. + +2/27/22 8:00:11 PM :Debug: Time:675.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.774s. + +2/27/22 8:00:11 PM :Debug: Time:675.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.845s. + +2/27/22 8:00:11 PM :Debug: Time:675.845s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:11 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:11 PM :Info: Looks like Speeduino + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.907s. + +2/27/22 8:00:11 PM :Debug: Time:675.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:675.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:675.977s. + +2/27/22 8:00:11 PM :Debug: Time:675.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:11 PM :Debug: Time:676.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:11 PM :Debug: Time:676.042s. + +2/27/22 8:00:11 PM :Debug: Time:676.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.106s. + +2/27/22 8:00:12 PM :Debug: Time:676.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.172s. + +2/27/22 8:00:12 PM :Debug: Time:676.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.237s. + +2/27/22 8:00:12 PM :Debug: Time:676.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.301s. + +2/27/22 8:00:12 PM :Debug: Time:676.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.373s. + +2/27/22 8:00:12 PM :Debug: Time:676.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.437s. + +2/27/22 8:00:12 PM :Debug: Time:676.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.504s. + +2/27/22 8:00:12 PM :Debug: Time:676.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.568s. + +2/27/22 8:00:12 PM :Debug: Time:676.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.641s. + +2/27/22 8:00:12 PM :Debug: Time:676.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.704s. + +2/27/22 8:00:12 PM :Debug: Time:676.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.771s. + +2/27/22 8:00:12 PM :Debug: Time:676.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.836s. + +2/27/22 8:00:12 PM :Debug: Time:676.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.908s. + +2/27/22 8:00:12 PM :Debug: Time:676.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:676.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:676.978s. + +2/27/22 8:00:12 PM :Debug: Time:676.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:12 PM :Debug: Time:677.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:12 PM :Debug: Time:677.046s. + +2/27/22 8:00:12 PM :Debug: Time:677.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.111s. + +2/27/22 8:00:13 PM :Debug: Time:677.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.174s. + +2/27/22 8:00:13 PM :Debug: Time:677.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.24s. + +2/27/22 8:00:13 PM :Debug: Time:677.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.31s. + +2/27/22 8:00:13 PM :Debug: Time:677.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.374s. + +2/27/22 8:00:13 PM :Debug: Time:677.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.439s. + +2/27/22 8:00:13 PM :Debug: Time:677.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.509s. + +2/27/22 8:00:13 PM :Debug: Time:677.509s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:13 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:13 PM :Info: Looks like Speeduino + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.572s. + +2/27/22 8:00:13 PM :Debug: Time:677.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.643s. + +2/27/22 8:00:13 PM :Debug: Time:677.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.707s. + +2/27/22 8:00:13 PM :Debug: Time:677.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.773s. + +2/27/22 8:00:13 PM :Debug: Time:677.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.836s. + +2/27/22 8:00:13 PM :Debug: Time:677.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.9s. + +2/27/22 8:00:13 PM :Debug: Time:677.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:677.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:677.972s. + +2/27/22 8:00:13 PM :Debug: Time:677.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:13 PM :Debug: Time:678.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:13 PM :Debug: Time:678.034s. + +2/27/22 8:00:13 PM :Debug: Time:678.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.102s. + +2/27/22 8:00:14 PM :Debug: Time:678.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.168s. + +2/27/22 8:00:14 PM :Debug: Time:678.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.24s. + +2/27/22 8:00:14 PM :Debug: Time:678.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.305s. + +2/27/22 8:00:14 PM :Debug: Time:678.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.37s. + +2/27/22 8:00:14 PM :Debug: Time:678.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.436s. + +2/27/22 8:00:14 PM :Debug: Time:678.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.501s. + +2/27/22 8:00:14 PM :Debug: Time:678.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.573s. + +2/27/22 8:00:14 PM :Debug: Time:678.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.644s. + +2/27/22 8:00:14 PM :Debug: Time:678.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.712s. + +2/27/22 8:00:14 PM :Debug: Time:678.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.776s. + +2/27/22 8:00:14 PM :Debug: Time:678.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.841s. + +2/27/22 8:00:14 PM :Debug: Time:678.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.908s. + +2/27/22 8:00:14 PM :Debug: Time:678.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:678.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:678.97s. + +2/27/22 8:00:14 PM :Debug: Time:678.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:14 PM :Debug: Time:679.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:14 PM :Debug: Time:679.036s. + +2/27/22 8:00:14 PM :Debug: Time:679.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.107s. + +2/27/22 8:00:15 PM :Debug: Time:679.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.172s. + +2/27/22 8:00:15 PM :Debug: Time:679.172s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:15 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:15 PM :Info: Looks like Speeduino + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.236s. + +2/27/22 8:00:15 PM :Debug: Time:679.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.301s. + +2/27/22 8:00:15 PM :Debug: Time:679.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.367s. + +2/27/22 8:00:15 PM :Debug: Time:679.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.44s. + +2/27/22 8:00:15 PM :Debug: Time:679.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.504s. + +2/27/22 8:00:15 PM :Debug: Time:679.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.569s. + +2/27/22 8:00:15 PM :Debug: Time:679.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.634s. + +2/27/22 8:00:15 PM :Debug: Time:679.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.707s. + +2/27/22 8:00:15 PM :Debug: Time:679.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.772s. + +2/27/22 8:00:15 PM :Debug: Time:679.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.837s. + +2/27/22 8:00:15 PM :Debug: Time:679.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.901s. + +2/27/22 8:00:15 PM :Debug: Time:679.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:679.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:679.967s. + +2/27/22 8:00:15 PM :Debug: Time:679.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:15 PM :Debug: Time:680.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:15 PM :Debug: Time:680.039s. + +2/27/22 8:00:15 PM :Debug: Time:680.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.105s. + +2/27/22 8:00:16 PM :Debug: Time:680.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.169s. + +2/27/22 8:00:16 PM :Debug: Time:680.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.234s. + +2/27/22 8:00:16 PM :Debug: Time:680.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.306s. + +2/27/22 8:00:16 PM :Debug: Time:680.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.371s. + +2/27/22 8:00:16 PM :Debug: Time:680.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.436s. + +2/27/22 8:00:16 PM :Debug: Time:680.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.501s. + +2/27/22 8:00:16 PM :Debug: Time:680.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.566s. + +2/27/22 8:00:16 PM :Debug: Time:680.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.632s. + +2/27/22 8:00:16 PM :Debug: Time:680.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.71s. + +2/27/22 8:00:16 PM :Debug: Time:680.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.778s. + +2/27/22 8:00:16 PM :Debug: Time:680.778s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:16 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:16 PM :Info: Looks like Speeduino + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.842s. + +2/27/22 8:00:16 PM :Debug: Time:680.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.911s. + +2/27/22 8:00:16 PM :Debug: Time:680.911s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:680.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:680.976s. + +2/27/22 8:00:16 PM :Debug: Time:680.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:16 PM :Debug: Time:681.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:16 PM :Debug: Time:681.041s. + +2/27/22 8:00:16 PM :Debug: Time:681.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.104s. + +2/27/22 8:00:17 PM :Debug: Time:681.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.17s. + +2/27/22 8:00:17 PM :Debug: Time:681.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.235s. + +2/27/22 8:00:17 PM :Debug: Time:681.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.299s. + +2/27/22 8:00:17 PM :Debug: Time:681.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.366s. + +2/27/22 8:00:17 PM :Debug: Time:681.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.438s. + +2/27/22 8:00:17 PM :Debug: Time:681.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.502s. + +2/27/22 8:00:17 PM :Debug: Time:681.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.574s. + +2/27/22 8:00:17 PM :Debug: Time:681.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.645s. + +2/27/22 8:00:17 PM :Debug: Time:681.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.712s. + +2/27/22 8:00:17 PM :Debug: Time:681.712s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.776s. + +2/27/22 8:00:17 PM :Debug: Time:681.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.84s. + +2/27/22 8:00:17 PM :Debug: Time:681.84s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.91s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.91s. + +2/27/22 8:00:17 PM :Debug: Time:681.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:681.978s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:681.978s. + +2/27/22 8:00:17 PM :Debug: Time:681.978s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:17 PM :Debug: Time:682.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:17 PM :Debug: Time:682.044s. + +2/27/22 8:00:17 PM :Debug: Time:682.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.108s. + +2/27/22 8:00:18 PM :Debug: Time:682.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.173s. + +2/27/22 8:00:18 PM :Debug: Time:682.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.238s. + +2/27/22 8:00:18 PM :Debug: Time:682.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.302s. + +2/27/22 8:00:18 PM :Debug: Time:682.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.375s. + +2/27/22 8:00:18 PM :Debug: Time:682.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.439s. + +2/27/22 8:00:18 PM :Debug: Time:682.439s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:18 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:18 PM :Info: Looks like Speeduino + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.502s. + +2/27/22 8:00:18 PM :Debug: Time:682.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.569s. + +2/27/22 8:00:18 PM :Debug: Time:682.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.641s. + +2/27/22 8:00:18 PM :Debug: Time:682.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.705s. + +2/27/22 8:00:18 PM :Debug: Time:682.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.775s. + +2/27/22 8:00:18 PM :Debug: Time:682.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.843s. + +2/27/22 8:00:18 PM :Debug: Time:682.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.909s. + +2/27/22 8:00:18 PM :Debug: Time:682.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:682.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:682.975s. + +2/27/22 8:00:18 PM :Debug: Time:682.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:18 PM :Debug: Time:683.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:18 PM :Debug: Time:683.046s. + +2/27/22 8:00:18 PM :Debug: Time:683.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.114s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.115s. + +2/27/22 8:00:19 PM :Debug: Time:683.115s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.177s. + +2/27/22 8:00:19 PM :Debug: Time:683.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.242s. + +2/27/22 8:00:19 PM :Debug: Time:683.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.307s. + +2/27/22 8:00:19 PM :Debug: Time:683.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.371s. + +2/27/22 8:00:19 PM :Debug: Time:683.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.436s. + +2/27/22 8:00:19 PM :Debug: Time:683.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.508s. + +2/27/22 8:00:19 PM :Debug: Time:683.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.573s. + +2/27/22 8:00:19 PM :Debug: Time:683.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.644s. + +2/27/22 8:00:19 PM :Debug: Time:683.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.714s. + +2/27/22 8:00:19 PM :Debug: Time:683.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.778s. + +2/27/22 8:00:19 PM :Debug: Time:683.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.843s. + +2/27/22 8:00:19 PM :Debug: Time:683.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.907s. + +2/27/22 8:00:19 PM :Debug: Time:683.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:683.977s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:683.977s. + +2/27/22 8:00:19 PM :Debug: Time:683.977s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:19 PM :Debug: Time:684.045s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:19 PM :Debug: Time:684.045s. + +2/27/22 8:00:19 PM :Debug: Time:684.045s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:20 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:20 PM :Info: Looks like Speeduino + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.11s. + +2/27/22 8:00:20 PM :Debug: Time:684.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.176s. + +2/27/22 8:00:20 PM :Debug: Time:684.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.24s. + +2/27/22 8:00:20 PM :Debug: Time:684.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.307s. + +2/27/22 8:00:20 PM :Debug: Time:684.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.376s. + +2/27/22 8:00:20 PM :Debug: Time:684.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.444s. + +2/27/22 8:00:20 PM :Debug: Time:684.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.508s. + +2/27/22 8:00:20 PM :Debug: Time:684.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.574s. + +2/27/22 8:00:20 PM :Debug: Time:684.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.645s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.645s. + +2/27/22 8:00:20 PM :Debug: Time:684.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.713s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.713s. + +2/27/22 8:00:20 PM :Debug: Time:684.713s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.777s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.778s. + +2/27/22 8:00:20 PM :Debug: Time:684.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.841s. + +2/27/22 8:00:20 PM :Debug: Time:684.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.913s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.913s. + +2/27/22 8:00:20 PM :Debug: Time:684.913s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:684.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:684.974s. + +2/27/22 8:00:20 PM :Debug: Time:684.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:20 PM :Debug: Time:685.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:20 PM :Debug: Time:685.044s. + +2/27/22 8:00:20 PM :Debug: Time:685.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.108s. + +2/27/22 8:00:21 PM :Debug: Time:685.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.174s. + +2/27/22 8:00:21 PM :Debug: Time:685.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.237s. + +2/27/22 8:00:21 PM :Debug: Time:685.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.304s. + +2/27/22 8:00:21 PM :Debug: Time:685.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.377s. + +2/27/22 8:00:21 PM :Debug: Time:685.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.441s. + +2/27/22 8:00:21 PM :Debug: Time:685.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.505s. + +2/27/22 8:00:21 PM :Debug: Time:685.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.57s. + +2/27/22 8:00:21 PM :Debug: Time:685.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.636s. + +2/27/22 8:00:21 PM :Debug: Time:685.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.701s. + +2/27/22 8:00:21 PM :Debug: Time:685.701s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:21 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:21 PM :Info: Looks like Speeduino + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.771s. + +2/27/22 8:00:21 PM :Debug: Time:685.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.836s. + +2/27/22 8:00:21 PM :Debug: Time:685.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.902s. + +2/27/22 8:00:21 PM :Debug: Time:685.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:685.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:685.968s. + +2/27/22 8:00:21 PM :Debug: Time:685.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:21 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:21 PM :Debug: Time:686.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:21 PM :Debug: Time:686.038s. + +2/27/22 8:00:21 PM :Debug: Time:686.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.107s. + +2/27/22 8:00:22 PM :Debug: Time:686.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.172s. + +2/27/22 8:00:22 PM :Debug: Time:686.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.235s. + +2/27/22 8:00:22 PM :Debug: Time:686.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.301s. + +2/27/22 8:00:22 PM :Debug: Time:686.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.374s. + +2/27/22 8:00:22 PM :Debug: Time:686.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.438s. + +2/27/22 8:00:22 PM :Debug: Time:686.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.505s. + +2/27/22 8:00:22 PM :Debug: Time:686.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.576s. + +2/27/22 8:00:22 PM :Debug: Time:686.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.64s. + +2/27/22 8:00:22 PM :Debug: Time:686.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.706s. + +2/27/22 8:00:22 PM :Debug: Time:686.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.772s. + +2/27/22 8:00:22 PM :Debug: Time:686.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.835s. + +2/27/22 8:00:22 PM :Debug: Time:686.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.9s. + +2/27/22 8:00:22 PM :Debug: Time:686.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:686.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:686.969s. + +2/27/22 8:00:22 PM :Debug: Time:686.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:22 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:22 PM :Debug: Time:687.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:22 PM :Debug: Time:687.04s. + +2/27/22 8:00:22 PM :Debug: Time:687.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.104s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.104s. + +2/27/22 8:00:23 PM :Debug: Time:687.104s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.17s. + +2/27/22 8:00:23 PM :Debug: Time:687.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.235s. + +2/27/22 8:00:23 PM :Debug: Time:687.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.299s. + +2/27/22 8:00:23 PM :Debug: Time:687.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.365s. + +2/27/22 8:00:23 PM :Debug: Time:687.365s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:23 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:23 PM :Info: Looks like Speeduino + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.438s. + +2/27/22 8:00:23 PM :Debug: Time:687.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.502s. + +2/27/22 8:00:23 PM :Debug: Time:687.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.568s. + +2/27/22 8:00:23 PM :Debug: Time:687.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.64s. + +2/27/22 8:00:23 PM :Debug: Time:687.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.704s. + +2/27/22 8:00:23 PM :Debug: Time:687.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.768s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.768s. + +2/27/22 8:00:23 PM :Debug: Time:687.768s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.834s. + +2/27/22 8:00:23 PM :Debug: Time:687.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.898s. + +2/27/22 8:00:23 PM :Debug: Time:687.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:687.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:687.968s. + +2/27/22 8:00:23 PM :Debug: Time:687.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:23 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:23 PM :Debug: Time:688.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:23 PM :Debug: Time:688.038s. + +2/27/22 8:00:23 PM :Debug: Time:688.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.105s. + +2/27/22 8:00:24 PM :Debug: Time:688.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.175s. + +2/27/22 8:00:24 PM :Debug: Time:688.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.243s. + +2/27/22 8:00:24 PM :Debug: Time:688.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.309s. + +2/27/22 8:00:24 PM :Debug: Time:688.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.372s. + +2/27/22 8:00:24 PM :Debug: Time:688.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.442s. + +2/27/22 8:00:24 PM :Debug: Time:688.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.504s. + +2/27/22 8:00:24 PM :Debug: Time:688.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.575s. + +2/27/22 8:00:24 PM :Debug: Time:688.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.639s. + +2/27/22 8:00:24 PM :Debug: Time:688.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.704s. + +2/27/22 8:00:24 PM :Debug: Time:688.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.774s. + +2/27/22 8:00:24 PM :Debug: Time:688.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.839s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.839s. + +2/27/22 8:00:24 PM :Debug: Time:688.839s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.909s. + +2/27/22 8:00:24 PM :Debug: Time:688.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:688.974s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:688.974s. + +2/27/22 8:00:24 PM :Debug: Time:688.974s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:24 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:24 PM :Info: Looks like Speeduino + +2/27/22 8:00:24 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:24 PM :Debug: Time:689.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:24 PM :Debug: Time:689.04s. + +2/27/22 8:00:24 PM :Debug: Time:689.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.105s. + +2/27/22 8:00:25 PM :Debug: Time:689.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.174s. + +2/27/22 8:00:25 PM :Debug: Time:689.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.244s. + +2/27/22 8:00:25 PM :Debug: Time:689.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.307s. + +2/27/22 8:00:25 PM :Debug: Time:689.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.377s. + +2/27/22 8:00:25 PM :Debug: Time:689.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.443s. + +2/27/22 8:00:25 PM :Debug: Time:689.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.51s. + +2/27/22 8:00:25 PM :Debug: Time:689.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.579s. + +2/27/22 8:00:25 PM :Debug: Time:689.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.649s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.649s. + +2/27/22 8:00:25 PM :Debug: Time:689.649s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.714s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.714s. + +2/27/22 8:00:25 PM :Debug: Time:689.715s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.778s. + +2/27/22 8:00:25 PM :Debug: Time:689.778s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.843s. + +2/27/22 8:00:25 PM :Debug: Time:689.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.914s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.914s. + +2/27/22 8:00:25 PM :Debug: Time:689.914s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:689.982s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:689.983s. + +2/27/22 8:00:25 PM :Debug: Time:689.983s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:25 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:25 PM :Debug: Time:690.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:25 PM :Debug: Time:690.046s. + +2/27/22 8:00:25 PM :Debug: Time:690.046s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.111s. + +2/27/22 8:00:26 PM :Debug: Time:690.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.176s. + +2/27/22 8:00:26 PM :Debug: Time:690.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.24s. + +2/27/22 8:00:26 PM :Debug: Time:690.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.306s. + +2/27/22 8:00:26 PM :Debug: Time:690.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.37s. + +2/27/22 8:00:26 PM :Debug: Time:690.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.436s. + +2/27/22 8:00:26 PM :Debug: Time:690.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.509s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.509s. + +2/27/22 8:00:26 PM :Debug: Time:690.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.574s. + +2/27/22 8:00:26 PM :Debug: Time:690.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.64s. + +2/27/22 8:00:26 PM :Debug: Time:690.64s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:26 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:26 PM :Info: Looks like Speeduino + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.704s. + +2/27/22 8:00:26 PM :Debug: Time:690.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.769s. + +2/27/22 8:00:26 PM :Debug: Time:690.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.835s. + +2/27/22 8:00:26 PM :Debug: Time:690.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.908s. + +2/27/22 8:00:26 PM :Debug: Time:690.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:690.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:690.973s. + +2/27/22 8:00:26 PM :Debug: Time:690.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:26 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:26 PM :Debug: Time:691.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:26 PM :Debug: Time:691.038s. + +2/27/22 8:00:26 PM :Debug: Time:691.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.103s. + +2/27/22 8:00:27 PM :Debug: Time:691.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.168s. + +2/27/22 8:00:27 PM :Debug: Time:691.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.235s. + +2/27/22 8:00:27 PM :Debug: Time:691.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.313s. + +2/27/22 8:00:27 PM :Debug: Time:691.313s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.381s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.381s. + +2/27/22 8:00:27 PM :Debug: Time:691.381s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.447s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.447s. + +2/27/22 8:00:27 PM :Debug: Time:691.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.511s. + +2/27/22 8:00:27 PM :Debug: Time:691.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.576s. + +2/27/22 8:00:27 PM :Debug: Time:691.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.647s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.647s. + +2/27/22 8:00:27 PM :Debug: Time:691.647s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.71s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.71s. + +2/27/22 8:00:27 PM :Debug: Time:691.71s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.781s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.781s. + +2/27/22 8:00:27 PM :Debug: Time:691.781s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.844s. + +2/27/22 8:00:27 PM :Debug: Time:691.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.909s. + +2/27/22 8:00:27 PM :Debug: Time:691.91s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:691.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:691.974s. + +2/27/22 8:00:27 PM :Debug: Time:691.974s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:27 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:27 PM :Debug: Time:692.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:27 PM :Debug: Time:692.047s. + +2/27/22 8:00:27 PM :Debug: Time:692.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.11s. + +2/27/22 8:00:28 PM :Debug: Time:692.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.175s. + +2/27/22 8:00:28 PM :Debug: Time:692.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.239s. + +2/27/22 8:00:28 PM :Debug: Time:692.239s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:28 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Info: Looks like Speeduino +2/27/22 8:00:28 PM :Debug: Time:692.305s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.305s. + +2/27/22 8:00:28 PM :Debug: Time:692.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.37s. + +2/27/22 8:00:28 PM :Debug: Time:692.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.443s. + +2/27/22 8:00:28 PM :Debug: Time:692.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.508s. + +2/27/22 8:00:28 PM :Debug: Time:692.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.578s. + +2/27/22 8:00:28 PM :Debug: Time:692.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.645s. + +2/27/22 8:00:28 PM :Debug: Time:692.645s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.708s. + +2/27/22 8:00:28 PM :Debug: Time:692.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.773s. + +2/27/22 8:00:28 PM :Debug: Time:692.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.837s. + +2/27/22 8:00:28 PM :Debug: Time:692.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.905s. + +2/27/22 8:00:28 PM :Debug: Time:692.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:692.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:692.97s. + +2/27/22 8:00:28 PM :Debug: Time:692.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:28 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:28 PM :Debug: Time:693.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:28 PM :Debug: Time:693.042s. + +2/27/22 8:00:28 PM :Debug: Time:693.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.111s. + +2/27/22 8:00:29 PM :Debug: Time:693.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.18s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.18s. + +2/27/22 8:00:29 PM :Debug: Time:693.18s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.244s. + +2/27/22 8:00:29 PM :Debug: Time:693.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.308s. + +2/27/22 8:00:29 PM :Debug: Time:693.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.378s. + +2/27/22 8:00:29 PM :Debug: Time:693.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.446s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.447s. + +2/27/22 8:00:29 PM :Debug: Time:693.447s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.508s. + +2/27/22 8:00:29 PM :Debug: Time:693.509s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.577s. + +2/27/22 8:00:29 PM :Debug: Time:693.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.642s. + +2/27/22 8:00:29 PM :Debug: Time:693.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.706s. + +2/27/22 8:00:29 PM :Debug: Time:693.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.771s. + +2/27/22 8:00:29 PM :Debug: Time:693.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.844s. + +2/27/22 8:00:29 PM :Debug: Time:693.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.907s. + +2/27/22 8:00:29 PM :Debug: Time:693.907s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:29 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:29 PM :Info: Looks like Speeduino + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:693.98s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:693.98s. + +2/27/22 8:00:29 PM :Debug: Time:693.98s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:29 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:29 PM :Debug: Time:694.046s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:29 PM :Debug: Time:694.046s. + +2/27/22 8:00:29 PM :Debug: Time:694.047s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.11s. + +2/27/22 8:00:30 PM :Debug: Time:694.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.176s. + +2/27/22 8:00:30 PM :Debug: Time:694.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.239s. + +2/27/22 8:00:30 PM :Debug: Time:694.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.305s. + +2/27/22 8:00:30 PM :Debug: Time:694.305s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.376s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.376s. + +2/27/22 8:00:30 PM :Debug: Time:694.376s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.441s. + +2/27/22 8:00:30 PM :Debug: Time:694.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.503s. + +2/27/22 8:00:30 PM :Debug: Time:694.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.574s. + +2/27/22 8:00:30 PM :Debug: Time:694.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.642s. + +2/27/22 8:00:30 PM :Debug: Time:694.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.711s. + +2/27/22 8:00:30 PM :Debug: Time:694.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.774s. + +2/27/22 8:00:30 PM :Debug: Time:694.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.844s. + +2/27/22 8:00:30 PM :Debug: Time:694.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.909s. + +2/27/22 8:00:30 PM :Debug: Time:694.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:694.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:694.973s. + +2/27/22 8:00:30 PM :Debug: Time:694.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:30 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:30 PM :Debug: Time:695.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:30 PM :Debug: Time:695.042s. + +2/27/22 8:00:30 PM :Debug: Time:695.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.106s. + +2/27/22 8:00:31 PM :Debug: Time:695.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.177s. + +2/27/22 8:00:31 PM :Debug: Time:695.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.239s. + +2/27/22 8:00:31 PM :Debug: Time:695.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.309s. + +2/27/22 8:00:31 PM :Debug: Time:695.309s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.375s. + +2/27/22 8:00:31 PM :Debug: Time:695.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.439s. + +2/27/22 8:00:31 PM :Debug: Time:695.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.503s. + +2/27/22 8:00:31 PM :Debug: Time:695.503s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:31 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:31 PM :Info: Looks like Speeduino + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.569s. + +2/27/22 8:00:31 PM :Debug: Time:695.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.642s. + +2/27/22 8:00:31 PM :Debug: Time:695.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.706s. + +2/27/22 8:00:31 PM :Debug: Time:695.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.772s. + +2/27/22 8:00:31 PM :Debug: Time:695.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.843s. + +2/27/22 8:00:31 PM :Debug: Time:695.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.907s. + +2/27/22 8:00:31 PM :Debug: Time:695.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:695.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:695.971s. + +2/27/22 8:00:31 PM :Debug: Time:695.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:31 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:31 PM :Debug: Time:696.043s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:31 PM :Debug: Time:696.043s. + +2/27/22 8:00:31 PM :Debug: Time:696.043s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.107s. + +2/27/22 8:00:32 PM :Debug: Time:696.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.171s. + +2/27/22 8:00:32 PM :Debug: Time:696.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.236s. + +2/27/22 8:00:32 PM :Debug: Time:696.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.31s. + +2/27/22 8:00:32 PM :Debug: Time:696.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.377s. + +2/27/22 8:00:32 PM :Debug: Time:696.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.444s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.444s. + +2/27/22 8:00:32 PM :Debug: Time:696.444s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.513s. + +2/27/22 8:00:32 PM :Debug: Time:696.513s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.576s. + +2/27/22 8:00:32 PM :Debug: Time:696.577s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.64s. + +2/27/22 8:00:32 PM :Debug: Time:696.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.703s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.703s. + +2/27/22 8:00:32 PM :Debug: Time:696.703s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.769s. + +2/27/22 8:00:32 PM :Debug: Time:696.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.842s. + +2/27/22 8:00:32 PM :Debug: Time:696.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.906s. + +2/27/22 8:00:32 PM :Debug: Time:696.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:696.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:696.97s. + +2/27/22 8:00:32 PM :Debug: Time:696.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:32 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:32 PM :Debug: Time:697.034s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:32 PM :Debug: Time:697.034s. + +2/27/22 8:00:32 PM :Debug: Time:697.034s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.106s. + +2/27/22 8:00:33 PM :Debug: Time:697.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.171s. + +2/27/22 8:00:33 PM :Debug: Time:697.171s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:33 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:33 PM :Info: Looks like Speeduino + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.241s. + +2/27/22 8:00:33 PM :Debug: Time:697.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.307s. + +2/27/22 8:00:33 PM :Debug: Time:697.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.372s. + +2/27/22 8:00:33 PM :Debug: Time:697.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.436s. + +2/27/22 8:00:33 PM :Debug: Time:697.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.508s. + +2/27/22 8:00:33 PM :Debug: Time:697.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.574s. + +2/27/22 8:00:33 PM :Debug: Time:697.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.637s. + +2/27/22 8:00:33 PM :Debug: Time:697.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.702s. + +2/27/22 8:00:33 PM :Debug: Time:697.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.769s. + +2/27/22 8:00:33 PM :Debug: Time:697.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.841s. + +2/27/22 8:00:33 PM :Debug: Time:697.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.912s. + +2/27/22 8:00:33 PM :Debug: Time:697.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:697.98s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:697.98s. + +2/27/22 8:00:33 PM :Debug: Time:697.98s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:33 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:33 PM :Debug: Time:698.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:33 PM :Debug: Time:698.042s. + +2/27/22 8:00:33 PM :Debug: Time:698.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.111s. + +2/27/22 8:00:34 PM :Debug: Time:698.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.179s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.179s. + +2/27/22 8:00:34 PM :Debug: Time:698.179s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.243s. + +2/27/22 8:00:34 PM :Debug: Time:698.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.307s. + +2/27/22 8:00:34 PM :Debug: Time:698.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.372s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.372s. + +2/27/22 8:00:34 PM :Debug: Time:698.372s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.437s. + +2/27/22 8:00:34 PM :Debug: Time:698.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.502s. + +2/27/22 8:00:34 PM :Debug: Time:698.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.574s. + +2/27/22 8:00:34 PM :Debug: Time:698.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.644s. + +2/27/22 8:00:34 PM :Debug: Time:698.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.712s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.713s. + +2/27/22 8:00:34 PM :Debug: Time:698.714s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.778s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.778s. + +2/27/22 8:00:34 PM :Debug: Time:698.778s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:34 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:34 PM :Info: Looks like Speeduino + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.841s. + +2/27/22 8:00:34 PM :Debug: Time:698.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.904s. + +2/27/22 8:00:34 PM :Debug: Time:698.904s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:698.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:698.97s. + +2/27/22 8:00:34 PM :Debug: Time:698.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:34 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:34 PM :Debug: Time:699.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:34 PM :Debug: Time:699.041s. + +2/27/22 8:00:34 PM :Debug: Time:699.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.107s. + +2/27/22 8:00:35 PM :Debug: Time:699.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.177s. + +2/27/22 8:00:35 PM :Debug: Time:699.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.241s. + +2/27/22 8:00:35 PM :Debug: Time:699.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.307s. + +2/27/22 8:00:35 PM :Debug: Time:699.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.379s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.379s. + +2/27/22 8:00:35 PM :Debug: Time:699.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.441s. + +2/27/22 8:00:35 PM :Debug: Time:699.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.512s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.512s. + +2/27/22 8:00:35 PM :Debug: Time:699.512s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.575s. + +2/27/22 8:00:35 PM :Debug: Time:699.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.644s. + +2/27/22 8:00:35 PM :Debug: Time:699.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.708s. + +2/27/22 8:00:35 PM :Debug: Time:699.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.776s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.776s. + +2/27/22 8:00:35 PM :Debug: Time:699.776s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.841s. + +2/27/22 8:00:35 PM :Debug: Time:699.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.912s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.912s. + +2/27/22 8:00:35 PM :Debug: Time:699.912s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:699.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:699.973s. + +2/27/22 8:00:35 PM :Debug: Time:699.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:35 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:35 PM :Debug: Time:700.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:35 PM :Debug: Time:700.044s. + +2/27/22 8:00:35 PM :Debug: Time:700.044s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.109s. + +2/27/22 8:00:36 PM :Debug: Time:700.109s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.174s. + +2/27/22 8:00:36 PM :Debug: Time:700.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.244s. + +2/27/22 8:00:36 PM :Debug: Time:700.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.312s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.312s. + +2/27/22 8:00:36 PM :Debug: Time:700.312s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.377s. + +2/27/22 8:00:36 PM :Debug: Time:700.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.44s. + +2/27/22 8:00:36 PM :Debug: Time:700.44s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:36 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:36 PM :Info: Looks like Speeduino + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.504s. + +2/27/22 8:00:36 PM :Debug: Time:700.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.569s. + +2/27/22 8:00:36 PM :Debug: Time:700.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.635s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.635s. + +2/27/22 8:00:36 PM :Debug: Time:700.635s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.705s. + +2/27/22 8:00:36 PM :Debug: Time:700.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.772s. + +2/27/22 8:00:36 PM :Debug: Time:700.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.844s. + +2/27/22 8:00:36 PM :Debug: Time:700.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.908s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.908s. + +2/27/22 8:00:36 PM :Debug: Time:700.908s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:700.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:700.971s. + +2/27/22 8:00:36 PM :Debug: Time:700.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:36 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:36 PM :Debug: Time:701.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:36 PM :Debug: Time:701.036s. + +2/27/22 8:00:36 PM :Debug: Time:701.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.101s. + +2/27/22 8:00:37 PM :Debug: Time:701.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.172s. + +2/27/22 8:00:37 PM :Debug: Time:701.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.244s. + +2/27/22 8:00:37 PM :Debug: Time:701.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.311s. + +2/27/22 8:00:37 PM :Debug: Time:701.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.375s. + +2/27/22 8:00:37 PM :Debug: Time:701.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.445s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.445s. + +2/27/22 8:00:37 PM :Debug: Time:701.445s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.511s. + +2/27/22 8:00:37 PM :Debug: Time:701.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.575s. + +2/27/22 8:00:37 PM :Debug: Time:701.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.641s. + +2/27/22 8:00:37 PM :Debug: Time:701.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.705s. + +2/27/22 8:00:37 PM :Debug: Time:701.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.769s. + +2/27/22 8:00:37 PM :Debug: Time:701.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.844s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.844s. + +2/27/22 8:00:37 PM :Debug: Time:701.844s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.906s. + +2/27/22 8:00:37 PM :Debug: Time:701.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:701.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:701.97s. + +2/27/22 8:00:37 PM :Debug: Time:701.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:37 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:37 PM :Debug: Time:702.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:37 PM :Debug: Time:702.037s. + +2/27/22 8:00:37 PM :Debug: Time:702.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.107s. + +2/27/22 8:00:38 PM :Debug: Time:702.107s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:38 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:38 PM :Info: Looks like Speeduino + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.178s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.178s. + +2/27/22 8:00:38 PM :Debug: Time:702.178s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.245s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.245s. + +2/27/22 8:00:38 PM :Debug: Time:702.245s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.309s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.31s. + +2/27/22 8:00:38 PM :Debug: Time:702.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.375s. + +2/27/22 8:00:38 PM :Debug: Time:702.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.438s. + +2/27/22 8:00:38 PM :Debug: Time:702.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.504s. + +2/27/22 8:00:38 PM :Debug: Time:702.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.569s. + +2/27/22 8:00:38 PM :Debug: Time:702.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.633s. + +2/27/22 8:00:38 PM :Debug: Time:702.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.706s. + +2/27/22 8:00:38 PM :Debug: Time:702.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.769s. + +2/27/22 8:00:38 PM :Debug: Time:702.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.836s. + +2/27/22 8:00:38 PM :Debug: Time:702.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.901s. + +2/27/22 8:00:38 PM :Debug: Time:702.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:702.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:702.972s. + +2/27/22 8:00:38 PM :Debug: Time:702.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:38 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:38 PM :Debug: Time:703.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:38 PM :Debug: Time:703.042s. + +2/27/22 8:00:38 PM :Debug: Time:703.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.111s. + +2/27/22 8:00:39 PM :Debug: Time:703.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.174s. + +2/27/22 8:00:39 PM :Debug: Time:703.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.236s. + +2/27/22 8:00:39 PM :Debug: Time:703.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.31s. + +2/27/22 8:00:39 PM :Debug: Time:703.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.377s. + +2/27/22 8:00:39 PM :Debug: Time:703.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.441s. + +2/27/22 8:00:39 PM :Debug: Time:703.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.505s. + +2/27/22 8:00:39 PM :Debug: Time:703.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.571s. + +2/27/22 8:00:39 PM :Debug: Time:703.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.644s. + +2/27/22 8:00:39 PM :Debug: Time:703.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.707s. + +2/27/22 8:00:39 PM :Debug: Time:703.707s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:39 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:39 PM :Info: Looks like Speeduino + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.772s. + +2/27/22 8:00:39 PM :Debug: Time:703.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.837s. + +2/27/22 8:00:39 PM :Debug: Time:703.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.9s. + +2/27/22 8:00:39 PM :Debug: Time:703.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:703.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:703.972s. + +2/27/22 8:00:39 PM :Debug: Time:703.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:39 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:39 PM :Debug: Time:704.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:39 PM :Debug: Time:704.042s. + +2/27/22 8:00:39 PM :Debug: Time:704.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.111s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.111s. + +2/27/22 8:00:40 PM :Debug: Time:704.111s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.174s. + +2/27/22 8:00:40 PM :Debug: Time:704.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.24s. + +2/27/22 8:00:40 PM :Debug: Time:704.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.308s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.308s. + +2/27/22 8:00:40 PM :Debug: Time:704.308s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.371s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.371s. + +2/27/22 8:00:40 PM :Debug: Time:704.371s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.44s. + +2/27/22 8:00:40 PM :Debug: Time:704.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.51s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.51s. + +2/27/22 8:00:40 PM :Debug: Time:704.51s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.579s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.579s. + +2/27/22 8:00:40 PM :Debug: Time:704.579s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.643s. + +2/27/22 8:00:40 PM :Debug: Time:704.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.704s. + +2/27/22 8:00:40 PM :Debug: Time:704.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.77s. + +2/27/22 8:00:40 PM :Debug: Time:704.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.841s. + +2/27/22 8:00:40 PM :Debug: Time:704.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.906s. + +2/27/22 8:00:40 PM :Debug: Time:704.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:704.975s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:704.975s. + +2/27/22 8:00:40 PM :Debug: Time:704.975s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:40 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:40 PM :Debug: Time:705.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:40 PM :Debug: Time:705.042s. + +2/27/22 8:00:40 PM :Debug: Time:705.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.108s. + +2/27/22 8:00:41 PM :Debug: Time:705.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.172s. + +2/27/22 8:00:41 PM :Debug: Time:705.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.242s. + +2/27/22 8:00:41 PM :Debug: Time:705.242s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.306s. + +2/27/22 8:00:41 PM :Debug: Time:705.306s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.377s. + +2/27/22 8:00:41 PM :Debug: Time:705.377s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:41 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:41 PM :Info: Looks like Speeduino + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.441s. + +2/27/22 8:00:41 PM :Debug: Time:705.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.505s. + +2/27/22 8:00:41 PM :Debug: Time:705.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.57s. + +2/27/22 8:00:41 PM :Debug: Time:705.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.642s. + +2/27/22 8:00:41 PM :Debug: Time:705.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.706s. + +2/27/22 8:00:41 PM :Debug: Time:705.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.77s. + +2/27/22 8:00:41 PM :Debug: Time:705.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.836s. + +2/27/22 8:00:41 PM :Debug: Time:705.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.907s. + +2/27/22 8:00:41 PM :Debug: Time:705.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:705.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:705.969s. + +2/27/22 8:00:41 PM :Debug: Time:705.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:41 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:41 PM :Debug: Time:706.042s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:41 PM :Debug: Time:706.042s. + +2/27/22 8:00:41 PM :Debug: Time:706.042s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.11s. + +2/27/22 8:00:42 PM :Debug: Time:706.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.176s. + +2/27/22 8:00:42 PM :Debug: Time:706.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.239s. + +2/27/22 8:00:42 PM :Debug: Time:706.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.31s. + +2/27/22 8:00:42 PM :Debug: Time:706.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.377s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.377s. + +2/27/22 8:00:42 PM :Debug: Time:706.377s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.441s. + +2/27/22 8:00:42 PM :Debug: Time:706.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.506s. + +2/27/22 8:00:42 PM :Debug: Time:706.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.57s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.57s. + +2/27/22 8:00:42 PM :Debug: Time:706.57s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.636s. + +2/27/22 8:00:42 PM :Debug: Time:706.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.708s. + +2/27/22 8:00:42 PM :Debug: Time:706.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.772s. + +2/27/22 8:00:42 PM :Debug: Time:706.772s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.838s. + +2/27/22 8:00:42 PM :Debug: Time:706.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.902s. + +2/27/22 8:00:42 PM :Debug: Time:706.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:706.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:706.966s. + +2/27/22 8:00:42 PM :Debug: Time:706.966s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:42 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:42 PM :Info: Looks like Speeduino + +2/27/22 8:00:42 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:42 PM :Debug: Time:707.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:42 PM :Debug: Time:707.039s. + +2/27/22 8:00:42 PM :Debug: Time:707.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.102s. + +2/27/22 8:00:43 PM :Debug: Time:707.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.168s. + +2/27/22 8:00:43 PM :Debug: Time:707.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.233s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.233s. + +2/27/22 8:00:43 PM :Debug: Time:707.233s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.3s. + +2/27/22 8:00:43 PM :Debug: Time:707.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.365s. + +2/27/22 8:00:43 PM :Debug: Time:707.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.438s. + +2/27/22 8:00:43 PM :Debug: Time:707.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.502s. + +2/27/22 8:00:43 PM :Debug: Time:707.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.567s. + +2/27/22 8:00:43 PM :Debug: Time:707.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.639s. + +2/27/22 8:00:43 PM :Debug: Time:707.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.704s. + +2/27/22 8:00:43 PM :Debug: Time:707.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.77s. + +2/27/22 8:00:43 PM :Debug: Time:707.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.835s. + +2/27/22 8:00:43 PM :Debug: Time:707.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.907s. + +2/27/22 8:00:43 PM :Debug: Time:707.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:707.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:707.973s. + +2/27/22 8:00:43 PM :Debug: Time:707.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:43 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:43 PM :Debug: Time:708.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:43 PM :Debug: Time:708.041s. + +2/27/22 8:00:43 PM :Debug: Time:708.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.11s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.11s. + +2/27/22 8:00:44 PM :Debug: Time:708.11s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.174s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.174s. + +2/27/22 8:00:44 PM :Debug: Time:708.174s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.24s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.24s. + +2/27/22 8:00:44 PM :Debug: Time:708.24s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.31s. + +2/27/22 8:00:44 PM :Debug: Time:708.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.379s. + +2/27/22 8:00:44 PM :Debug: Time:708.379s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.442s. + +2/27/22 8:00:44 PM :Debug: Time:708.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.506s. + +2/27/22 8:00:44 PM :Debug: Time:708.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.571s. + +2/27/22 8:00:44 PM :Debug: Time:708.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.636s. + +2/27/22 8:00:44 PM :Debug: Time:708.636s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:44 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:44 PM :Info: Looks like Speeduino + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.701s. + +2/27/22 8:00:44 PM :Debug: Time:708.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.773s. + +2/27/22 8:00:44 PM :Debug: Time:708.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.838s. + +2/27/22 8:00:44 PM :Debug: Time:708.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.907s. + +2/27/22 8:00:44 PM :Debug: Time:708.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:708.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:708.976s. + +2/27/22 8:00:44 PM :Debug: Time:708.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:44 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:44 PM :Debug: Time:709.041s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:44 PM :Debug: Time:709.041s. + +2/27/22 8:00:44 PM :Debug: Time:709.041s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.106s. + +2/27/22 8:00:45 PM :Debug: Time:709.106s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.17s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.17s. + +2/27/22 8:00:45 PM :Debug: Time:709.17s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.235s. + +2/27/22 8:00:45 PM :Debug: Time:709.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.3s. + +2/27/22 8:00:45 PM :Debug: Time:709.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.373s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.373s. + +2/27/22 8:00:45 PM :Debug: Time:709.373s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.442s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.442s. + +2/27/22 8:00:45 PM :Debug: Time:709.442s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.511s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.511s. + +2/27/22 8:00:45 PM :Debug: Time:709.511s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.576s. + +2/27/22 8:00:45 PM :Debug: Time:709.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.64s. + +2/27/22 8:00:45 PM :Debug: Time:709.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.711s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.711s. + +2/27/22 8:00:45 PM :Debug: Time:709.711s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.779s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.779s. + +2/27/22 8:00:45 PM :Debug: Time:709.779s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.843s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.843s. + +2/27/22 8:00:45 PM :Debug: Time:709.843s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.907s. + +2/27/22 8:00:45 PM :Debug: Time:709.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:709.976s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:709.976s. + +2/27/22 8:00:45 PM :Debug: Time:709.976s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:45 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:45 PM :Debug: Time:710.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:45 PM :Debug: Time:710.039s. + +2/27/22 8:00:45 PM :Debug: Time:710.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.108s. + +2/27/22 8:00:46 PM :Debug: Time:710.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.172s. + +2/27/22 8:00:46 PM :Debug: Time:710.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.237s. + +2/27/22 8:00:46 PM :Debug: Time:710.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.301s. + +2/27/22 8:00:46 PM :Debug: Time:710.301s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:46 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:46 PM :Info: Looks like Speeduino + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.374s. + +2/27/22 8:00:46 PM :Debug: Time:710.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.438s. + +2/27/22 8:00:46 PM :Debug: Time:710.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.503s. + +2/27/22 8:00:46 PM :Debug: Time:710.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.567s. + +2/27/22 8:00:46 PM :Debug: Time:710.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.639s. + +2/27/22 8:00:46 PM :Debug: Time:710.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.704s. + +2/27/22 8:00:46 PM :Debug: Time:710.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.767s. + +2/27/22 8:00:46 PM :Debug: Time:710.767s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.834s. + +2/27/22 8:00:46 PM :Debug: Time:710.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.906s. + +2/27/22 8:00:46 PM :Debug: Time:710.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:710.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:710.97s. + +2/27/22 8:00:46 PM :Debug: Time:710.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:46 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:46 PM :Debug: Time:711.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:46 PM :Debug: Time:711.035s. + +2/27/22 8:00:46 PM :Debug: Time:711.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.1s. + +2/27/22 8:00:47 PM :Debug: Time:711.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.172s. + +2/27/22 8:00:47 PM :Debug: Time:711.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.235s. + +2/27/22 8:00:47 PM :Debug: Time:711.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.302s. + +2/27/22 8:00:47 PM :Debug: Time:711.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.374s. + +2/27/22 8:00:47 PM :Debug: Time:711.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.438s. + +2/27/22 8:00:47 PM :Debug: Time:711.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.508s. + +2/27/22 8:00:47 PM :Debug: Time:711.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.578s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.578s. + +2/27/22 8:00:47 PM :Debug: Time:711.578s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.641s. + +2/27/22 8:00:47 PM :Debug: Time:711.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.705s. + +2/27/22 8:00:47 PM :Debug: Time:711.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.769s. + +2/27/22 8:00:47 PM :Debug: Time:711.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.841s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.841s. + +2/27/22 8:00:47 PM :Debug: Time:711.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.903s. + +2/27/22 8:00:47 PM :Debug: Time:711.903s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:47 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:47 PM :Info: Looks like Speeduino + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:711.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:711.97s. + +2/27/22 8:00:47 PM :Debug: Time:711.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:47 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:47 PM :Debug: Time:712.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:47 PM :Debug: Time:712.035s. + +2/27/22 8:00:47 PM :Debug: Time:712.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.1s. + +2/27/22 8:00:48 PM :Debug: Time:712.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.166s. + +2/27/22 8:00:48 PM :Debug: Time:712.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.238s. + +2/27/22 8:00:48 PM :Debug: Time:712.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.302s. + +2/27/22 8:00:48 PM :Debug: Time:712.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.367s. + +2/27/22 8:00:48 PM :Debug: Time:712.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.44s. + +2/27/22 8:00:48 PM :Debug: Time:712.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.504s. + +2/27/22 8:00:48 PM :Debug: Time:712.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.569s. + +2/27/22 8:00:48 PM :Debug: Time:712.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.634s. + +2/27/22 8:00:48 PM :Debug: Time:712.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.706s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.706s. + +2/27/22 8:00:48 PM :Debug: Time:712.706s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.77s. + +2/27/22 8:00:48 PM :Debug: Time:712.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.835s. + +2/27/22 8:00:48 PM :Debug: Time:712.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.9s. + +2/27/22 8:00:48 PM :Debug: Time:712.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:712.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:712.973s. + +2/27/22 8:00:48 PM :Debug: Time:712.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:48 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:48 PM :Debug: Time:713.038s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:48 PM :Debug: Time:713.038s. + +2/27/22 8:00:48 PM :Debug: Time:713.038s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.108s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.108s. + +2/27/22 8:00:49 PM :Debug: Time:713.108s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.175s. + +2/27/22 8:00:49 PM :Debug: Time:713.175s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.239s. + +2/27/22 8:00:49 PM :Debug: Time:713.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.311s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.311s. + +2/27/22 8:00:49 PM :Debug: Time:713.311s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.38s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.38s. + +2/27/22 8:00:49 PM :Debug: Time:713.38s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.443s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.443s. + +2/27/22 8:00:49 PM :Debug: Time:713.443s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.507s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.507s. + +2/27/22 8:00:49 PM :Debug: Time:713.507s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.577s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.577s. + +2/27/22 8:00:49 PM :Debug: Time:713.577s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:49 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:49 PM :Info: Looks like Speeduino + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.644s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.644s. + +2/27/22 8:00:49 PM :Debug: Time:713.644s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.708s. + +2/27/22 8:00:49 PM :Debug: Time:713.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.773s. + +2/27/22 8:00:49 PM :Debug: Time:713.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.837s. + +2/27/22 8:00:49 PM :Debug: Time:713.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.901s. + +2/27/22 8:00:49 PM :Debug: Time:713.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:713.973s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:713.973s. + +2/27/22 8:00:49 PM :Debug: Time:713.973s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:49 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:49 PM :Debug: Time:714.044s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:49 PM :Debug: Time:714.045s. + +2/27/22 8:00:49 PM :Debug: Time:714.045s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.112s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.112s. + +2/27/22 8:00:50 PM :Debug: Time:714.112s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.177s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.177s. + +2/27/22 8:00:50 PM :Debug: Time:714.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.242s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.242s. + +2/27/22 8:00:50 PM :Debug: Time:714.243s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.307s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.307s. + +2/27/22 8:00:50 PM :Debug: Time:714.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.378s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.378s. + +2/27/22 8:00:50 PM :Debug: Time:714.378s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.441s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.441s. + +2/27/22 8:00:50 PM :Debug: Time:714.441s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.506s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.506s. + +2/27/22 8:00:50 PM :Debug: Time:714.506s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.575s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.575s. + +2/27/22 8:00:50 PM :Debug: Time:714.575s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.642s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.642s. + +2/27/22 8:00:50 PM :Debug: Time:714.642s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.707s. + +2/27/22 8:00:50 PM :Debug: Time:714.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.775s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.775s. + +2/27/22 8:00:50 PM :Debug: Time:714.775s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.845s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.845s. + +2/27/22 8:00:50 PM :Debug: Time:714.845s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.909s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.909s. + +2/27/22 8:00:50 PM :Debug: Time:714.909s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:714.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:714.972s. + +2/27/22 8:00:50 PM :Debug: Time:714.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:50 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:50 PM :Debug: Time:715.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:50 PM :Debug: Time:715.037s. + +2/27/22 8:00:50 PM :Debug: Time:715.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.101s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.101s. + +2/27/22 8:00:51 PM :Debug: Time:715.101s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.173s. + +2/27/22 8:00:51 PM :Debug: Time:715.173s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:51 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:51 PM :Info: Looks like Speeduino + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.237s. + +2/27/22 8:00:51 PM :Debug: Time:715.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.303s. + +2/27/22 8:00:51 PM :Debug: Time:715.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.367s. + +2/27/22 8:00:51 PM :Debug: Time:715.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.439s. + +2/27/22 8:00:51 PM :Debug: Time:715.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.503s. + +2/27/22 8:00:51 PM :Debug: Time:715.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.568s. + +2/27/22 8:00:51 PM :Debug: Time:715.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.632s. + +2/27/22 8:00:51 PM :Debug: Time:715.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.704s. + +2/27/22 8:00:51 PM :Debug: Time:715.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.774s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.774s. + +2/27/22 8:00:51 PM :Debug: Time:715.774s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.842s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.842s. + +2/27/22 8:00:51 PM :Debug: Time:715.842s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.906s. + +2/27/22 8:00:51 PM :Debug: Time:715.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:715.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:715.971s. + +2/27/22 8:00:51 PM :Debug: Time:715.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:51 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:51 PM :Debug: Time:716.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:51 PM :Debug: Time:716.036s. + +2/27/22 8:00:51 PM :Debug: Time:716.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.1s. + +2/27/22 8:00:52 PM :Debug: Time:716.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.166s. + +2/27/22 8:00:52 PM :Debug: Time:716.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.243s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.244s. + +2/27/22 8:00:52 PM :Debug: Time:716.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.31s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.31s. + +2/27/22 8:00:52 PM :Debug: Time:716.31s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.375s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.375s. + +2/27/22 8:00:52 PM :Debug: Time:716.375s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.44s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.44s. + +2/27/22 8:00:52 PM :Debug: Time:716.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.503s. + +2/27/22 8:00:52 PM :Debug: Time:716.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.568s. + +2/27/22 8:00:52 PM :Debug: Time:716.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.64s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.64s. + +2/27/22 8:00:52 PM :Debug: Time:716.64s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.705s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.705s. + +2/27/22 8:00:52 PM :Debug: Time:716.705s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.769s. + +2/27/22 8:00:52 PM :Debug: Time:716.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.834s. + +2/27/22 8:00:52 PM :Debug: Time:716.834s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:52 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:52 PM :Info: Looks like Speeduino + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.907s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.907s. + +2/27/22 8:00:52 PM :Debug: Time:716.907s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:716.971s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:716.971s. + +2/27/22 8:00:52 PM :Debug: Time:716.971s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:52 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:52 PM :Debug: Time:717.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:52 PM :Debug: Time:717.035s. + +2/27/22 8:00:52 PM :Debug: Time:717.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.1s. + +2/27/22 8:00:53 PM :Debug: Time:717.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.172s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.172s. + +2/27/22 8:00:53 PM :Debug: Time:717.172s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.236s. + +2/27/22 8:00:53 PM :Debug: Time:717.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.301s. + +2/27/22 8:00:53 PM :Debug: Time:717.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.374s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.374s. + +2/27/22 8:00:53 PM :Debug: Time:717.374s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.438s. + +2/27/22 8:00:53 PM :Debug: Time:717.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.503s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.503s. + +2/27/22 8:00:53 PM :Debug: Time:717.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.568s. + +2/27/22 8:00:53 PM :Debug: Time:717.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.632s. + +2/27/22 8:00:53 PM :Debug: Time:717.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.699s. + +2/27/22 8:00:53 PM :Debug: Time:717.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.771s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.771s. + +2/27/22 8:00:53 PM :Debug: Time:717.771s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.835s. + +2/27/22 8:00:53 PM :Debug: Time:717.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.899s. + +2/27/22 8:00:53 PM :Debug: Time:717.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:717.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:717.965s. + +2/27/22 8:00:53 PM :Debug: Time:717.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:53 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:53 PM :Debug: Time:718.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:53 PM :Debug: Time:718.037s. + +2/27/22 8:00:53 PM :Debug: Time:718.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.107s. + +2/27/22 8:00:54 PM :Debug: Time:718.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.176s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.177s. + +2/27/22 8:00:54 PM :Debug: Time:718.177s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.241s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.241s. + +2/27/22 8:00:54 PM :Debug: Time:718.241s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.303s. + +2/27/22 8:00:54 PM :Debug: Time:718.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.368s. + +2/27/22 8:00:54 PM :Debug: Time:718.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.432s. + +2/27/22 8:00:54 PM :Debug: Time:718.432s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:54 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:54 PM :Info: Looks like Speeduino + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.497s. + +2/27/22 8:00:54 PM :Debug: Time:718.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.574s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.574s. + +2/27/22 8:00:54 PM :Debug: Time:718.574s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.643s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.643s. + +2/27/22 8:00:54 PM :Debug: Time:718.643s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.707s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.707s. + +2/27/22 8:00:54 PM :Debug: Time:718.707s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.773s. + +2/27/22 8:00:54 PM :Debug: Time:718.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.838s. + +2/27/22 8:00:54 PM :Debug: Time:718.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.903s. + +2/27/22 8:00:54 PM :Debug: Time:718.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:718.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:718.967s. + +2/27/22 8:00:54 PM :Debug: Time:718.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:54 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:54 PM :Debug: Time:719.04s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:54 PM :Debug: Time:719.04s. + +2/27/22 8:00:54 PM :Debug: Time:719.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.105s. + +2/27/22 8:00:55 PM :Debug: Time:719.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.169s. + +2/27/22 8:00:55 PM :Debug: Time:719.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.234s. + +2/27/22 8:00:55 PM :Debug: Time:719.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.299s. + +2/27/22 8:00:55 PM :Debug: Time:719.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.367s. + +2/27/22 8:00:55 PM :Debug: Time:719.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.432s. + +2/27/22 8:00:55 PM :Debug: Time:719.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.508s. + +2/27/22 8:00:55 PM :Debug: Time:719.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.576s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.576s. + +2/27/22 8:00:55 PM :Debug: Time:719.576s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.639s. + +2/27/22 8:00:55 PM :Debug: Time:719.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.702s. + +2/27/22 8:00:55 PM :Debug: Time:719.703s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.769s. + +2/27/22 8:00:55 PM :Debug: Time:719.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.833s. + +2/27/22 8:00:55 PM :Debug: Time:719.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.906s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.906s. + +2/27/22 8:00:55 PM :Debug: Time:719.906s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:719.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:719.969s. + +2/27/22 8:00:55 PM :Debug: Time:719.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:55 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:55 PM :Debug: Time:720.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:55 PM :Debug: Time:720.035s. + +2/27/22 8:00:55 PM :Debug: Time:720.035s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.099s. + +2/27/22 8:00:56 PM :Debug: Time:720.099s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:56 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:56 PM :Info: Looks like Speeduino + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.166s. + +2/27/22 8:00:56 PM :Debug: Time:720.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.238s. + +2/27/22 8:00:56 PM :Debug: Time:720.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.304s. + +2/27/22 8:00:56 PM :Debug: Time:720.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.368s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.368s. + +2/27/22 8:00:56 PM :Debug: Time:720.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.432s. + +2/27/22 8:00:56 PM :Debug: Time:720.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.499s. + +2/27/22 8:00:56 PM :Debug: Time:720.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.571s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.571s. + +2/27/22 8:00:56 PM :Debug: Time:720.571s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.637s. + +2/27/22 8:00:56 PM :Debug: Time:720.638s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.702s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.702s. + +2/27/22 8:00:56 PM :Debug: Time:720.702s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.773s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.773s. + +2/27/22 8:00:56 PM :Debug: Time:720.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.838s. + +2/27/22 8:00:56 PM :Debug: Time:720.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.899s. + +2/27/22 8:00:56 PM :Debug: Time:720.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:720.968s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:720.968s. + +2/27/22 8:00:56 PM :Debug: Time:720.968s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:56 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:56 PM :Debug: Time:721.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:56 PM :Debug: Time:721.039s. + +2/27/22 8:00:56 PM :Debug: Time:721.04s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.109s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.109s. + +2/27/22 8:00:57 PM :Debug: Time:721.109s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.171s. + +2/27/22 8:00:57 PM :Debug: Time:721.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.237s. + +2/27/22 8:00:57 PM :Debug: Time:721.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.301s. + +2/27/22 8:00:57 PM :Debug: Time:721.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.366s. + +2/27/22 8:00:57 PM :Debug: Time:721.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.438s. + +2/27/22 8:00:57 PM :Debug: Time:721.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.502s. + +2/27/22 8:00:57 PM :Debug: Time:721.503s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.569s. + +2/27/22 8:00:57 PM :Debug: Time:721.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.632s. + +2/27/22 8:00:57 PM :Debug: Time:721.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.704s. + +2/27/22 8:00:57 PM :Debug: Time:721.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.767s. + +2/27/22 8:00:57 PM :Debug: Time:721.767s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:57 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:57 PM :Info: Looks like Speeduino + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.832s. + +2/27/22 8:00:57 PM :Debug: Time:721.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.898s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.898s. + +2/27/22 8:00:57 PM :Debug: Time:721.898s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:721.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:721.964s. + +2/27/22 8:00:57 PM :Debug: Time:721.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:57 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:57 PM :Debug: Time:722.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:57 PM :Debug: Time:722.036s. + +2/27/22 8:00:57 PM :Debug: Time:722.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.102s. + +2/27/22 8:00:58 PM :Debug: Time:722.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.171s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.171s. + +2/27/22 8:00:58 PM :Debug: Time:722.171s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.239s. + +2/27/22 8:00:58 PM :Debug: Time:722.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.303s. + +2/27/22 8:00:58 PM :Debug: Time:722.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.365s. + +2/27/22 8:00:58 PM :Debug: Time:722.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.438s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.438s. + +2/27/22 8:00:58 PM :Debug: Time:722.438s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.505s. + +2/27/22 8:00:58 PM :Debug: Time:722.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.569s. + +2/27/22 8:00:58 PM :Debug: Time:722.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.634s. + +2/27/22 8:00:58 PM :Debug: Time:722.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.697s. + +2/27/22 8:00:58 PM :Debug: Time:722.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.762s. + +2/27/22 8:00:58 PM :Debug: Time:722.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.834s. + +2/27/22 8:00:58 PM :Debug: Time:722.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.904s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.904s. + +2/27/22 8:00:58 PM :Debug: Time:722.904s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:722.972s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:722.972s. + +2/27/22 8:00:58 PM :Debug: Time:722.972s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:58 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:58 PM :Debug: Time:723.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:58 PM :Debug: Time:723.037s. + +2/27/22 8:00:58 PM :Debug: Time:723.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.103s. + +2/27/22 8:00:59 PM :Debug: Time:723.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.168s. + +2/27/22 8:00:59 PM :Debug: Time:723.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.238s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.238s. + +2/27/22 8:00:59 PM :Debug: Time:723.238s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.299s. + +2/27/22 8:00:59 PM :Debug: Time:723.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.364s. + +2/27/22 8:00:59 PM :Debug: Time:723.364s. . & . . . . . . . . ~ . . . . . +2/27/22 8:00:59 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:00:59 PM :Info: Looks like Speeduino + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.436s. + +2/27/22 8:00:59 PM :Debug: Time:723.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.501s. + +2/27/22 8:00:59 PM :Debug: Time:723.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.564s. + +2/27/22 8:00:59 PM :Debug: Time:723.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.637s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.637s. + +2/27/22 8:00:59 PM :Debug: Time:723.637s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.701s. + +2/27/22 8:00:59 PM :Debug: Time:723.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.767s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.767s. + +2/27/22 8:00:59 PM :Debug: Time:723.767s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.831s. + +2/27/22 8:00:59 PM :Debug: Time:723.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.897s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.897s. + +2/27/22 8:00:59 PM :Debug: Time:723.897s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:723.962s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:723.962s. + +2/27/22 8:00:59 PM :Debug: Time:723.962s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:00:59 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:00:59 PM :Debug: Time:724.035s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:00:59 PM :Debug: Time:724.036s. + +2/27/22 8:00:59 PM :Debug: Time:724.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.106s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.107s. + +2/27/22 8:01:00 PM :Debug: Time:724.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.175s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.176s. + +2/27/22 8:01:00 PM :Debug: Time:724.176s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.239s. + +2/27/22 8:01:00 PM :Debug: Time:724.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.304s. + +2/27/22 8:01:00 PM :Debug: Time:724.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.369s. + +2/27/22 8:01:00 PM :Debug: Time:724.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.432s. + +2/27/22 8:01:00 PM :Debug: Time:724.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.497s. + +2/27/22 8:01:00 PM :Debug: Time:724.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.569s. + +2/27/22 8:01:00 PM :Debug: Time:724.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.634s. + +2/27/22 8:01:00 PM :Debug: Time:724.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.697s. + +2/27/22 8:01:00 PM :Debug: Time:724.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.764s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.764s. + +2/27/22 8:01:00 PM :Debug: Time:724.764s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.83s. + +2/27/22 8:01:00 PM :Debug: Time:724.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.902s. + +2/27/22 8:01:00 PM :Debug: Time:724.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:724.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:724.967s. + +2/27/22 8:01:00 PM :Debug: Time:724.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:00 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:00 PM :Debug: Time:725.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:00 PM :Debug: Time:725.031s. + +2/27/22 8:01:00 PM :Debug: Time:725.031s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:01 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:01 PM :Info: Looks like Speeduino + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.097s. + +2/27/22 8:01:01 PM :Debug: Time:725.097s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.169s. + +2/27/22 8:01:01 PM :Debug: Time:725.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.235s. + +2/27/22 8:01:01 PM :Debug: Time:725.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.299s. + +2/27/22 8:01:01 PM :Debug: Time:725.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.364s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.364s. + +2/27/22 8:01:01 PM :Debug: Time:725.364s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.436s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.436s. + +2/27/22 8:01:01 PM :Debug: Time:725.436s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.501s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.501s. + +2/27/22 8:01:01 PM :Debug: Time:725.501s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.572s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.572s. + +2/27/22 8:01:01 PM :Debug: Time:725.572s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.639s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.639s. + +2/27/22 8:01:01 PM :Debug: Time:725.639s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.704s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.704s. + +2/27/22 8:01:01 PM :Debug: Time:725.704s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.769s. + +2/27/22 8:01:01 PM :Debug: Time:725.769s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.838s. + +2/27/22 8:01:01 PM :Debug: Time:725.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.9s. + +2/27/22 8:01:01 PM :Debug: Time:725.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:725.97s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:725.97s. + +2/27/22 8:01:01 PM :Debug: Time:725.97s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:01 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:01 PM :Debug: Time:726.036s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:01 PM :Debug: Time:726.036s. + +2/27/22 8:01:01 PM :Debug: Time:726.036s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.105s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.105s. + +2/27/22 8:01:02 PM :Debug: Time:726.105s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.169s. + +2/27/22 8:01:02 PM :Debug: Time:726.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.237s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.237s. + +2/27/22 8:01:02 PM :Debug: Time:726.237s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.301s. + +2/27/22 8:01:02 PM :Debug: Time:726.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.37s. + +2/27/22 8:01:02 PM :Debug: Time:726.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.433s. + +2/27/22 8:01:02 PM :Debug: Time:726.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.502s. + +2/27/22 8:01:02 PM :Debug: Time:726.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.566s. + +2/27/22 8:01:02 PM :Debug: Time:726.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.63s. + +2/27/22 8:01:02 PM :Debug: Time:726.63s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:02 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:02 PM :Info: Looks like Speeduino + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.696s. + +2/27/22 8:01:02 PM :Debug: Time:726.696s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.762s. + +2/27/22 8:01:02 PM :Debug: Time:726.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.834s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.834s. + +2/27/22 8:01:02 PM :Debug: Time:726.834s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.899s. + +2/27/22 8:01:02 PM :Debug: Time:726.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:726.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:726.964s. + +2/27/22 8:01:02 PM :Debug: Time:726.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:02 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:02 PM :Debug: Time:727.037s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:02 PM :Debug: Time:727.037s. + +2/27/22 8:01:02 PM :Debug: Time:727.037s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.1s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.1s. + +2/27/22 8:01:03 PM :Debug: Time:727.1s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.164s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.164s. + +2/27/22 8:01:03 PM :Debug: Time:727.164s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.228s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.228s. + +2/27/22 8:01:03 PM :Debug: Time:727.228s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.301s. + +2/27/22 8:01:03 PM :Debug: Time:727.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.366s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.366s. + +2/27/22 8:01:03 PM :Debug: Time:727.366s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.431s. + +2/27/22 8:01:03 PM :Debug: Time:727.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.496s. + +2/27/22 8:01:03 PM :Debug: Time:727.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.567s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.567s. + +2/27/22 8:01:03 PM :Debug: Time:727.567s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.633s. + +2/27/22 8:01:03 PM :Debug: Time:727.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.698s. + +2/27/22 8:01:03 PM :Debug: Time:727.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.763s. + +2/27/22 8:01:03 PM :Debug: Time:727.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.829s. + +2/27/22 8:01:03 PM :Debug: Time:727.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.901s. + +2/27/22 8:01:03 PM :Debug: Time:727.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:727.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:727.965s. + +2/27/22 8:01:03 PM :Debug: Time:727.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:03 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:03 PM :Debug: Time:728.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:03 PM :Debug: Time:728.03s. + +2/27/22 8:01:03 PM :Debug: Time:728.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.102s. + +2/27/22 8:01:04 PM :Debug: Time:728.102s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.168s. + +2/27/22 8:01:04 PM :Debug: Time:728.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.232s. + +2/27/22 8:01:04 PM :Debug: Time:728.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.297s. + +2/27/22 8:01:04 PM :Debug: Time:728.297s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:04 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:04 PM :Info: Looks like Speeduino + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.37s. + +2/27/22 8:01:04 PM :Debug: Time:728.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.434s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.434s. + +2/27/22 8:01:04 PM :Debug: Time:728.434s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.505s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.505s. + +2/27/22 8:01:04 PM :Debug: Time:728.505s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.573s. + +2/27/22 8:01:04 PM :Debug: Time:728.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.636s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.636s. + +2/27/22 8:01:04 PM :Debug: Time:728.636s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.701s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.701s. + +2/27/22 8:01:04 PM :Debug: Time:728.701s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.772s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.772s. + +2/27/22 8:01:04 PM :Debug: Time:728.773s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.84s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.84s. + +2/27/22 8:01:04 PM :Debug: Time:728.841s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.905s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.905s. + +2/27/22 8:01:04 PM :Debug: Time:728.905s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:728.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:728.969s. + +2/27/22 8:01:04 PM :Debug: Time:728.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:04 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:04 PM :Debug: Time:729.039s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:04 PM :Debug: Time:729.039s. + +2/27/22 8:01:04 PM :Debug: Time:729.039s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.107s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.107s. + +2/27/22 8:01:05 PM :Debug: Time:729.107s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.173s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.173s. + +2/27/22 8:01:05 PM :Debug: Time:729.173s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.236s. + +2/27/22 8:01:05 PM :Debug: Time:729.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.3s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.3s. + +2/27/22 8:01:05 PM :Debug: Time:729.3s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.367s. + +2/27/22 8:01:05 PM :Debug: Time:729.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.437s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.437s. + +2/27/22 8:01:05 PM :Debug: Time:729.437s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.502s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.502s. + +2/27/22 8:01:05 PM :Debug: Time:729.502s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.566s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.566s. + +2/27/22 8:01:05 PM :Debug: Time:729.566s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.63s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.63s. + +2/27/22 8:01:05 PM :Debug: Time:729.631s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.695s. + +2/27/22 8:01:05 PM :Debug: Time:729.695s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.76s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.76s. + +2/27/22 8:01:05 PM :Debug: Time:729.76s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.832s. + +2/27/22 8:01:05 PM :Debug: Time:729.832s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.897s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.897s. + +2/27/22 8:01:05 PM :Debug: Time:729.897s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:729.962s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:729.962s. + +2/27/22 8:01:05 PM :Debug: Time:729.962s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:05 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:05 PM :Info: Looks like Speeduino + +2/27/22 8:01:05 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:05 PM :Debug: Time:730.027s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:05 PM :Debug: Time:730.027s. + +2/27/22 8:01:05 PM :Debug: Time:730.027s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.094s. + +2/27/22 8:01:06 PM :Debug: Time:730.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.165s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.165s. + +2/27/22 8:01:06 PM :Debug: Time:730.165s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.235s. + +2/27/22 8:01:06 PM :Debug: Time:730.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.302s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.302s. + +2/27/22 8:01:06 PM :Debug: Time:730.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.368s. + +2/27/22 8:01:06 PM :Debug: Time:730.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.431s. + +2/27/22 8:01:06 PM :Debug: Time:730.431s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.497s. + +2/27/22 8:01:06 PM :Debug: Time:730.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.561s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.561s. + +2/27/22 8:01:06 PM :Debug: Time:730.561s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.626s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.626s. + +2/27/22 8:01:06 PM :Debug: Time:730.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.698s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.698s. + +2/27/22 8:01:06 PM :Debug: Time:730.698s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.765s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.765s. + +2/27/22 8:01:06 PM :Debug: Time:730.765s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.835s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.835s. + +2/27/22 8:01:06 PM :Debug: Time:730.835s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.903s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.903s. + +2/27/22 8:01:06 PM :Debug: Time:730.903s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:730.969s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:730.969s. + +2/27/22 8:01:06 PM :Debug: Time:730.969s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:06 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:06 PM :Debug: Time:731.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:06 PM :Debug: Time:731.03s. + +2/27/22 8:01:06 PM :Debug: Time:731.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.098s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.098s. + +2/27/22 8:01:07 PM :Debug: Time:731.098s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.168s. + +2/27/22 8:01:07 PM :Debug: Time:731.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.236s. + +2/27/22 8:01:07 PM :Debug: Time:731.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.299s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.299s. + +2/27/22 8:01:07 PM :Debug: Time:731.299s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.365s. + +2/27/22 8:01:07 PM :Debug: Time:731.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.429s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.429s. + +2/27/22 8:01:07 PM :Debug: Time:731.429s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.5s. + +2/27/22 8:01:07 PM :Debug: Time:731.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.564s. + +2/27/22 8:01:07 PM :Debug: Time:731.564s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:07 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:07 PM :Info: Looks like Speeduino + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.629s. + +2/27/22 8:01:07 PM :Debug: Time:731.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.699s. + +2/27/22 8:01:07 PM :Debug: Time:731.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.761s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.762s. + +2/27/22 8:01:07 PM :Debug: Time:731.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.832s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.832s. + +2/27/22 8:01:07 PM :Debug: Time:731.833s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.897s. + +2/27/22 8:01:07 PM :Debug: Time:731.897s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:731.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:731.967s. + +2/27/22 8:01:07 PM :Debug: Time:731.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:07 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:07 PM :Debug: Time:732.028s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:07 PM :Debug: Time:732.028s. + +2/27/22 8:01:07 PM :Debug: Time:732.028s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.098s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.098s. + +2/27/22 8:01:08 PM :Debug: Time:732.098s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.167s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.167s. + +2/27/22 8:01:08 PM :Debug: Time:732.167s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.235s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.235s. + +2/27/22 8:01:08 PM :Debug: Time:732.235s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.298s. + +2/27/22 8:01:08 PM :Debug: Time:732.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.363s. + +2/27/22 8:01:08 PM :Debug: Time:732.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.427s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.427s. + +2/27/22 8:01:08 PM :Debug: Time:732.427s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.492s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.492s. + +2/27/22 8:01:08 PM :Debug: Time:732.492s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.564s. + +2/27/22 8:01:08 PM :Debug: Time:732.564s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.628s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.628s. + +2/27/22 8:01:08 PM :Debug: Time:732.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.694s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.694s. + +2/27/22 8:01:08 PM :Debug: Time:732.694s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.758s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.759s. + +2/27/22 8:01:08 PM :Debug: Time:732.759s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.831s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.831s. + +2/27/22 8:01:08 PM :Debug: Time:732.831s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.895s. + +2/27/22 8:01:08 PM :Debug: Time:732.895s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:732.959s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:732.959s. + +2/27/22 8:01:08 PM :Debug: Time:732.959s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:08 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:08 PM :Debug: Time:733.024s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:08 PM :Debug: Time:733.024s. + +2/27/22 8:01:08 PM :Debug: Time:733.024s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.096s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.096s. + +2/27/22 8:01:09 PM :Debug: Time:733.096s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.161s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.161s. + +2/27/22 8:01:09 PM :Debug: Time:733.161s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.226s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.226s. + +2/27/22 8:01:09 PM :Debug: Time:733.226s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:09 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:09 PM :Info: Looks like Speeduino + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.298s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.298s. + +2/27/22 8:01:09 PM :Debug: Time:733.298s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.363s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.363s. + +2/27/22 8:01:09 PM :Debug: Time:733.363s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.433s. + +2/27/22 8:01:09 PM :Debug: Time:733.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.5s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.5s. + +2/27/22 8:01:09 PM :Debug: Time:733.5s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.565s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.565s. + +2/27/22 8:01:09 PM :Debug: Time:733.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.629s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.629s. + +2/27/22 8:01:09 PM :Debug: Time:733.629s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.693s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.693s. + +2/27/22 8:01:09 PM :Debug: Time:733.693s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.757s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.757s. + +2/27/22 8:01:09 PM :Debug: Time:733.757s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.829s. + +2/27/22 8:01:09 PM :Debug: Time:733.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.899s. + +2/27/22 8:01:09 PM :Debug: Time:733.899s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:733.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:733.967s. + +2/27/22 8:01:09 PM :Debug: Time:733.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:09 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:09 PM :Debug: Time:734.032s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:09 PM :Debug: Time:734.032s. + +2/27/22 8:01:09 PM :Debug: Time:734.032s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.102s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.102s. + +2/27/22 8:01:10 PM :Debug: Time:734.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.169s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.169s. + +2/27/22 8:01:10 PM :Debug: Time:734.169s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.232s. + +2/27/22 8:01:10 PM :Debug: Time:734.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.297s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.297s. + +2/27/22 8:01:10 PM :Debug: Time:734.297s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.367s. + +2/27/22 8:01:10 PM :Debug: Time:734.368s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.435s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.435s. + +2/27/22 8:01:10 PM :Debug: Time:734.435s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.499s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.499s. + +2/27/22 8:01:10 PM :Debug: Time:734.499s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.563s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.563s. + +2/27/22 8:01:10 PM :Debug: Time:734.563s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.628s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.628s. + +2/27/22 8:01:10 PM :Debug: Time:734.628s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.693s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.693s. + +2/27/22 8:01:10 PM :Debug: Time:734.693s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.764s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.764s. + +2/27/22 8:01:10 PM :Debug: Time:734.764s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.833s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.833s. + +2/27/22 8:01:10 PM :Debug: Time:734.833s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:10 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:10 PM :Info: Looks like Speeduino + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.901s. + +2/27/22 8:01:10 PM :Debug: Time:734.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:734.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:734.966s. + +2/27/22 8:01:10 PM :Debug: Time:734.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:10 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:10 PM :Debug: Time:735.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:10 PM :Debug: Time:735.03s. + +2/27/22 8:01:10 PM :Debug: Time:735.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.099s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.099s. + +2/27/22 8:01:11 PM :Debug: Time:735.099s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.162s. + +2/27/22 8:01:11 PM :Debug: Time:735.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.232s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.232s. + +2/27/22 8:01:11 PM :Debug: Time:735.232s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.295s. + +2/27/22 8:01:11 PM :Debug: Time:735.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.36s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.36s. + +2/27/22 8:01:11 PM :Debug: Time:735.36s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.425s. + +2/27/22 8:01:11 PM :Debug: Time:735.425s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.498s. + +2/27/22 8:01:11 PM :Debug: Time:735.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.562s. + +2/27/22 8:01:11 PM :Debug: Time:735.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.627s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.627s. + +2/27/22 8:01:11 PM :Debug: Time:735.627s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.693s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.693s. + +2/27/22 8:01:11 PM :Debug: Time:735.693s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.764s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.764s. + +2/27/22 8:01:11 PM :Debug: Time:735.764s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.829s. + +2/27/22 8:01:11 PM :Debug: Time:735.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.893s. + +2/27/22 8:01:11 PM :Debug: Time:735.893s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:735.966s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:735.966s. + +2/27/22 8:01:11 PM :Debug: Time:735.966s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:11 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:11 PM :Debug: Time:736.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:11 PM :Debug: Time:736.03s. + +2/27/22 8:01:11 PM :Debug: Time:736.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.095s. + +2/27/22 8:01:12 PM :Debug: Time:736.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.159s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.159s. + +2/27/22 8:01:12 PM :Debug: Time:736.159s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.223s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.223s. + +2/27/22 8:01:12 PM :Debug: Time:736.223s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.295s. + +2/27/22 8:01:12 PM :Debug: Time:736.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.359s. + +2/27/22 8:01:12 PM :Debug: Time:736.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.425s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.425s. + +2/27/22 8:01:12 PM :Debug: Time:736.425s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.49s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.49s. + +2/27/22 8:01:12 PM :Debug: Time:736.49s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:12 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:12 PM :Info: Looks like Speeduino + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.562s. + +2/27/22 8:01:12 PM :Debug: Time:736.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.633s. + +2/27/22 8:01:12 PM :Debug: Time:736.633s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.7s. + +2/27/22 8:01:12 PM :Debug: Time:736.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.766s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.766s. + +2/27/22 8:01:12 PM :Debug: Time:736.766s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.83s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.83s. + +2/27/22 8:01:12 PM :Debug: Time:736.83s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.895s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.896s. + +2/27/22 8:01:12 PM :Debug: Time:736.896s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:736.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:736.964s. + +2/27/22 8:01:12 PM :Debug: Time:736.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:12 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:12 PM :Debug: Time:737.026s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:12 PM :Debug: Time:737.026s. + +2/27/22 8:01:12 PM :Debug: Time:737.026s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.095s. + +2/27/22 8:01:13 PM :Debug: Time:737.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.158s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.158s. + +2/27/22 8:01:13 PM :Debug: Time:737.158s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.223s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.223s. + +2/27/22 8:01:13 PM :Debug: Time:737.223s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.295s. + +2/27/22 8:01:13 PM :Debug: Time:737.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.36s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.36s. + +2/27/22 8:01:13 PM :Debug: Time:737.36s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.426s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.426s. + +2/27/22 8:01:13 PM :Debug: Time:737.426s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.497s. + +2/27/22 8:01:13 PM :Debug: Time:737.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.562s. + +2/27/22 8:01:13 PM :Debug: Time:737.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.632s. + +2/27/22 8:01:13 PM :Debug: Time:737.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.7s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.7s. + +2/27/22 8:01:13 PM :Debug: Time:737.7s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.762s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.762s. + +2/27/22 8:01:13 PM :Debug: Time:737.762s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.829s. + +2/27/22 8:01:13 PM :Debug: Time:737.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.896s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.896s. + +2/27/22 8:01:13 PM :Debug: Time:737.896s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:737.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:737.965s. + +2/27/22 8:01:13 PM :Debug: Time:737.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:13 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:13 PM :Debug: Time:738.028s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:13 PM :Debug: Time:738.028s. + +2/27/22 8:01:13 PM :Debug: Time:738.028s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.097s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.097s. + +2/27/22 8:01:14 PM :Debug: Time:738.097s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:14 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:14 PM :Info: Looks like Speeduino + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.166s. + +2/27/22 8:01:14 PM :Debug: Time:738.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.234s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.234s. + +2/27/22 8:01:14 PM :Debug: Time:738.234s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.301s. + +2/27/22 8:01:14 PM :Debug: Time:738.301s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.365s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.365s. + +2/27/22 8:01:14 PM :Debug: Time:738.365s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.439s. + +2/27/22 8:01:14 PM :Debug: Time:738.439s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.504s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.504s. + +2/27/22 8:01:14 PM :Debug: Time:738.504s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.564s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.565s. + +2/27/22 8:01:14 PM :Debug: Time:738.565s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.631s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.631s. + +2/27/22 8:01:14 PM :Debug: Time:738.631s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.695s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.695s. + +2/27/22 8:01:14 PM :Debug: Time:738.695s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.76s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.76s. + +2/27/22 8:01:14 PM :Debug: Time:738.76s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.829s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.829s. + +2/27/22 8:01:14 PM :Debug: Time:738.829s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.893s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.893s. + +2/27/22 8:01:14 PM :Debug: Time:738.893s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:738.959s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:738.959s. + +2/27/22 8:01:14 PM :Debug: Time:738.959s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:14 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:14 PM :Debug: Time:739.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:14 PM :Debug: Time:739.029s. + +2/27/22 8:01:14 PM :Debug: Time:739.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.092s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.092s. + +2/27/22 8:01:15 PM :Debug: Time:739.092s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.162s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.162s. + +2/27/22 8:01:15 PM :Debug: Time:739.162s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.244s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.244s. + +2/27/22 8:01:15 PM :Debug: Time:739.244s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.306s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.306s. + +2/27/22 8:01:15 PM :Debug: Time:739.307s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.37s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.37s. + +2/27/22 8:01:15 PM :Debug: Time:739.37s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.439s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.44s. + +2/27/22 8:01:15 PM :Debug: Time:739.44s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.508s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.508s. + +2/27/22 8:01:15 PM :Debug: Time:739.508s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.573s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.573s. + +2/27/22 8:01:15 PM :Debug: Time:739.573s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.641s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.641s. + +2/27/22 8:01:15 PM :Debug: Time:739.641s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.708s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.708s. + +2/27/22 8:01:15 PM :Debug: Time:739.708s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.769s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.769s. + +2/27/22 8:01:15 PM :Debug: Time:739.769s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:15 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:15 PM :Info: Looks like Speeduino + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.837s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.837s. + +2/27/22 8:01:15 PM :Debug: Time:739.837s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.901s. + +2/27/22 8:01:15 PM :Debug: Time:739.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:739.967s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:739.967s. + +2/27/22 8:01:15 PM :Debug: Time:739.967s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:15 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:15 PM :Debug: Time:740.031s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:15 PM :Debug: Time:740.031s. + +2/27/22 8:01:15 PM :Debug: Time:740.031s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.103s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.103s. + +2/27/22 8:01:16 PM :Debug: Time:740.103s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.168s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.168s. + +2/27/22 8:01:16 PM :Debug: Time:740.168s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.239s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.239s. + +2/27/22 8:01:16 PM :Debug: Time:740.239s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.303s. + +2/27/22 8:01:16 PM :Debug: Time:740.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.367s. + +2/27/22 8:01:16 PM :Debug: Time:740.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.432s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.432s. + +2/27/22 8:01:16 PM :Debug: Time:740.432s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.497s. + +2/27/22 8:01:16 PM :Debug: Time:740.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.569s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.569s. + +2/27/22 8:01:16 PM :Debug: Time:740.569s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.634s. + +2/27/22 8:01:16 PM :Debug: Time:740.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.699s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.699s. + +2/27/22 8:01:16 PM :Debug: Time:740.699s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.764s. + +2/27/22 8:01:16 PM :Debug: Time:740.764s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.836s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.836s. + +2/27/22 8:01:16 PM :Debug: Time:740.836s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.901s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.901s. + +2/27/22 8:01:16 PM :Debug: Time:740.901s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:740.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:740.964s. + +2/27/22 8:01:16 PM :Debug: Time:740.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:16 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:16 PM :Debug: Time:741.03s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:16 PM :Debug: Time:741.03s. + +2/27/22 8:01:16 PM :Debug: Time:741.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.095s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.095s. + +2/27/22 8:01:17 PM :Debug: Time:741.095s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.166s. + +2/27/22 8:01:17 PM :Debug: Time:741.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.231s. + +2/27/22 8:01:17 PM :Debug: Time:741.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.303s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.303s. + +2/27/22 8:01:17 PM :Debug: Time:741.303s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.367s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.367s. + +2/27/22 8:01:17 PM :Debug: Time:741.367s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.431s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.431s. + +2/27/22 8:01:17 PM :Debug: Time:741.431s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:17 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:17 PM :Info: Looks like Speeduino + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.496s. + +2/27/22 8:01:17 PM :Debug: Time:741.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.568s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.568s. + +2/27/22 8:01:17 PM :Debug: Time:741.568s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.632s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.632s. + +2/27/22 8:01:17 PM :Debug: Time:741.632s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.697s. + +2/27/22 8:01:17 PM :Debug: Time:741.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.763s. + +2/27/22 8:01:17 PM :Debug: Time:741.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.827s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.827s. + +2/27/22 8:01:17 PM :Debug: Time:741.827s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.899s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.899s. + +2/27/22 8:01:17 PM :Debug: Time:741.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:741.964s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:741.964s. + +2/27/22 8:01:17 PM :Debug: Time:741.964s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:17 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:17 PM :Debug: Time:742.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:17 PM :Debug: Time:742.029s. + +2/27/22 8:01:17 PM :Debug: Time:742.03s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.093s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.093s. + +2/27/22 8:01:18 PM :Debug: Time:742.093s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.166s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.166s. + +2/27/22 8:01:18 PM :Debug: Time:742.166s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.231s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.231s. + +2/27/22 8:01:18 PM :Debug: Time:742.231s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.295s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.295s. + +2/27/22 8:01:18 PM :Debug: Time:742.295s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.359s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.359s. + +2/27/22 8:01:18 PM :Debug: Time:742.359s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.43s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.43s. + +2/27/22 8:01:18 PM :Debug: Time:742.43s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.496s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.496s. + +2/27/22 8:01:18 PM :Debug: Time:742.496s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.56s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.56s. + +2/27/22 8:01:18 PM :Debug: Time:742.56s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.625s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.625s. + +2/27/22 8:01:18 PM :Debug: Time:742.625s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.697s. + +2/27/22 8:01:18 PM :Debug: Time:742.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.763s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.763s. + +2/27/22 8:01:18 PM :Debug: Time:742.763s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.827s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.827s. + +2/27/22 8:01:18 PM :Debug: Time:742.827s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.9s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.9s. + +2/27/22 8:01:18 PM :Debug: Time:742.9s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:742.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:742.965s. + +2/27/22 8:01:18 PM :Debug: Time:742.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:18 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:18 PM :Debug: Time:743.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:18 PM :Debug: Time:743.029s. + +2/27/22 8:01:18 PM :Debug: Time:743.029s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:19 PM :Info: Getting ECU name for signature: 'speeduino DBW 2.0.0' +2/27/22 8:01:19 PM :Info: Looks like Speeduino + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.094s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.094s. + +2/27/22 8:01:19 PM :Debug: Time:743.094s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.16s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.161s. + +2/27/22 8:01:19 PM :Debug: Time:743.161s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.227s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.227s. + +2/27/22 8:01:19 PM :Debug: Time:743.227s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.301s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.301s. + +2/27/22 8:01:19 PM :Debug: Time:743.302s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.369s. + +2/27/22 8:01:19 PM :Debug: Time:743.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.433s. + +2/27/22 8:01:19 PM :Debug: Time:743.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.498s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.498s. + +2/27/22 8:01:19 PM :Debug: Time:743.498s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.562s. + +2/27/22 8:01:19 PM :Debug: Time:743.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.633s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.634s. + +2/27/22 8:01:19 PM :Debug: Time:743.634s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.697s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.697s. + +2/27/22 8:01:19 PM :Debug: Time:743.697s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.77s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.77s. + +2/27/22 8:01:19 PM :Debug: Time:743.77s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.838s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.838s. + +2/27/22 8:01:19 PM :Debug: Time:743.838s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.902s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.902s. + +2/27/22 8:01:19 PM :Debug: Time:743.902s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:743.965s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:743.965s. + +2/27/22 8:01:19 PM :Debug: Time:743.965s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:19 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:19 PM :Debug: Time:744.029s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:19 PM :Debug: Time:744.029s. + +2/27/22 8:01:19 PM :Debug: Time:744.029s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.093s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.093s. + +2/27/22 8:01:20 PM :Debug: Time:744.093s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.165s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.165s. + +2/27/22 8:01:20 PM :Debug: Time:744.165s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.236s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.236s. + +2/27/22 8:01:20 PM :Debug: Time:744.236s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.304s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.304s. + +2/27/22 8:01:20 PM :Debug: Time:744.304s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.369s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.369s. + +2/27/22 8:01:20 PM :Debug: Time:744.369s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.433s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.433s. + +2/27/22 8:01:20 PM :Debug: Time:744.433s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.497s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.497s. + +2/27/22 8:01:20 PM :Debug: Time:744.497s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.562s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.562s. + +2/27/22 8:01:20 PM :Debug: Time:744.562s. . & . . . . . . . . ~ . . . . . + +2/27/22 8:01:20 PM :Debug: Purged 16 orphaned bytes: +2/27/22 8:01:20 PM :Debug: Time:744.634s. 0xF5 0x26 0x0 0x0 0x0 0x0 0x94 0x0 0x0 0x0 0x7E 0x1 0x0 0x0 0x0 0x0 +2/27/22 8:01:20 PM :Debug: Time:744.634s. + +2/27/22 8:01:20 PM :Debug: Time:744.634s. . & . . . . . . . . ~ . . . . . +2/27/22 8:01:20 PM :Info: Re-establishing connection to: RS232: Port:COM8, Baud:115200 +2/27/22 8:01:20 PM :Debug: can not close Port: jssc.SerialPort@1c07f0e, message: Port name - COM8; Method name - setEventsMask(); Exception type - Can't set mask. +2/27/22 8:01:20 PM :Warning: Failed to re-establish connection to: RS232: Port:COM8, Baud:115200 +2/27/22 8:01:20 PM :Info: Connection Check failed, forcing offline. +2/27/22 8:01:21 PM :Debug: controllerOnline = 0.0 +2/27/22 8:01:21 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:01:21 PM :Debug: Went offline +2/27/22 8:01:21 PM :Debug: controllerOnline = 0.0 +2/27/22 8:01:21 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:01:21 PM :Info: Went offline 2 +2/27/22 8:01:21 PM :Debug: Port not valid: Unable to open port: COM8 +Please check your Communications Settings. +2/27/22 8:07:20 PM :Debug: goOffline Starting, Time:0 +2/27/22 8:07:20 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 8:07:20 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 8:07:20 PM :Debug: goOffline Starting, Time:0 +2/27/22 8:07:20 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 8:07:20 PM :Debug: goOffline about to stopProcessing, Time:1 +2/27/22 8:07:20 PM :Debug: goOffline closed port, Time:1 +2/27/22 8:07:20 PM :Debug: goOffline closed port, Time:1 +2/27/22 8:07:20 PM :Debug: set baud to 115200 +2/27/22 8:07:20 PM :Debug: set baud to 115200 +2/27/22 8:07:20 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread58384.68729449401 +2/27/22 8:07:20 PM :Debug: goOffline comm thread stopped, Time:114 +2/27/22 8:07:20 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:07:20 PM :Debug: goOffline comm thread stopped, Time:501 +2/27/22 8:07:20 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:07:23 PM :Debug: set baud to 115200 +2/27/22 8:07:23 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 8:07:23 PM :Info: Comm Read Thread Change! Old Thread:COMM Thread58384.68729449401, new Thread:Thread-260 +2/27/22 8:07:24 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:07:24 PM :Debug: set baud to 115200 +2/27/22 8:07:24 PM :Info: Com Thread created: COMM Thread20170.9940706154 +2/27/22 8:07:25 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread20170.9940706154 +2/27/22 8:07:25 PM :Info: Comm Read Thread Change! Old Thread:Thread-260, new Thread:COMM Thread20170.9940706154 +2/27/22 8:07:26 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:07:26 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:07:26 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:07:26 PM :Debug: controllerOnline = 1.0 +2/27/22 8:07:26 PM :Warning: COM5 port instance already found, trying to close. +2/27/22 8:07:27 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:07:27 PM :Info: Timeout reading page 1, increased blockReadTimeout to 1651, trying once more. +2/27/22 8:07:30 PM :Debug: Read All Data +2/27/22 8:07:30 PM :Debug: result.FAILED: 1 tryCount +2/27/22 8:07:32 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:07:32 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:07:33 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:07:33 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:07:33 PM :Debug: controllerOnline = 1.0 +2/27/22 8:07:33 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 8:07:33 PM :Info: CRC from controller page 1:x4F xF3 x2D xA0 O.-. +2/27/22 8:07:33 PM :Info: Local Data CRC for page 1: xF5 xC2 x75 x09 ..u. +2/27/22 8:07:33 PM :Debug: Read page time: 172ms. +2/27/22 8:07:33 PM :Info: Checksum page 1 data read: x4F xF3 x2D xA0 O.-. +2/27/22 8:07:33 PM :Debug: Read All Data +2/27/22 8:07:33 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:07:33 PM :Debug: DiffTime: 4 ms. +2/27/22 8:07:33 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:07:33 PM :Debug: CRC matches for page 1:x4F xF3 x2D xA0 O.-. +2/27/22 8:07:33 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:07:33 PM :Debug: Read All Data +2/27/22 8:07:33 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:07:33 PM :Debug: DiffTime: 1 ms. +2/27/22 8:07:33 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:07:35 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:07:35 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:35 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileInputStream.open0(Native Method) + at java.io.FileInputStream.open(FileInputStream.java:195) + at java.io.FileInputStream.(FileInputStream.java:138) + at V.s.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) + Error loading .msq: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +Root Problem:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +U.g: Error loading .msq: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +Root Problem:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +Nested Exception - Root cause: +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileInputStream.open0(Native Method) + at java.io.FileInputStream.open(FileInputStream.java:195) + at java.io.FileInputStream.(FileInputStream.java:138) + at V.s.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:07:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:07:37 PM :Debug: Flush lasted: 70ms. +2/27/22 8:07:37 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:07:37 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:07:37 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:07:37 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:07:40 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:07:40 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:40 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileInputStream.open0(Native Method) + at java.io.FileInputStream.open(FileInputStream.java:195) + at java.io.FileInputStream.(FileInputStream.java:138) + at V.s.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) + Error loading .msq: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +Root Problem:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +U.g: Error loading .msq: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) +Root Problem:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +Nested Exception - Root cause: +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileInputStream.open0(Native Method) + at java.io.FileInputStream.open(FileInputStream.java:195) + at java.io.FileInputStream.(FileInputStream.java:138) + at V.s.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.c(Unknown Source) + at aJ.hb.a(Unknown Source) + at aJ.hb.b(Unknown Source) + at aJ.hb.a(Unknown Source) + at F.an.a(Unknown Source) + at F.an.a(Unknown Source) + at F.ax.run(Unknown Source) +2/27/22 8:07:43 PM :Info: dirtyData.size(): 0 +2/27/22 8:07:43 PM :Info: dirtyData.size(): 0 +2/27/22 8:07:43 PM :Debug: Flush lasted: 80ms. +2/27/22 8:07:43 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:07:43 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:07:43 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:07:43 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:07:46 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:07:46 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.g.e(Unknown Source) + at aJ.g.n(Unknown Source) + at aJ.g.x(Unknown Source) + at aJ.cO.windowClosing(Unknown Source) + at java.awt.Window.processWindowEvent(Window.java:2058) + at javax.swing.JFrame.processWindowEvent(JFrame.java:305) + at java.awt.Window.processEvent(Window.java:2017) + at aJ.cO.processEvent(Unknown Source) + at java.awt.Component.dispatchEventImpl(Component.java:4891) + at java.awt.Container.dispatchEventImpl(Container.java:2294) + at java.awt.Window.dispatchEventImpl(Window.java:2750) + at java.awt.Component.dispatchEvent(Component.java:4713) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:758) + at java.awt.EventQueue.access$500(EventQueue.java:97) + at java.awt.EventQueue$3.run(EventQueue.java:709) + at java.awt.EventQueue$3.run(EventQueue.java:703) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:86) + at java.awt.EventQueue$4.run(EventQueue.java:731) + at java.awt.EventQueue$4.run(EventQueue.java:729) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:728) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:201) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:116) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:105) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:101) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:93) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:82) +2/27/22 8:07:46 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq +java.io.FileNotFoundException: C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2\DBW_code_26.10.2021\CurrentTune.msq (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:101) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at V.Y.a(Unknown Source) + at aJ.g.a(Unknown Source) + at aJ.g.e(Unknown Source) + at aJ.g.n(Unknown Source) + at aJ.g.x(Unknown Source) + at aJ.cO.windowClosing(Unknown Source) + at java.awt.Window.processWindowEvent(Window.java:2058) + at javax.swing.JFrame.processWindowEvent(JFrame.java:305) + at java.awt.Window.processEvent(Window.java:2017) + at aJ.cO.processEvent(Unknown Source) + at java.awt.Component.dispatchEventImpl(Component.java:4891) + at java.awt.Container.dispatchEventImpl(Container.java:2294) + at java.awt.Window.dispatchEventImpl(Window.java:2750) + at java.awt.Component.dispatchEvent(Component.java:4713) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:758) + at java.awt.EventQueue.access$500(EventQueue.java:97) + at java.awt.EventQueue$3.run(EventQueue.java:709) + at java.awt.EventQueue$3.run(EventQueue.java:703) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:86) + at java.awt.EventQueue$4.run(EventQueue.java:731) + at java.awt.EventQueue$4.run(EventQueue.java:729) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$JavaSecurityAccessImpl.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:728) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:201) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:116) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:105) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:101) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:93) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:82) +2/27/22 8:07:48 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:07:48 PM :Info: closeApp Called +2/27/22 8:07:48 PM :Debug: TuneLog Editor set text +2/27/22 8:07:49 PM :Info: Finalizing Sensors +Saved user properties successfully +Starting on DESKTOP-MVON5FO +TunerStudio 3.1.08 started on Sun Feb 27 20:11:40 CET 2022 +JRE 1.8.0_66, Windows 10 10.0, x86 +java.library.path=./lib +TunerStudioMS.jar +Look:Metal, ClassName:'javax.swing.plaf.metal.MetalLookAndFeel' +Look:Nimbus, ClassName:'javax.swing.plaf.nimbus.NimbusLookAndFeel' +Look:CDE/Motif, ClassName:'com.sun.java.swing.plaf.motif.MotifLookAndFeel' +Look:Windows, ClassName:'com.sun.java.swing.plaf.windows.WindowsLookAndFeel' +Look:Windows Classic, ClassName:'com.sun.java.swing.plaf.windows.WindowsClassicLookAndFeel' +Look:Night Shade, ClassName:'de.muntjak.tinylookandfeel.TinyLookAndFeel' +Setting Look & Feel to:javax.swing.plaf.metal.MetalLookAndFeel +ScrollBar.width +2/27/22 8:11:40 PM :Debug: no update:defaultFont +2/27/22 8:11:40 PM :Info: Initializing File Dialogs. +2/27/22 8:11:40 PM :Debug: hid: 488.97412 +2/27/22 8:11:41 PM :Info: Loading Language Content. +2/27/22 8:11:43 PM :Debug: Command Non-VolatileBytes for F resolved to: x46 F +2/27/22 8:11:43 PM :Debug: Command Non-VolatileBytes for I resolved to: x49 I +2/27/22 8:11:43 PM :Debug: Command Non-VolatileBytes for f resolved to: x66 f +2/27/22 8:11:43 PM :Info: Initializing Help. +2/27/22 8:11:43 PM :Info: Initializing Edition Features. +2/27/22 8:11:43 PM :Info: Initializing App Events. +2/27/22 8:11:43 PM :Debug: App Name:TunerStudio, appEdition:MS Lite! +2/27/22 8:11:43 PM :Debug: Dummy Function Factory Created. +2/27/22 8:11:43 PM :Info: Initializing User Interface +2/27/22 8:11:45 PM :Info: Loading Font list. +2/27/22 8:11:45 PM :Debug: Time to retreive font name list: 15 ms. +2/27/22 8:11:45 PM :Info: +2/27/22 8:11:45 PM :Info: Initializing UI Components. +2/27/22 8:11:45 PM :Info: Ready +MSmain: No check, last update check=Sun Feb 27 18:14:34 CET 2022 +MSad: No check, last update check=Sun Feb 27 18:14:37 CET 2022 +2/27/22 8:11:55 PM :Debug: Directory Changed: + Old:C:\Users\v0stap\Documents + New:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2 +2/27/22 8:11:58 PM :Debug: Directory Changed: + Old:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2 + New:C:\Users\v0stap\Desktop +2/27/22 8:12:04 PM :Debug: Directory Changed: + Old:C:\Users\v0stap\Desktop + New:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2 +2/27/22 8:12:10 PM :Debug: Directory Changed: + Old:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0\DBW_v2 + New:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0 +2/27/22 8:33:17 PM :Debug: Directory Changed: + Old:C:\Users\v0stap\STM32CubeIDE\workspace_1.8.0 + New:C:\Users\v0stap\Desktop +2/27/22 8:33:19 PM :Debug: File Changed: + Old:null + New:C:\Users\v0stap\Desktop\DBW_code_26.10.2021 +2/27/22 8:33:20 PM :Info: Opening Project ... +2/27/22 8:33:20 PM :Debug: Opening project: C:\Users\v0stap\Desktop\DBW_code_26.10.2021 +2/27/22 8:33:20 PM :Debug: Reading translation file as plain text +2/27/22 8:33:20 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 8:33:20 PM :Debug: Filtered ConfigurationOptionGroup in 2ms. +2/27/22 8:33:20 PM :Info: Supported iniSpecVersion=3.71 +2/27/22 8:33:20 PM :Info: Read file canPcVariables.ini: 1.4447ms +2/27/22 8:33:20 PM :Info: Filtered ini: 0.053299ms +2/27/22 8:33:20 PM :Info: No iniVersion defined +2/27/22 8:33:20 PM :Info: Loading Trigger Wheels +2/27/22 8:33:20 PM :Info: Loaded All known ini sections +2/27/22 8:33:20 PM :Info: Parsed and validated ini "canPcVariables.ini" in : 16ms. +2/27/22 8:33:20 PM :Info: Read file mainController.ini: 1.630301ms +2/27/22 8:33:20 PM :Info: Filtered ini: 0.0995ms +2/27/22 8:33:20 PM :Info: No iniVersion defined +2/27/22 8:33:20 PM :Debug: ini signature: speeduino DBW 2.0.0 +2/27/22 8:33:20 PM :Info: Set Write Blocks on = true +2/27/22 8:33:20 PM :Info: Loading Trigger Wheels +2/27/22 8:33:20 PM :Info: Loading Depricated ini section [UserDefined], use [UiDialogs] +2/27/22 8:33:20 PM :Info: Loaded All known ini sections +2/27/22 8:33:20 PM :Info: Parsed and validated ini "mainController.ini" in : 16ms. +2/27/22 8:33:20 PM :Info: Not Loading default Tools because non are defined for signature: speeduino DBW 2.0.0 +2/27/22 8:33:20 PM :Info: Time to load primary config: 54.0182ms. used cached config: false +SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder". +SLF4J: Defaulting to no-operation (NOP) logger implementation +SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details. +2/27/22 8:33:20 PM :Debug: set baud to 115200 +2/27/22 8:33:20 PM :Debug: Adding Configuration: DBW_code_26.10.2021 +2/27/22 8:33:20 PM :Debug: controllerOnline = 0.0 +2/27/22 8:33:20 PM :Info: No secl OutputChannel, och sync monitor disabled. +2/27/22 8:33:20 PM :Debug: Fill Constants: 16 +2/27/22 8:33:20 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 8:33:20 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq +2/27/22 8:33:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:20 PM :Debug: Flush lasted: 78ms. +2/27/22 8:33:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:20 PM :Debug: Flush lasted: 79ms. +2/27/22 8:33:20 PM :Debug: Skip Burn, last write page: -2 +2/27/22 8:33:20 PM :Info: !!! Loaded config in 303 +2/27/22 8:33:20 PM :Info: !!! Activated Project 443 +2/27/22 8:33:20 PM :Info: Opening Gauge Cluster.. +2/27/22 8:33:20 PM :Debug: High Speed Paint: true +2/27/22 8:33:20 PM :Info: +2/27/22 8:33:20 PM :Info: Com Thread created: COMM Thread75178.9368412808 +2/27/22 8:33:20 PM :Info: endModalBlock called, but Root Pane is not a ProgressPane. +2/27/22 8:33:20 PM :Debug: !!! Opened Dash 662 +2/27/22 8:33:20 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread75178.9368412808 +2/27/22 8:33:20 PM :Info: DBW_code_26.10.2021 Ready +2/27/22 8:33:20 PM :Debug: Port not valid: Unable to open port: /dev/ttyUSB0 +Please check your Communications Settings. +2/27/22 8:33:20 PM :Debug: Tuning View Files loaded in 0.2081ms. +2/27/22 8:33:21 PM :Info: No Persistor set, not activating persisted triggers. +2/27/22 8:33:25 PM :Debug: goOffline Starting, Time:0 +2/27/22 8:33:25 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 8:33:25 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 8:33:25 PM :Debug: goOffline closed port, Time:0 +2/27/22 8:33:25 PM :Debug: goOffline Starting, Time:0 +2/27/22 8:33:25 PM :Info: Deactivated Turbo Baud, goOffline +2/27/22 8:33:25 PM :Debug: goOffline about to stopProcessing, Time:0 +2/27/22 8:33:25 PM :Debug: goOffline closed port, Time:0 +2/27/22 8:33:25 PM :Debug: set baud to 115200 +2/27/22 8:33:25 PM :Debug: set baud to 115200 +2/27/22 8:33:25 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread75178.9368412808 +2/27/22 8:33:25 PM :Debug: goOffline comm thread stopped, Time:312 +2/27/22 8:33:25 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:33:25 PM :Debug: goOffline comm thread stopped, Time:504 +2/27/22 8:33:25 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:33:31 PM :Debug: set baud to 115200 +2/27/22 8:33:31 PM :Debug: Received Instruction: Test Connection, Page: 0 +2/27/22 8:33:31 PM :Info: Comm Read Thread Change! Old Thread:null, new Thread:Thread-21 +2/27/22 8:33:31 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:33:32 PM :Debug: set baud to 115200 +2/27/22 8:33:32 PM :Info: Com Thread created: COMM Thread23701.072868971616 +2/27/22 8:33:32 PM :Info: Comm Manager for DBW_code_26.10.2021 Started, thread ID: COMM Thread23701.072868971616 +2/27/22 8:33:32 PM :Info: Comm Read Thread Change! Old Thread:Thread-21, new Thread:COMM Thread23701.072868971616 +2/27/22 8:33:33 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:33:33 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:33:33 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:33:33 PM :Debug: controllerOnline = 1.0 +2/27/22 8:33:33 PM :Warning: COM5 port instance already found, trying to close. +2/27/22 8:33:34 PM :Debug: Read from RS232: Port:COM5, Baud:115200, signature:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:33:34 PM :Info: Timeout reading page 1, increased blockReadTimeout to 651, trying once more. +2/27/22 8:33:36 PM :Debug: Read All Data +2/27/22 8:33:36 PM :Debug: result.FAILED: 1 tryCount +2/27/22 8:33:37 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:33:37 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:33:37 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:33:37 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:33:37 PM :Debug: controllerOnline = 1.0 +2/27/22 8:33:37 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 8:33:37 PM :Info: CRC from controller page 1:x4F xF3 x2D xA0 O.-. +2/27/22 8:33:37 PM :Info: Local Data CRC for page 1: xF6 xEF xD3 x26 ...& +2/27/22 8:33:37 PM :Debug: Read page time: 172ms. +2/27/22 8:33:37 PM :Info: Checksum page 1 data read: x4F xF3 x2D xA0 O.-. +2/27/22 8:33:37 PM :Debug: Read All Data +2/27/22 8:33:37 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:33:37 PM :Debug: DiffTime: 6 ms. +2/27/22 8:33:37 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:33:38 PM :Debug: CRC matches for page 1:x4F xF3 x2D xA0 O.-. +2/27/22 8:33:38 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:33:38 PM :Debug: Read All Data +2/27/22 8:33:38 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:33:38 PM :Debug: DiffTime: 1 ms. +2/27/22 8:33:38 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:33:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:33:39 PM :Info: Time to save msq: 28.3154 +2/27/22 8:33:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:33:39 PM :Info: dirtyData.size(): 4 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:39 PM :Debug: Flush lasted: 95ms. +2/27/22 8:33:39 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:33:39 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:33:39 PM :Info: Queueing burn to page:1 +2/27/22 8:33:39 PM :Info: Sending, 0 bytes. +2/27/22 8:33:39 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/27/22 8:33:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:39 PM :Debug: Flush lasted: 0ms. +2/27/22 8:33:39 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:33:39 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:33:39 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:33:39 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:33:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:33:41 PM :Info: Time to save msq: 6.8554 +2/27/22 8:33:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:33:41 PM :Info: dirtyData.size(): 4 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:41 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:33:42 PM :Debug: removed expired instruction +2/27/22 8:33:42 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:42 PM :Debug: Flush lasted: 55ms. +2/27/22 8:33:42 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:33:42 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:33:42 PM :Info: Queueing burn to page:1 +2/27/22 8:33:42 PM :Info: Sending, 0 bytes. +2/27/22 8:33:42 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/27/22 8:33:42 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:42 PM :Info: dirtyData.size(): 0 +2/27/22 8:33:42 PM :Debug: Flush lasted: 0ms. +2/27/22 8:33:42 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:33:42 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:33:42 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:33:42 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:33:42 PM :Debug: Burn time:256ms. +2/27/22 8:33:42 PM :Debug: burned page 1 +2/27/22 8:33:42 PM :Debug: Queued Write instructions:828 to page(s) 1, +2/27/22 8:33:42 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 8:33:42 PM :Info: CRC from controller page 1:xB7 x71 xC1 x23 .q.# +2/27/22 8:33:42 PM :Info: Local Data CRC for page 1: xF6 xEF xD3 x26 ...& +2/27/22 8:33:42 PM :Info: Retrying CRC call to see if it agrees after read: +2/27/22 8:33:42 PM :Debug: CRC matches for page 1:xB7 x71 xC1 x23 .q.# +2/27/22 8:33:43 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/27/22 8:33:43 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:33:43 PM :Debug: CRC matches for page 1:xB7 x71 xC1 x23 .q.# +2/27/22 8:33:43 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:33:43 PM :Debug: Read All Data +2/27/22 8:33:43 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:33:43 PM :Debug: DiffTime: 0 ms. +2/27/22 8:33:43 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:34:05 PM :Debug: Burn time:257ms. +2/27/22 8:34:05 PM :Debug: burned page 1 +2/27/22 8:34:05 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:34:05 PM :Debug: CRC matches for page 1:xF6 xEF xD3 x26 ...& +2/27/22 8:34:05 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:34:05 PM :Debug: CRC matches for page 1:xF6 xEF xD3 x26 ...& +2/27/22 8:34:05 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:34:05 PM :Debug: Read All Data +2/27/22 8:34:05 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:34:05 PM :Debug: DiffTime: 0 ms. +2/27/22 8:34:05 PM :Debug: Time to get Panels = 0ms. +2/27/22 8:34:06 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:34:06 PM :Info: Time to save msq: 2.5214 +2/27/22 8:34:06 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:35:20 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:35:21 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:35:21 PM :Debug: controllerOnline = 0.0 +2/27/22 8:35:21 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:35:21 PM :Debug: Went offline +2/27/22 8:35:21 PM :Debug: controllerOnline = 0.0 +2/27/22 8:35:21 PM :Debug: Deactivated fast paint Main Dashboard +2/27/22 8:35:21 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:35:21 PM :Info: Went offline 2 + +2/27/22 8:36:13 PM :Debug: Purged 2 orphaned bytes: +2/27/22 8:36:13 PM :Debug: Time:173.496s. 0xFF 0xFF +2/27/22 8:36:13 PM :Debug: Time:173.496s. + +2/27/22 8:36:13 PM :Debug: Time:173.496s. . . + +2/27/22 8:36:14 PM :Debug: Purged 1 orphaned bytes: +2/27/22 8:36:14 PM :Debug: Time:174.475s. 0xFF +2/27/22 8:36:14 PM :Debug: Time:174.475s. + +2/27/22 8:36:14 PM :Debug: Time:174.475s. . +2/27/22 8:36:15 PM :Warning: Unsupported Controller Firmware: r?? + +2/27/22 8:39:30 PM :Debug: Purged 1 orphaned bytes: +2/27/22 8:39:30 PM :Debug: Time:370.207s. 0xFF +2/27/22 8:39:30 PM :Debug: Time:370.207s. + +2/27/22 8:39:30 PM :Debug: Time:370.207s. . +2/27/22 8:46:16 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:46:16 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:46:16 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:46:16 PM :Debug: controllerOnline = 1.0 +2/27/22 8:46:16 PM :Debug: CRC matches for page 1:xF6 xEF xD3 x26 ...& +2/27/22 8:46:16 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:46:16 PM :Debug: Read All Data +2/27/22 8:46:16 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:46:16 PM :Debug: DiffTime: 0 ms. +2/27/22 8:46:44 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:46:44 PM :Info: Initiating read page 1 : 2:832 +2/27/22 8:46:44 PM :Debug: CRC matches for page 1:xF6 xEF xD3 x26 ...& +2/27/22 8:46:44 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:47:02 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:02 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:48 PM :Debug: Received Instruction: , Page: 0 +2/27/22 8:47:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:47:50 PM :Info: dirtyData.size(): 0 +2/27/22 8:47:50 PM :Info: dirtyData.size(): 0 +2/27/22 8:47:50 PM :Debug: Flush lasted: 71ms. +2/27/22 8:47:50 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:47:50 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:47:50 PM :Info: Queueing burn to page:1 +2/27/22 8:47:50 PM :Debug: Burn time:257ms. +2/27/22 8:47:50 PM :Debug: burned page 1 +2/27/22 8:47:50 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:47:50 PM :Debug: CRC matches for page 1:xFB xAB x28 x16 ..(. +2/27/22 8:47:52 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:47:52 PM :Info: Time to save msq: 9.8616 +2/27/22 8:47:52 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:48:17 PM :Debug: Received Instruction: , Page: 0 +2/27/22 8:48:22 PM :Info: dirtyData.size(): 0 +2/27/22 8:48:22 PM :Info: dirtyData.size(): 0 +2/27/22 8:48:22 PM :Debug: Flush lasted: 89ms. +2/27/22 8:48:22 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:48:22 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:48:22 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:48:22 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:48:22 PM :Info: dirtyData.size(): 0 +2/27/22 8:48:22 PM :Info: dirtyData.size(): 0 +2/27/22 8:48:22 PM :Debug: Flush lasted: 89ms. +2/27/22 8:48:22 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:48:22 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:48:22 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:48:22 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:48:43 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:48:43 PM :Info: Initiating read page 1 : 14:834 +2/27/22 8:48:43 PM :Debug: CRC matches for page 1:xFB xAB x28 x16 ..(. +2/27/22 8:48:43 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:49:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:29 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:29 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:50 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:49:56 PM :Debug: Received Instruction: , Page: 0 +2/27/22 8:49:56 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:50:23 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:50:23 PM :Debug: Received Instruction: , Page: 0 +2/27/22 8:50:49 PM :Info: dirtyData.size(): 0 +2/27/22 8:50:49 PM :Info: dirtyData.size(): 0 +2/27/22 8:50:49 PM :Debug: Flush lasted: 83ms. +2/27/22 8:50:49 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:50:49 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:50:49 PM :Info: Queueing burn to page:1 +2/27/22 8:50:49 PM :Debug: Burn time:257ms. +2/27/22 8:50:49 PM :Debug: burned page 1 +2/27/22 8:50:49 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:50:49 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:50:51 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:50:51 PM :Info: Time to save msq: 8.285 +2/27/22 8:50:51 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:50:51 PM :Info: dirtyData.size(): 0 +2/27/22 8:50:51 PM :Info: dirtyData.size(): 0 +2/27/22 8:50:51 PM :Debug: Flush lasted: 83ms. +2/27/22 8:50:51 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:50:51 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:50:51 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:50:51 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:51:03 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:51:03 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:51:03 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:51:03 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:51:17 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:17 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:17 PM :Debug: Flush lasted: 84ms. +2/27/22 8:51:17 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:51:17 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:17 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:51:17 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:51:18 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:18 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:18 PM :Debug: Flush lasted: 70ms. +2/27/22 8:51:18 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:51:18 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:18 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:51:18 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:51:26 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:51:26 PM :Info: Initiating read page 1 : 826:2 +2/27/22 8:51:27 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:51:27 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:51:34 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:34 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:34 PM :Debug: Flush lasted: 71ms. +2/27/22 8:51:34 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:51:34 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:34 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:51:34 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:51:36 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:51:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:37 PM :Debug: Flush lasted: 78ms. +2/27/22 8:51:37 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:51:37 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:37 PM :Info: Queueing burn to page:1 +2/27/22 8:51:37 PM :Debug: Burn time:256ms. +2/27/22 8:51:37 PM :Debug: burned page 1 +2/27/22 8:51:37 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:51:37 PM :Debug: CRC matches for page 1:xA1 x57 x8E xFB .W.. +2/27/22 8:51:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:51:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:51:39 PM :Info: Time to save msq: 4.5899 +2/27/22 8:51:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:51:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:39 PM :Debug: Flush lasted: 83ms. +2/27/22 8:51:39 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:51:39 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:39 PM :Info: Queueing burn to page:1 +2/27/22 8:51:40 PM :Debug: Burn time:256ms. +2/27/22 8:51:40 PM :Debug: burned page 1 +2/27/22 8:51:40 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:51:40 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:51:41 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:41 PM :Info: dirtyData.size(): 0 +2/27/22 8:51:41 PM :Debug: Flush lasted: 83ms. +2/27/22 8:51:41 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:51:41 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:51:41 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:51:41 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:51:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:51:41 PM :Info: Time to save msq: 6.6944 +2/27/22 8:51:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:51:50 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:52:04 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:52:29 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:52:29 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:52:30 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:52:30 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:52:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:52:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:52:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:52:37 PM :Info: dirtyData.size(): 0 +2/27/22 8:52:37 PM :Debug: Flush lasted: 70ms. +2/27/22 8:52:37 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:52:37 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:52:37 PM :Info: Queueing burn to page:1 +2/27/22 8:52:37 PM :Debug: Burn time:257ms. +2/27/22 8:52:37 PM :Debug: burned page 1 +2/27/22 8:52:37 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:52:37 PM :Debug: CRC matches for page 1:xF0 xFF xE4 x68 ...h +2/27/22 8:52:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:52:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:52:39 PM :Info: Time to save msq: 2.6294 +2/27/22 8:52:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:52:39 PM :Info: dirtyData.size(): 0 +2/27/22 8:52:39 PM :Debug: Flush lasted: 83ms. +2/27/22 8:52:39 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:52:39 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:52:39 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:52:39 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:52:41 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:52:50 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:52:50 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:52:50 PM :Debug: CRC matches for page 1:xF0 xFF xE4 x68 ...h +2/27/22 8:52:50 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:53:00 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:53:00 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:53:02 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:02 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:02 PM :Debug: Flush lasted: 84ms. +2/27/22 8:53:02 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:53:02 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:53:02 PM :Info: Queueing burn to page:1 +2/27/22 8:53:02 PM :Debug: Burn time:257ms. +2/27/22 8:53:02 PM :Debug: burned page 1 +2/27/22 8:53:02 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:53:02 PM :Debug: CRC matches for page 1:xE3 x4C xFA x6D .L.m +2/27/22 8:53:03 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:03 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:03 PM :Debug: Flush lasted: 83ms. +2/27/22 8:53:03 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:53:03 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:53:03 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:53:03 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:53:04 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:53:04 PM :Info: Time to save msq: 3.9071 +2/27/22 8:53:04 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:53:09 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:53:16 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:53:16 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:53:16 PM :Debug: CRC matches for page 1:xE3 x4C xFA x6D .L.m +2/27/22 8:53:16 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:53:26 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:53:26 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:53:26 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:26 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:26 PM :Debug: Flush lasted: 71ms. +2/27/22 8:53:26 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:53:26 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:53:26 PM :Info: Queueing burn to page:1 +2/27/22 8:53:27 PM :Debug: Burn time:256ms. +2/27/22 8:53:27 PM :Debug: burned page 1 +2/27/22 8:53:27 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:53:27 PM :Debug: CRC matches for page 1:x55 xC4 x27 x5A U.'Z +2/27/22 8:53:27 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:27 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:27 PM :Debug: Flush lasted: 84ms. +2/27/22 8:53:27 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:53:27 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:53:27 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:53:27 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:53:28 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:28 PM :Info: dirtyData.size(): 0 +2/27/22 8:53:28 PM :Debug: Flush lasted: 83ms. +2/27/22 8:53:28 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:53:28 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:53:28 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:53:28 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:53:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:53:28 PM :Info: Time to save msq: 15.7559 +2/27/22 8:53:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:53:31 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:56:07 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:56:18 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:57:33 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:57:46 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:58:05 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:58:05 PM :Info: Initiating read page 1 : 14:834 +2/27/22 8:58:05 PM :Debug: CRC matches for page 1:x55 xC4 x27 x5A U.'Z +2/27/22 8:58:05 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:58:08 PM :Info: dirtyData.size(): 0 +2/27/22 8:58:08 PM :Info: dirtyData.size(): 0 +2/27/22 8:58:08 PM :Debug: Flush lasted: 70ms. +2/27/22 8:58:08 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:58:08 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:58:08 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:58:08 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:58:12 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:58:12 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:58:12 PM :Debug: CRC matches for page 1:x55 xC4 x27 x5A U.'Z +2/27/22 8:58:12 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:58:20 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:58:20 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:58:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:58:20 PM :Info: dirtyData.size(): 0 +2/27/22 8:58:20 PM :Debug: Flush lasted: 70ms. +2/27/22 8:58:20 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:58:20 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:58:20 PM :Info: Queueing burn to page:1 +2/27/22 8:58:21 PM :Debug: Burn time:256ms. +2/27/22 8:58:21 PM :Debug: burned page 1 +2/27/22 8:58:21 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:58:21 PM :Debug: CRC matches for page 1:x27 xA7 x85 xA2 '... +2/27/22 8:58:22 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:58:22 PM :Info: Time to save msq: 5.0614 +2/27/22 8:58:22 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:58:25 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:59:04 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:59:05 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 8:59:06 PM :Debug: controllerOnline = 0.0 +2/27/22 8:59:06 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:59:06 PM :Debug: Went offline +2/27/22 8:59:06 PM :Debug: controllerOnline = 0.0 +2/27/22 8:59:06 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:59:06 PM :Info: Went offline 2 +2/27/22 8:59:07 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 8:59:08 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 8:59:08 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 8:59:08 PM :Debug: controllerOnline = 1.0 +2/27/22 8:59:08 PM :Debug: CRC matches for page 1:x27 xA7 x85 xA2 '... +2/27/22 8:59:08 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 8:59:08 PM :Debug: Read All Data +2/27/22 8:59:08 PM :Debug: isBlank Time: 0 ms. +2/27/22 8:59:08 PM :Debug: DiffTime: 0 ms. +2/27/22 8:59:08 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:08 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:08 PM :Debug: Flush lasted: 83ms. +2/27/22 8:59:08 PM :Debug: Skip Burn, last write page: -2 +2/27/22 8:59:46 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 8:59:46 PM :Info: Initiating read page 1 : 26:824 +2/27/22 8:59:46 PM :Debug: CRC matches for page 1:x27 xA7 x85 xA2 '... +2/27/22 8:59:46 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 8:59:52 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:59:52 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:52 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 8:59:52 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:52 PM :Debug: Flush lasted: 42ms. +2/27/22 8:59:52 PM :Debug: Burn Page anonymous: 1 +2/27/22 8:59:52 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:59:52 PM :Info: Queueing burn to page:1 +2/27/22 8:59:52 PM :Debug: Burn time:258ms. +2/27/22 8:59:52 PM :Debug: burned page 1 +2/27/22 8:59:52 PM :Debug: No Remaining Queue Write instructions +2/27/22 8:59:53 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 8:59:53 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:53 PM :Info: dirtyData.size(): 0 +2/27/22 8:59:53 PM :Debug: Flush lasted: 84ms. +2/27/22 8:59:53 PM :Debug: Burn Page anonymous: -1 +2/27/22 8:59:53 PM :Debug: Received Instruction: , Page: 1 +2/27/22 8:59:53 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 8:59:53 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 8:59:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 8:59:54 PM :Info: Time to save msq: 5.1068 +2/27/22 8:59:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 8:59:56 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:00:11 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:00:11 PM :Info: Initiating read page 1 : 28:64 +2/27/22 9:00:11 PM :Debug: CRC matches for page 1:x99 x21 x90 xFA .!.. +2/27/22 9:00:11 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:00:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:00:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:00:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:00:34 PM :Info: dirtyData.size(): 0 +2/27/22 9:00:34 PM :Info: dirtyData.size(): 0 +2/27/22 9:00:34 PM :Debug: Flush lasted: 70ms. +2/27/22 9:00:34 PM :Debug: Burn Page anonymous: 1 +2/27/22 9:00:34 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:00:34 PM :Info: Queueing burn to page:1 +2/27/22 9:00:34 PM :Debug: Burn time:257ms. +2/27/22 9:00:34 PM :Debug: burned page 1 +2/27/22 9:00:34 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:00:34 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:00:35 PM :Info: dirtyData.size(): 0 +2/27/22 9:00:35 PM :Info: dirtyData.size(): 0 +2/27/22 9:00:35 PM :Debug: Flush lasted: 70ms. +2/27/22 9:00:35 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:00:35 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:00:35 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:00:35 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:00:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 9:00:36 PM :Info: Time to save msq: 3.7381 +2/27/22 9:00:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 9:00:37 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:01:00 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:01:17 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:01:25 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:01:25 PM :Info: Initiating read page 1 : 26:824 +2/27/22 9:01:26 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:01:26 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:01:31 PM :Info: dirtyData.size(): 0 +2/27/22 9:01:31 PM :Info: dirtyData.size(): 0 +2/27/22 9:01:31 PM :Debug: Flush lasted: 83ms. +2/27/22 9:01:31 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:01:31 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:01:31 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:01:31 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:01:41 PM :Info: dirtyData.size(): 0 +2/27/22 9:01:41 PM :Info: dirtyData.size(): 0 +2/27/22 9:01:41 PM :Debug: Flush lasted: 83ms. +2/27/22 9:01:41 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:01:41 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:01:41 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:01:42 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:01:43 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:02:10 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:02:10 PM :Info: Initiating read page 1 : 26:824 +2/27/22 9:02:11 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:02:11 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:02:18 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:18 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:18 PM :Debug: Flush lasted: 71ms. +2/27/22 9:02:18 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:02:18 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:02:18 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:02:18 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:02:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:19 PM :Debug: Flush lasted: 90ms. +2/27/22 9:02:19 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:02:19 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:02:19 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:02:19 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:02:26 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:02:26 PM :Info: Initiating read page 1 : 14:834 +2/27/22 9:02:26 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:02:26 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:02:29 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:02:31 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:02:33 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:02:35 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:02:40 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:02:41 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:02:42 PM :Debug: controllerOnline = 0.0 +2/27/22 9:02:42 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:02:42 PM :Debug: Went offline +2/27/22 9:02:42 PM :Debug: controllerOnline = 0.0 +2/27/22 9:02:42 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:02:42 PM :Info: Went offline 2 +2/27/22 9:02:51 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/27/22 9:02:52 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/27/22 9:02:52 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 9:02:52 PM :Debug: controllerOnline = 1.0 +2/27/22 9:02:52 PM :Info: CRC Mismatch, will need to refresh page from controller +2/27/22 9:02:52 PM :Info: CRC from controller page 1:xAB x89 x70 xB4 ..p. +2/27/22 9:02:52 PM :Info: Local Data CRC for page 1: x23 x8A x05 xF4 #... +2/27/22 9:02:52 PM :Debug: Read page time: 172ms. +2/27/22 9:02:52 PM :Info: Checksum page 1 data read: xAB x89 x70 xB4 ..p. +2/27/22 9:02:52 PM :Debug: Read All Data +2/27/22 9:02:52 PM :Debug: isBlank Time: 0 ms. +2/27/22 9:02:52 PM :Debug: DiffTime: 3 ms. +2/27/22 9:02:52 PM :Debug: Time to get Panels = 0ms. +2/27/22 9:02:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 9:02:54 PM :Info: Time to save msq: 5.9759 +2/27/22 9:02:54 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 9:02:54 PM :Info: dirtyData.size(): 2 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:02:54 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:54 PM :Debug: Flush lasted: 17ms. +2/27/22 9:02:54 PM :Debug: Burn Page anonymous: 1 +2/27/22 9:02:54 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:02:54 PM :Info: Queueing burn to page:1 +2/27/22 9:02:54 PM :Info: Sending, 0 bytes. +2/27/22 9:02:54 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/27/22 9:02:54 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:54 PM :Info: dirtyData.size(): 0 +2/27/22 9:02:54 PM :Debug: Flush lasted: 71ms. +2/27/22 9:02:54 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:02:54 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:02:54 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:02:54 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/27/22 9:02:54 PM :Debug: Burn time:258ms. +2/27/22 9:02:54 PM :Debug: burned page 1 +2/27/22 9:02:54 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:02:54 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:02:54 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:02:54 PM :Debug: CRC matches for page 1:x23 x8A x05 xF4 #... +2/27/22 9:02:54 PM :Info: CrC matched skipped controller read on page:1 +2/27/22 9:02:54 PM :Debug: Read All Data +2/27/22 9:02:54 PM :Debug: isBlank Time: 0 ms. +2/27/22 9:02:54 PM :Debug: DiffTime: 1 ms. +2/27/22 9:02:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 9:02:55 PM :Info: Time to save msq: 4.6597 +2/27/22 9:02:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 9:03:01 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:03:03 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:03:04 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:03:45 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:03:45 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:04:10 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:04:17 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:04:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:04:18 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:18 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:18 PM :Debug: Flush lasted: 75ms. +2/27/22 9:04:18 PM :Debug: Burn Page anonymous: 1 +2/27/22 9:04:18 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:04:18 PM :Info: Queueing burn to page:1 +2/27/22 9:04:18 PM :Debug: Burn time:257ms. +2/27/22 9:04:18 PM :Debug: burned page 1 +2/27/22 9:04:18 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:04:19 PM :Debug: CRC matches for page 1:xAC xA6 x16 xBE .... +2/27/22 9:04:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 9:04:20 PM :Info: Time to save msq: 3.958 +2/27/22 9:04:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 9:04:36 PM :Debug: Received Instruction: , Page: 0 +2/27/22 9:04:40 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:40 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:40 PM :Debug: Flush lasted: 79ms. +2/27/22 9:04:40 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:04:40 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:04:40 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:04:40 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:04:41 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:41 PM :Info: dirtyData.size(): 0 +2/27/22 9:04:41 PM :Debug: Flush lasted: 79ms. +2/27/22 9:04:41 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:04:41 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:04:41 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:04:41 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:05:14 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/27/22 9:05:38 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:05:38 PM :Info: Initiating read page 1 : 724:64 +2/27/22 9:05:38 PM :Debug: CRC matches for page 1:xAC xA6 x16 xBE .... +2/27/22 9:05:38 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:05:45 PM :Info: dirtyData.size(): 0 +2/27/22 9:05:45 PM :Info: dirtyData.size(): 0 +2/27/22 9:05:45 PM :Debug: Flush lasted: 84ms. +2/27/22 9:05:45 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:05:45 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:05:45 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:05:45 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:05:52 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/27/22 9:05:52 PM :Info: Initiating read page 1 : 28:64 +2/27/22 9:05:52 PM :Debug: CRC matches for page 1:xAC xA6 x16 xBE .... +2/27/22 9:05:52 PM :Info: CrC matched skipped controller read on page:0 +2/27/22 9:05:56 PM :Debug: Clearing selection. Vertical: false +2/27/22 9:06:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:06:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:06:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/27/22 9:06:16 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:16 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:16 PM :Debug: Flush lasted: 70ms. +2/27/22 9:06:16 PM :Debug: Burn Page anonymous: 1 +2/27/22 9:06:16 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:06:16 PM :Info: Queueing burn to page:1 +2/27/22 9:06:17 PM :Debug: Burn time:257ms. +2/27/22 9:06:17 PM :Debug: burned page 1 +2/27/22 9:06:17 PM :Debug: No Remaining Queue Write instructions +2/27/22 9:06:17 PM :Debug: CRC matches for page 1:x0F x52 xE9 x1A .R.. +2/27/22 9:06:19 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/27/22 9:06:19 PM :Info: Time to save msq: 6.7018 +2/27/22 9:06:19 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/27/22 9:06:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:19 PM :Debug: Flush lasted: 70ms. +2/27/22 9:06:19 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:06:19 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:06:19 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:06:19 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/27/22 9:06:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:19 PM :Info: dirtyData.size(): 0 +2/27/22 9:06:19 PM :Debug: Flush lasted: 70ms. +2/27/22 9:06:19 PM :Debug: Burn Page anonymous: -1 +2/27/22 9:06:19 PM :Debug: Received Instruction: , Page: 1 +2/27/22 9:06:19 PM :Info: skip burn to page:1, lastWritePage = -2 +2/27/22 9:06:19 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 5:56:54 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:56:54 PM :Debug: can not close Port: jssc.SerialPort@180fbfb, message: Port name - COM5; Method name - setEventsMask(); Exception type - Can't set mask. +2/28/22 5:56:54 PM :Warning: Failed to re-establish connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:56:54 PM :Info: Connection Check failed, forcing offline. +2/28/22 5:56:54 PM :Debug: controllerOnline = 0.0 +2/28/22 5:56:54 PM :Debug: No Remaining Queue Write instructions +2/28/22 5:56:54 PM :Debug: Went offline +2/28/22 5:56:54 PM :Debug: controllerOnline = 0.0 +2/28/22 5:56:54 PM :Debug: No Remaining Queue Write instructions +2/28/22 5:56:54 PM :Info: Went offline 2 +2/28/22 5:56:55 PM :Debug: Port not valid: Unable to open port: COM5 +Please check your Communications Settings. +2/28/22 5:59:19 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 5:59:20 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 5:59:20 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 5:59:20 PM :Debug: controllerOnline = 1.0 +2/28/22 5:59:20 PM :Debug: CRC matches for page 1:x0F x52 xE9 x1A .R.. +2/28/22 5:59:20 PM :Info: CrC matched skipped controller read on page:1 +2/28/22 5:59:20 PM :Debug: Read All Data +2/28/22 5:59:20 PM :Debug: isBlank Time: 0 ms. +2/28/22 5:59:20 PM :Debug: DiffTime: 2 ms. +2/28/22 5:59:24 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:59:25 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:59:25 PM :Debug: controllerOnline = 0.0 +2/28/22 5:59:25 PM :Debug: No Remaining Queue Write instructions +2/28/22 5:59:25 PM :Debug: Went offline +2/28/22 5:59:25 PM :Debug: controllerOnline = 0.0 +2/28/22 5:59:26 PM :Debug: No Remaining Queue Write instructions +2/28/22 5:59:26 PM :Info: Went offline 2 +2/28/22 5:59:34 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 5:59:34 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 5:59:34 PM :Debug: controllerOnline = 1.0 +2/28/22 5:59:49 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:59:51 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 5:59:53 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:00:03 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:00:03 PM :Info: Initiating read page 1 : 2:832 +2/28/22 6:00:04 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:00:04 PM :Info: CRC from controller page 1:x4F xF3 x2D xA0 O.-. +2/28/22 6:00:04 PM :Info: Local Data CRC for page 1: x0F x52 xE9 x1A .R.. +2/28/22 6:00:04 PM :Info: Checksum of data read: x01 x53 x4F xEA .SO. +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:32 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:00:32 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:22:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:22:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:23:04 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:23:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:23:07 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:07 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:07 PM :Debug: Flush lasted: 82ms. +2/28/22 6:23:07 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:23:07 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:23:07 PM :Info: Queueing burn to page:1 +2/28/22 6:23:07 PM :Debug: Burn time:257ms. +2/28/22 6:23:07 PM :Debug: burned page 1 +2/28/22 6:23:07 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:23:07 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:23:07 PM :Info: CRC from controller page 1:xD1 xD3 x26 x2A ..&* +2/28/22 6:23:07 PM :Info: Local Data CRC for page 1: x6B x5A x2B xF4 kZ+. +2/28/22 6:23:07 PM :Info: Retrying CRC call to see if it agrees after read: +2/28/22 6:23:07 PM :Debug: CRC matches for page 1:xD1 xD3 x26 x2A ..&* +2/28/22 6:23:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:23:09 PM :Info: Time to save msq: 9.132 +2/28/22 6:23:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:23:18 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/28/22 6:23:29 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:23:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:23:31 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:31 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:31 PM :Debug: Flush lasted: 90ms. +2/28/22 6:23:31 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:23:31 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:23:31 PM :Info: Queueing burn to page:1 +2/28/22 6:23:31 PM :Debug: Burn time:256ms. +2/28/22 6:23:31 PM :Debug: burned page 1 +2/28/22 6:23:31 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:23:31 PM :Debug: CRC matches for page 1:x10 x41 xBF xEE .A.. +2/28/22 6:23:33 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:23:33 PM :Info: Time to save msq: 6.2948 +2/28/22 6:23:33 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:23:35 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:35 PM :Info: dirtyData.size(): 0 +2/28/22 6:23:35 PM :Debug: Flush lasted: 83ms. +2/28/22 6:23:35 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:23:35 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:23:35 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:23:35 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:24:38 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:24:38 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:24:38 PM :Debug: CRC matches for page 1:x10 x41 xBF xEE .A.. +2/28/22 6:24:38 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:24:45 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:24:48 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:25:18 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:25:18 PM :Info: Initiating read page 1 : 826:2 +2/28/22 6:25:18 PM :Debug: CRC matches for page 1:x10 x41 xBF xEE .A.. +2/28/22 6:25:18 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:25:23 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:25:25 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:25:26 PM :Info: dirtyData.size(): 0 +2/28/22 6:25:26 PM :Info: dirtyData.size(): 0 +2/28/22 6:25:26 PM :Debug: Flush lasted: 89ms. +2/28/22 6:25:26 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:25:26 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:25:26 PM :Info: Queueing burn to page:1 +2/28/22 6:25:26 PM :Debug: Burn time:256ms. +2/28/22 6:25:26 PM :Debug: burned page 1 +2/28/22 6:25:26 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:25:26 PM :Debug: CRC matches for page 1:x14 x57 x42 xE7 .WB. +2/28/22 6:25:27 PM :Info: dirtyData.size(): 0 +2/28/22 6:25:27 PM :Info: dirtyData.size(): 0 +2/28/22 6:25:27 PM :Debug: Flush lasted: 84ms. +2/28/22 6:25:27 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:25:27 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:25:27 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:25:27 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:25:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:25:28 PM :Info: Time to save msq: 7.1958 +2/28/22 6:25:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:25:29 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:25:48 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:25:48 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:28 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:34 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:26:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:26:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:26:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:26:38 PM :Debug: Flush lasted: 84ms. +2/28/22 6:26:38 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:26:38 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:26:38 PM :Info: Queueing burn to page:1 +2/28/22 6:26:38 PM :Debug: Burn time:256ms. +2/28/22 6:26:38 PM :Debug: burned page 1 +2/28/22 6:26:38 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:26:38 PM :Debug: CRC matches for page 1:xB4 x97 x9E xB7 .... +2/28/22 6:26:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:26:39 PM :Info: Time to save msq: 6.9231 +2/28/22 6:26:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:26:43 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:27:22 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:27:23 PM :Info: dirtyData.size(): 0 +2/28/22 6:27:24 PM :Info: dirtyData.size(): 0 +2/28/22 6:27:24 PM :Debug: Flush lasted: 78ms. +2/28/22 6:27:24 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:27:24 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:27:24 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:27:24 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:27:26 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:27:30 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:27:40 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:27:40 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:27:41 PM :Debug: controllerOnline = 0.0 +2/28/22 6:27:41 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:27:41 PM :Debug: Went offline +2/28/22 6:27:41 PM :Debug: controllerOnline = 0.0 +2/28/22 6:27:41 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:27:41 PM :Info: Went offline 2 +2/28/22 6:27:43 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 6:27:43 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 6:27:43 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:27:43 PM :Debug: controllerOnline = 1.0 +2/28/22 6:27:43 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:27:43 PM :Info: CRC from controller page 1:xB4 x97 x9E xB7 .... +2/28/22 6:27:43 PM :Info: Local Data CRC for page 1: x89 xF7 xB7 x07 .... +2/28/22 6:27:43 PM :Debug: Read page time: 171ms. +2/28/22 6:27:43 PM :Info: Checksum page 1 data read: xB4 x97 x9E xB7 .... +2/28/22 6:27:43 PM :Debug: Read All Data +2/28/22 6:27:43 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:27:43 PM :Debug: DiffTime: 3 ms. +2/28/22 6:27:43 PM :Debug: Time to get Panels = 0ms. +2/28/22 6:27:48 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:27:48 PM :Info: Time to save msq: 3.6083 +2/28/22 6:27:48 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:27:48 PM :Info: dirtyData.size(): 1 +2/28/22 6:27:48 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:27:48 PM :Info: dirtyData.size(): 0 +2/28/22 6:27:48 PM :Debug: Flush lasted: 48ms. +2/28/22 6:27:48 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:27:48 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:27:48 PM :Info: Queueing burn to page:1 +2/28/22 6:27:48 PM :Info: Sending, 0 bytes. +2/28/22 6:27:48 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/28/22 6:27:48 PM :Info: dirtyData.size(): 0 +2/28/22 6:27:48 PM :Info: dirtyData.size(): 0 +2/28/22 6:27:48 PM :Debug: Flush lasted: 71ms. +2/28/22 6:27:48 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:27:48 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:27:48 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:27:48 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:27:48 PM :Debug: Burn time:257ms. +2/28/22 6:27:48 PM :Debug: burned page 1 +2/28/22 6:27:48 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:27:48 PM :Debug: CRC matches for page 1:x89 xF7 xB7 x07 .... +2/28/22 6:27:48 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:27:48 PM :Debug: CRC matches for page 1:x89 xF7 xB7 x07 .... +2/28/22 6:27:48 PM :Info: CrC matched skipped controller read on page:1 +2/28/22 6:27:48 PM :Debug: Read All Data +2/28/22 6:27:48 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:27:48 PM :Debug: DiffTime: 0 ms. +2/28/22 6:27:50 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:27:50 PM :Info: Time to save msq: 4.3284 +2/28/22 6:27:50 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:28:13 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:28:14 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:28:15 PM :Debug: controllerOnline = 0.0 +2/28/22 6:28:15 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:28:15 PM :Debug: Went offline +2/28/22 6:28:15 PM :Debug: controllerOnline = 0.0 +2/28/22 6:28:15 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:28:15 PM :Info: Went offline 2 +2/28/22 6:28:16 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 6:28:17 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 6:28:17 PM :Debug: controllerOnline = 1.0 +2/28/22 6:28:54 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:28:55 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:28:56 PM :Debug: controllerOnline = 0.0 +2/28/22 6:28:56 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:28:56 PM :Debug: Went offline +2/28/22 6:28:56 PM :Debug: controllerOnline = 0.0 +2/28/22 6:28:56 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:28:56 PM :Info: Went offline 2 +2/28/22 6:29:04 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 6:29:05 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 6:29:05 PM :Debug: controllerOnline = 1.0 +2/28/22 6:29:11 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:29:12 PM :Info: Initiating read page 1 : 826:2 +2/28/22 6:29:12 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:29:12 PM :Info: CRC from controller page 1:x4F xF3 x2D xA0 O.-. +2/28/22 6:29:12 PM :Info: Local Data CRC for page 1: x89 xF7 xB7 x07 .... +2/28/22 6:29:12 PM :Info: Checksum of data read: x41 xD9 x12 xFF A... +2/28/22 6:29:12 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:20 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:20 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:20 PM :Debug: Flush lasted: 83ms. +2/28/22 6:29:20 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:29:20 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:20 PM :Info: Queueing burn to page:1 +2/28/22 6:29:20 PM :Debug: Burn time:257ms. +2/28/22 6:29:20 PM :Debug: burned page 1 +2/28/22 6:29:20 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:29:20 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:29:20 PM :Info: CRC from controller page 1:x4B xE5 xD0 xA9 K... +2/28/22 6:29:20 PM :Info: Local Data CRC for page 1: x89 xF7 xB7 x07 .... +2/28/22 6:29:20 PM :Info: Retrying CRC call to see if it agrees after read: +2/28/22 6:29:20 PM :Debug: CRC matches for page 1:x4B xE5 xD0 xA9 K... +2/28/22 6:29:21 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:29:21 PM :Info: Time to save msq: 10.0927 +2/28/22 6:29:21 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:29:25 PM :Debug: Writing the last 0 comm interactions including the burn, crc and page read to the log file here: +2/28/22 6:29:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:30 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:31 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:31 PM :Debug: Flush lasted: 84ms. +2/28/22 6:29:31 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:29:31 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:31 PM :Info: Queueing burn to page:1 +2/28/22 6:29:31 PM :Debug: Burn time:256ms. +2/28/22 6:29:31 PM :Debug: burned page 1 +2/28/22 6:29:31 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:29:31 PM :Debug: CRC matches for page 1:x73 x93 xCE xA8 s... +2/28/22 6:29:32 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:29:32 PM :Info: Time to save msq: 3.153 +2/28/22 6:29:32 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:29:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:33 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:33 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:33 PM :Debug: Flush lasted: 89ms. +2/28/22 6:29:33 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:29:33 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:33 PM :Info: Queueing burn to page:1 +2/28/22 6:29:33 PM :Debug: Burn time:258ms. +2/28/22 6:29:33 PM :Debug: burned page 1 +2/28/22 6:29:33 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:29:33 PM :Debug: CRC matches for page 1:x4B xE5 xD0 xA9 K... +2/28/22 6:29:34 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:34 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:34 PM :Debug: Flush lasted: 85ms. +2/28/22 6:29:34 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:29:34 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:34 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:29:34 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:29:34 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:29:34 PM :Info: Time to save msq: 9.0022 +2/28/22 6:29:34 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:29:40 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:29:40 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:29:40 PM :Debug: CRC matches for page 1:x4B xE5 xD0 xA9 K... +2/28/22 6:29:40 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:29:47 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:29:50 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:51 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:51 PM :Debug: Flush lasted: 80ms. +2/28/22 6:29:51 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:29:51 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:51 PM :Info: Queueing burn to page:1 +2/28/22 6:29:51 PM :Debug: Burn time:256ms. +2/28/22 6:29:51 PM :Debug: burned page 1 +2/28/22 6:29:51 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:29:51 PM :Debug: CRC matches for page 1:x33 x24 x16 xB9 3$.. +2/28/22 6:29:52 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:52 PM :Info: dirtyData.size(): 0 +2/28/22 6:29:52 PM :Debug: Flush lasted: 83ms. +2/28/22 6:29:52 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:29:52 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:29:52 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:29:52 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:29:53 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:29:53 PM :Info: Time to save msq: 3.7406 +2/28/22 6:29:53 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:30:20 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:30:20 PM :Info: Initiating read page 1 : 2:832 +2/28/22 6:30:21 PM :Debug: CRC matches for page 1:x33 x24 x16 xB9 3$.. +2/28/22 6:30:21 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:21 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:48 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:30:48 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:32:23 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:32:23 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:32:29 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:32:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:32:32 PM :Info: dirtyData.size(): 0 +2/28/22 6:32:32 PM :Info: dirtyData.size(): 0 +2/28/22 6:32:32 PM :Debug: Flush lasted: 84ms. +2/28/22 6:32:32 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:32:32 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:32:32 PM :Info: Queueing burn to page:1 +2/28/22 6:32:32 PM :Debug: Burn time:257ms. +2/28/22 6:32:32 PM :Debug: burned page 1 +2/28/22 6:32:32 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:32:32 PM :Debug: CRC matches for page 1:x37 xD6 x3D x7F 7.=. +2/28/22 6:32:34 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:32:34 PM :Info: Time to save msq: 3.7986 +2/28/22 6:32:34 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:32:35 PM :Info: dirtyData.size(): 0 +2/28/22 6:32:36 PM :Info: dirtyData.size(): 0 +2/28/22 6:32:36 PM :Debug: Flush lasted: 84ms. +2/28/22 6:32:36 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:32:36 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:32:36 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:32:36 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:32:41 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:32:41 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:32:41 PM :Debug: CRC matches for page 1:x37 xD6 x3D x7F 7.=. +2/28/22 6:32:41 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:33:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:16 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:16 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:28 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:33 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:33:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:33:36 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:36 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:36 PM :Debug: Flush lasted: 89ms. +2/28/22 6:33:36 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:33:36 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:33:36 PM :Info: Queueing burn to page:1 +2/28/22 6:33:37 PM :Debug: Burn time:257ms. +2/28/22 6:33:37 PM :Debug: burned page 1 +2/28/22 6:33:37 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:33:37 PM :Debug: CRC matches for page 1:xE4 xBB xB3 x9D .... +2/28/22 6:33:38 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:33:38 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:33:38 PM :Info: Time to save msq: 8.8695 +2/28/22 6:33:38 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:33:42 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:42 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:42 PM :Debug: Flush lasted: 75ms. +2/28/22 6:33:42 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:33:42 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:33:42 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:33:42 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:33:43 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:43 PM :Info: dirtyData.size(): 0 +2/28/22 6:33:43 PM :Debug: Flush lasted: 72ms. +2/28/22 6:33:43 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:33:43 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:33:43 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:33:43 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:33:50 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:33:50 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:33:51 PM :Debug: controllerOnline = 0.0 +2/28/22 6:33:51 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:33:51 PM :Debug: Went offline +2/28/22 6:33:51 PM :Debug: controllerOnline = 0.0 +2/28/22 6:33:51 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:33:51 PM :Info: Went offline 2 +2/28/22 6:33:53 PM :Warning: Unsupported Controller Firmware: ?? +2/28/22 6:33:54 PM :Warning: Unsupported Controller Firmware: ?? +2/28/22 6:33:55 PM :Warning: Unsupported Controller Firmware: ? +2/28/22 6:33:58 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 6:33:58 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 6:33:58 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:33:58 PM :Debug: controllerOnline = 1.0 +2/28/22 6:33:58 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:33:58 PM :Info: CRC from controller page 1:xE4 xBB xB3 x9D .... +2/28/22 6:33:58 PM :Info: Local Data CRC for page 1: xD9 xDB x9A x2D ...- +2/28/22 6:33:59 PM :Debug: Read page time: 171ms. +2/28/22 6:33:59 PM :Info: Checksum page 1 data read: xE4 xBB xB3 x9D .... +2/28/22 6:33:59 PM :Debug: Read All Data +2/28/22 6:33:59 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:33:59 PM :Debug: DiffTime: 2 ms. +2/28/22 6:33:59 PM :Debug: Time to get Panels = 0ms. +2/28/22 6:34:03 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:34:03 PM :Info: Time to save msq: 7.4882 +2/28/22 6:34:03 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:34:03 PM :Info: dirtyData.size(): 1 +2/28/22 6:34:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:34:03 PM :Info: dirtyData.size(): 0 +2/28/22 6:34:03 PM :Debug: Flush lasted: 63ms. +2/28/22 6:34:03 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:34:03 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:34:03 PM :Info: Queueing burn to page:1 +2/28/22 6:34:03 PM :Info: Sending, 0 bytes. +2/28/22 6:34:03 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/28/22 6:34:03 PM :Info: dirtyData.size(): 0 +2/28/22 6:34:03 PM :Info: dirtyData.size(): 0 +2/28/22 6:34:03 PM :Debug: Flush lasted: 71ms. +2/28/22 6:34:03 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:34:03 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:34:03 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:34:03 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:34:04 PM :Debug: Burn time:257ms. +2/28/22 6:34:04 PM :Debug: burned page 1 +2/28/22 6:34:04 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:34:04 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:34:04 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:34:04 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:34:04 PM :Info: CrC matched skipped controller read on page:1 +2/28/22 6:34:04 PM :Debug: Read All Data +2/28/22 6:34:04 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:34:04 PM :Debug: DiffTime: 0 ms. +2/28/22 6:34:06 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:34:06 PM :Info: Time to save msq: 3.0799 +2/28/22 6:34:06 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:35:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:35:17 PM :Info: Time to save msq: 3.3183 +2/28/22 6:35:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:35:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:35:17 PM :Info: Time to save msq: 2.5037 +2/28/22 6:35:17 PM :Info: DBW_code_26.10.2021 Tune Saved! +2/28/22 6:35:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:35:32 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:35:33 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:35:33 PM :Debug: controllerOnline = 0.0 +2/28/22 6:35:33 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:35:33 PM :Debug: Went offline +2/28/22 6:35:33 PM :Debug: controllerOnline = 0.0 +2/28/22 6:35:33 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:35:33 PM :Info: Went offline 2 +2/28/22 6:35:57 PM :Info: Sig Bytes:x73 x70 x65 x65 x64 x75 x69 x6E x6F x20 x44 x42 x57 x20 x32 x2E speeduino.DBW.2. +x30 x2E x30 x00 0.0. +2/28/22 6:35:57 PM :Info: Communicating with sig:speeduino DBW 2.0.0, speeduino DBW 2.0.0 +2/28/22 6:35:57 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:35:57 PM :Debug: controllerOnline = 1.0 +2/28/22 6:35:57 PM :Info: CRC Mismatch, will need to refresh page from controller +2/28/22 6:35:57 PM :Info: CRC from controller page 1:x4F xF3 x2D xA0 O.-. +2/28/22 6:35:57 PM :Info: Local Data CRC for page 1: xD9 xDB x9A x2D ...- +2/28/22 6:35:57 PM :Debug: Read page time: 172ms. +2/28/22 6:35:57 PM :Info: Checksum page 1 data read: x4F xF3 x2D xA0 O.-. +2/28/22 6:35:57 PM :Debug: Read All Data +2/28/22 6:35:57 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:35:57 PM :Debug: DiffTime: 2 ms. +2/28/22 6:35:57 PM :Debug: Time to get Panels = 0ms. +2/28/22 6:36:01 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:36:01 PM :Info: Time to save msq: 2.9172 +2/28/22 6:36:01 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:36:01 PM :Info: dirtyData.size(): 2 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:36:01 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:01 PM :Debug: Flush lasted: 89ms. +2/28/22 6:36:01 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:36:01 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:36:01 PM :Info: Queueing burn to page:1 +2/28/22 6:36:01 PM :Info: Sending, 0 bytes. +2/28/22 6:36:01 PM :Info: Loaded Restore point C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq + Sending, 0 bytes. +2/28/22 6:36:01 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:01 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:01 PM :Debug: Flush lasted: 71ms. +2/28/22 6:36:01 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:36:01 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:36:01 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:36:01 PM :Debug: Received Instruction: Read All Tune Data, Page: 0 +2/28/22 6:36:12 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq +2/28/22 6:36:12 PM :Info: Tune opened, 0 bytes updated. File:C:\Users\v0stap\Desktop\DBW_code_26.10.2021\CurrentTune.msq +2/28/22 6:36:12 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:12 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:12 PM :Debug: Flush lasted: 0ms. +2/28/22 6:36:12 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:12 PM :Info: dirtyData.size(): 0 +2/28/22 6:36:12 PM :Debug: Flush lasted: 72ms. +2/28/22 6:36:12 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:36:12 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:36:12 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:36:22 PM :Debug: Burn time:257ms. +2/28/22 6:36:22 PM :Debug: burned page 1 +2/28/22 6:36:22 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:36:22 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:36:22 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:36:22 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:36:22 PM :Info: CrC matched skipped controller read on page:1 +2/28/22 6:36:22 PM :Debug: Read All Data +2/28/22 6:36:22 PM :Debug: isBlank Time: 0 ms. +2/28/22 6:36:22 PM :Debug: DiffTime: 1 ms. +2/28/22 6:36:22 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:36:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:36:23 PM :Info: Time to save msq: 2.3919 +2/28/22 6:36:23 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:36:46 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:36:46 PM :Info: Initiating read page 1 : 826:2 +2/28/22 6:36:46 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:36:46 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:36:49 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:37:49 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:37:49 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:37:49 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:37:49 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:38:00 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:38:02 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:02 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:02 PM :Debug: Flush lasted: 82ms. +2/28/22 6:38:02 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:38:02 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:38:02 PM :Info: Queueing burn to page:1 +2/28/22 6:38:02 PM :Debug: Burn time:257ms. +2/28/22 6:38:02 PM :Debug: burned page 1 +2/28/22 6:38:02 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:38:02 PM :Debug: CRC matches for page 1:x57 xD8 x80 x34 W..4 +2/28/22 6:38:04 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:38:04 PM :Info: Time to save msq: 4.0816 +2/28/22 6:38:04 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:38:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:38:15 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:15 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:15 PM :Debug: Flush lasted: 85ms. +2/28/22 6:38:15 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:38:15 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:38:15 PM :Info: Queueing burn to page:1 +2/28/22 6:38:15 PM :Debug: Burn time:256ms. +2/28/22 6:38:15 PM :Debug: burned page 1 +2/28/22 6:38:15 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:38:15 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:38:16 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:38:16 PM :Info: Time to save msq: 5.1551 +2/28/22 6:38:16 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:38:50 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:50 PM :Info: dirtyData.size(): 0 +2/28/22 6:38:50 PM :Debug: Flush lasted: 74ms. +2/28/22 6:38:50 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:38:50 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:38:50 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:38:50 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:39:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:20 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:22 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:25 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:28 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:28 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:28 PM :Debug: Flush lasted: 83ms. +2/28/22 6:39:28 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:39:28 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:39:28 PM :Info: Queueing burn to page:1 +2/28/22 6:39:29 PM :Debug: Burn time:257ms. +2/28/22 6:39:29 PM :Debug: burned page 1 +2/28/22 6:39:29 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:39:29 PM :Debug: CRC matches for page 1:xB8 xF7 xF4 xBB .... +2/28/22 6:39:30 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:39:30 PM :Info: Time to save msq: 4.4671 +2/28/22 6:39:30 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:39:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:45 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:50 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:50 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:50 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:50 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:50 PM :Debug: Flush lasted: 4ms. +2/28/22 6:39:50 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:39:50 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:39:50 PM :Info: Queueing burn to page:1 +2/28/22 6:39:50 PM :Debug: Burn time:257ms. +2/28/22 6:39:50 PM :Debug: burned page 1 +2/28/22 6:39:50 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:39:50 PM :Debug: CRC matches for page 1:xD9 xDB x9A x2D ...- +2/28/22 6:39:51 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:39:51 PM :Info: Time to save msq: 11.1099 +2/28/22 6:39:51 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:39:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:39:57 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:57 PM :Info: dirtyData.size(): 0 +2/28/22 6:39:57 PM :Debug: Flush lasted: 84ms. +2/28/22 6:39:57 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:39:57 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:39:57 PM :Info: Queueing burn to page:1 +2/28/22 6:39:57 PM :Debug: Burn time:257ms. +2/28/22 6:39:57 PM :Debug: burned page 1 +2/28/22 6:39:57 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:39:57 PM :Debug: CRC matches for page 1:x1E xAC xA8 x5E ...^ +2/28/22 6:39:59 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:39:59 PM :Info: Time to save msq: 3.7448 +2/28/22 6:39:59 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:40:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:08 PM :Info: dirtyData.size(): 0 +2/28/22 6:40:08 PM :Info: dirtyData.size(): 0 +2/28/22 6:40:08 PM :Debug: Flush lasted: 84ms. +2/28/22 6:40:08 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:40:08 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:40:08 PM :Info: Queueing burn to page:1 +2/28/22 6:40:08 PM :Debug: Burn time:257ms. +2/28/22 6:40:08 PM :Debug: burned page 1 +2/28/22 6:40:08 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:40:08 PM :Debug: CRC matches for page 1:x57 xD8 x80 x34 W..4 +2/28/22 6:40:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:40:09 PM :Info: Time to save msq: 3.0345 +2/28/22 6:40:09 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:40:16 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:40:16 PM :Info: Initiating read page 1 : 724:64 +2/28/22 6:40:16 PM :Debug: CRC matches for page 1:x57 xD8 x80 x34 W..4 +2/28/22 6:40:16 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:40:26 PM :Info: dirtyData.size(): 0 +2/28/22 6:40:26 PM :Info: dirtyData.size(): 0 +2/28/22 6:40:26 PM :Debug: Flush lasted: 84ms. +2/28/22 6:40:26 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:40:26 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:40:26 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:40:26 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:40:34 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:40:34 PM :Info: Initiating read page 1 : 788:32 +2/28/22 6:40:34 PM :Debug: CRC matches for page 1:x57 xD8 x80 x34 W..4 +2/28/22 6:40:34 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:40:45 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:45 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:45 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:49 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:54 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:40:57 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:40:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:08 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:08 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:08 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:09 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:09 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:10 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:10 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:10 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:12 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:17 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:41:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:41:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:15 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:15 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:24 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:42:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:36 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:42:51 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:51 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:42:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:04 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:09 PM :Info: dirtyData.size(): 0 +2/28/22 6:43:09 PM :Info: dirtyData.size(): 0 +2/28/22 6:43:09 PM :Debug: Flush lasted: 70ms. +2/28/22 6:43:09 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:43:09 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:43:09 PM :Info: Queueing burn to page:1 +2/28/22 6:43:09 PM :Debug: Burn time:256ms. +2/28/22 6:43:09 PM :Debug: burned page 1 +2/28/22 6:43:09 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:43:09 PM :Debug: CRC matches for page 1:xF6 x10 x78 xD8 ..x. +2/28/22 6:43:10 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:43:10 PM :Info: Time to save msq: 7.6558 +2/28/22 6:43:10 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:43:26 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:43:26 PM :Info: Initiating read page 1 : 724:64 +2/28/22 6:43:26 PM :Debug: CRC matches for page 1:xF6 x10 x78 xD8 ..x. +2/28/22 6:43:26 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:43:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:34 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:43:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:43:58 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:44:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:05 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:44:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:14 PM :Debug: Clearing selection. Vertical: false +2/28/22 6:44:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:44:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:46:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:46:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:46:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:46:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:46:19 PM :Debug: Flush lasted: 71ms. +2/28/22 6:46:19 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:46:19 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:46:19 PM :Info: Queueing burn to page:1 +2/28/22 6:46:20 PM :Debug: Burn time:257ms. +2/28/22 6:46:20 PM :Debug: burned page 1 +2/28/22 6:46:20 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:46:20 PM :Debug: CRC matches for page 1:x45 x95 xE9 x8F E... +2/28/22 6:46:22 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:46:22 PM :Info: Time to save msq: 4.4483 +2/28/22 6:46:22 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:46:33 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:46:55 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:46:55 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:46:55 PM :Info: dirtyData.size(): 0 +2/28/22 6:46:55 PM :Info: dirtyData.size(): 0 +2/28/22 6:46:55 PM :Debug: Flush lasted: 70ms. +2/28/22 6:46:55 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:46:55 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:46:55 PM :Info: Queueing burn to page:1 +2/28/22 6:46:55 PM :Debug: Burn time:257ms. +2/28/22 6:46:55 PM :Debug: burned page 1 +2/28/22 6:46:55 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:46:55 PM :Debug: CRC matches for page 1:x81 x7E x96 x40 .~.@ +2/28/22 6:46:57 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:46:57 PM :Info: Time to save msq: 7.4785 +2/28/22 6:46:57 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:46:57 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:47:05 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:47:11 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:47:11 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:47:11 PM :Debug: CRC matches for page 1:x81 x7E x96 x40 .~.@ +2/28/22 6:47:11 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:47:13 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:18 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:23 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:26 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:28 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:29 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:29 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:30 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:30 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:31 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:32 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:35 PM :Debug: Received Instruction: , Page: 0 +2/28/22 6:47:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:47:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:47:38 PM :Debug: Flush lasted: 70ms. +2/28/22 6:47:38 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:47:38 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:47:38 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:47:38 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:47:40 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:47:51 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:47:51 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:47:56 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:47:56 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:48:13 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:48:13 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:48:13 PM :Debug: CRC matches for page 1:xAA xA6 xB0 x38 ...8 +2/28/22 6:48:13 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:48:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:48:38 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:48:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:48:38 PM :Info: dirtyData.size(): 0 +2/28/22 6:48:38 PM :Debug: Flush lasted: 70ms. +2/28/22 6:48:38 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:48:38 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:48:38 PM :Info: Queueing burn to page:1 +2/28/22 6:48:39 PM :Debug: Burn time:257ms. +2/28/22 6:48:39 PM :Debug: burned page 1 +2/28/22 6:48:39 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:48:39 PM :Debug: CRC matches for page 1:x0B xF7 x6F xF2 ..o. +2/28/22 6:48:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:48:41 PM :Info: Time to save msq: 6.3708 +2/28/22 6:48:41 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:49:13 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:49:13 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:13 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:13 PM :Debug: Flush lasted: 70ms. +2/28/22 6:49:13 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:49:13 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:49:13 PM :Info: Queueing burn to page:1 +2/28/22 6:49:14 PM :Debug: Burn time:256ms. +2/28/22 6:49:14 PM :Debug: burned page 1 +2/28/22 6:49:14 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:49:14 PM :Debug: CRC matches for page 1:xCA x94 xD0 xE4 .... +2/28/22 6:49:14 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:14 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:14 PM :Debug: Flush lasted: 70ms. +2/28/22 6:49:14 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:49:14 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:49:14 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:49:15 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:49:15 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:49:15 PM :Info: Time to save msq: 6.4934 +2/28/22 6:49:15 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:49:19 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:49:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:49:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:40 PM :Debug: Flush lasted: 70ms. +2/28/22 6:49:40 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:49:40 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:49:40 PM :Info: Queueing burn to page:1 +2/28/22 6:49:41 PM :Debug: Burn time:256ms. +2/28/22 6:49:41 PM :Debug: burned page 1 +2/28/22 6:49:41 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:49:41 PM :Debug: CRC matches for page 1:x44 x97 xCA xFD D... +2/28/22 6:49:41 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:41 PM :Info: dirtyData.size(): 0 +2/28/22 6:49:41 PM :Debug: Flush lasted: 72ms. +2/28/22 6:49:41 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:49:41 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:49:41 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:49:41 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:49:42 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:49:43 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:49:43 PM :Info: Time to save msq: 6.084 +2/28/22 6:49:43 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:50:06 PM :Info: dirtyData.size(): 0 +2/28/22 6:50:06 PM :Info: dirtyData.size(): 0 +2/28/22 6:50:06 PM :Debug: Flush lasted: 71ms. +2/28/22 6:50:06 PM :Debug: Skip Burn, last write page: -2 +2/28/22 6:50:07 PM :Info: dirtyData.size(): 0 +2/28/22 6:50:07 PM :Info: dirtyData.size(): 0 +2/28/22 6:50:07 PM :Debug: Flush lasted: 79ms. +2/28/22 6:50:07 PM :Debug: Skip Burn, last write page: -2 +2/28/22 6:50:37 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:50:47 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:50:47 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:50:47 PM :Debug: CRC matches for page 1:x44 x97 xCA xFD D... +2/28/22 6:50:47 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:51:14 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:14 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:14 PM :Debug: Flush lasted: 83ms. +2/28/22 6:51:14 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:51:14 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:51:14 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:51:14 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:51:19 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:51:19 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:51:19 PM :Debug: CRC matches for page 1:x44 x97 xCA xFD D... +2/28/22 6:51:19 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:51:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:51:39 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:51:39 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:39 PM :Debug: Flush lasted: 20ms. +2/28/22 6:51:39 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:51:39 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:51:39 PM :Info: Queueing burn to page:1 +2/28/22 6:51:39 PM :Debug: Burn time:257ms. +2/28/22 6:51:39 PM :Debug: burned page 1 +2/28/22 6:51:39 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:51:39 PM :Debug: CRC matches for page 1:x02 x55 x7A x86 .Uz. +2/28/22 6:51:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:51:40 PM :Debug: Flush lasted: 72ms. +2/28/22 6:51:40 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:51:40 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:51:40 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:51:40 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:51:40 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:51:40 PM :Info: Time to save msq: 4.9702 +2/28/22 6:51:40 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:51:41 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:54:33 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:54:33 PM :Info: Initiating read page 1 : 14:834 +2/28/22 6:54:33 PM :Debug: CRC matches for page 1:x02 x55 x7A x86 .Uz. +2/28/22 6:54:33 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:54:35 PM :Info: dirtyData.size(): 0 +2/28/22 6:54:35 PM :Info: dirtyData.size(): 0 +2/28/22 6:54:35 PM :Debug: Flush lasted: 77ms. +2/28/22 6:54:35 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:54:35 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:54:35 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:54:35 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:54:50 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:54:50 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:54:50 PM :Debug: CRC matches for page 1:x02 x55 x7A x86 .Uz. +2/28/22 6:54:50 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:55:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:55:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:55:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:55:40 PM :Debug: Flush lasted: 32ms. +2/28/22 6:55:40 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:55:40 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:55:40 PM :Info: Queueing burn to page:1 +2/28/22 6:55:41 PM :Debug: Burn time:256ms. +2/28/22 6:55:41 PM :Debug: burned page 1 +2/28/22 6:55:41 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:55:41 PM :Debug: CRC matches for page 1:x74 x20 x66 xE0 t.f. +2/28/22 6:55:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:55:42 PM :Info: Time to save msq: 5.6523 +2/28/22 6:55:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:56:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:56:17 PM :Info: dirtyData.size(): 0 +2/28/22 6:56:17 PM :Info: dirtyData.size(): 0 +2/28/22 6:56:17 PM :Debug: Flush lasted: 70ms. +2/28/22 6:56:17 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:56:17 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:56:17 PM :Info: Queueing burn to page:1 +2/28/22 6:56:18 PM :Debug: Burn time:257ms. +2/28/22 6:56:18 PM :Debug: burned page 1 +2/28/22 6:56:18 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:56:18 PM :Debug: CRC matches for page 1:x7A x5F x0A xD1 z_.. +2/28/22 6:56:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:56:20 PM :Info: Time to save msq: 6.208 +2/28/22 6:56:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:56:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:56:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:56:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:56:40 PM :Info: dirtyData.size(): 0 +2/28/22 6:56:40 PM :Debug: Flush lasted: 71ms. +2/28/22 6:56:40 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:56:40 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:56:40 PM :Info: Queueing burn to page:1 +2/28/22 6:56:40 PM :Debug: Burn time:257ms. +2/28/22 6:56:40 PM :Debug: burned page 1 +2/28/22 6:56:40 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:56:40 PM :Debug: CRC matches for page 1:x03 x5A x42 x1E .ZB. +2/28/22 6:56:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:56:42 PM :Info: Time to save msq: 3.5705 +2/28/22 6:56:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:56:55 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:57:10 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:57:10 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:10 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:10 PM :Debug: Flush lasted: 70ms. +2/28/22 6:57:10 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:57:10 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:57:10 PM :Info: Queueing burn to page:1 +2/28/22 6:57:10 PM :Debug: Burn time:256ms. +2/28/22 6:57:10 PM :Debug: burned page 1 +2/28/22 6:57:10 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:57:10 PM :Debug: CRC matches for page 1:x0D x25 x2E x2F .%./ +2/28/22 6:57:10 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:11 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:11 PM :Debug: Flush lasted: 70ms. +2/28/22 6:57:11 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:57:11 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:57:11 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:57:11 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:57:12 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:57:12 PM :Info: Time to save msq: 2.9317 +2/28/22 6:57:12 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:57:21 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:57:21 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:57:21 PM :Debug: CRC matches for page 1:x0D x25 x2E x2F .%./ +2/28/22 6:57:21 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:57:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:57:33 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:33 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:57:33 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:33 PM :Debug: Flush lasted: 6ms. +2/28/22 6:57:33 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:57:33 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:57:33 PM :Info: Queueing burn to page:1 +2/28/22 6:57:34 PM :Debug: Burn time:256ms. +2/28/22 6:57:34 PM :Debug: burned page 1 +2/28/22 6:57:34 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:57:34 PM :Debug: CRC matches for page 1:x74 x20 x66 xE0 t.f. +2/28/22 6:57:35 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:57:35 PM :Info: Time to save msq: 3.0752 +2/28/22 6:57:35 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:57:42 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:42 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:42 PM :Debug: Flush lasted: 79ms. +2/28/22 6:57:42 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:57:42 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:57:42 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:57:42 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:57:43 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:43 PM :Info: dirtyData.size(): 0 +2/28/22 6:57:43 PM :Debug: Flush lasted: 72ms. +2/28/22 6:57:43 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:57:43 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:57:43 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:57:43 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:57:47 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:58:06 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:58:06 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:58:06 PM :Debug: CRC matches for page 1:x74 x20 x66 xE0 t.f. +2/28/22 6:58:06 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:58:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:58:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:58:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:19 PM :Debug: Flush lasted: 71ms. +2/28/22 6:58:19 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:58:19 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:58:19 PM :Info: Queueing burn to page:1 +2/28/22 6:58:19 PM :Debug: Burn time:257ms. +2/28/22 6:58:19 PM :Debug: burned page 1 +2/28/22 6:58:19 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:58:19 PM :Debug: CRC matches for page 1:x09 xF9 xC3 xFE .... +2/28/22 6:58:20 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:20 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:20 PM :Debug: Flush lasted: 70ms. +2/28/22 6:58:20 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:58:20 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:58:20 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:58:20 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:58:21 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:58:21 PM :Info: Time to save msq: 3.3944 +2/28/22 6:58:21 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:58:22 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 6:58:33 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:58:33 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:58:33 PM :Debug: CRC matches for page 1:x09 xF9 xC3 xFE .... +2/28/22 6:58:33 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:58:47 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:58:47 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:47 PM :Info: dirtyData.size(): 0 +2/28/22 6:58:47 PM :Debug: Flush lasted: 15ms. +2/28/22 6:58:47 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:58:47 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:58:47 PM :Info: Queueing burn to page:1 +2/28/22 6:58:47 PM :Debug: Burn time:256ms. +2/28/22 6:58:47 PM :Debug: burned page 1 +2/28/22 6:58:47 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:58:47 PM :Debug: CRC matches for page 1:x07 x86 xAF xCF .... +2/28/22 6:58:48 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:58:49 PM :Info: Time to save msq: 5.6287 +2/28/22 6:58:49 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:59:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:59:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:59:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 6:59:17 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:18 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:18 PM :Debug: Flush lasted: 70ms. +2/28/22 6:59:18 PM :Debug: Burn Page anonymous: 1 +2/28/22 6:59:18 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:59:18 PM :Info: Queueing burn to page:1 +2/28/22 6:59:18 PM :Debug: Burn time:256ms. +2/28/22 6:59:18 PM :Debug: burned page 1 +2/28/22 6:59:18 PM :Debug: No Remaining Queue Write instructions +2/28/22 6:59:18 PM :Debug: CRC matches for page 1:xBB x32 x5F x07 .2_. +2/28/22 6:59:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:19 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:19 PM :Debug: Flush lasted: 79ms. +2/28/22 6:59:19 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:59:19 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:59:19 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:59:19 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:59:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 6:59:20 PM :Info: Time to save msq: 6.193 +2/28/22 6:59:20 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 6:59:37 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 6:59:37 PM :Info: Initiating read page 1 : 26:824 +2/28/22 6:59:37 PM :Debug: CRC matches for page 1:xBB x32 x5F x07 .2_. +2/28/22 6:59:37 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 6:59:46 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:46 PM :Info: dirtyData.size(): 0 +2/28/22 6:59:46 PM :Debug: Flush lasted: 71ms. +2/28/22 6:59:46 PM :Debug: Burn Page anonymous: -1 +2/28/22 6:59:46 PM :Debug: Received Instruction: , Page: 1 +2/28/22 6:59:46 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 6:59:46 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 6:59:48 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:00:08 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:00:08 PM :Info: Initiating read page 1 : 28:64 +2/28/22 7:00:08 PM :Debug: CRC matches for page 1:xBB x32 x5F x07 .2_. +2/28/22 7:00:08 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:00:13 PM :Info: dirtyData.size(): 0 +2/28/22 7:00:13 PM :Info: dirtyData.size(): 0 +2/28/22 7:00:13 PM :Debug: Flush lasted: 83ms. +2/28/22 7:00:13 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:00:13 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:00:13 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:00:13 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:01:16 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:01:16 PM :Info: Initiating read page 1 : 14:834 +2/28/22 7:01:16 PM :Debug: CRC matches for page 1:xBB x32 x5F x07 .2_. +2/28/22 7:01:16 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:04:48 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:05:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:05:28 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:05:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:05:38 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:05:54 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:06:08 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:06:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:06:40 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:06:44 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:06:44 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:07:15 PM :Info: dirtyData.size(): 0 +2/28/22 7:07:15 PM :Info: dirtyData.size(): 0 +2/28/22 7:07:15 PM :Debug: Flush lasted: 80ms. +2/28/22 7:07:15 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:07:15 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:07:15 PM :Info: Queueing burn to page:1 +2/28/22 7:07:15 PM :Debug: Burn time:256ms. +2/28/22 7:07:15 PM :Debug: burned page 1 +2/28/22 7:07:15 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:07:16 PM :Debug: CRC matches for page 1:x96 xCE xEB x31 ...1 +2/28/22 7:07:17 PM :Info: dirtyData.size(): 0 +2/28/22 7:07:17 PM :Info: dirtyData.size(): 0 +2/28/22 7:07:17 PM :Debug: Flush lasted: 78ms. +2/28/22 7:07:17 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:07:17 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:07:17 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:07:17 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:07:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:07:17 PM :Info: Time to save msq: 5.6915 +2/28/22 7:07:17 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:08:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:11 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:17 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:08:44 PM :Info: dirtyData.size(): 0 +2/28/22 7:08:44 PM :Info: dirtyData.size(): 0 +2/28/22 7:08:44 PM :Debug: Flush lasted: 71ms. +2/28/22 7:08:44 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:08:44 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:08:44 PM :Info: Queueing burn to page:1 +2/28/22 7:08:45 PM :Debug: Burn time:257ms. +2/28/22 7:08:45 PM :Debug: burned page 1 +2/28/22 7:08:45 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:08:45 PM :Debug: CRC matches for page 1:x33 xCB x17 xB2 3... +2/28/22 7:08:46 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:08:47 PM :Info: Time to save msq: 4.1121 +2/28/22 7:08:47 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:09:13 PM :Debug: EventTrigger Stop Data log Triggered. expression: 0 +2/28/22 7:09:13 PM :Debug: Starting Log for 1 Configs. +2/28/22 7:09:13 PM :Debug: Time to subscribe all data log channels: 0.0157 +2/28/22 7:09:13 PM :Debug: MLG header created +2/28/22 7:09:13 PM :Info: Started Data Log to file: C:\Users\v0stap\Desktop\DBW_code_26.10.2021\DataLogs\2022-02-28_18.35.22.mlg +2/28/22 7:09:13 PM :Info: Channels active on main config DBW_code_26.10.2021: 33 +2/28/22 7:09:13 PM :Info: Capturing DataLog +2/28/22 7:10:28 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:10:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:10:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:10:41 PM :Info: dirtyData.size(): 0 +2/28/22 7:10:41 PM :Info: dirtyData.size(): 0 +2/28/22 7:10:41 PM :Debug: Flush lasted: 80ms. +2/28/22 7:10:41 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:10:41 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:10:41 PM :Info: Queueing burn to page:1 +2/28/22 7:10:41 PM :Debug: Burn time:256ms. +2/28/22 7:10:41 PM :Debug: burned page 1 +2/28/22 7:10:41 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:10:41 PM :Debug: CRC matches for page 1:x81 x00 x8B x4B ...K +2/28/22 7:10:42 PM :Info: dirtyData.size(): 0 +2/28/22 7:10:42 PM :Info: dirtyData.size(): 0 +2/28/22 7:10:42 PM :Debug: Flush lasted: 71ms. +2/28/22 7:10:42 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:10:42 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:10:42 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:10:42 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:10:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:10:42 PM :Info: Time to save msq: 21.7077 +2/28/22 7:10:42 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:10:46 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:10:46 PM :Info: Initiating read page 1 : 724:64 +2/28/22 7:10:46 PM :Debug: CRC matches for page 1:x81 x00 x8B x4B ...K +2/28/22 7:10:46 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:12:00 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:00 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:35 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:37 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:55 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:55 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:57 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:59 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:12:59 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:06 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:06 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:11 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:11 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:18 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:20 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:20 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:23 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:26 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:30 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:13:37 PM :Info: dirtyData.size(): 0 +2/28/22 7:13:37 PM :Info: dirtyData.size(): 0 +2/28/22 7:13:37 PM :Debug: Flush lasted: 71ms. +2/28/22 7:13:37 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:13:37 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:13:37 PM :Info: Queueing burn to page:1 +2/28/22 7:13:38 PM :Debug: Burn time:256ms. +2/28/22 7:13:38 PM :Debug: burned page 1 +2/28/22 7:13:38 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:13:38 PM :Debug: CRC matches for page 1:x72 x57 x30 x04 rW0. +2/28/22 7:13:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:13:39 PM :Info: Time to save msq: 7.2806 +2/28/22 7:13:39 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:14:13 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:14:32 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:14:32 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:14:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:14:39 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:14:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:14:43 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:12 PM :Warning: Invalid numeric value: 0.-0, setting back to: 0.0 +2/28/22 7:15:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:19 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:24 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:41 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:42 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:44 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:44 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:46 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:15:58 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:01 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:03 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:05 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:07 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:09 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:09 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:12 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:12 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:23 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:23 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:23 PM :Debug: Flush lasted: 70ms. +2/28/22 7:16:23 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:16:23 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:16:23 PM :Info: Queueing burn to page:1 +2/28/22 7:16:23 PM :Debug: Burn time:257ms. +2/28/22 7:16:23 PM :Debug: burned page 1 +2/28/22 7:16:23 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:16:24 PM :Debug: CRC matches for page 1:x8C xB5 x16 x9D .... +2/28/22 7:16:25 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:16:25 PM :Info: Time to save msq: 7.0456 +2/28/22 7:16:25 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:16:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:31 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:16:34 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:34 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:34 PM :Debug: Flush lasted: 70ms. +2/28/22 7:16:34 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:16:34 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:16:34 PM :Info: Queueing burn to page:1 +2/28/22 7:16:34 PM :Debug: Burn time:256ms. +2/28/22 7:16:34 PM :Debug: burned page 1 +2/28/22 7:16:34 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:16:34 PM :Debug: CRC matches for page 1:x69 x65 x40 x8D ie@. +2/28/22 7:16:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:16:36 PM :Info: Time to save msq: 3.9937 +2/28/22 7:16:36 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:16:47 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:47 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:47 PM :Debug: Flush lasted: 71ms. +2/28/22 7:16:47 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:16:47 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:16:47 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:16:47 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:16:48 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:48 PM :Info: dirtyData.size(): 0 +2/28/22 7:16:48 PM :Debug: Flush lasted: 83ms. +2/28/22 7:16:48 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:16:48 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:16:48 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:16:48 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:16:55 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:16:55 PM :Info: Initiating read page 1 : 26:824 +2/28/22 7:16:55 PM :Debug: CRC matches for page 1:x69 x65 x40 x8D ie@. +2/28/22 7:16:55 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:17:14 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:17:22 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:17:26 PM :Info: dirtyData.size(): 0 +2/28/22 7:17:26 PM :Info: dirtyData.size(): 0 +2/28/22 7:17:26 PM :Debug: Flush lasted: 73ms. +2/28/22 7:17:26 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:17:26 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:17:26 PM :Info: Queueing burn to page:1 +2/28/22 7:17:27 PM :Debug: Burn time:256ms. +2/28/22 7:17:27 PM :Debug: burned page 1 +2/28/22 7:17:27 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:17:27 PM :Debug: CRC matches for page 1:xD4 x1F xF5 x6C ...l +2/28/22 7:17:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:17:28 PM :Info: Time to save msq: 3.1695 +2/28/22 7:17:28 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:17:50 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:18:22 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:18:22 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:18:25 PM :Info: dirtyData.size(): 0 +2/28/22 7:18:25 PM :Info: dirtyData.size(): 0 +2/28/22 7:18:25 PM :Debug: Flush lasted: 78ms. +2/28/22 7:18:25 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:18:25 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:18:25 PM :Info: Queueing burn to page:1 +2/28/22 7:18:25 PM :Debug: Burn time:257ms. +2/28/22 7:18:25 PM :Debug: burned page 1 +2/28/22 7:18:25 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:18:25 PM :Debug: CRC matches for page 1:xCC xF0 xF7 x2C ..., +2/28/22 7:18:26 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:18:26 PM :Info: Time to save msq: 4.2678 +2/28/22 7:18:26 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:18:37 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:18:37 PM :Info: Time to save msq: 3.797 +2/28/22 7:18:37 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:18:37 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:18:37 PM :Info: Time to save msq: 3.1434 +2/28/22 7:18:37 PM :Info: DBW_code_26.10.2021 Tune Saved! +2/28/22 7:18:37 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:18:40 PM :Debug: File Not Found for signature: C:\Program Files (x86)\EFIAnalytics\TunerStudioMS\2022-02-28_18.35.22.msq +2/28/22 7:18:40 PM :Debug: File Not Found for signature: C:\Program Files (x86)\EFIAnalytics\TunerStudioMS\2022-02-28_19.09.11.msq +2/28/22 7:18:43 PM :Debug: File Not Found for signature: C:\Users\v0stap\Desktop\DBW_code_26.10.2021\2022-02-28_19.09.11.msq +2/28/22 7:18:43 PM :Debug: EcuConfigName for Save:DBW_code_26.10.2021 +2/28/22 7:18:43 PM :Info: file:2022-02-28_19.09.11.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:18:43 PM :Debug: File does not exist, creating new: +C:\Users\v0stap\Desktop\DBW_code_26.10.2021\2022-02-28_19.09.11.msq +2/28/22 7:18:43 PM :Info: Time to save msq: 15.4426 +2/28/22 7:18:43 PM :Info: DBW_code_26.10.2021 Tune Saved! +2/28/22 7:18:43 PM :Info: file:2022-02-28_19.09.11.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:19:48 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:19:48 PM :Info: Initiating read page 1 : 26:824 +2/28/22 7:19:48 PM :Debug: CRC matches for page 1:xCC xF0 xF7 x2C ..., +2/28/22 7:19:48 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:19:51 PM :Info: dirtyData.size(): 0 +2/28/22 7:19:51 PM :Info: dirtyData.size(): 0 +2/28/22 7:19:51 PM :Debug: Flush lasted: 78ms. +2/28/22 7:19:51 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:19:51 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:19:51 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:19:52 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:19:54 PM :Debug: Received Instruction: Read Chunk 1, Page: 1 +2/28/22 7:19:54 PM :Info: Initiating read page 1 : 14:834 +2/28/22 7:19:54 PM :Debug: CRC matches for page 1:xCC xF0 xF7 x2C ..., +2/28/22 7:19:54 PM :Info: CrC matched skipped controller read on page:0 +2/28/22 7:20:11 PM :Debug: Received Instruction: Write byte, Page: 1 +2/28/22 7:20:11 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:11 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:11 PM :Debug: Flush lasted: 54ms. +2/28/22 7:20:11 PM :Debug: Burn Page anonymous: 1 +2/28/22 7:20:11 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:20:11 PM :Info: Queueing burn to page:1 +2/28/22 7:20:11 PM :Debug: Burn time:256ms. +2/28/22 7:20:11 PM :Debug: burned page 1 +2/28/22 7:20:11 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:20:11 PM :Debug: CRC matches for page 1:x0D x93 x48 x3A ..H: +2/28/22 7:20:12 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:12 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:12 PM :Debug: Flush lasted: 77ms. +2/28/22 7:20:12 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:20:12 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:20:12 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:20:12 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:20:13 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:20:13 PM :Info: Time to save msq: 6.4333 +2/28/22 7:20:13 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:20:16 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:16 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:16 PM :Debug: Flush lasted: 71ms. +2/28/22 7:20:16 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:20:16 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:20:16 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:20:16 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:20:16 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:16 PM :Info: dirtyData.size(): 0 +2/28/22 7:20:16 PM :Debug: Flush lasted: 83ms. +2/28/22 7:20:16 PM :Debug: Burn Page anonymous: -1 +2/28/22 7:20:16 PM :Debug: Received Instruction: , Page: 1 +2/28/22 7:20:16 PM :Info: skip burn to page:1, lastWritePage = -2 +2/28/22 7:20:16 PM :Debug: Request to burn page, but no writes have been performed. Ignoring burn. page: 1 +2/28/22 7:27:23 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:27:24 PM :Info: Re-establishing connection to: RS232: Port:COM5, Baud:115200 +2/28/22 7:27:25 PM :Debug: controllerOnline = 0.0 +2/28/22 7:27:25 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:27:25 PM :Debug: Went offline +2/28/22 7:27:25 PM :Debug: controllerOnline = 0.0 +2/28/22 7:27:25 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:27:25 PM :Info: Went offline 2 +2/28/22 7:29:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:29:55 PM :Info: Time to save msq: 5.5071 +2/28/22 7:29:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:29:55 PM :Info: closeApp Called +2/28/22 7:29:55 PM :Debug: TuneLog Editor set text +2/28/22 7:29:55 PM :Info: Data log stopped +2/28/22 7:29:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot pause Monitoring of it. +2/28/22 7:29:55 PM :Info: Time to save msq: 3.616 +2/28/22 7:29:55 PM :Info: file:CurrentTune.msq is not Monitored, cannot unpause Monitoring of it. +2/28/22 7:29:55 PM :Debug: goOffline Starting, Time:0 +2/28/22 7:29:55 PM :Info: Deactivated Turbo Baud, goOffline +2/28/22 7:29:55 PM :Debug: goOffline about to stopProcessing, Time:0 +2/28/22 7:29:55 PM :Debug: goOffline closed port, Time:0 +2/28/22 7:29:56 PM :Info: FileOutputStream Closed. +2/28/22 7:29:56 PM :Info: DBW_code_26.10.2021 ComThread stopped COMM Thread23701.072868971616 +2/28/22 7:29:56 PM :Debug: goOffline comm thread stopped, Time:1023 +2/28/22 7:29:56 PM :Debug: No Remaining Queue Write instructions +2/28/22 7:29:56 PM :Debug: removing Configuration: DBW_code_26.10.2021 +2/28/22 7:29:56 PM :Info: No Persistor set, not saving active triggers. +2/28/22 7:29:56 PM :Debug: ############################################# Save Project Backup ########################################## +2/28/22 7:29:56 PM :Info: Finalizing Sensors +Saved user properties successfully diff --git a/DBW_V2/mainController.ini b/DBW_V2/mainController.ini new file mode 100644 index 0000000..b1559a5 --- /dev/null +++ b/DBW_V2/mainController.ini @@ -0,0 +1,787 @@ +;------------------------------------------------------------------------------- +; Set all config variables are visible +#set USE_CRC_DATA_CHECK +#set CAN_PASSTHROUGH + + + + +[MegaTune] + + MTversion = 2.25 ; MegaTune itself; needs to match exec version. + +#if CAN_PASSTHROUGH + ; Big endian format for CAN comms!!!!! + versionInfo = "r\$tsCanId\x0e\x00\x00\x00\x14" ; Title bar + queryCommand = "r\$tsCanId\x0f\x00\x00\x00\x14" ; Verify against signature. + ;signature = "DMLab DBW V2.00 " ; ECU sends a null at 20th byte. + +#else +; little endian format for serial comms + versionInfo = "r\$tsCanId\x0e\x00\x00\x14\x00" ; Title bar + queryCommand = "r\$tsCanId\x0f\x00\x00\x14\x00" ; Verify against signature. + +;using valid signature for development purpose only. MUST BE DELETED OR CORRECTED in realese + ;signature = "speeduino dbw_v0.80" ; ECU sends a null at 20th byte. + +#endif + +signature = "speeduino DBW 2.0.0" +;signature = "MS3 test signature " + + +;------------------------------------------------------------------------------- +[TunerStudio] + iniSpecVersion = 3.0 + +[PcVariables] + ; valid types: boolean, double, int, list + ; + ; no offset as they are local variables. + ; entry format the same as Constants, except there is no offset. + ; arrays are not yet supported. + ; name = class, type, shape, units, scale, translate, lo, hi, digits + ; name = type, min, max; + ; + ; type List: value will be index. + + ;tsCanId = bits, U08, [0:3] ; The short one, just numbers + tsCanId = bits, U08, [0:3], "CAN ID 0", "CAN ID 1", "CAN ID 2", "CAN ID 3", "CAN ID 4", "CAN ID 5", "CAN ID 6", "CAN ID 7", "CAN ID 8", "CAN ID 9", "CAN ID 10","CAN ID 11","CAN ID 12","CAN ID 13","CAN ID 14","INVALID" + +[ReferenceTables] + + + +[Constants] + + + pageActivationDelay = 256 + blockReadTimeout = 256 + tsWriteBlocks = on + writeBlocks = on + interWriteDelay = 0 + + + + + endianness = little + nPages = 1 + pageSize = 856 + + + pageIdentifier = "\$tsCanId\x01" + burnCommand = "b\$tsCanId\x01" + pageReadCommand = "r\$tsCanId\x01%2o%2c" + pageValueWrite = "w\$tsCanId\x01\%2o%2c%v" +#if USE_CRC_DATA_CHECK + crc32CheckCommand = "k\$tsCanId\x01\x00\x00\x00\x00" +#endif + + + + +blockingFactor = 2048 + + + page = 1 + ; name =class, type, offset, shape, units, scale, translate, lo, hi, digits + + +pps_calc_option =bits, U08, 0, [0:0], "Linear","Polynomal"; +tps_calc_option =bits, U08, 1, [0:0], "Linear","Polynomal"; + +pps1_min =scalar, U16, 2, "ADC", 1, 0, 0, 4095, 0; +pps1_max =scalar, U16, 4, "ADC", 1, 0, 0, 4095, 0; +pps2_min =scalar, U16, 6, "ADC", 1, 0, 0, 4095, 0; +pps2_mid =scalar, U16, 8, "ADC", 1, 0, 0, 4095, 0; +pps2_mid_pct =scalar, U16, 10, "%", 0.1, 0, 0, 100, 1; +pps2_max =scalar, U16, 12, "ADC", 1, 0, 0, 4095, 0; + +tps1_min =scalar, U16, 14, "ADC", 1, 0, 0, 4095, 0; +tps1_max =scalar, U16, 16, "ADC", 1, 0, 0, 4095, 0; +tps2_min =scalar, U16, 18, "ADC", 1, 0, 0, 4095, 0; +tps2_mid =scalar, U16, 20, "ADC", 1, 0, 0, 4095, 0; +tps2_mid_pct =scalar, U16, 22, "%", 0.1, 0, 0, 100, 1; +tps2_max =scalar, U16, 24, "ADC", 1, 0, 0, 4095, 0; + +pps2tps_option =bits, U08, 26, [0:0], "Curve","MS3 CAN bus"; +idle_input_option =bits, U08, 27, [0:1], "Disabled","PWM input 1", "PWM input 2", "MS2/3 CAN Advanced BSCT"; + + +pps_bins =array, S16, 28, [16], "%", 0.1, 0, -10, 110, 1; +tps_bins =array, S16, 60, [16], "%", 0.1, 0, -10, 110, 1; + + +idle_input_bins=array, S16, 92, [8], "%", 0.1, 0, 0, 100, 1; +idle_tps_adder_bins=array, S16, 108, [8], "%", 0.1, 0, -30, 30, 1; + +;124 +motor_pwm_fq =scalar, U16, 124, "Hz", 1, 0, 300, 5000, 0; +motor_ctl_period=scalar, U16, 126, "mS", 1, 0, 1, 100, 0; +motor_pid_option=bits, U16, 128, [0:1], "STATIC", "STATIC FW-RW", "TABLE", "INVALID" ; + + + +motor_fw_p =scalar, S16, 130, "", 0.001, 0, -1, 5, 3 +motor_fw_i =scalar, S16, 132, "", 0.001, 0, -1, 5, 3 +motor_fw_d =scalar, S16, 134, "", 0.001, 0, -1, 5, 3 +motor_rw_p =scalar, S16, 136, "", 0.001, 0, -1, 5, 3 +motor_rw_i =scalar, S16, 138, "", 0.001, 0, -1, 5, 3 +motor_rw_d =scalar, S16, 140, "", 0.001, 0, -1, 5, 3 + + + + +motor_p_tps_bins=array, S16, 142, [16], "%", 0.1, 0, -10, 110, 1; +motor_p_error_bins=array, S16, 174, [16], "%", 0.1, 0, -100, 100, 1; +motor_p_table =array, S16, 206, [16x16], "", 0.001, 0, -1; 5, 3; +;720 + +i_limmit =scalar, S16, 718, "%", 0.01, 0, 0, 100, 1; +motor_dc_max =scalar, S16, 720, "%", 0.01, 0, 0, 100, 1; +motor_dc_min =scalar, S16, 722, "%", 0.01, 0, -100, 0, 1; + + + + +tps_dc_tps_bins=array, S16, 724, [16], "%", 0.1, 0, -10, 110, 1; +tps_dc_offset_bins=array, S16, 756, [16], "%", 0.01, 0, -50, 70, 1; +;790 + +vbat_bins =array, U16, 788, [8], "V", 0.0062842, 0, 0, 25, 1; +motor_pwm_corr_bins=array, S16, 804, [8], "%", 0.1, 0, -100, 200, 1; +pwm_deadtime =scalar, U16, 820, "uS", 1, 0, 0, 500, 0; + +can_dbw_id =scalar, U16, 822, "", 1, 0, 1, 2040, 0; +can_idle_base_id=scalar, U16, 824, "", 1, 0, 1, 1983, 0; + +config_bits_agreement =bits, U16, 826, [0:0], "Disagree", "Agree"; +config_bits_calibrated =bits, U16, 826, [1:1], "Not calibrated", "Calibrated"; +config_bits_safety =bits, U16, 826, [3:3], "Disabled", "Enabled"; + +pps1_margin =scalar, U16, 828, "ADC", 1, 0, 0, 500, 0; +pps2_margin =scalar, U16, 830, "ADC", 1, 0, 0, 500, 0; +pps_delta_margin =scalar, S16, 832, "%", 0.1, 0, 0, 500, 1; + + +tps1_margin =scalar, U16, 834, "ADC", 1, 0, 0, 500, 0; +tps2_margin =scalar, U16, 836, "ADC", 1, 0, 0, 500, 0; +tps_delta_margin =scalar, S16, 838, "%", 0.1, 0, 0, 500, 1; + + +tps_error_margin1 =scalar, S16, 840, "%", 0.1, 0, 0, 200, 1; +tps_error_time1 =scalar, U16, 842, "mS", 1, 0, 0, 10000, 0; + + +tps_error_margin2 =scalar, S16, 844, "%", 0.1, 0, 0, 200, 1; +tps_error_time2 =scalar, U16, 846, "mS", 1, 0, 0, 10000, 0; + +;848 + +can_dbw_poll_perod =scalar, U16, 848, "mS", 1, 0, 3, 50, 0; + + +can_ms29bit_id =scalar, U08, 850, "", 1, 0, 1, 14, 0; +can_ms29bit_options =bits, U08, 851, [0:0], "Disabled", "Enabled" ; + + +can_bcst_data_enable=bits, U08, 852, [0:0], "Disabled", "Enabled" ; +can_bcst_data_period=scalar, U08, 853, "mS", 1, 0, 10, 200, 0; +can_bcst_canid =scalar, U16, 854, "", 1, 0, 1, 2047, 0; + +;856 + + + +[Menu] + + menuDialog = main + menu = "Controller Calibration" + subMenu = setup_c, "Configure this first !!!!" + subMenu =pps_cal, "PPS Calibration" + subMenu =tps_cal, "TPS Calibration" + subMenu =gen, "General Settings" + subMenu =pps2tps_c, "TPS Target" + subMenu = Ptable,"Proportional gain table", {motor_pid_option ==2} + subMenu =idle_c, "Idle Control TPS adder", {idle_input_option !=0} + subMenu = dc_c, "DC Bias correction" + subMenu = vbat_c, "Battery voltage compensation" + subMenu = can, "CAN bus settings" + + + + + + + + + + + +[ControllerCommands] +; + cmd_apply = "z\$tsCanId\x01\x00\x00\x00\x01" + cmd_tesmode_on = "z\$tsCanId\x01\x00\x00\x00\x02" + cmd_tesmode_off = "z\$tsCanId\x01\x00\x00\x00\x03" + cmd_autocal = "z\$tsCanId\x01\x00\x00\x00\x04" + + + + + + +;------------------------------------------------------------------------------- + +[UserDefined] +; define a MegaTune compatible version here +; no need to for std_enrichments, it is built in. + +;Testmode +;------------------------------------------------------------------------------ + + ;dialog = outputTestbuttons1a, "", xAxis + ;commandButton = "Label Text", command, { Enabled Condition }, optionalFlags + ; The rem > 0 expression is just for testing.. It works when the MS is on the Stim with rpm. + ; a status bit there would be the expected real expression + ;commandButton = "Enable Test Mode", cmdEnterTestMode, { (!(status3 & 8)) && (rpm == 0)} + + ; if clickOnCloseIfEnabled is set, then the command assigned to this button will be run on the + ; dialog close, but only if the enable condition is true + ; valid click flags are: + ; clickOnCloseIfEnabled - the command will be sent on dialog close if active condition is true + ; clickOnCloseIfDisabled - the command will be sent on dialog close if active condition is false + ; clickOnClose - the command will be sent on dialog close always + + + + +dialog = can_dbw, "Megasquirt 3 DBW integration" + + field= "Tuning using MS CAN 29bit protocol", can_ms29bit_options + field= "Device ID on MS CAN [1..14]", can_ms29bit_id, {can_ms29bit_options==1} + +dialog = can_bcst, "Data broadcast to CAN" + + field = "Broadcast my data to CAN",can_bcst_data_enable + field = "Data broadcast period",can_bcst_data_period, {can_bcst_data_enable==1} + field = "Base ID for broadcast",can_bcst_canid , {can_bcst_data_enable==1} + + +dialog = can, "CAN bus settings" + panel = can_dbw + panel = can_bcst + + +;################################# +;PPS + + + + + + +dialog = safety_c, "Safety Functions" + field = "Safety Functions include TPS and PPS" + field = "ADC range checking. As well calculated position difference checking" + field = "on out of bound conditions DBW motor is unpowered" + field = "and controller enters in fault state." + field = "Configure PID regulator properly, " + field = "incorrect PID coeficients can led to uncontroled " + field = "throttle movement, which currently is not checked" + field = "However You can specify time and precision for throttle to" + field = "achieve target position" + field = "Safety features", config_bits_safety + +dialog = agreement_c, "Agreement" + field = "This is experimental device!!!" + field = "This device cannot be used in safety critical applications" + field = "NOT TO BE USED ON PUBLIC ROAD VEHICLES!!!" + field = "NO ANY WARRANTY OR LIABILITY !!!" + field = "Select if You acept these terms" + field = "You are using this device on YOUR OWN LIABILITY" + field = "Please be responsible for what You are doing." + field = "Configure device properly and turn on safety functions" + field = "", config_bits_agreement; + + +dialog = setup_c, "" + panel = agreement_c + panel = safety_c + +dialog = pps1_g,"", xAxis + gauge = pps1_adc_g + gauge = pps1_g + +dialog = pps2_g,"", xAxis + gauge = pps2_adc_g + gauge = pps2_g + +dialog = pps_g,"", xAxis + gauge = pps_delta_g + gauge = pps_g + +dialog = pps_gauges, "", yAxis + panel = pps1_g + panel = pps2_g + panel = pps_g + +dialog = pps_s, "Safety Settings" + field = "ADC count permitted above PPS1 100% adc count" + field = "or below PPS1 0% count" + field = "",pps1_margin + field = "ADC count permitted above PPS2 100% adc count" + field = "or below PPS2 0% count" + field = "",pps2_margin + ;field = Maximum difference % between PPS1 and PPS2 + field = "Maximum difference % between PPS1 and PPS2",pps_delta_margin + + +dialog = pps_p,"" + field = "PPS1 0% ADC count", pps1_min; + field = "PPS1 100% ADC count", pps1_max; + ;field = "PPS2 calculation method", pps_calc_option; + field = "PPS2 0% ADC count", pps2_min; + ;field = "PPS2 middle position", pps2_mid_pct, {pps_calc_option == 1}; + ;field = "PPS2 middle ADC count", pps2_mid, {pps_calc_option == 1}; + field = "PPS2 100% ADC count", pps2_max; + commandButton = "Apply", cmd_apply + field = "Switch on test mode to enable sensors" + commandButton = "TEST MODE ON", cmd_tesmode_on , {} + commandButton = "TEST MODE OFF", cmd_tesmode_off + panel = pps_s + + + + + + + +dialog = pps_cal, "PPS Calibration",xAxis + panel = pps_p + panel = pps_gauges + + + +dialog = tps_s, "Safety Settings" + field = "ADC count permitted above TPS1 100% adc count" + field = "or below TPS1 0% count" + field = "",tps1_margin + field = "ADC count permitted above TPS2 100% adc count" + field = "or below TPS2 0% count" + field = "",tps2_margin + ;field = Maximum difference % between TPS1 and TPS2 + field = "Maximum difference % between TPS1 and TPS2",tps_delta_margin + field = "Movement control 1" + field = "Time to reach target position", tps_error_time1 + field = "Precision to be achieved in specified time", tps_error_margin1 + field = "Movement control 2" + field = "Time to reach target position", tps_error_time2 + field = "Precision to be achieved in specified time", tps_error_margin2 + + + + +;################################# +;TPS + +dialog = tps1_g,"", xAxis + gauge = tps1_adc_g + gauge = tps1_g + +dialog = tps2_g,"", xAxis + gauge = tps2_adc_g + gauge = tps2_g + +dialog = tps_g,"", xAxis + gauge = tps_delta_g + gauge = tps_g + +dialog = tps_gauges, "", yAxis + panel = tps1_g + panel = tps2_g + panel = tps_g + +dialog = tps_p, "TPS Calibration", + + field = "TPS1 0% ADC count", tps1_min; + field = "TPS1 100% ADC count", tps1_max; + ;field = "TPS2 calculation method", tps_calc_option; + field = "TPS2 0% ADC count", tps2_min; + ;field = "TPS2 middle position", tps2_mid_pct; + ;field = "TPS2 middle ADC count", tps2_mid; + field = "TPS2 100% ADC count", tps2_max; + commandButton = "Apply", cmd_apply + commandButton = "TEST MODE ON", cmd_tesmode_on + commandButton = "TEST MODE OFF", cmd_tesmode_off + commandButton = "Autocalibrate TPS", cmd_autocal , + panel = tps_s + + +dialog = tps_cal, "TPS Calibration",xAxis + panel = tps_p + panel = tps_gauges + + + + + + +dialog = gen, "General Settings" + field = "PPS and TPS sensors are", config_bits_calibrated + field = "TPS target calculation", pps2tps_option + field = "MS3 DBW base CAN ID [decimal]", can_dbw_id, {pps2tps_option==1} + field = "TPS target poll period",can_dbw_poll_perod,, {pps2tps_option==1} + field = "Idle Control",idle_input_option + field = "MS2/MS3 BCST base CAN ID [decimal]", can_idle_base_id, {idle_input_option == 3} + field = "Motor PWM Frequency",motor_pwm_fq + field = "PID Control Period", motor_ctl_period + field = "PID Coefiicients",motor_pid_option + field = "Static/Forward P", motor_fw_p,{motor_pid_option <2} + field = "Static/Forward I",motor_fw_i + field = "Static/Forward D",motor_fw_d + field = "Backward P",motor_rw_p,{motor_pid_option ==1} + field = "Backward I",motor_rw_i,{motor_pid_option ==1} + field = "Backward D",motor_rw_d,{motor_pid_option ==1} + field = "Integral limit +/-",i_limmit + field = "Maximum PWM",motor_dc_max + field = "Minimum PWM",motor_dc_min + field = "Motor freewheel time", pwm_deadtime + + + + + + + + + + + +[UserDefinedTS] + + +[CurveEditor] + + +curve = pps2tps_c, "TPS Target" + columnLabel = "Pedal position", "Throttle Position" + xAxis = -10, 110, 12 + yAxis = -10, 110, 12 + xBins = pps_bins, pps + yBins = tps_bins + +curve = idle_c, "Idle TPS Target adder" + columnLabel = "Idle input", "TPS target modifier" + xAxis = 0, 100, 10 + yAxis = -10, 10, 10 + xBins = idle_input_bins, idle_dc + yBins = idle_tps_adder_bins + +curve = dc_c, "DC Bias" + columnLabel = "Throttle Position", "DC Bias" + xAxis = 0, 100, 10 + yAxis = -10, 10, 10 + xBins = tps_dc_tps_bins, tps + yBins = tps_dc_offset_bins + +curve = vbat_c, "Battery voltage correction" + columnLabel = "Battery Voltage", "Correction" + xAxis = 0, 25, 10 + yAxis = -200, 200, 10 + xBins = vbat_bins, vbat + yBins = motor_pwm_corr_bins + + + + + +[TableEditor] + ; table_id, map3d_id, "title", page + + ; table = tKnockNoiceRefTable, mKnockNoiceRefTable, "Knock Noice Refference Table", 1 ; constant, variable + ; xBins = KnockNoiceRpmBins, rpm + ; yBins = KnockNoiceLoadBins, ignload + ; zBins = KnockNoiceRefTable + + ; upDownLabel = "RICHER", "LEANER" + ; gridHeight = 2.0 + ; gridOrient = 250, 0, 340 ; Space 123 rotation of grid in degrees. + + + ; table_id, map3d_id, "title", page + + table = Ptable, Ptablemap, "P table", 1 + xBins = motor_p_tps_bins, tps + yBins = motor_p_error_bins, tps_error + zBins = motor_p_table + gridHeight = 1.0 + gridOrient = 250, 0, 340 ; + upDownLabel = "(More)", "(Less)" + + + + +;------------------------------------------------------------------------------- + +[GaugeConfigurations] + + ;------------------------------------------------------------------------------- + ; Notes on some of the gauges. + ; + ; The accelEnrichGauge is now a composite of both acceleration enrichment + ; and deceleration enleanment numbers. See the definition of the variable + ; accDecEnrich in the OutputChannels section. + ; + ; David Hooke contributed the lambda gauge and associated transfer + ; function files. + ; + ; "The lambda gauge is the best way (my opinion) to report data from a + ; wide band EGO gauge, it standardizes the output irrespective of fuel + ; or mix of fuels, so you needn't do any brainwork to know if your 75% + ; gasoline and 25% methanol is rich at 10:1 or not. + ; + ; "Use the file WBlambda100AVR.inc, if using a standard ADC (e.g., AVR cpu). + ; Use the file WBlambda100MOT.inc, if using a biased ADC (e.g., MOT cpu)." + ;------------------------------------------------------------------------------- + ; Define a gauge's characteristics here, then go to a specific layout + ; block (Tuning or FrontPage) and use the name you've defined here to + ; display that gauge in a particular position. + ; + ; Name = Case-sensitive, user-defined name for this gauge configuration. + ; Var = Case-sensitive name of variable to be displayed, see the + ; OutputChannels block in this file for possible values. + ; Title = Title displayed at the top of the gauge. + ; Units = Units displayed below value on gauge. + ; Lo = Lower scale limit of gauge. + ; Hi = Upper scale limit of gauge. + ; LoD = Lower limit at which danger color is used for gauge background. + ; LoW = Lower limit at which warning color is used. + ; HiW = Upper limit at which warning color is used. + ; HiD = Upper limit at which danger color is used. + ; vd = Decimal places in displayed value + ; ld = Label decimal places for display of Lo and Hi, above. + + ;Name Var Title Units Lo Hi LoD LoW HiW HiD vd ld + + + +; uptime_gauge =uptime, "Uptime Gauge", "S", 0, 3600, 0, 0, 100000, 100000, 0, 0; + +; lambda_gauge =lambda, "Lambda", "", 0.6, 1.15, 0.7, 0.8, 1.3, 1.5, 3, 3; +; afr_gague =AFR, "AFR Gauge", "", 10, 20, 10.5, 11.5, 15.5, 16, 2, 2; +; s_AFR_gauge =s_AFR, "AFR Gauge", "", 10, 20, 10.5, 11.5, 15.5, 16, 2, 2; + + +clock_g =clock, "Uptime", "S", 0, 3600, 0, 0, 100000, 100000, 1, 1; + +status0_g =status0, "STATUS 0", "", 0, 10000, 0, 0, 10000, 10000, 0, 0; +status1_g =status1, "STATUS 1", "", 0, 10000, 0, 0, 10000, 10000, 0, 0; +status2_g =status2, "STATUS 2", "", 0, 10000, 0, 0, 10000, 10000, 0, 0; +status3_g =status3, "STATUS 3", "", 0, 10000, 0, 0, 10000, 10000, 0, 0; + +pps1_adc_g =pps1_adc, "PPS1 ADC", "", 0, 4095, 0, 0, 4095, 4095, 0, 0; +pps2_adc_g =pps2_adc, "PPS2 ADC", "", 0, 4095, 0, 0, 4095, 4095, 0, 0; +tps1_adc_g =tps1_adc, "TPS1 ADC", "", 0, 4095, 0, 0, 4095, 4095, 0, 0; +tps2_adc_g =tps2_adc, "TPS1 ADC", "", 0, 4095, 0, 0, 4095, 4095, 0, 0; +motor_current_adc_g=motor_current_adc, "Motor Current ADC","", 0, 4095, 0, 0, 4095, 4095, 0, 0; +motor_current_g =motor_current, "Motor Current","A", 0, 8, 0, 0, 5, 6.5, 2, 2; +vbat_adc_g =vbat_adc, "PPS1 ADC", "", 0, 4095, 0, 0, 4095, 4095, 0, 0; +vbat_g =vbat, "Battery Voltage","V", 5, 20, 0, 6.5, 15.5, 18, 1, 1; + + + +pps1_g =pps1, "PPS1", "%", 0, 100, 0, 0, 100, 100, 1, 1; +pps2_g =pps2, "PPS2", "%", 0, 100, 0, 0, 100, 100, 1, 1; +tps1_g =tps1, "TPS1", "%", 0, 100, 0, 0, 100, 100, 1, 1; +tps2_g =tps2, "TPS2", "%", 0, 100, 0, 0, 100, 100, 1, 1; +pps_g =pps, "PPS", "%", 0, 100, 0, 0, 100, 100, 1, 1; +tps_g =tps, "TPS", "%", 0, 100, 0, 0, 100, 100, 1, 1; +tps_error_g =tps_error, "TPS ERROR", "%", -30,30, -30,-10,10, 30, 1, 1; +motor_pwm_g =motor_pwm, "Motor PWM", "%", -100,100, -100, -100,100,100, 1, 1; +idle_dc_g =idle_dc, "Idle input", "%", 0,100, 5, 7, 92, 97, 1, 1; +pps_delta_g =pps_delta, "PPS delta", "%", -10, 10, -7, -3, 3, 7, 1, 1; +tps_delta_g =tps_delta, "TPS Delta", "%", -10, 10, -7, -3, 3, 7, 1, 1; +tps_target_g =tps_target, "TPS Target", "%", 0, 100, 0, 0, 100, 100, 1, 1; +;------------------------------------------------------------------------------- + +[FrontPage] + + gauge1 = pps1_g + gauge2 = pps2_g + gauge3 = pps_g + gauge4 = tps1_g + gauge5 = tps2_g + gauge6 = tps_g + gauge7 = vbat_g + gauge8 = motor_current_g + + ;---------------------------------------------------------------------------- + ; Indicators + ; expr off-label on-label, off-bg, off-fg, on-bg, on-fg + ; indicator = { tpsaen }, "Not Accelerating", "AE", cyan, white, red, black + ; + + ;indicator = { controller_status & 1} , "OK", "OK", white, black, green, black +; indicator = { controller_status & 2} , "FAULT", "FAULT", white, black, green, black + +;controller_error_code =scalar, U16, 8, "", 1, 0; +;controller_status =scalar, U32, 0, "", 1, 0; + +;#define DBW_STATUS0_READY_F 0x1 +;#define DBW_STATUS0_AGREEMENT_F 0x2 +;#define DBW_STATUS0_SENSOR_CAL_F 0x4 +;#define DBW_STATUS0_FAULT_F 0x8 +;#define DBW_STATUS0_CAN_MSDBW_F 0x10 +;#define DBW_STATUS0_CAN_RX_BCST_F 0x20 +;#define DBW_STATUS0_PWM_IDLE_F 0x40 +;#define DBW_STATUS0_GPI1_F 0x80 +;#define DBW_STATUS0_GPI2_F 0x100 +;#define DBW_STATUS0_GPO1_F 0x200 +;#define DBW_STATUS0_GPO2_F 0x400 +;#define DBW_STATUS0_PPSTPS_CAL_F 0x800 +;#define DBW_STATUS0_UNPROTECTED_F 0x1000 +;#define DBW_STATUS0_CONF_ERROR_F 0x2000 +;#define DBW_STATUS0_SENSOR_FAULT_F 0x4000 + + + + + +indicator = { status0 & 1} , "READY", "NOT READY", white, black, red, black ; + +indicator = { status0 & 8} , "DRIVER FAULT", "DRIVER OK", white, black, red, black +indicator = { status0 & 16} , "MS3 DBW CAN OK", "MS3 DBW CAN FAULT", white, black, red, black +indicator = { status0 & 32} , "IDLE CAN OK", "IDLE CAN FAULT", white, black, red, black +indicator = { status0 & 64} , "PWM IDLE INPUT", "PWM IDLE INPUT FAULT", white, black, red, black +indicator = { status0 & 128} , "GPI1", "GPI1", white, black, red, black +indicator = { status0 & 256} , "GPI2", "GPI2", white, black, red, black +indicator = { status0 & 512} , "GPO1", "GPO1", white, black, red, black +indicator = { status0 & 1024} , "GPO2", "GPO2", white, black, red, black +indicator = { status0 & 2048} , "Autocalicration", "Autocalicration", white, black, red, black +indicator = { status0 & 4096} , "Protected", "Unprotected", white, black, red, black ; +indicator = { status0 & 8192} , "Config Error", "Config Error", white, black, red, black +indicator = { status0 & 16384} , "Sensors OK", "Sensor Fault", white, black, red, black +;indicator = { status0 & 32768} , "GPO2", "GPO2", white, black, red, black + + +indicator = { status1 & 0x0001} , "Saftey Disabled", "Safety Enabled", red, red, green, green; +indicator = { status0 & 2} , "NO AGGEEMENT", "AGREEMENT OK", white, red, white, green +indicator = { status0 & 4} , "NOT CALIBRATED", "CALIBRATED", white, black, red, black + + + + +;------------------------------------------------------------------------------- + + +[RunTime] +; barHysteresis = 2.5 ; Seconds +;#if CELSIUS +; coolantBar = -40, 100 +; matBar = -40, 100 +;#else +; coolantBar = -40, 215 +; matBar = -40, 215 +;#endif +; +; batteryBar = 6, 15 +; dutyCycleBar = 0, 100 +;#if NARROW_BAND_EGO +; egoBar = 0, 1.0 +;#else +; egoBar = 0, 5.0 +;#endif +; gammaEBar = 0, 200 +; mapBar = 0, 255 +; pulseWidthBar = 0, 25.5 +; rpmBar = 0, 8000 +; throttleBar = 0, 100; +; +; egoCorrBar = 0, 200 +; baroCorrBar = 0, 200 +; warmupCorrBar = 0, 200 +; airdenCorrBar = 0, 200 +; veCorrBar = 0, 200 +; accCorrBar = 0, 100 + +;------------------------------------------------------------------------------- + +;[Tuning] +;------------------------------------------------------------------------------- + +[OutputChannels] + ; The number of bytes MegaTune should expect as a result + ; of sending the "A" command to MegaSquirt is determined + ; by the value of ochBlockSize, so be very careful when + ; you change it. + + deadValue = { 0 } ; Convenient unchanging value. + +#if CAN_PASSTHROUGH + ochGetCommand = "r\$tsCanId\x07%2o%2c" ; leave this alone +#else +; fast get via serial + ochGetCommand = "A" +#endif + + + ochBlockSize = 48 + + + +clock =scalar, U32, 0, "S", 0.001, 0; +status0 =scalar, U16, 4, "", 1, 0; +status1 =scalar, U16, 6, "", 1, 0; +status2 =scalar, U16, 8, "", 1, 0; +status3 =scalar, U16, 10, "", 1, 0; + +pps1_adc =scalar, U16, 12, "", 1, 0; +pps2_adc =scalar, U16, 14, "", 1, 0; +tps1_adc =scalar, U16, 16, "", 1, 0; +tps2_adc =scalar, U16, 18, "", 1, 0; +motor_current_adc =scalar, U16, 20, "", 1, 0; +motor_current =scalar, U16, 20, "", 0.0028727, 0; +vbat_adc =scalar, U16, 22, "", 1, 0; +vbat =scalar, U16, 22, "V", 0.0062842, 0; + + + +pps1 =scalar, S16, 24, "%", 0.1, 0; +pps2 =scalar, S16, 26, "%", 0.1, 0; +tps1 =scalar, S16, 28, "%", 0.1, 0; +tps2 =scalar, S16, 30, "%", 0.1, 0; +pps =scalar, S16, 32, "%", 0.1, 0; +tps =scalar, S16, 34, "%", 0.1, 0; +tps_error =scalar, S16, 36, "%", 0.1, 0; +motor_pwm =scalar, S16, 38, "%", 0.01, 0; +idle_dc =scalar, U16, 40, "%", 0.1, 0; +pps_delta =scalar, S16, 42, "%", 0.1, 0; +tps_delta =scalar, S16, 44, "%", 0.1, 0; +tps_target =scalar, S16, 46, "%", 0.1, 0; + + +;48 +;------------------------------------------------------------------------------- + +[Datalog] + ; Full datalog. + ; + ; Default user-defined log emulates the full datalog. + ; + ; The entries are saved in the datalog file in the order in + ; which they appear in the list below. + ; + ; Channel - Case sensitive name of output channel to be logged. + ; Label - String written to header line of log. Be careful + ; about changing these, as programs like MSLVV and + ; MSTweak key off specific column names. + ; Type - Data type of output, converted before writing. + ; Format - C-style output format of data. + ; + ; Channel Label Type Format + ; -------------- ---------- ----- ------ + ;entry = uptime, "Up_time", float, "%.3f" + ;entry =controller_status, "Controller Status", decimal, "%d" + ;entry =uptime, "Time", float, "%f" + +