/*
 * inputs.c
 *
 *  Created on: Mar 15, 2022
 *      Author: v0stap
 */

//Includes
#include "main.h"
//Variables
uint32_t counter0 = 0, counter1 = 0, Counter = 0;
uint8_t gap = 0;
// idle in section
void TIM3_Init(void) { //configure IN1 as Iddle input PB4 TIM3
	// PB4 AF1 TIM3 Input1
	RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
	GPIOB->MODER &= ~(3 << (4 * 2));
	GPIOB->MODER |= (2 << (4 * 2));
	GPIOB->OTYPER &= ~(1 << 4 * 1);
	GPIOB->OSPEEDR &= ~(3 << (4 * 2));
	GPIOB->PUPDR &= ~(3 << (4 * 2));
	GPIOB->AFR[0] &= ~(15 << (4 * 4));
	GPIOB->AFR[0] |= (1 << (4 * 4));
	RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
	/* (1) Select the active input TI1 for TIM3_CCR1 (CC1S = 01),
	 select the active input TI1 for TIM3_CCR2 (CC2S = 10) */
	/* (2) Select TI1FP1 as valid trigger input (TS = 101)
	 configure the slave mode in reset mode (SMS = 100) */
	/* (3) Enable capture by setting CC1E and CC2E
	 select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0, reset
	 value),
	 select the falling edge on CC2 (CC2P = 1). */
	/* (4) Enable interrupt on Capture/Compare 1 */
	/* (5) Enable counter */
	TIM3->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1)*/
	TIM3->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS_2; /* (2) */
	TIM3->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
	TIM3->DIER |= TIM_DIER_CC1IE; /* (4) */
	TIM3->CR1 |= TIM_CR1_CEN; /* (5) */
	NVIC_EnableIRQ(TIM3_IRQn);
}
void TIM14_Init(void) { //configure IN2 as rpm input PB1 TIM14
	// PB1 AF0 TIM14 Input1
	// prescaler 1:21 ->1/4uS tick (since APBx presc !=1, timer clocks = APBx_cls x 2)
	RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
	GPIOB->MODER &= ~(3 << (1 * 2));
	GPIOB->MODER |= (2 << (1 * 2));
	GPIOB->OTYPER &= ~(1 << 1 * 1);
	GPIOB->OSPEEDR &= ~(3 << (1 * 2));
	GPIOB->PUPDR &= ~(3 << (1 * 2));
	GPIOB->AFR[0] &= ~(15 << (1 * 4));
	GPIOB->AFR[0] |= (0 << (1 * 4));
	RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
	TIM14->ARR = 0xFFFF;
	TIM14->PSC = 599;
	/* (1) Select the active input TI1 (CC1S = 01),
	 program the input filter for 8 clock cycles (IC1F = 0011),
	 select the rising edge on CC1 (CC1P = 0, reset value)
	 and prescaler at each valid transition (IC1PS = 00, reset value) */
	/* (2) Enable capture by setting CC1E */
	/* (3) Enable interrupt on Capture/Compare */
	/* (4) Enable counter */
	TIM14->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1)*/
	TIM14->CCER |= TIM_CCER_CC1E; /* (2) */
	TIM14->DIER |= TIM_DIER_CC1IE; /* (3) */
	TIM14->CR1 |= TIM_CR1_CEN; /* (4) */
	NVIC_EnableIRQ(TIM14_IRQn);
}
void TIM3_IRQHandler(void) {
	if ((TIM3->SR & TIM_SR_CC1IF) != 0) {
		if ((TIM3->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
		{
			/* Overflow error management */
			/* Reinitialize the laps computing */
			TIM3->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
			return;
		} else {
			counter0 = TIM3->CCR1;
			var.idle_dc = (TIM3->CCR2) * 1000 / TIM3->CCR1; //Get DC
			//	printf("data1 =%d; data2 =%d \n",counter0,counter1);
		}
	} else {
		/* Unexpected Interrupt */
		/* Manage an error for robust application */
	}
}
void TIM14_IRQHandler(void) {
	if ((TIM14->SR & TIM_SR_CC1IF) != 0) {
		if ((TIM14->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
		{
			/* Overflow error management */
			/* Reinitialize the laps computing */
			TIM14->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
			var.rpm = 0;
			gap = 0;
			return;
		}
		if (gap == 0) /* Test if it is the first rising edge */
		{
			counter0 = TIM14->CCR1; /* Read the capture counter which clears the
			 CC1ICF */
			gap = 1; /* Indicate that the first rising edge has yet been detected */
		} else {
			counter1 = TIM14->CCR1; /* Read the capture counter which clears the
			 CC1ICF */
			if (counter1 > counter0) /* Check capture counter overflow */
			{
				Counter = counter1 - counter0;
			} else {
				Counter = counter1 + 0xFFFF - counter0 + 1;
			}
			counter0 = counter1;
			var.rpm = Counter;
		}
	} else {
		/* Unexpected Interrupt */
		/* Manage an error for robust application */
	}
}
